Texas Instruments PCM4202EVM User Manual
User's Guide
SBAU103 – August 2004
PCM4202EVM User's Guide
This document provides the information needed to set up and operate the
PCM4202EVM evaluation module (EVM). For a more detailed description of the
PCM4202, please refer to the product datasheet available from the Texas Instruments
web site at http://www.ti.com. Additional support documents are listed in the sections of
this guide entitled Related Documentation from Texas Instruments and Additional
Documentation. Throughout this document, the acronym EVM and the phrase
evaluation module are synonymous with the PCM4202EVM. This user's guide includes
setup and configuration instructions, information regarding absolute operating conditions for power supplies and input/output connections, an electrical schematic, PCB
layout drawings, and a bill of materials (BOM) for the EVM.
Contents
1 Introduction ........................................................................................ 3
2 Getting Started ..................................................................................... 7
3 Hardware Description and Configuration .................................................... 8
4 Schematic, PCB Layout, and Bill of Materials ............................................. 13
List of Figures
1 PCM4202 Functional Block Diagram .......................................................... 3
2 PCM4202EVM Functional Block Diagram .................................................... 5
3 DIT (Transmitter) Reset Circuitry ............................................................. 13
4 PCM4202EVM Schematic Diagram ........................................................... 14
5 Top Side Silkscreen ............................................................................. 16
6 Bottom Side Silkscreen ........................................................................ 17
7 Top Layer (Component Side) .................................................................. 18
8 Ground Plane Layer ............................................................................. 19
9 Power Plane Layer .............................................................................. 20
10 Bottom Layer (Solder Side) .................................................................... 21
List of Tables
1 Absolute Operating Conditions ................................................................ 8
2 Audio Data Format Selection ................................................................... 9
3 System Clock Source Selection .............................................................. 10
4 Sampling Mode Selection: PCM Slave Mode Audio Formats .......................... 11
5 Sampling Mode Selection: PCM Master Mode Audio Formats ......................... 11
6 Sampling Mode Selection: DSD Output Mode ............................................. 11
7 Digital High-Pass Filter Configuration ...................................................... 11
PCM4202EVM User's GuideSBAU103 – August 2004 1
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8 Digital Interface Transmitter Configuration ................................................ 12
9 Transmitter Master Clock Configuration.................................................... 12
10 Transmitter Output Mode Configuration.................................................... 12
11 PCM4202EVM Bill of Materials ................................................................ 22
PCM4202EVM User's Guide2 SBAU103–August 2004
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Delta−Sigma
Modulator
Audio
Serial
Port
Clock
Control
VINR+
VINR
−
LRCK
or DSDBCK
BCK
or DSDL
DATA
or DSDR
CLIPR
CLIPL
Decimation
Filter
Voltage
Reference
NDR
V
REF
R
COM
R
V
COM
L
Voltage
Reference
V
REF
L
GNDL
Delta−Sigma
Modulator
VINL
−
VINL+
Power
V
CC
AGND VDDDGND
HPF
Decimation
Filter
HPF
Reset
Logic
S/M
FMT0
FMT1
HPFD
FS0
FS1
FS2
SCKI
RST
Introduction
1 Introduction
The PCM4202 is a high-performance, two-channel stereo audio analog-to-digital (A/D) converter
designed for use in professional and broadcast audio applications. The PCM4202 features
simultaneous 24-bit linear PCM or 1-bit Direct Stream Digital (DSD) data output for both channels.
Sampling rates up to 216kHz are supported for PCM output formats, while 64x or 128x
oversampled 1-bit data is supported for the DSD output mode. Native support for both PCM and
DSD data formats makes the PCM4202 ideal for use in a variety of audio recording and processing
applications.
The PCM4202 features 1-bit delta-sigma (∆Σ) modulators employing a novel density modulated
dithering scheme, yielding improved dynamic performance. Differential voltage inputs are utilized
for the modulators, providing excellent common-mode rejection. On-chip voltage references are
provided for the modulators, in addition to generating DC common-mode bias voltage outputs for
use with external input circuitry. Linear phase digital decimation filtering is provided for the 24-bit
PCM output, with a minimum stop band attenuation of -100dB for all sampling modes.
The PCM output mode features clipping flag outputs for each channel, as well as a digital high-pass
filter for DC removal. The PCM4202 is configured using dedicated input pins for sampling mode
and audio data format selection, high-pass filter enable/disable, and reset/power-down operation.
A +5V power supply is required for the analog section of the device, while a +3.3V power supply is
required for the digital circuitry. Figure 1 shows the functional block diagram of the PCM4202.
Figure 1. PCM4202 Functional Block Diagram
PCM4202EVM User's GuideSBAU103 – August 2004 3
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Introduction
1.1 PCM4204EVM Features
The PCM4202EVM provides a convenient platform for evaluating the performance and functionality
of the PCM4202 product. The primary EVM features include:
• Simple configuration using onboard DIP switches
• Two differential voltage inputs supporting either 3-pin XLR or Balanced TRS connections
• Low-noise input buffer circuits utilizing the OPA1632 fully differential audio amplifier
• Two 75Ω AES3-encoded outputs, supporting operation up to 216kHz sampling rates
• Buffered Audio Serial Port supports a two-channel, 24-bit linear PCM data interface for external
hardware and signal processors. Sampling rates up to 216kHz are supported.
• Two onboard system clock oscillators, operating at 22.5792MHz and 24.576MHz respectively,
supporting standard PCM sampling rates, including 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz,
and 192kHz.
• External system clock inputs supporting alternative sampling rates up to 216kHz.
The PCM4202EVM requires +15V, -15V, and +5V analog power supplies. Additionally, a +5V digital
power supply is required, with a +3.3V digital supply being derived onboard using a linear voltage
regulator IC.
1.2 PCM4202EVM General Description and Functional Block Diagram
The PCM4202EVM provides a complete platform for evaluating the performance and features of
the PCM4202 stereo audio A/D converter. Figure 2 illustrates the functional block diagram for the
evaluation module.
PCM4202EVM User's Guide4 SBAU103 – August 2004
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J1
Left Channel
Input
J2
Right Channel
Input
Analog
Input Buffers
OPA1632 x 2
U1
PCM4202
BUF
S/M
PCM Data
Switch
SW1
Switch
SW3
GND
To
DIT Circuitry
J3
+5VA
−
15V+15V
BUF
DIT
U12
DIT4192
J5
AES3 Out #1
Stereo: L + R
Mono: L
HDR
J4
Audio
Serial Port
U6
REG1117
+3.3V
+15
GND
−15GND
+5VA
U13
DIT4192
J6
AES3 Out #2
Stereo: L + R
Mono: R
X1
22.5792M
J7
EXT CLOCK INPUT
Switch
SW5
System
Clock
To
Clock Enables
X2
24.576M
J8
+5VD
+5VD
GND
+3.3VD
+3.3V
JMP3
Introduction
Two differential analog inputs are supported at connectors J1 and J2, corresponding to Left and
Right analog input channels, respectively. These connectors support either 3-pin male XLR or
balanced TRS input plugs. Each of the analog inputs is buffered and filtered using a low noise input
circuit, utilizing a Texas Instruments OPA1632 fully differential amplifier. The output of each buffer
Figure 2. PCM4202EVM Functional Block Diagram
circuit is connected to a corresponding differential input of the PCM4202. The PCM4202 is then
used to convert the analog signal to either a 24-bit linear PCM or 1-bit DSD representation in the
digital domain.
The 24-bit PCM or 1-bit DSD data output is made available at header J4. The 24-bit PCM audio
data is also made available at the AES3 encoded data outputs provided at RCA jacks J5 and J6.
The buffered header is convenient for interfacing to external development hardware or digital signal
processors, while the AES3 encoded outputs may be connected to audio test systems or
commercial audio equipment.
Power is connected to the board at either terminal block J3 for the analog supplies, or at terminal
block J8 for the digital supplies.
PCM4202EVM User's GuideSBAU103 – August 2004 5
Introduction
Manual reset circuits are provided for both the PCM4202 (U1) and the AES3 transmitters (U12 and
U13). The ADC RESET switch (SW2) is utilized for resetting the A/D converter, while the DIT
RESET switch (SW4) is utilized for resetting the AES3 transmitters.
The system or master clock for the evaluation module may be generated onboard or by an external
clock source. Oscillators X1 and X2 operate at fixed clock frequencies of 22.5792MHz and
24.576MHz, respectively. The oscillators provide low jitter clock sources for measuring the
performance of the PCM4202 in Master mode operation. Alternatively, an external clock source
may be connected at J7 for Master mode operation, supporting alternate system clock and
sampling frequencies. For Slave mode operation, the system clock is provided from an external
source through header J4 and buffer U9. Switch SW5 provides clock configuration control for the
oscillators and the external clock input at connector J7.
1.3 Related Documentation from Texas Instruments
The following documents provide information regarding Texas Instrument integrated circuits used in
the assembly of the PCM4202EVM. The latest revisions of these documents are available from the
TI web site at http://www.ti.com.
Data Sheet Literature Number
PCM4202 Datasheet SBAS290
DIT4192 Datasheet SBOS229
OPA227 Datasheet SBOS110
OPA1632 Datasheet SBOS286
REG1117 Datasheet SBVS001
SN74AHC08 Datasheet SCLS236
SN74AHC14 Datasheet SCLS238
SN74ALVC245 Datasheet SCES271
SN74LVC1G125 Datasheet SCES223
www.ti.com
1.4 Additional Documentation
The following documents or references provide information regarding selected non-TI components
used in the assembly of the PCM4202EVM. These documents are available from the corresponding
manufacturer.
Document/Reference Manufacturer
SM7745H Series CMOS Oscillators Pletronics ( http://www.pletronics.com )
6 SBAU103–August 2004PCM4202EVM User's Guide
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2 Getting Started
This section provides information regarding handling and unpacking the PCM4202EVM, as well as
absolute operating conditions for the unit.
2.1 Electrostatic Discharge Warning
Failure to observe proper ESD handling precautions may result in damage to
EVM components.
Many of the components on the PCM4202EVM are susceptible to damage by electrostatic
discharge (ESD). Customers are advised to observe proper ESD handling procedure when
unpacking and handling the EVM, including the use of a grounded wrist strap at an approved ESD
workstation. Failure to observe ESD handling procedures may result in damage to EVM
components.
2.2 EVM Package Contents
Upon opening the PCM4202EVM package, please check to make sure that the following items are
included:
· One PCM4202EVM
· One printed copy of the PCM4202 product datasheet
· One printed copy of this PCM4202EVM User's Guide
Getting Started
CAUTION
If any of these items are missing, please contact the Texas Instruments Product Information Center
nearest you to inquire about replacements.
2.3 Absolute Operating Conditions
Exceeding the absolute operating conditions may result in damage to the
evaluation module and/or the equipment connected to it.
The user should be aware of the absolute operating conditions for the PCM4202EVM. Table 1
summarizes the critical data points.
CAUTION
SBAU103– August 2004 PCM4202EVM User's Guide 7
Hardware Description and Configuration
Table 1. Absolute Operating Conditions
Power Supplies
+15V +5.0 +16.0 V
-15V -5.0 -16.0 V
+5VA +4.5 +5.5 V
+5VD +4.5 +5.5 V
EXT +3.3V +3.0 +3.6 V
Audio Serial Port (J4)
VIH, Input High Voltage (VDD= +3.0V to +3.6V) 0.7 x V
VIL, Input Low Voltage (VDD= +3.0V to +3.6V) -0.3 0.3 x V
Analog Inputs (connectors J1 and J2)
Differential Input Voltage, RMS 7.9 V
Differential Input Voltage, Peak-to-Peak 22.3 V
3 Hardware Description and Configuration
This section provides hardware description and configuration information for the PCM4202EVM.
www.ti.com
Min Max Units
DD
VDD+ 0.3 V
DD
V
RMS
PP
3.1 Power Supply Configuration
The PCM4202EVM requires three analog power supplies and one digital power supply for
operation. The analog supplies are connected at terminal block J3, while the digital supply is
connected at terminal block J8.
Analog supplies include +15V and -15V DC for powering the input buffer circuits, as well as +5.0V
DC for powering the analog section of the PCM4202. All supplies should be rated for at least
500mA of output current.
The digital supply requires +5.0V DC and should be rated for at least 500mA of output current. The
+5.0V supply is regulated to +3.3V DC by an onboard Texas Instruments REG1117 linear voltage
regulator (U6), which is used to power the digital section of the PCM4202 and the majority of the
support logic circuitry. The core logic and line driver sections of the AES3 transmitters (U12 and
U13) utilize the +5.0V digital supply directly.
An optional external +3.3V DC digital power supply is supported at terminal block J8. Jumper JMP3
is utilized to select either the onboard voltage regulator (U6) or an external +3.3V power source.
Shorting pins 1 and 2 together using the supplied jumper block selects the onboard +3.3V voltage
regulator. Shorting pins 3 and 4 together will select the external +3.3V supply terminal (EXT
+3.3VD) on terminal block J14. Only one source may be selected at any time.
PCM4202EVM User's Guide8 SBAU103–August 2004
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