User's Guide
SBAU103 – August 2004
PCM4202EVM User's Guide
This document provides the information needed to set up and operate the
PCM4202EVM evaluation module (EVM). For a more detailed description of the
PCM4202, please refer to the product datasheet available from the Texas Instruments
web site at http://www.ti.com. Additional support documents are listed in the sections of
this guide entitled Related Documentation from Texas Instruments and Additional
Documentation. Throughout this document, the acronym EVM and the phrase
evaluation module are synonymous with the PCM4202EVM. This user's guide includes
setup and configuration instructions, information regarding absolute operating conditions for power supplies and input/output connections, an electrical schematic, PCB
layout drawings, and a bill of materials (BOM) for the EVM.
Contents
1 Introduction ........................................................................................ 3
2 Getting Started ..................................................................................... 7
3 Hardware Description and Configuration .................................................... 8
4 Schematic, PCB Layout, and Bill of Materials ............................................. 13
List of Figures
1 PCM4202 Functional Block Diagram .......................................................... 3
2 PCM4202EVM Functional Block Diagram .................................................... 5
3 DIT (Transmitter) Reset Circuitry ............................................................. 13
4 PCM4202EVM Schematic Diagram ........................................................... 14
5 Top Side Silkscreen ............................................................................. 16
6 Bottom Side Silkscreen ........................................................................ 17
7 Top Layer (Component Side) .................................................................. 18
8 Ground Plane Layer ............................................................................. 19
9 Power Plane Layer .............................................................................. 20
10 Bottom Layer (Solder Side) .................................................................... 21
List of Tables
1 Absolute Operating Conditions ................................................................ 8
2 Audio Data Format Selection ................................................................... 9
3 System Clock Source Selection .............................................................. 10
4 Sampling Mode Selection: PCM Slave Mode Audio Formats .......................... 11
5 Sampling Mode Selection: PCM Master Mode Audio Formats ......................... 11
6 Sampling Mode Selection: DSD Output Mode ............................................. 11
7 Digital High-Pass Filter Configuration ...................................................... 11
PCM4202EVM User's GuideSBAU103 – August 2004 1
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8 Digital Interface Transmitter Configuration ................................................ 12
9 Transmitter Master Clock Configuration.................................................... 12
10 Transmitter Output Mode Configuration.................................................... 12
11 PCM4202EVM Bill of Materials ................................................................ 22
PCM4202EVM User's Guide2 SBAU103–August 2004
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Delta−Sigma
Modulator
Audio
Serial
Port
Clock
Control
VINR+
VINR
−
LRCK
or DSDBCK
BCK
or DSDL
DATA
or DSDR
CLIPR
CLIPL
Decimation
Filter
Voltage
Reference
NDR
V
REF
R
COM
R
V
COM
L
Voltage
Reference
V
REF
L
GNDL
Delta−Sigma
Modulator
VINL
−
VINL+
Power
V
CC
AGND VDDDGND
HPF
Decimation
Filter
HPF
Reset
Logic
S/M
FMT0
FMT1
HPFD
FS0
FS1
FS2
SCKI
RST
Introduction
1 Introduction
The PCM4202 is a high-performance, two-channel stereo audio analog-to-digital (A/D) converter
designed for use in professional and broadcast audio applications. The PCM4202 features
simultaneous 24-bit linear PCM or 1-bit Direct Stream Digital (DSD) data output for both channels.
Sampling rates up to 216kHz are supported for PCM output formats, while 64x or 128x
oversampled 1-bit data is supported for the DSD output mode. Native support for both PCM and
DSD data formats makes the PCM4202 ideal for use in a variety of audio recording and processing
applications.
The PCM4202 features 1-bit delta-sigma (∆Σ) modulators employing a novel density modulated
dithering scheme, yielding improved dynamic performance. Differential voltage inputs are utilized
for the modulators, providing excellent common-mode rejection. On-chip voltage references are
provided for the modulators, in addition to generating DC common-mode bias voltage outputs for
use with external input circuitry. Linear phase digital decimation filtering is provided for the 24-bit
PCM output, with a minimum stop band attenuation of -100dB for all sampling modes.
The PCM output mode features clipping flag outputs for each channel, as well as a digital high-pass
filter for DC removal. The PCM4202 is configured using dedicated input pins for sampling mode
and audio data format selection, high-pass filter enable/disable, and reset/power-down operation.
A +5V power supply is required for the analog section of the device, while a +3.3V power supply is
required for the digital circuitry. Figure 1 shows the functional block diagram of the PCM4202.
Figure 1. PCM4202 Functional Block Diagram
PCM4202EVM User's GuideSBAU103 – August 2004 3
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Introduction
1.1 PCM4204EVM Features
The PCM4202EVM provides a convenient platform for evaluating the performance and functionality
of the PCM4202 product. The primary EVM features include:
• Simple configuration using onboard DIP switches
• Two differential voltage inputs supporting either 3-pin XLR or Balanced TRS connections
• Low-noise input buffer circuits utilizing the OPA1632 fully differential audio amplifier
• Two 75Ω AES3-encoded outputs, supporting operation up to 216kHz sampling rates
• Buffered Audio Serial Port supports a two-channel, 24-bit linear PCM data interface for external
hardware and signal processors. Sampling rates up to 216kHz are supported.
• Two onboard system clock oscillators, operating at 22.5792MHz and 24.576MHz respectively,
supporting standard PCM sampling rates, including 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz,
and 192kHz.
• External system clock inputs supporting alternative sampling rates up to 216kHz.
The PCM4202EVM requires +15V, -15V, and +5V analog power supplies. Additionally, a +5V digital
power supply is required, with a +3.3V digital supply being derived onboard using a linear voltage
regulator IC.
1.2 PCM4202EVM General Description and Functional Block Diagram
The PCM4202EVM provides a complete platform for evaluating the performance and features of
the PCM4202 stereo audio A/D converter. Figure 2 illustrates the functional block diagram for the
evaluation module.
PCM4202EVM User's Guide4 SBAU103 – August 2004
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J1
Left Channel
Input
J2
Right Channel
Input
Analog
Input Buffers
OPA1632 x 2
U1
PCM4202
BUF
S/M
PCM Data
Switch
SW1
Switch
SW3
GND
To
DIT Circuitry
J3
+5VA
−
15V+15V
BUF
DIT
U12
DIT4192
J5
AES3 Out #1
Stereo: L + R
Mono: L
HDR
J4
Audio
Serial Port
U6
REG1117
+3.3V
+15
GND
−15GND
+5VA
U13
DIT4192
J6
AES3 Out #2
Stereo: L + R
Mono: R
X1
22.5792M
J7
EXT CLOCK INPUT
Switch
SW5
System
Clock
To
Clock Enables
X2
24.576M
J8
+5VD
+5VD
GND
+3.3VD
+3.3V
JMP3
Introduction
Two differential analog inputs are supported at connectors J1 and J2, corresponding to Left and
Right analog input channels, respectively. These connectors support either 3-pin male XLR or
balanced TRS input plugs. Each of the analog inputs is buffered and filtered using a low noise input
circuit, utilizing a Texas Instruments OPA1632 fully differential amplifier. The output of each buffer
Figure 2. PCM4202EVM Functional Block Diagram
circuit is connected to a corresponding differential input of the PCM4202. The PCM4202 is then
used to convert the analog signal to either a 24-bit linear PCM or 1-bit DSD representation in the
digital domain.
The 24-bit PCM or 1-bit DSD data output is made available at header J4. The 24-bit PCM audio
data is also made available at the AES3 encoded data outputs provided at RCA jacks J5 and J6.
The buffered header is convenient for interfacing to external development hardware or digital signal
processors, while the AES3 encoded outputs may be connected to audio test systems or
commercial audio equipment.
Power is connected to the board at either terminal block J3 for the analog supplies, or at terminal
block J8 for the digital supplies.
PCM4202EVM User's GuideSBAU103 – August 2004 5
Introduction
Manual reset circuits are provided for both the PCM4202 (U1) and the AES3 transmitters (U12 and
U13). The ADC RESET switch (SW2) is utilized for resetting the A/D converter, while the DIT
RESET switch (SW4) is utilized for resetting the AES3 transmitters.
The system or master clock for the evaluation module may be generated onboard or by an external
clock source. Oscillators X1 and X2 operate at fixed clock frequencies of 22.5792MHz and
24.576MHz, respectively. The oscillators provide low jitter clock sources for measuring the
performance of the PCM4202 in Master mode operation. Alternatively, an external clock source
may be connected at J7 for Master mode operation, supporting alternate system clock and
sampling frequencies. For Slave mode operation, the system clock is provided from an external
source through header J4 and buffer U9. Switch SW5 provides clock configuration control for the
oscillators and the external clock input at connector J7.
1.3 Related Documentation from Texas Instruments
The following documents provide information regarding Texas Instrument integrated circuits used in
the assembly of the PCM4202EVM. The latest revisions of these documents are available from the
TI web site at http://www.ti.com.
Data Sheet Literature Number
PCM4202 Datasheet SBAS290
DIT4192 Datasheet SBOS229
OPA227 Datasheet SBOS110
OPA1632 Datasheet SBOS286
REG1117 Datasheet SBVS001
SN74AHC08 Datasheet SCLS236
SN74AHC14 Datasheet SCLS238
SN74ALVC245 Datasheet SCES271
SN74LVC1G125 Datasheet SCES223
www.ti.com
1.4 Additional Documentation
The following documents or references provide information regarding selected non-TI components
used in the assembly of the PCM4202EVM. These documents are available from the corresponding
manufacturer.
Document/Reference Manufacturer
SM7745H Series CMOS Oscillators Pletronics ( http://www.pletronics.com )
6 SBAU103–August 2004PCM4202EVM User's Guide
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2 Getting Started
This section provides information regarding handling and unpacking the PCM4202EVM, as well as
absolute operating conditions for the unit.
2.1 Electrostatic Discharge Warning
Failure to observe proper ESD handling precautions may result in damage to
EVM components.
Many of the components on the PCM4202EVM are susceptible to damage by electrostatic
discharge (ESD). Customers are advised to observe proper ESD handling procedure when
unpacking and handling the EVM, including the use of a grounded wrist strap at an approved ESD
workstation. Failure to observe ESD handling procedures may result in damage to EVM
components.
2.2 EVM Package Contents
Upon opening the PCM4202EVM package, please check to make sure that the following items are
included:
· One PCM4202EVM
· One printed copy of the PCM4202 product datasheet
· One printed copy of this PCM4202EVM User's Guide
Getting Started
CAUTION
If any of these items are missing, please contact the Texas Instruments Product Information Center
nearest you to inquire about replacements.
2.3 Absolute Operating Conditions
Exceeding the absolute operating conditions may result in damage to the
evaluation module and/or the equipment connected to it.
The user should be aware of the absolute operating conditions for the PCM4202EVM. Table 1
summarizes the critical data points.
CAUTION
SBAU103– August 2004 PCM4202EVM User's Guide 7
Hardware Description and Configuration
Table 1. Absolute Operating Conditions
Power Supplies
+15V +5.0 +16.0 V
-15V -5.0 -16.0 V
+5VA +4.5 +5.5 V
+5VD +4.5 +5.5 V
EXT +3.3V +3.0 +3.6 V
Audio Serial Port (J4)
VIH, Input High Voltage (VDD= +3.0V to +3.6V) 0.7 x V
VIL, Input Low Voltage (VDD= +3.0V to +3.6V) -0.3 0.3 x V
Analog Inputs (connectors J1 and J2)
Differential Input Voltage, RMS 7.9 V
Differential Input Voltage, Peak-to-Peak 22.3 V
3 Hardware Description and Configuration
This section provides hardware description and configuration information for the PCM4202EVM.
www.ti.com
Min Max Units
DD
VDD+ 0.3 V
DD
V
RMS
PP
3.1 Power Supply Configuration
The PCM4202EVM requires three analog power supplies and one digital power supply for
operation. The analog supplies are connected at terminal block J3, while the digital supply is
connected at terminal block J8.
Analog supplies include +15V and -15V DC for powering the input buffer circuits, as well as +5.0V
DC for powering the analog section of the PCM4202. All supplies should be rated for at least
500mA of output current.
The digital supply requires +5.0V DC and should be rated for at least 500mA of output current. The
+5.0V supply is regulated to +3.3V DC by an onboard Texas Instruments REG1117 linear voltage
regulator (U6), which is used to power the digital section of the PCM4202 and the majority of the
support logic circuitry. The core logic and line driver sections of the AES3 transmitters (U12 and
U13) utilize the +5.0V digital supply directly.
An optional external +3.3V DC digital power supply is supported at terminal block J8. Jumper JMP3
is utilized to select either the onboard voltage regulator (U6) or an external +3.3V power source.
Shorting pins 1 and 2 together using the supplied jumper block selects the onboard +3.3V voltage
regulator. Shorting pins 3 and 4 together will select the external +3.3V supply terminal (EXT
+3.3VD) on terminal block J14. Only one source may be selected at any time.
PCM4202EVM User's Guide8 SBAU103–August 2004
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3.2 Analog Inputs
The PCM4202EVM includes two Neutrik combo XLR connectors, which accept either 3-pin male
XLR or ¼-inch TRS phono plugs. The connectors are numbered J1 and J2, corresponding to the
left and right channels, respectively.
The analog inputs can accept up to a 7.9V
then attenuated by a factor of 3.7 by the input buffer circuit, which corresponds to the 6.0V
full-scale differential input voltage for the PCM4202 analog inputs.
The input buffer circuits are each comprised of a single OPA1632 fully differential audio amplifier
and associated passive components. The input buffer provides active attenuation and low pass
filtering for the analog input signal. The OPA1632 outputs are DC level-shifted by approximately
+2.5V using the amplifiers V
the PCM4202 V
L (pin 3) or V
COM
3.3 Audio Data Format Selection
Switch SW1 is used to select the audio data format for the PCM4202. Table 2 summarizes the
available audio data formats for both Slave and Master mode operation and the corresponding
SW1 switch settings.
Hardware Description and Configuration
(or 22.3VPP) differential input signal. This signal is
RMS
IN input (pin 2), which are connected to a buffered version of either
COM
R outputs (pin 26).
COM
PP
Table 2. Audio Data Format Selection
FMT1 FMT0 Audio Data Format (Slave or Master Mode)
LO LO 24-Bit Left Justified PCM Data
LO HI 24-Bit I2S PCM Data
HI LO 24-Bit Right Justified PCM Data
HI HI DSD Output Mode (Master Mode only)
For Slave mode operation, the Audio Serial Port header (connector J4) is utilized to interface to a
Master device, such as a digital signal processor, FPGA, or an audio test system with a
synchronous serial port interface. The system clock (SCKI), bit clock (BCK), and left/right word
clock (LRCK) are generated by the Master device and are used to drive the SCKI (pin 18), BCK
(pin 16), and LRCK (pin 17) inputs of the PCM4202. Serial audio data is output at DATA (pin 15).
Slave mode supports PCM-formatted output data only. DSD output data is available only in
Master mode.
For Master mode, the system clock is provided by one of the sources described in Section 3.4 of
this document. The PCM4202 internally generates the BCK and LRCK clocks, which are then
output to the Audio Serial Port header (connector J4) and the AES3 digital interface transmitters,
which then drive output connectors J5 and J6.
Master mode may also be configured to support 1-bit DSD-formatted audio output data, as shown
in Table 2. For the DSD mode formats, header J4 provides the output interface. The DATA output
functions as the RIght channel DSD output (DSDR), the BCK output servers as the left channel
DSD output (DSDL), and the LRCK output becomes the DSD bit clock (DSDBCK).
PCM4202EVM User's GuideSBAU103– August 2004 9
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Hardware Description and Configuration
3.4 System Clock Configuration
Switch SW5 is used to select the system clock source for the PCM4202EVM. Table 3 summarizes
the available clock source options. The onboard oscillators support standard PCM sampling rates in
Master mode, including 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, and 192kHz. The external
clock input (connector J7) may be used to supply alternate system clock frequencies that support
alternative sample rates.
Table 3. System Clock Source Selection
Switch SW5
EXT OSC1 OSC0
LO LO LO External clock input at J7 Master
HI LO LO External clock input at the SCKI pin of header J4 Slave
HI LO HI Oscillator X1, 22.5792MHz Master
HI HI LO Oscillator X2, 22.576MHz Master
3.5 Sampling Mode Selection
The sampling mode of the PCM4202 is selected using switch SW1. Table 4 through Table 6
summarize the available sampling modes for both PCM and DSD output modes.
Single Rate sampling mode is designed for output sampling rates up to 54kHz. The modulator
oversampling rate is set to 128x.
Dual Rate sampling mode is designed for output sampling rates greater than 54kHz and up to
108kHz. The modulator oversampling rate is set to 64x.
Quad Rate sampling mode is designed for output sampling rates greater than 108kHz and up to
216kHz. The modulator oversampling rate is set to 32x.
System Clock Source Used for Master or Slave Mode Operation?
10 PCM4202EVM User's Guide SBAU103 – August 2004
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Table 4. Sampling Mode Selection: PCM Slave Mode Audio Formats
FS2 FS1 FS0 Sampling Mode
LO LO LO Single Rate with Clock Auto-Detection
LO LO HI Dual Rate with Clock Auto-Detection
LO HI LO Quad Rate with Clock Auto-Detection
LO HI HI Reserved
HI LO LO Reserved
HI LO HI Reserved
HI HI LO Reserved
HI HI HI Reserved
Table 5. Sampling Mode Selection: PCM Master Mode Audio Formats
FS2 FS1 FS0 Sampling Mode
LO LO LO Single Rate with f
LO LO HI Single Rate with f
LO HI LO Single Rate with f
LO HI HI Single Rate with f
HI LO LO Dual Rate with f
HI LO HI Dual Rate with f
HI HI LO Quad Rate with f
HI HI HI Quad Rate with f
SCKI
SCKI
SCKI
SCKI
SCKI
SCKI
SCKI
SCKI
= 768f
= 512f
= 384f
= 256f
= 384f
= 256f
= 192f
= 128f
Hardware Description and Configuration
S
S
S
S
S
S
S
S
Table 6. Sampling Mode Selection: DSD Output Mode
FS2 FS1 FS0 Sampling Mode
LO LO LO 128fsDSD Output Rate with f
LO LO HI 128fsDSD Output Rate with f
LO HI LO 128fsDSD Output Rate with f
LO HI HI 128fsDSD Output Rate with f
HI LO LO 64fsDSD Output Rate with f
HI LO HI 64fsDSD Output Rate with f
HI HI LO Reserved
HI HI HI Reserved
3.6 Digital High-Pass Filter
The PCM4202 includes a digital high-pass filter function for both channels, designed for removing
the DC component from the digitized signal. The high-pass filter is not available when using the
DSD output mode. The high-pass filter function may be enabled or disabled using the HPFD switch
on SW1. Table 7 summarizes the operation of the HPFD switch.
HPFD Digital High-Pass Filter Function
LO Enabled
HI Disabled
= 768f
SCKI
SCKI
SCKI
SCKI
SCKI
SCKI
= 512f
= 384f
= 256f
= 384f
= 256f
S
S
S
S
S
S
Table 7. Digital High-Pass Filter Configuration
PCM4202EVM User's GuideSBAU103– August 2004 11
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Hardware Description and Configuration
3.7 Digital Interface Transmitter Configuration
Two Texas Instruments DIT4192 digital interface transmitters provide AES3-encoded outputs for
the PCM4202EVM. Switch SW3 is utilized to configure the transmitters. The outputs of the
transmitters are available at connectors J5 and J6, which are RCA phono jacks. These outputs are
designed for use with 75Ω coaxial cable connections.
The transmitters are enabled using the DIT switch of SW3. The DIT switch operation is summarized
in Table 8 .
DIT Digital Interface Filter Function
LO Enabled
HI Disabled
The audio data format for the transmitters is hardwired for 24-bit I2S data format. When using the
transmitters, the PCM4202 audio data format must be set to 24-bit I2S, as shown in Table 2 .
Like the PCM4202, the DIT4192 transmitters must be configured for the proper master (or system) clock
frequency. The transmitter master clock is driven by the same source as the PCM4202 system clock, as
described in Section 3.4 of this document. Table 9 summarizes the master clock options for the DIT4192
transmitters using switch SW3.
Table 8. Digital Interface Transmitter Configuration
Table 9. Transmitter Master Clock Configuration
CLK1 CLK0 Transmitter MCLK Frequency
LO LO 128f
LO HI 256f
HI LO 384f
HI HI 512f
S
S
S
S
The DIT4192 transmitters may be operated in either Stereo or Mono mode. In Stereo mode, two channels
of audio data are transmitted at the input sampling frequency. In Mono mode, two consecutive samples of
only one channel are transmitted at one-half the input sampling rate. The Mono mode is useful for
performance testing with fS= 176.4kHz or fS= 192kHz with a system that can only accept only half these
rates. This is the case with the Audio Precision System Two Cascade or Cascade Plus test system, which
was used for factory performance testing of the PCM4202. Mono mode can be used in conjunction with
the Audio Precision Dual BNC digital input mode to test at sampling rates up to 216kHz.
The MONO switch on SW3 is used to enable or disable Mono mode operation. Table 10 summarizes the
operation of the MONO switch.
Table 10. Transmitter Output Mode Configuration
MONO Transmitter Output Mode
LO Stereo Mode
HI Mono Mode
Left and Right channel data are output on both J5 and J6
Left channel data is output on J5
Right channel data is output on J6
PCM4202EVM User's Guide12 SBAU103 – August 2004
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3.8 Reset Operations
The PCM4202EVM includes two reset switches, SW2 and SW4. Both are momentary contact
pushbutton switches that are normally open. SW2 provides the manual reset for the PCM4202
(U1), while switch SW4 provides the manual reset for the two DIT4192 transmitters (U12 and U13).
The PCM4202 may be reset at any time my momentarily pressing and then releasing switch SW2.
This generates a reset pulse and initiates a reset sequence for the device.
For the DIT reset function, the output of the reset circuit is connected to the RST pins of DIT4192
transmitters (U12 and U13). The transmitters may be reset only when the DIT switch of SW3 is set
LO by momentarily pressing and then releasing switch SW4. If the DIT switch is set HI, the output
of the AND gate in the reset circuit is forced low, which will force both transmitters into power-down
mode. The transmitter reset circuit is shown in Figure 3.
SW4
N.O.
+3.3V
From DIT
Schematic, PCB Layout, and Bill of Materials
U7
U8
To RST of
U12 and U13
Figure 3. DIT (Transmitter) Reset Circuitry
4 Schematic, PCB Layout, and Bill of Materials
This section provides the electrical schematic and physical layout information for the
PCM4202EVM. The bill of materials is included as a component reference.
Board layouts are not to scale. These figures are intended to show how the board is
laid out; they are not intended to be used for manufacturing PCM4202EVM PCBs.
4.1 Schematic
The electrical schematic for the PCM4202EVM is shown in Figure 4. The components shown in the
schematic are listed in Table 11 for reference.
NOTE
PCM4202EVM User's GuideSBAU103– August 2004 13
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Schematic, PCB Layout, and Bill of Materials
PCM4202EVM User's Guide14 SBAU103 – August 2004
Figure 4. PCM4202EVM Schematic Diagram
www.ti.com
4.2 PCB Layout
Schematic, PCB Layout, and Bill of Materials
The PCM4202EVM is a 4-layer printed circuit board with the following layer structure:
• Layer 1: Top (Component Side)
• Layer 2: Ground Plane
• Layer 3: Power
• Layer 4: Bottom (Solder Side)
The ground plane doubles as a heat sink for the PCM4202 PowerPAD package. Refer to the
product datasheet for more information on the purpose and application of the PowerPAD
connection.
Figure 5 through Figure 10 show the top side silk screen, along with the top, ground plane, power,
and bottom layers of the printed circuit board.
PCM4202EVM User's GuideSBAU103 – August 2004 15
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Schematic, PCB Layout, and Bill of Materials
Figure 5. Top Side Silkscreen
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Schematic, PCB Layout, and Bill of Materials
Figure 6. Bottom Side Silkscreen
17SBAU103 – August 2004 PCM4202EVM User's Guide
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Schematic, PCB Layout, and Bill of Materials
Figure 7. Top Layer (Component Side)
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Schematic, PCB Layout, and Bill of Materials
Figure 8. Ground Plane Layer
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Schematic, PCB Layout, and Bill of Materials
Figure 9. Power Plane Layer
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Schematic, PCB Layout, and Bill of Materials
Figure 10. Bottom Layer (Solder Side)
PCM4202EVM User's GuideSBAU103 – August 2004 21
Schematic, PCB Layout, and Bill of Materials
4.3 Bill of Materials
The Bill of Materials, listing the components used in the assembly of the PCM4202EVM, is shown
in Table 11.
Table 11. PCM4202EVM Bill of Materials
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ITEM VALUE Ref Des BOARD MFR PART NUMBER DESCRIPTION
1 100pF C45-C48 4 Kemet C0603C101J5GACTU Chip Capacitor, C0G Ceramic, 100pF
2 1nF C31-C34 4 Kemet C0805C102J3GAC Chip Capacitor, C0G Ceramic, 1nF
3 2.7nF C49, C50 2 Kemet C0805C272J3GAC Chip Capacitor, C0G Ceramic, 2.7nF
4 0.01µF C5-C7, 17 Kemet C0603C103J5RACTU Chip Capacitor, X7R Ceramic, 0.01µF
C10-C17, ±5%, 50WV, Size = 0603
C19-C24
5 0.1µF C51-C70 20 Kemet C0603C104J4RACTU Chip Capacitor, X7R Ceramic, 0.1µF
6 10µF C35-C44 10 Kemet T494C106K025AS Chip Capacitor, Low ESR Tantalum,
7 33µF C71-C78 8 Kemet T494B336K010AS Chip Capacitor, Low ESR Tantalum,
8 100µF C8, C9, 5 Panasonic EEV-FK1E101XP Capacitor, SMT Aluminum Electrolytic,
C18, C25, 100µF ±20%, 25WV
C26
9 D1, D2 2 Lumex SML-LX1206IC-TR Red LED, Surface Mount, Size = 1206
10 J1, J2 2 Neutrik NCJ6FI Combo Connector, Female XLR and
11 J3 1 Weidmuller 9967720000 3.5mm PCB Terminal Block, 6 poles
12 J4 1 Samtec TSW-105-07-G-D Terminal Strip, 10-pin (5x2)
13 J5, J6 2 CUI Stack RJC-041 RCA Phono Jack, Black Shell
14 J7 1 Kings Electronics KC-79-274-M06 BNC Connector, Female, PC Mount
15 J8 1 Weidmuller 169968000 3.5mm PCB Terminal Block, 3 poles
16 JMP1, 2 Samtec TSW-102-07-G-S Terminal Strip, 2-pin (2x1)
JMP2
17 JMP3 1 Samtec TSW-102-07-G-D Terminal Strip, 4-pin (2x2)
18 0 R1-R8 8 Panasonic ERJ-6EY0R00V Chip Resistor, 0W, Shunt, Size = 0805
19 40.2 R20-R23 4 Panasonic ERJ-6EN-F40R2V Chip Resistor, Thick Film, 1% Toler-
20 75 R15 1 Panasonic ERJ-6ENF75R0V Chip Resistor, Thick Film, 1% Toler-
21 121 R28, R29 2 Panasonic ERJ-6ENF1210V Chip Resistor, Thick Film, 1% Toler-
22 150 R30, R31 2 Panasonic ERJ-6ENF1500V Chip Resistor, Thick Film, 1% Toler-
23 270 R16-R19 4 Panasonic ERA-6YEB271V Chip Resistor, Metal Film, 0.1% Toler-
24 475 R26, R27 2 Panasonic ERJ-6ENF4750V Chip Resistor, Thick Film, 1% Toler-
25 1K R9-R14 6 Panasonic ERA-6YEB102V Chip Resistor, Metal Film, 0.1% Toler-
26 10K R24, R25 2 Panasonic ERJ-6ENF1002V Chip Resistor, Thick Film, 1% Toler-
27 100 RN2, RN4 2 CTS 742C083101J Thick Film Chip Resistor Array, 100W,
QTY PER MFR
±5%, 50WV, Size = 0603
±5%, 25WV, Size = 0805
±5%, 25WV, Size = 0805
±5%, 16WV, Size = 0603
10µF ±10%, 25WV, Size = C
33µF ±10%, 10WV, Size = B
TRS, Vertical PC Mount
ance, 40.2W, 1/10W, Size = 0805
ance, 75W, 1/10W, Size = 0805
ance, 121W, 1/10W, Size = 0805
ance, 150W, 1/10W, Size = 0805
ance, 270W, 1/10W, Size = 0805
ance, 475W, 1/10W, Size = 0805
ance, 1kW, 1/10W, Size = 0805
ance, 10kW, 1/10W, Size = 0805
8-Terminal, 4 Resistors, Isolated
PCM4202EVM User's Guide22 SBAU103– August 2004
www.ti.com
Schematic, PCB Layout, and Bill of Materials
Table
11.
PCM4202EVM
QTY PER MFR
ITEM VALUE Ref Des BOARD MFR PART NUMBER DESCRIPTION
28 10K RN1, RN3, 3 CTS 742C163103J Thick Film Chip Resistor Array, 10kΩ,
RN5 16-Terminal, 8 Resistors, Isolated
29 SW1 1 ITT Industries/ TDA08H0SK1 DIP Switch, 8 Element, Half-Pitch, Sur-
C&K face-Mount, Tape Sealed
30 SW2, SW4 2 Omron B3S-1000 Momentary Tact Switch, SMT without
31 SW3, SW5 2 ITT Industries/ TDA04H0SK1 DIP Switch, 4 Element, Half-Pitch, Sur-
C&K face-Mount, Tape Sealed
32 U1 1 Texas PCM4202DB Stereo Audio A/D Converter
Instruments
33 U2, U4 2 Texas OPA1632DGN Fully-Differential Audio Amplifier
Instruments
34 U3, U5 2 Texas OPA227UA Precision Operational Amplifier
Instruments
35 U7 1 Texas SN74AHC14DBR Hex Schmitt-Trigger Inverters
Instruments
36 U8 1 Texas SN74AHC08DBR Quad 2-Input Positive AND Gates
Instruments
37 U9-U11 3 Texas SN74ALVC245PW Octal Bus Transceiver with Tri-State
Instruments Outputs
38 U12, U13 2 Texas DIT4192IPW 192kHz Digital Audio Transmitter
Instruments
39 U14 1 Texas SN74LVC1G125DBV Single Non-Inverting Buffer with
Instruments Tri-State Output
40 U6 1 Texas REG1117-3.3 Linear Voltage Regulator, +3.3V
Instruments
41 TP1-TP6 6 Keystone 5006 PCB Test Point, Compact, Through-hole
Electronics
42 X1 1 Pletronics SM7745HSW- +3.3V Surface-Mount Clock Oscillator,
43 X2 1 Pletronics SM7745HSW-24.576M +3.3V Surface-Mount Clock Oscillator,
44 3 Samtec SNT-100-BK-G-H Shorting Blocks
42 4 3M Bumpon SJ-5003 Self-Adhesive Rubber Feet
Bill
of
Materials
(continued)
Ground Terminal
22.5792M CMOS Output with Active High Enable,
22.5792MHz±50ppm
CMOS Output with Active High Enable,
24.576MHz±50ppm
PCM4202EVM User's GuideSBAU103 – August 2004 23
www.ti.com
Schematic, PCB Layout, and Bill of Materials
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PCM4202EVM User's Guide24 SBAU103 – August 2004
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