Texas Instruments PBGA User Manual
Application Report
SSZA002B–August 2009–Revised August 2015
Plastic Ball Grid Array (PBGA)
SSZA002B – August 2009 – Revised August 2015 Plastic Ball Grid Array (PBGA) 1
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SSZA002B – August 2015
1.0 Introduction:
The Plastic Ball Grid Array or PBGA package, qualified and ramped by Texas Instruments Philippines is a cavityup laminate based substrate package in which the die is attached to the substrate in the norm al die up manner. The
wire- bonded device and the complete assembly is then overmolded and solder balls attached to form the package.
This package provides a cost-effective packaging solution, offering higher density over traditional leadframe
packages. Texas Instruments’ advanced design and simulation capabilities enable package optimizations needed for
maximum electrical and thermal performance. The PBGA package is offered in a range of sizes from 17mm x 17mm
to 35mm x 35mm, in ball pitch of 0.8mm and 1.0mm, to provide a ball count ranging from 208 to 976 balls. PBGA
ckages are available in 2 and 4 layer substrate designs.
pa
Conventional PBGA
Substrate and Structure
Wire Bonds
Conductor Traces
Die
Transfer Molded Overmold
Solder Balls
PBGA Package Configuration
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SSZA002B – August 2015
Features
Dimensions (mm)
Comments
Substrates Thickness (2ML)
0.56 +/- 0.04
Overall thickness ( Core+SR+inner layer+outer layer)
Substrate Thickness (4ML)
0.61 +/- 0.05
Overall thickness ( Core+SR+inner layer+outer layer)
Copper Thickness
0.015
Trace/Space Widths
0.05
minimum
Soldermask Thickness
0.02
Over Copper
Via
0.2
Normal
Solder Pad Cu
0.60~0.65
Solder Mask Opening
0.40~0.50
Typical process flow for PBGA assembly
WAFER
Typical Nominal Dimensions of Selected pBGA Substrate Features
SA
PMC
BALL ATTACH
ENCAPSULATION
IR REFLOW
PACK/PACK LA
SHIP
inc. Bake
DIE
VM/LA
HEATSLUG DISPENSE
BALL INSPECT
Plasma
Clean
FLUX
WIRE
Plasma
Clean
MARK/
SINGULAT
ELECTRICAL
V A
Ω
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SSZA002B – August 2015
17x17 23x23 27x27 31x31 35x35
208ZFE/ZKB 288ZDQ 388ZDS 772ZXM 976ZEY
256ZDH/ZFE/ZKB 324ZDU/ZDW 456ZXF/ZXZ 900ZXM
352ZDU 484ZED
376ZDW/ZDU 520ZXF
388ZDW 580ZEQ
420ZDQ 632ZXZ
432ZDU
0.8
640ZKK
pBGA Package Product Guide
Packag e S ize (mm)
Pitch
(mm)
1
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SSZA002B – August 2015
A typical package outline with 1mm pitch and appropriate tolerances are shown below.
ZXZ (S-PBGA-N456)
2.0 PC Board Design Guidelines:
The PBGA is compliant with JEDEC MS-034. IPC-SM-782 usually dictates the guidelines by which the PC Board
(PCB) pattern should be designed. Working with an Electronics Manufacturing Service provider and/or PCB design
house with experience designing and mounting this package type is recommended. The following guidelines are
offered based on best known practice at the moment based on Texas Instruments evaluations and research.
Package Height .......... ranges depending on body size, ball size and layer count.
Package Size ............. Ranging from 17mm x 17mm to 35mm x35mm
Ball Pitch .................... 0.8 mm and 1.0mm
The PBGA package is primarily composed of copper laminated BT substrate. This adds stiffness to the package
and uniform expansion during board mount and board level temperature cycling. Also, because of cavity up
configuration, the solder balls for this package may be placed in a complete array over the entire bottom side.
Therefore, balls immediately under the die may be used as thermal paths to further enhance the thermal performance.
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SSZA002B – August 2015
All measurements in mm
Ball size, SMO, Pad Size and Apertures are shown in Diameters
PCB Design
Stencil Design
SMO
Pad Size
Thickness
Aperature
SMD
0.400
0.500
NSMD
0.500
0.400
SMD
0.450
0.550
NSMD
0.550
0.450
2.1 PCB Land Pattern and Solder Mask Design
The solder lands on the package side are always Solder Mask Defined (SMD). The land pattern on the PCB
should be designed to correspond with the land pattern on the package. The land on the PCB should be Non-Solder
Mask Defined (NSMD) in order to realize the best board level reliability performance.
SOLDER PAD GEOMETRY
For NSMD pads, TI recommends a clearance (typically 3 mils) between the copper pad and solder mask to avoid
overlap between the solder joint and solder mask due to mask registration tolerances.
The diameter of the solder ball land on the PCB should be the same or up to 20% less than that of the package
substrate solder land. The trace leading into the NSMD ball land on the PCB should not exceed more than 50% of the
land diameter. Again, this is to avoid too much solder wetting this lead-in to the ball thereby creating too much ball
collapse and possibly i mpacting board level reliability.
Optium Land Configurations
Ball Pitch Solder Mask Type
0.8
1
Note: Area Aspect Ratio = Area of Aperture / Area of Aperture Wall
Note: For optial release of solder paste, it is recommended Area Aspect Ratio ≥ 0.66
0.152 0.400 0.66
0.152 0.450 0.74
Area Aspect Ratio
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SSZA002B – August 2015
2.2 Escape routing guidelines
A typical PBGA has four or five rows of solder balls around the periphery of the package. The number of lines routed (N)
between the pads on the PCB is defined by the pad size and trace (width and spacing) fabrication capabilities of the PCB
manufacturer. For NSMD pads, exposure of underlying copper traces is forbidden, so the diameter and tolerance of the
solder mask opening define D. The following relationship is used to define N:
Figure 8. P = Pad Pitch
D = Pad Diameter
L = Line Width
S = Line Space
As shown below, 1 mm ball pitch with 4 rows of solder balls can be routed to 4 layers of PCB which uses a 0.125 mm
line width and 0.125 mm line space.
1 mm Ball Pitch with 0.125 mm Line Width/Spacing
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