Texas Instruments MSP430F2272TDA, MSP430F2252IYFF, MSP430F2232IDA, MSP430F2232IYFF, MSP430F2252IDA User Manual

...

MSP430F22x2 MSP430F22x4

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MIXED SIGNAL MICROCONTROLLER

FEATURES

• Low Supply Voltage Range: 1.8 V to 3.6 V

• Ultra-Low Power Consumption – Active Mode: 270 µA at 1 MHz, 2.2 V – Standby Mode: 0.7 µA – Off Mode (RAM Retention): 0.1 µA

• Ultra-Fast Wake-Up From Standby Mode in Less Than 1 µs

• 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time

• Basic Clock Module Configurations – Internal Frequencies up to 16 MHz With

Four Calibrated Frequencies to ±1% – 512B RAM

– Internal Very-Low-Power Low-Frequency – MSP430F2252

Oscillator – 32-kHz Crystal – High-Frequency (HF) Crystal up to 16 MHz – Resonator – External Digital Clock Source – External Resistor

• 16-Bit Timer_A With Three Capture/Compare Registers

• 16-Bit Timer_B With Three Capture/Compare Registers

• Universal Serial Communication Interface – Enhanced UART Supporting Auto-Baudrate

Detection (LIN) – IrDA Encoder and Decoder – Synchronous SPI – I2C™

• 10-Bit 200-ksps Analog-to-Digital (A/D) Converter With Internal Reference, Sampleand-Hold, Autoscan, and Data Transfer Controller

• Two Configurable Operational Amplifiers (MSP430F22x4 Only)

• Brownout Detector

• Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse

• Bootstrap Loader

• On-Chip Emulation Module

• Family Members Include: – MSP430F2232

– 8KB + 256B Flash Memory

– 16KB + 256B Flash Memory – 512B RAM

– MSP430F2272

– 32KB + 256B Flash Memory – 1KB RAM

– MSP430F2234

– 8KB + 256B Flash Memory – 512B RAM

– MSP430F2254

– 16KB + 256B Flash Memory – 512B RAM

– MSP430F2274

– 32KB + 256B Flash Memory – 1KB RAM

• Available in a 38-Pin Thin Shrink Small-Outline Package (TSSOP) (DA), 40-Pin QFN Package (RHA), and 49-Pin Ball Grid Array Package (YFF) (See Table 1)

• For Complete Module Descriptions, See the MSP430x2xx Family User's Guide (SLAU144)

SLAS504G –JULY 2006–REVISED AUGUST 2012

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2MSP430 is a trademark of Texas Instruments. 3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

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DESCRIPTION

The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.

The MSP430F22x4/MSP430F22x2 series is an ultra-low-power mixed signal microcontroller with two built-in 16bit timers, a universal serial communication interface, 10-bit A/D converter with integrated reference and data transfer controller (DTC), two general-purpose operational amplifiers in the MSP430F22x4 devices, and 32 I/O pins.

Typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system. Stand-alone radio-frequency (RF) sensor front ends are another area of application.

Table 1. Available Options

PACKAGED DEVICES

-40°C to 85°C

-40°C to 105°C

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

PLASTIC 49-PIN BGA PLASTIC 38-PIN TSSOP PLASTIC 40-PIN QFN

(YFF) (DA) (RHA)

MSP430F2232IYFF MSP430F2232IDA MSP430F2232IRHA MSP430F2252IYFF MSP430F2252IDA MSP430F2252IRHA MSP430F2272IYFF MSP430F2272IDA MSP430F2272IRHA MSP430F2234IYFF MSP430F2234IDA MSP430F2234IRHA MSP430F2254IYFF MSP430F2254IDA MSP430F2254IRHA MSP430F2274IYFF MSP430F2274IDA MSP430F2274IRHA

MSP430F2232TDA MSP430F2232TRHA MSP430F2252TDA MSP430F2252TRHA MSP430F2272TDA MSP430F2272TRHA MSP430F2234TDA MSP430F2234TRHA MSP430F2254TDA MSP430F2254TRHA MSP430F2274TDA MSP430F2274TRHA

(1)(2)

Development Tool Support

All MSP430™ microcontrollers include an Embedded Emulation Module (EEM) that allows advanced debugging and programming through easy-to-use development tools. Recommended hardware options include:

• Debugging and Programming Interface – MSP-FET430UIF (USB) – MSP-FET430PIF (Parallel Port)

• Debugging and Programming Interface with Target Board – MSP-FET430U38 (DA package)

• Production Programmer – MSP-GANG430

1TEST/SBWTCK

2DVCC

3P2.5/R

OSC

XOUT/P2.7

XIN/P2.6 6

RST/NMI/SBWTDIO

P2.0/ACLK/A0/OA0I0

P2.1/TAINCLK/SMCLK/A1/OA0O 9

P2.2/TA0/A2/OA0I1

P3.0/UCB0STE/UCA0CLK/A5

P3.1/UCB0SIMO/UCB0SDA 12

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK/UCA0STE 14

P4.0/TB0

P4.1/TB1

P4.2/TB2

P4.3/TB0/A12/OA0O

18 P4.4/TB1/A13/OA1O

38 P1.7/TA2/TDO/TDI

37 P1.6/TA1/TDI

P1.5/TA0/TMS

35 P1.4/SMCLK/TCK

P1.3/TA2

P1.2/TA1

32 P1.1/TA0

P1.0/TACLK/ADC10CLK

P2.4/TA2/A4/VREF+/VeREF+/OA1I0

29 P2.3/TA1/A3/VREF−/VeREF−/OA1I1/OA1O

28 P3.7/A7/OA1I2

27 P3.6/A6/OA0I2

26 P3.5/UCA0RXD/UCA0SOMI

P3.4/UCA0TXD/UCA0SIMO

23AVCC

AVSS

P4.7/TBCLK

P4.6/TBOUTH/A15/OA1I3

DVSS

P4.5/TB2/A14/OA0I3

1TEST/SBWTCK

2DVCC

3P2.5/R

OSC

XOUT/P2.7

XIN/P2.6 6

RST/NMI/SBWTDIO

P2.0/ACLK/A0

P2.1/TAINCLK/SMCLK/A1 9

P2.2/TA0/A2

P3.0/UCB0STE/UCA0CLK/A5

P3.1/UCB0SIMO/UCB0SDA 12

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK/UCA0STE 14

P4.0/TB0

P4.1/TB1

P4.2/TB2

P4.3/TB0/A12

18 P4.4/TB1/A13

38 P1.7/TA2/TDO/TDI

37 P1.6/TA1/TDI

P1.5/TA0/TMS

35 P1.4/SMCLK/TCK

P1.3/TA2

P1.2/TA1

32 P1.1/TA0

P1.0/TACLK/ADC10CLK

P2.4/TA2/A4/VREF+/VeREF+

29 P2.3/TA1/A3/VREF−/VeREF−

28 P3.7/A7

27 P3.6/A6

26 P3.5/UCA0RXD/UCA0SOMI

P3.4/UCA0TXD/UCA0SIMO

23AVCC

AVSS

P4.7/TBCLK

P4.6/TBOUTH/A15

DVSS

P4.5/TB2/A14

MSP430F22x2 MSP430F22x4

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MSP430F22x2 Device Pinout, DA Package

SLAS504G –JULY 2006–REVISED AUGUST 2012

MSP430F22x4 Device Pinout, DA Package

1DVSS

P1.5/TA0/TMS

P1.0/TACLK/ADC10CLK

P1.1/TA0

P1.2/TA1

P1.3/TA2

P1.4/SMCLK/TCK

P2.4/TA2/A4/VREF+/VeREF+

P2.5/R

OSC

DVCC

TEST/SBWTCK

P1.6/TA1/TDI/TCLK

12 14 15 16 17 18 19

3839 37 36 35 34 33 32

XOUT/P2.7

XIN/P2.6

DVSS

RST/NMI/SBWTDIO

P2.0/ACLK/A0

P2.1/TAINCLK/SMCLK/A1

P2.2/TA0/A2

P3.0/UCB0STE/UCA0CLK/A5

P3.1/UCB0SIMO/UCB0SDA

DVCC

P1.7/TA2/TDO/TDI

P2.3/TA1/A3/VREF−/VeREF−

P3.7/A7

P3.6/A6

P3.5/UCA0RXD/UCA0SOMI

P3.4/UCA0TXD/UCA0SIMO

AVCC

AVSS

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK/UCA0STE

P4.0/TB0

P4.1/TB1

P4.2/TB2

P4.3/TB0/A12

P4.4/TB1/A13

P4.5/TB2/A14

P4.6/TBOUTH/A15

P4.7/TBCLK

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

MSP430F22x2 Device Pinout, RHA Package

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1DVSS

P1.5/TA0/TMS

P1.0/TACLK/ADC10CLK

P1.1/TA0

P1.2/TA1

P1.3/TA2

P1.4/SMCLK/TCK

P2.4/TA2/A4/VREF+/VeREF+/OA1I0

P2.5/R

OSC

DVCC

TEST/SBWTCK

P1.6/TA1/TDI/TCLK

12 14 15 16 17 18 19

3839 37 36 35 34 33 32

XOUT/P2.7

XIN/P2.6

DVSS

RST/NMI/SBWTDIO

P2.0/ACLK/A0/OA0I0

P2.1/TAINCLK/SMCLK/A1/OA0O

P2.2/TA0/A2/OA0I1

P3.0/UCB0STE/UCA0CLK/A5

P3.1/UCB0SIMO/UCB0SDA

DVCC

P1.7/TA2/TDO/TDI

P2.3/TA1/A3/VREF−/VeREF−/OA1I1/OA1O

P3.7/A7/OA1I2

P3.6/A6/OA0I2

P3.5/UCA0RXD/UCA0SOMI

P3.4/UCA0TXD/UCA0SIMO

AVCC

AVSS

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK/UCA0STE

P4.0/TB0

P4.1/TB1

P4.2/TB2

P4.3/TB0/A12/OA0O

P4.4/TB1/A13/OA1O

P4.5/TB2/A14/OA0I3

P4.6/TBOUTH/A15/OA1I3

P4.7/TBCLK

MSP430F22x2 MSP430F22x4

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MSP430F22x4 Device Pinout, RHA Package

SLAS504G –JULY 2006–REVISED AUGUST 2012

A1 A2 A4A3 A5 A6 A7

TOP VIEW

B1 B2 B4B3 B5 B6 B7

C1 C2 C4C3 C5 C6 C7

D1 D2 D4D3 D5 D6 D7

E1 E2 E4E3 E5 E6 E7

F1 F2 F4F3 F5 F6 F7

G1 G2 G4G3 G5 G6 G7

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

MSP430F22x4, MSP430F22x2 Device Pinout, YFF Package

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Package Dimensions

The package dimensions for this YFF package are shown in Table 2. See the package drawing at the end of this data sheet for more details.

Table 2. YFF Package Dimensions

PACKAGED DEVICES D E

MSP430F22x2 MSP430F22x4

3.33 ± 0.03 mm 3.49 ± 0.03 mm

Basic Clock

System+

RAM

1kB 512B 512B

Brownout

Protection

RST/NMI

VCC VSS

MCLK

SMCLK

Watchdog

WDT+

15/16−Bit

Timer_A3

3 CC

Registers

16MHz

CPU

incl. 16

Registers

Emulation

(2BP)

XOUT

JTAG

Interface

Flash

32kB 16kB

8kB

ACLK

XIN

MDB

MAB

Spy−Bi Wire

Timer_B3

3 CC

Registers,

Shadow

Reg

USCI_A0:

UART/LIN,

IrDA, SPI

USCI_B0:

SPI, I2C

OA0, OA1

2 Op Amps

ADC10

10−Bit

12 Channels, Autoscan,

DTC

Ports P1/P2

2x8 I/O

Interrupt

capability,

pull−up/down

resistors

Ports P3/P4

2x8 I/O

pull−up/down

resistors

P1.x/P2.x

2x8

P3.x/P4.x

2x8

Basic Clock

System+

RAM

1kB 512B 512B

Brownout

Protection

RST/NMI

VCC VSS

MCLK

SMCLK

Watchdog

WDT+

15/16−Bit

Timer_A3

3 CC

Registers

16MHz

CPU

incl. 16

Registers

Emulation

(2BP)

XOUT

JTAG

Interface

Flash

32kB 16kB

8kB

ACLK

XIN

MDB

MAB

Spy−Bi Wire

Timer_B3

3 CC

Registers,

Shadow

Reg

USCI_A0:

UART/LIN,

IrDA, SPI

USCI_B0:

SPI, I2C

ADC10

10−Bit

12 Channels, Autoscan,

DTC

Ports P1/P2

2x8 I/O

Interrupt

capability,

pull−up/down

resistors

Ports P3/P4

2x8 I/O

pull−up/down

resistors

P1.x/P2.x

2x8

P3.x/P4.x

2x8

MSP430F22x2 MSP430F22x4

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MSP430F22x2 Functional Block Diagram

SLAS504G –JULY 2006–REVISED AUGUST 2012

MSP430F22x4 Functional Block Diagram

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Table 3. Terminal Functions, MSP430F22x2

TERMINAL

NAME

P1.0/TACLK/ADC10CLK F2 31 29 I/O Timer_A, clock signal TACLK input

P1.1/TA0 G2 32 30 I/O Timer_A, capture: CCI0A input, compare: OUT0 output

P1.2/TA1 E2 33 31 I/O

P1.3/TA2 G1 34 32 I/O

P1.4/SMCLK/TCK F1 35 33 I/O SMCLK signal output

P1.5/TA0/TMS E1 36 34 I/O Timer_A, compare: OUT0 output

P1.6/TA1/TDI/TCLK E3 37 35 I/O Timer_A, compare: OUT1 output

REF-

REF+

(1)

/ V

eREF-

eREF+

P1.7/TA2/TDO/TDI

P2.0/ACLK/A0 A4 8 6 I/O ACLK output

P2.1/TAINCLK/SMCLK/A1 B4 9 7 I/O

P2.2/TA0/A2 A5 10 8 I/O Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output

P2.3/TA1/A3/V

P2.4/TA2/A4/V

P2.5/R

OSC

XIN/P2.6 A2 6 3 I/O

YFF DA RHA

NO. I/O DESCRIPTION

General-purpose digital I/O pin

ADC10, conversion clock General-purpose digital I/O pin

BSL transmit General-purpose digital I/O pin Timer_A, capture: CCI1A input, compare: OUT1 output General-purpose digital I/O pin Timer_A, capture: CCI2A input, compare: OUT2 output General-purpose digital I/O pin

Test Clock input for device programming and test General-purpose digital I/O pin

Test Mode Select input for device programming and test General-purpose digital I/O pin

Test Data Input or Test Clock Input for programming and test General-purpose digital I/O pin

D2 38 36 I/O Timer_A, compare: OUT2 output

Test Data Output or Test Data Input for programming and test General-purpose digital I/O pin

ADC10, analog input A0 General-purpose digital I/O pin Timer_A, clock signal at INCLK SMCLK signal output ADC10, analog input A1 General-purpose digital I/O pin

ADC10, analog input A2 General-purpose digital I/O pin

F3 29 27 I/O

G3 30 28 I/O

C2 3 40 I/O

Timer_A, capture CCI1B input, compare: OUT1 output ADC10, analog input A3 Negative reference voltage input General-purpose digital I/O pin Timer_A, compare: OUT2 output ADC10, analog input A4 Positive reference voltage output or input General-purpose digital I/O pin Input for external DCO resistor to define DCO frequency Input terminal of crystal oscillator General-purpose digital I/O pin

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MSP430F22x2 MSP430F22x4

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SLAS504G –JULY 2006–REVISED AUGUST 2012

Table 3. Terminal Functions, MSP430F22x2 (continued)

TERMINAL

NAME

XOUT/P2.7 A1 5 2 I/O

P3.0/UCB0STE/UCA0CLK/ A5

P3.1/UCB0SIMO/ UCB0SDA

P3.2/UCB0SOMI/UCB0SCL A7 13 11 I/O USCI_B0 SPI mode: slave out/master in

P3.3/UCB0CLK/UCA0STE B6 14 12 I/O USCI_B0 clock input/output

P3.4/UCA0TXD/ UCA0SIMO

P3.5/UCA0RXD/ UCA0SOMI

P3.6/A6 F4 27 25 I/O

P3.7/A7 G4 28 26 I/O

P4.0/TB0 D6 17 15 I/O

P4.1/TB1 D7 18 16 I/O

P4.2/TB2 E6 19 17 I/O

P4.3/TB0/A12 E7 20 18 I/O Timer_B, capture: CCI0B input, compare: OUT0 output

P4.4/TB1/A13 F7 21 19 I/O Timer_B, capture: CCI1B input, compare: OUT1 output

P4.5/TB2/A14 F6 22 20 I/O Timer_B, compare: OUT2 output

P4.6/TBOUTH/A15 G7 23 21 I/O Timer_B, switch all TB0 to TB3 outputs to high impedance

YFF DA RHA

NO. I/O DESCRIPTION

Output terminal of crystal oscillator General-purpose digital I/O pin General-purpose digital I/O pin

B5 11 9 I/O

A6 12 10 I/O USCI_B0 SPI mode: slave in/master out

G6 25 23 I/O USCI_A0 UART mode: transmit data output

G5 26 24 I/O USCI_A0 UART mode: receive data input

USCI_B0 slave transmit enable USCI_A0 clock input/output ADC10, analog input A5 General-purpose digital I/O pin

USCI_B0 I2C mode: SDA I2C data General-purpose digital I/O pin

USCI_B0 I2C mode: SCL I2C clock General-purpose digital I/O pin

USCI_A0 slave transmit enable General-purpose digital I/O pin

USCI_A0 SPI mode: slave in/master out General-purpose digital I/O pin

USCI_A0 SPI mode: slave out/master in General-purpose digital I/O pin ADC10 analog input A6 General-purpose digital I/O pin ADC10 analog input A7 General-purpose digital I/O pin Timer_B, capture: CCI0A input, compare: OUT0 output General-purpose digital I/O pin Timer_B, capture: CCI1A input, compare: OUT1 output General-purpose digital I/O pin Timer_B, capture: CCI2A input, compare: OUT2 output General-purpose digital I/O pin

ADC10 analog input A12 General-purpose digital I/O pin

ADC10 analog input A13 General-purpose digital I/O pin

ADC10 analog input A14 General-purpose digital I/O pin

ADC10 analog input A15

(2)

(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to

this pad after reset.

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Table 3. Terminal Functions, MSP430F22x2 (continued)

TERMINAL

NAME

P4.7/TBCLK F5 24 22 I/O

RST/NMI/SBWTDIO B3 7 5 I

TEST/SBWTCK D1 1 37 I

QFN Pad NA NA Pad NA QFN package pad; connection to DVSSrecommended.

YFF DA RHA

E4, E5

NO. I/O DESCRIPTION

General-purpose digital I/O pin Timer_B, clock signal TBCLK input Reset or nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test Selects test mode for JTAG pins on Port 1. The device protection fuse is

connected to TEST. Spy-Bi-Wire test clock input during programming and test

C1, D3, D4,

C6, C7, 16 14 Analog supply voltage

A3, B1, B2, 4 1, 4 Digital ground reference C3,

B7,

2 38, 39 Digital supply voltage

15 13 Analog ground reference

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MSP430F22x2 MSP430F22x4

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SLAS504G –JULY 2006–REVISED AUGUST 2012

Table 4. Terminal Functions, MSP430F22x4

TERMINAL

NAME

P1.0/TACLK/ADC10CLK F2 31 29 I/O Timer_A, clock signal TACLK input

P1.1/TA0 G2 32 30 I/O Timer_A, capture: CCI0A input, compare: OUT0 output

P1.2/TA1 E2 33 31 I/O

P1.3/TA2 G1 34 32 I/O

P1.4/SMCLK/TCK F1 35 33 I/O SMCLK signal output

P1.5/TA0/TMS E1 36 34 I/O Timer_A, compare: OUT0 output

P1.6/TA1/TDI/TCLK E3 37 35 I/O Timer_A, compare: OUT1 output

P1.7/TA2/TDO/TDI

P2.0/ACLK/A0/OA0I0 A4 8 6 I/O

P2.1/TAINCLK/SMCLK/ A1/OA0O

P2.2/TA0/A2/OA0I1 A5 10 8 I/O

P2.3/TA1/A3/ V OA1I1/OA1O

(1)

REF-/VeREF-

YFF DA RHA

NO. I/O DESCRIPTION

General-purpose digital I/O pin

ADC10, conversion clock General-purpose digital I/O pin

Test Clock input for device programming and test General-purpose digital I/O pin

Test Mode Select input for device programming and test General-purpose digital I/O pin

Test Data Input or Test Clock Input for programming and test General-purpose digital I/O pin

D2 38 36 I/O Timer_A, compare: OUT2 output

Test Data Output or Test Data Input for programming and test General-purpose digital I/O pin ACLK output ADC10, analog input A0 OA0, analog input IO General-purpose digital I/O pin Timer_A, clock signal at INCLK

B4 9 7 I/O SMCLK signal output

ADC10, analog input A1 OA0, analog output General-purpose digital I/O pin Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output ADC10, analog input A2 OA0, analog input I1 General-purpose digital I/O pin Timer_A, capture CCI1B input, compare: OUT1 output

F3 29 27 I/O

ADC10, analog input A3 Negative reference voltage input OA1, analog input I1 OA1, analog output

(1) TDO or TDI is selected via JTAG instruction.

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Table 4. Terminal Functions, MSP430F22x4 (continued)

TERMINAL

NAME

P2.4/TA2/A4/ V

REF+/VeREF+

P2.5/R

XIN/P2.6 A2 6 3 I/O

XOUT/P2.7 A1 5 2 I/O

P3.0/UCB0STE/UCA0CLK/ A5

P3.1/UCB0SIMO/ UCB0SDA

P3.2/UCB0SOMI/UCB0SCL A7 13 11 I/O USCI_B0 SPI mode: slave out/master in

P3.3/UCB0CLK/UCA0STE B6 14 12 I/O USCI_B0 clock input/output

P3.4/UCA0TXD/ UCA0SIMO

P3.5/UCA0RXD/ UCA0SOMI

P3.6/A6/OA0I2 F4 27 25 I/O ADC10 analog input A6

P3.7/A7/OA1I2 G4 28 26 I/O ADC10 analog input A7

P4.0/TB0 D6 17 15 I/O

P4.1/TB1 D7 18 16 I/O

P4.2/TB2 E6 19 17 I/O

/OA1I0

OSC

YFF DA RHA

NO. I/O DESCRIPTION

General-purpose digital I/O pin Timer_A, compare: OUT2 output

G3 30 28 I/O ADC10, analog input A4

Positive reference voltage output or input OA1, analog input I/O

C2 3 40 I/O

B5 11 9 I/O

A6 12 10 I/O USCI_B0 SPI mode: slave in/master out

G6 25 23 I/O USCI_A0 UART mode: transmit data output

G5 26 24 I/O USCI_A0 UART mode: receive data input

General-purpose digital I/O pin Input for external DCO resistor to define DCO frequency Input terminal of crystal oscillator General-purpose digital I/O pin Output terminal of crystal oscillator General-purpose digital I/O pin General-purpose digital I/O pin USCI_B0 slave transmit enable USCI_A0 clock input/output ADC10, analog input A5 General-purpose digital I/O pin

USCI_B0 I2C mode: SDA I2C data General-purpose digital I/O pin

USCI_B0 I2C mode: SCL I2C clock General-purpose digital I/O pin

USCI_A0 slave transmit enable General-purpose digital I/O pin

USCI_A0 SPI mode: slave in/master out General-purpose digital I/O pin

USCI_A0 SPI mode: slave out/master in General-purpose digital I/O pin

OA0 analog input I2 General-purpose digital I/O pin

OA1 analog input I2 General-purpose digital I/O pin Timer_B, capture: CCI0A input, compare: OUT0 output General-purpose digital I/O pin Timer_B, capture: CCI1A input, compare: OUT1 output General-purpose digital I/O pin Timer_B, capture: CCI2A input, compare: OUT2 output

(2)

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(2) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to

this pad after reset.

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Table 4. Terminal Functions, MSP430F22x4 (continued)

TERMINAL

NAME

P4.3/TB0/A12/OA0O E7 20 18 I/O

P4.4/TB1/A13/OA1O F7 21 19 I/O

P4.5/TB2/A14/OA0I3 F6 22 20 I/O

P4.6/TBOUTH/A15/OA1I3 G7 23 21 I/O

P4.7/TBCLK F5 24 22 I/O

RST/NMI/SBWTDIO B3 7 5 I

TEST/SBWTCK D1 1 37 I

QFN Pad NA NA Pad NA QFN package pad; connection to DVSSrecommended.

YFF DA RHA

E4, E5

NO. I/O DESCRIPTION

General-purpose digital I/O pin Timer_B, capture: CCI0B input, compare: OUT0 output ADC10 analog input A12 OA0 analog output General-purpose digital I/O pin Timer_B, capture: CCI1B input, compare: OUT1 output ADC10 analog input A13 OA1 analog output General-purpose digital I/O pin Timer_B, compare: OUT2 output ADC10 analog input A14 OA0 analog input I3 General-purpose digital I/O pin Timer_B, switch all TB0 to TB3 outputs to high impedance ADC10 analog input A15 OA1 analog input I3 General-purpose digital I/O pin Timer_B, clock signal TBCLK input Reset or nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test Selects test mode for JTAG pins on Port 1. The device protection fuse is

connected to TEST. Spy-Bi-Wire test clock input during programming and test

C1, D3, D4,

C6, C7, 16 14 Analog supply voltage

A3, B1, B2, 4 1, 4 Digital ground reference C3,

B7,

2 38, 39 Digital supply voltage

15 13 Analog ground reference

General-PurposeRegister

ProgramCounter

StackPointer

StatusRegister

ConstantGenerator

General-PurposeRegister

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R12

R13

General-PurposeRegister

R10

R11

General-PurposeRegister

R14

R15

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SHORT-FORM DESCRIPTION

CPU

The MSP430™ CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses and can be handled with all instructions.

Instruction Set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data.

Table 5 shows examples of the three types of

instruction formats; Table 6 shows the address modes.

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Dual operands, source-destination ADD R4,R5 R4 + R5 → R5 Single operands, destination only CALL R8 PC → (TOS), R8 → PC Relative jump, unconditional/conditional JNE Jump-on-equal bit = 0

Register ✓ ✓ MOV Rs,Rd MOV R10,R11 R10 → R11 Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) → M(6+R6) Symbolic (PC relative) ✓ ✓ MOV EDE,TONI M(EDE) → M(TONI) Absolute ✓ ✓ MOV &MEM,&TCDAT M(MEM) → M(TCDAT) Indirect ✓ MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) → M(Tab+R6)

Indirect autoincrement ✓ MOV @Rn+,Rm MOV @R10+,R11 Immediate ✓ MOV #X,TONI MOV #45,TONI #45 → M(TONI)

(1) S = source (2) D = destination

INSTRUCTION FORMAT EXAMPLE OPERATION

ADDRESS MODE S

Table 5. Instruction Word Formats

Table 6. Address Mode Descriptions

(1)

(2)

SYNTAX EXAMPLE OPERATION

M(R10) → R11

R10 + 2 → R10

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Operating Modes

The MSP430 microcontrollers have one active mode and five software-selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

• Active mode (AM) – All clocks are active.

• Low-power mode 0 (LPM0) – CPU is disabled. – ACLK and SMCLK remain active. MCLK is disabled.

• Low-power mode 1 (LPM1) – CPU is disabled ACLK and SMCLK remain active. MCLK is disabled. – DCO dc-generator is disabled if DCO not used in active mode.

• Low-power mode 2 (LPM2) – CPU is disabled. – MCLK and SMCLK are disabled. – DCO dc-generator remains enabled. – ACLK remains active.

• Low-power mode 3 (LPM3) – CPU is disabled. – MCLK and SMCLK are disabled. – DCO dc-generator is disabled. – ACLK remains active.

• Low-power mode 4 (LPM4) – CPU is disabled. – ACLK is disabled. – MCLK and SMCLK are disabled. – DCO dc-generator is disabled. – Crystal oscillator is stopped.

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Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range of 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, if flash is not programmed), the CPU goes into LPM4 immediately after power up.

Table 7. Interrupt Vector Addresses

INTERRUPT SOURCE INTERRUPT FLAG WORD ADDRESS PRIORITY

Power-up

External reset

Watchdog Reset 0FFFEh 31, highest Flash key violation PC out-of-range

(1)

PORIFG

RSTIFG

WDTIFG

(2)

KEYV

NMI NMIIFG (non)-maskable,

Oscillator fault OFIFG (non)-maskable, 0FFFCh 30

Flash memory access violation ACCVIFG

Timer_B3 TBCCR0 CCIFG Timer_B3 maskable 0FFF8h 28

TBCCR1 and TBCCR2 CCIFGs,

TBIFG

(2)(3)

(4)

(2)(4)

Watchdog Timer WDTIFG maskable 0FFF4h 26

Timer_A3 TACCR0 CCIFG (see Note 3) maskable 0FFF2h 25

TACCR1 CCIFG

Timer_A3 TACCR2 CCIFG maskable 0FFF0h 24

USCI_A0/USCI_B0 Receive UCA0RXIFG, UCB0RXIFG USCI_A0/USCI_B0 Transmit UCA0TXIFG, UCB0TXIFG

ADC10 ADC10IFG

I/O Port P2

(eight flags)

I/O Port P1

(eight flags)

(5) (6)

P2IFG.0 to P2IFG.7

P1IFG.0 to P1IFG.7

TAIFG

(2)(4)

(2)

(4)

(2)(4)

(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from

within unused address range. (2) Multiple source flags (3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

Nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event. (4) Interrupt flags are located in the module. (5) This location is used as bootstrap loader security key (BSLSKEY).

A 0AA55h at this location disables the BSL completely.

A zero (0h) disables the erasure of the flash if an invalid password is supplied. (6) The interrupt vectors at addresses 0FFDCh to 0FFC0h are not used in this device and can be used for regular program code if

necessary.

SYSTEM

INTERRUPT

(non)-maskable

maskable 0FFFAh 29

0FFF6h 27

maskable 0FFEEh 23 maskable 0FFECh 22 maskable 0FFEAh 21

0FFE8h 20

maskable 0FFE6h 19

maskable 0FFE4h 18

0FFE2h 17 0FFE0h 16

0FFDEh 15

0FFDCh to 0FFC0h 14 to 0, lowest

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Special Function Registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement.

Legend

rw Bit can be read and written. rw-0, 1 Bit can be read and written. It is Reset or Set by PUC. rw-(0), (1) Bit can be read and written. It is Reset or Set by POR.

SFR bit is not present in device.

Table 8. Interrupt Enable 1

Address 7 6 5 4 3 2 1 0

00h ACCVIE NMIIE OFIE WDTIE

rw-0 rw-0 rw-0 rw-0

WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog timer is configured in interval

OFIE Oscillator fault interrupt enable NMIIE (Non)maskable interrupt enable ACCVIE Flash access violation interrupt enable

Address 7 6 5 4 3 2 1 0

01h UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE

timer mode.

Table 9. Interrupt Enable 2

rw-0 rw-0 rw-0 rw-0

UCA0RXIE USCI_A0 receive-interrupt enable UCA0TXIE USCI_A0 transmit-interrupt enable UCB0RXIE USCI_B0 receive-interrupt enable UCB0TXIE USCI_B0 transmit-interrupt enable

Table 10. Interrupt Flag Register 1

Address 7 6 5 4 3 2 1 0

02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG

rw-0 rw-(0) rw-(1) rw-1 rw-(0)

WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.

Reset on VCCpower-up or a reset condition at RST/NMI pin in reset mode. OFIFG Flag set on oscillator fault RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCCpower up. PORIFG Power-on reset interrupt flag. Set on VCCpower up. NMIIFG Set via RST/NMI pin

Table 11. Interrupt Flag Register 2

Address 7 6 5 4 3 2 1 0

03h UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG

rw-1 rw-0 rw-1 rw-0

UCA0RXIFG USCI_A0 receive-interrupt flag UCA0TXIFG USCI_A0 transmit-interrupt flag UCB0RXIFG USCI_B0 receive-interrupt flag UCB0TXIFG USCI_B0 transmit-interrupt flag

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Memory Organization

Table 12. Memory Organization

MSP430F223x MSP430F225x MSP430F227x

Memory Size 8KB Flash 16KB Flash 32KB Flash Main: interrupt vector Flash 0FFFFh-0FFC0h 0FFFFh-0FFC0h 0FFFFh-0FFC0h Main: code memory Flash 0FFFFh-0E000h 0FFFFh-0C000h 0FFFFh-08000h

Information memory

Boot memory

RAM Size

Peripherals 8-bit 0FFh-010h 0FFh-010h 0FFh-010h

Size 256 Byte 256 Byte 256 Byte

Flash 010FFh-01000h 010FFh-01000h 010FFh-01000h

Size 1KB 1KB 1KB

ROM 0FFFh-0C00h 0FFFh-0C00h 0FFFh-0C00h

512 Byte 512 Byte 1KB

03FFh-0200h 03FFh-0200h 05FFh-0200h

16-bit 01FFh-0100h 01FFh-0100h 01FFh-0100h

8-bit SFR 0Fh-00h 0Fh-00h 0Fh-00h

Bootstrap Loader (BSL)

The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User’s Guide (SLAU319).

Table 13. BSL Function Pins

BSL FUNCTION DA PACKAGE PINS RHA PACKAGE PINS YFF PACKAGE PINS

Data transmit 32 - P1.1 30 - P1.1 G3 - P1.1

Data receive 10 - P2.2 8 - P2.2 A5 - P2.2

Flash Memory

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

• Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size.

• Segments 0 to n may be erased in one step, or each segment may be individually erased.

• Segments A to D can be erased individually, or as a group with segments 0 to n. Segments A to D are also called information memory.

• Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is required.

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Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).

Oscillator and System Clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator, an internal digitally-controlled oscillator (DCO), and a high-frequency crystal oscillator. The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic clock module provides the following clock signals:

• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high-frequency crystal, or the internal verylow-power LF oscillator.

• Main clock (MCLK), the system clock used by the CPU.

• Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

Table 14. DCO Calibration Data

(Provided From Factory in Flash Information Memory Segment A)

DCO FREQUENCY CALIBRATION REGISTER SIZE ADDRESS

1 MHz

8 MHz

12 MHz

16 MHz

CALBC1_1MHZ byte 010FFh

CALDCO_1MHZ byte 010FEh

CALBC1_8MHZ byte 010FDh

CALDCO_8MHZ byte 010FCh

CALBC1_12MHZ byte 010FBh

CALDCO_12MHZ byte 010FAh

CALBC1_16MHZ byte 010F9h

CALDCO_16MHZ byte 010F8h

Brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off.

Digital I/O

There are four 8-bit I/O ports implemented—ports P1, P2, P3, and P4:

• All individual I/O bits are independently programmable.

• Any combination of input, output, and interrupt condition is possible.

• Edge-selectable interrupt input capability for all eight bits of port P1 and P2.

• Read/write access to port-control registers is supported by all instructions.

• Each I/O has an individually programmable pullup/pulldown resistor.

Because there are only three I/O pins implemented from port P2, bits [5:1] of all port P2 registers read as 0, and write data is ignored.

Watchdog Timer (WDT+)

The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals.

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Timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 15. Timer_A3 Signal Connections

INPUT PIN NUMBER DEVICE MODULE MODULE OUTPUT PIN NUMBER

DA RHA YFF DA RHA YFF

31 - P1.0 29 - P1.0 F2 - P1.0 TACLK TACLK Timer NA

9 - P2.1 7 - P2.1 B4 - P2.1 TAINCLK INCLK 32 - P1.1 30 - P1.1 G2 - P1.1 TA0 CCI0A CCR0 TA0 32 - P1.1 30 - P1.1 G2 - P1.1 10 - P2.2 8 - P2.2 A5 - P2.2 TA0 CCI0B 10 - P2.2 8 - P2.2 A5 - P2.2

33 - P1.2 31 - P1.2 E2 - P1.2 TA1 CCI1A CCR1 TA1 33 - P1.2 31 - P1.2 E2 - P1.2 29 - P2.3 27 - P2.3 F3 - P2.3 TA1 CCI1B 29 - P2.3 27 - P2.3 F3 - P2.3

34 - P1.3 32 - P1.3 G1 - P1.3 TA2 CCI2A CCR2 TA2 34 - P1.3 32 - P1.3 G1 - P1.3

INPUT INPUT OUTPUT

SIGNAL NAME SIGNAL

ACLK ACLK

SMCLK SMCLK

ACLK

(internal)

GND 36 - P1.5 34 - P1.5 E1 - P1.5

GND 37 - P1.6 35 - P1.6 E3 - P1.6

CCI2B 30 - P2.4 28 - P2.4 G3 - P2.4

GND 38 - P1.7 36 - P1.7 D2 - P1.7

MODULE

BLOCK

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Timer_B3

Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

Table 16. Timer_B3 Signal Connections

INPUT PIN NUMBER DEVICE MODULE MODULE OUTPUT PIN NUMBER

DA RHA YFF DA RHA YFF

24 - P4.7 22 - P4.7 F5 - P4.7 TBCLK TBCLK Timer NA

24 - P4.7 22 - P4.7 F5 - P4.7 TBCLK INCLK 17 - P4.0 15 - P4.0 D6 - P4.0 TB0 CCI0A CCR0 TB0 17 - P4.0 15 - P4.0 D6 - P4.0 20 - P4.3 18 - P4.3 E7 - P4.3 TB0 CCI0B 20 - P4.3 18 - P4.3 E7 - P4.3

18 - P4.1 16 - P4.1 D7 - P4.1 TB1 CCI1A CCR1 TB1 18 - P4.1 16 - P4.1 D7 - P4.1 21 - P4.4 19 - P4.4 F7 - P4.4 TB1 CCI1B 21 - P4.4 19 - P4.4 F7 - P4.4

19 - P4.2 17 - P4.2 E6 - P4.2 TB2 CCI2A CCR2 TB2 19 - P4.2 17 - P4.2 E6 - P4.2

INPUT INPUT OUTPUT

SIGNAL NAME SIGNAL

ACLK ACLK

SMCLK SMCLK

ACLK

(internal)

GND

CCI2B 22 - P4.5 20 - P4.5 F6 - P4.5

GND

MODULE

BLOCK

Universal Serial Communications Interface (USCI)

The USCI module is used for serial data communication. The USCI module supports synchronous communication protocols like SPI (3 or 4 pin), I2C and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.

USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA. USCI_B0 provides support for SPI (3 or 4 pin) and I2C.

ADC10

The ADC10 module supports fast, 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator and data transfer controller, or DTC, for automatic conversion result handling allowing ADC samples to be converted and stored without any CPU intervention.

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Operational Amplifier (OA) (MSP430F22x4 only)

The MSP430F22x4 has two configurable low-current general-purpose operational amplifiers. Each OA input and output terminal is software-selectable and offer a flexible choice of connections for various applications. The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.

Table 17. OA0 Signal Connections

ANALOG INPUT PIN NUMBER

DA RHA YFF

8 - A0 6 - A0 B4 - A0 OA0I0 OAxI0 10 - A2 8 - A2 B5 - A2 OA0I1 OA0I1 10 - A2 8 - A2 B5 - A2 OA0I1 OAxI1 27 - A6 25 - A6 F4 - A6 OA0I2 OAxIA

22 - A14 20 - A14 F6 - A14 OA0I3 OAxIB

Table 18. OA1 Signal Connections

ANALOG INPUT PIN NUMBER

DA RHA YFF

30 - A4 28 - A4 G3 - A4 OA1I0 OAxI0 10 - A2 8 - A2 B5 - A2 OA0I1 OA0I1 29 - A3 27 - A3 F3 - A3 OA1I1 OAxI1 28 - A7 26 - A7 G4 - A7 OA1I2 OAxIA

23 - A15 21 - A15 G7 - A15 OA1I3 OAxIB

DEVICE INPUT SIGNAL MODULE INPUT NAME

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Peripheral File Map

Table 19. Peripherals With Word Access

MODULE REGISTER NAME SHORT NAME ADDRESS

ADC10 ADC data transfer start address ADC10SA 1BCh

ADC memory ADC10MEM 1B4h ADC control register 1 ADC10CTL1 1B2h ADC control register 0 ADC10CTL0 1B0h ADC analog enable 0 ADC10AE0 04Ah ADC analog enable 1 ADC10AE1 04Bh ADC data transfer control register 1 ADC10DTC1 049h ADC data transfer control register 0 ADC10DTC0 048h

Timer_B Capture/compare register TBCCR2 0196h

Capture/compare register TBCCR1 0194h Capture/compare register TBCCR0 0192h Timer_B register TBR 0190h Capture/compare control TBCCTL2 0186h Capture/compare control TBCCTL1 0184h Capture/compare control TBCCTL0 0182h Timer_B control TBCTL 0180h Timer_B interrupt vector TBIV 011Eh

Timer_A Capture/compare register TACCR2 0176h

Capture/compare register TACCR1 0174h Capture/compare register TACCR0 0172h Timer_A register TAR 0170h Capture/compare control TACCTL2 0166h Capture/compare control TACCTL1 0164h Capture/compare control TACCTL0 0162h Timer_A control TACTL 0160h Timer_A interrupt vector TAIV 012Eh

Flash Memory Flash control 3 FCTL3 012Ch

Flash control 2 FCTL2 012Ah Flash control 1 FCTL1 0128h

Watchdog Timer+ Watchdog/timer control WDTCTL 0120h

OFFSET

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Table 20. Peripherals With Byte Access

MODULE REGISTER NAME SHORT NAME ADDRESS

OA1 (MSP430F22x4 only) Operational Amplifier 1 control register 1 OA1CTL1 0C3h

Operational Amplifier 1 control register 1 OA1CTL0 0C2h

OA0 (MSP430F22x4 only) Operational Amplifier 0 control register 1 OA0CTL1 0C1h

Operational Amplifier 0 control register 1 OA0CTL0 0C0h

USCI_B0 USCI_B0 transmit buffer UCB0TXBUF 06Fh

USCI_B0 receive buffer UCB0RXBUF 06Eh USCI_B0 status UCB0STAT 06Dh USCI_B0 bit rate control 1 UCB0BR1 06Bh USCI_B0 bit rate control 0 UCB0BR0 06Ah USCI_B0 control 1 UCB0CTL1 069h USCI_B0 control 0 UCB0CTL0 068h USCI_B0 I2C slave address UCB0SA 011Ah USCI_B0 I2C own address UCB0OA 0118h

USCI_A0 USCI_A0 transmit buffer UCA0TXBUF 067h

USCI_A0 receive buffer UCA0RXBUF 066h USCI_A0 status UCA0STAT 065h USCI_A0 modulation control UCA0MCTL 064h USCI_A0 baud rate control 1 UCA0BR1 063h USCI_A0 baud rate control 0 UCA0BR0 062h USCI_A0 control 1 UCA0CTL1 061h USCI_A0 control 0 UCA0CTL0 060h USCI_A0 IrDA receive control UCA0IRRCTL 05Fh USCI_A0 IrDA transmit control UCA0IRTCTL 05Eh USCI_A0 auto baud rate control UCA0ABCTL 05Dh

Basic Clock System+ Basic clock system control 3 BCSCTL3 053h

Basic clock system control 2 BCSCTL2 058h Basic clock system control 1 BCSCTL1 057h DCO clock frequency control DCOCTL 056h

Port P4 Port P4 resistor enable P4REN 011h

Port P4 selection P4SEL 01Fh Port P4 direction P4DIR 01Eh Port P4 output P4OUT 01Dh Port P4 input P4IN 01Ch

Port P3 Port P3 resistor enable P3REN 010h

Port P3 selection P3SEL 01Bh Port P3 direction P3DIR 01Ah Port P3 output P3OUT 019h Port P3 input P3IN 018h

Port P2 Port P2 resistor enable P2REN 02Fh

Port P2 selection P2SEL 02Eh Port P2 interrupt enable P2IE 02Dh Port P2 interrupt edge select P2IES 02Ch Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h

OFFSET

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Table 20. Peripherals With Byte Access (continued)

MODULE REGISTER NAME SHORT NAME ADDRESS

Port P1 Port P1 resistor enable P1REN 027h

Port P1 selection P1SEL 026h Port P1 interrupt enable P1IE 025h Port P1 interrupt edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h

Special Function SFR interrupt flag 2 IFG2 003h

SFR interrupt flag 1 IFG1 002h SFR interrupt enable 2 IE2 001h SFR interrupt enable 1 IE1 000h

OFFSET

4.15 MHz

12 MHz

16 MHz

1.8 V 2.2 V 2.7 V 3.3 V 3.6 V

Supply Voltage −V

System Frequency −MHz

Supply voltage range, during flash memory programming

Supply voltage range, during program execution

Legend:

7.5 MHz

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Absolute Maximum Ratings

Voltage applied at VCCto V Voltage applied to any pin

(2)

(1)

-0.3 V to 4.1 V

-0.3 V to VCC+ 0.3 V

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Diode current at any device terminal ±2 mA

Storage temperature, T

stg

(3)

Unprogrammed device -55°C to 150°C Programmed device -55°C to 150°C

(1) Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is

applied to the TEST pin when blowing the JTAG fuse.

(3) Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak

reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

Recommended Operating Conditions

(1)(2)

MIN NOM MAX UNIT

SYSTEM

During program

Supply voltage AVCC= DVCC= V

execution During program/erase

flash memory

Supply voltage AVSS= DVSS= V

Operating free-air temperature °C

Processor frequency (maximum MCLK frequency) (see Figure 1)

VCC= 1.8 V, Duty cycle = 50% ±10% dc 4.15

(1)(2)

VCC= 2.7 V, Duty cycle = 50% ±10% dc 12 MHz VCC≥ 3.3 V, Duty cycle = 50% ±10% dc 16

I version -40 85 T version -40 105

1.8 3.6 V

2.2 3.6 V 0 V

(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the

specified maximum frequency.

(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.

NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V

of 2.2 V.

Figure 1. Operating Area

MSP430F22x2 MSP430F22x4

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Active Mode Supply Current (into DVCC+ AVCC) Excluding External Current

SLAS504G –JULY 2006–REVISED AUGUST 2012

(1)(2)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

AM,1MHz

AM,4kHz

AM,100kHz

PARAMETER TEST CONDITIONS T

= f

Active mode (AM) current (1 MHz)

DCO

ACLK

Program executes in flash,

= f

MCLK

= 32768 Hz,

BCSCTL1 = CALBC1_1MHZ, µA DCOCTL = CALDCO_1MHZ,

= 1 MHz, 2.2 V 270 390

SMCLK

CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0

= f

Active mode (AM) current (1 MHz)

DCO

ACLK

Program executes in RAM,

= f

MCLK

= 32768 Hz,

BCSCTL1 = CALBC1_1MHZ, µA DCOCTL = CALDCO_1MHZ,

= 1 MHz, 2.2 V 240

SMCLK

CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0

= f

MCLK

4096 Hz, 85°C f

= 0 Hz,

Active mode (AM) Program executes in flash,

DCO

current (4 kHz) SELMx = 11, SELS = 1,

DIVMx = DIVSx = DIVAx = 11, CPUOFF = 0, SCG0 = 1, SCG1 = 0, OSCOFF = 0

SMCLK

= f

= 32768 Hz/8 = -40°C to

ACLK

105°C 18

-40°C to 85°C

105°C 20

-40°C to 85°C

105°C 95

-40°C to 85°C

Active mode (AM) current (100 kHz)

= f

MCLK

= 0 Hz,

ACLK

Program executes in flash, µA

SMCLK

= f

DCO(0, 0)

≈ 100 kHz,

RSELx = 0, DCOx = 0, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 1

105°C 105

MIN TYP MAX UNIT

3 V 390 550

3.3 V 340

2.2 V

3 V

2.2 V

3 V

5 9

µA

6 10

60 85

72 95

(1) All inputs are tied to 0 V or VCC. Outputs do not source or sink any current. (2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external

load capacitance is chosen to closely match the required 9 pF.

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

1.5 2.0 2.5 3.0 3.5 4.0

VCC− Supply Voltage − V

Active Mode Current − mA

DCO

= 1 MHz

DCO

= 8 MHz

DCO

= 12 MHz

DCO

= 16 MHz

0.0

1.0

2.0

3.0

4.0

5.0

0.0 4.0 8.0 12.0 16.0

DCO

− DCO Frequency − MHz

Active Mode Current − mA

TA= 25 °C

TA= 85 °C

VCC= 2.2 V

VCC= 3 V

TA= 25 °C

TA= 85 °C

MSP430F22x2 MSP430F22x4

SLAS504G –JULY 2006–REVISED AUGUST 2012

Typical Characteristics - Active-Mode Supply Current (Into DVCC+ AVCC)

ACTIVE-MODE CURRENT

vs ACTIVE-MODE CURRENT

SUPPLY VOLTAGE vs

TA= 25°C DCO FREQUENCY

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Figure 2. Figure 3.

MSP430F22x2 MSP430F22x4

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Low-Power-Mode Supply Currents (Into VCC) Excluding External Current

SLAS504G –JULY 2006–REVISED AUGUST 2012

(1)(2)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

LPM0,1MHz

PARAMETER TEST CONDITIONS T

= 0 MHz, 2.2 V 75 90

MCLK

= f

= 1 MHz,

DCO

= 32768 Hz,

Low-power mode 0 (LPM0) current

(3)

SMCLK

ACLK

BCSCTL1 = CALBC1_1MHZ, µA DCOCTL = CALDCO_1MHZ,

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0

= 0 MHz, 2.2 V 37 48

MCLK

LPM0,100kHz

Low-power mode 0 f (LPM0) current

(3)

= f

SMCLK

= 0 Hz,

ACLK

RSELx = 0, DCOx = 0,

DCO(0, 0)

≈ 100 kHz,

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 1

-40°C to 85°C

105°C 31

-40°C to 85°C

105°C 34

LPM2

Low-power mode 2 (LPM2) current

(4)

= f

MCLK

= 1 MHz,

DCO

= 32768 Hz,

ACLK

BCSCTL1 = CALBC1_1MHZ, µA

SMCLK

= 0 MHz,

DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0

-40°C 0.7 1.4 25°C 0.7 1.4 85°C 2.4 3.3

105°C 5 10

-40°C 0.9 1.5 25°C 0.9 1.5

LPM3,LFXT1

Low-power mode 3 f (LPM3) current

(4)

= f

DCO ACLK

CPUOFF = 1, SCG0 = 1,

= f

MCLK

= 32768 Hz,

SMCLK

= 0 MHz,

SCG1 = 1, OSCOFF = 0

85°C 2.6 3.8

105°C 6 12

-40°C 0.4 1 25°C 0.5 1 85°C 1.8 2.9

105°C 4.5 9

-40°C 0.5 1.2 25°C 0.6 1.2

LPM3,VLO

Low-power mode 3 current, (LPM3)

(4)

= f

DCO

ACLK

(VLO), µA

= f

MCLK

from internal LF oscillator

SMCLK

= 0 MHz,

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0

85°C 2.1 3.3

105°C 5.5 11

-40°C 0.1 0.5 25°C 0.1 0.5 85°C 1.5 3

105°C 4.5 9

LPM4

Low-power mode 4 f (LPM4) current

(5)

= f

DCO ACLK

CPUOFF = 1, SCG0 = 1, 3 V

= f

MCLK

= 0 Hz, 2.2 V/

SMCLK

= 0 MHz,

SCG1 = 1, OSCOFF = 1

load capacitance is chosen to closely match the required 9 pF. (3) Current for brownout and WDT clocked by SMCLK included. (4) Current for brownout and WDT clocked by ACLK included. (5) Current for brownout included.

MIN TYP MAX UNIT

3 V 90 120

3 V 41 65

2.2 V

3 V

22 29

25 32

2.2 V

3 V

2.2 V

3 V

µA

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