TEXAS INSTRUMENTS MSP430C33x Technical data

D

40°C to 85°C

MSP430C337IPJM

25°C

PMS430E337AHFD

Low Supply Voltage Range 2.5 V – 5.5 V

D

Low Operation Current, 400 mA at 1 MHz,
3V

D

Ultralow-Power Consumption:
– Standby Mode: 2 µA
– RAM Retention Off Mode: 0.1 µA

D

Five Power-Saving Modes

D

Wake-Up From Standby Mode in 6 µs

D

16-Bit RISC Architecture, 300 ns Instruction
Cycle Time

D

Single Common 32 kHz Crystal, Internal
System Clock up to 3.8 MHz

D

Integrated LCD Driver for up to 120
Segments

D

Integrated Hardware Multiplier Performs
Signed, Unsigned on Multiply, and MAC
Operations for Operands up to 16 × 16 Bits

D

Serial Communication Interface (USART),
Select Asynchronous UART or
Synchronous SPI by Software

description

MSP430C33x, MSP430P337A

MIXED SIGNAL MICROCONTROLLERS

SLAS227A – OCTOBER 1999 – REVISED JUNE 2000

D

Slope A/D Converter Using External
Components

D

16-Bit Timer With Five Capture/Compare
Registers

D

Serial Onboard Programming

D

Programmable Code Protection by Security
Fuse

D

Family Members Include:
– MSP430C336 – 24 KB ROM, 1 KB RAM
– MSP430C337 – 32 KB ROM, 1 KB RAM
– MSP430P337A – 32 KB OTP, 1 KB RAM

D

EPROM Version Available for Prototyping:
– PMS430E337A

D

Available in the Following Packages:
– 100 Pin Quad Flat-Pack (QFP)
– 100 Pin Ceramic Quad Flat-Pack (CFP)

(EPROM Version)

The Texas Instruments MSP430 is an ultralow-power mixed signal microcontroller family consisting of several
devices featuring different sets of modules targeted to various applications. The controller is designed to be
battery-operated for an extended application lifetime. With the 16-bit RISC architecture, 16 integrated registers
on the CPU, and a constant generator, the MSP430 achieves maximum code ef ficiency. The digital-controlled
oscillator, together with the frequency lock loop (FLL), provides a wake-up from a low-power mode to an active
mode in less than 6 ms. The MSP430x33x series microcontrollers have built-in hardware multiplication and
communication capability using asynchronous (UART) and synchronous protocols.

Typical applications of the MSP430 family include electronic gas, water, and electric meters and other sensor
systems that capture analog signals, convert them to digital values, process, displays, or transmits data to a
host system.

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

°

–

°

°

PLASTIC QFP

(PJM)

MSP430C336IPJM

MSP430P337AIPJM

—

CERAMIC QFP

(HFD)

—

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2000, Texas Instruments Incorporated

1

MSP430C33x, MSP430P337A
MIXED SIGNAL MICROCONTROLLERS

SLAS227A – OCTOBER 1999 – REVISED JUNE 2000

PJM or HFD PACKAGE

(TOP VIEW)

V

CC1

CIN
TP0.0
TP0.1
TP0.2
TP0.3
TP0.4
TP0.5

P0.0

P0.1/RXD

P0.2/TXD

P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2

V

SS2

V

CC2

NC

SS1

Xin

Xout/TCLK

RST/NMI

TCK

TMS

TDI/VPP

XBUF

V

96

97

98

99

100

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

35

34

33

32

31

TDO/TDI

92

93

94

95

39

38

37

36

R33

91

40

R23

90

41

R13

89

42

R03

S27/O27

S29/O29/CMPI

S28/O28

85

86

87

88

46

45

43

44

S26/O26

S25/O25

S24/O24

82

83

84

49

48

47

S23/O23

81

80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

NC
S22/O22
S21/O21
S20/O20
S19/O19
S18/O18
S17/O17
S16/O16
S15/O15
S14/O14
S13/O13
S12/O12
S11/O11
S10/O10
S9/O9
S8/O8
S7/07

S6/O6
S5/O5
S4/O4
S3/O3
S2/O2
S1
S0
COM0

COM1
COM2

COM3
V

SS3

P4.7/URXD

P2.3

P2.4

P2.5

P2.6

P2.7

P3.0

NC – No internal connection

P3.1

P3.3/TA0

P3.2/TACLK

P3.4/TA1

P3.5/TA2

P3.6/TA3

P3.7/TA4

P4.0

P4.1

P4.2/STE

P4.4/SOMI

P4.3/SIMO

P4.5/UCLK

P4.6/UTXD

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

I/O Port

8 I/O’s, All With

I/O Port

1x8 Digital

Interr. Cap.

I/O’s

3 Int. Vectors

TXD

MSP430C33x, MSP430P337A

MIXED SIGNAL MICROCONTROLLERS

SLAS227A – OCTOBER 1999 – REVISED JUNE 2000

Com0–3

S0–28/O2–28

S29/O29/CMPI

R33

LCD

120 Segments

Basic

Timer1

1, 2, 3, 4 MUX

LCD

f

CMPI

R23

R13

R03

V

V

V

V

V

SS3

SS2

SS1

CC2

CC1

XIN Xout/TCLK XBUF RST/NMI P4.0 P4.7 P2.x P1.x P3.0 P3.7 P0.0 P0.7

I/O Port

8 8

I/O Port

Power-on-

1024B

32 kB OPT or

24/32 kB ROM

ACLK

Oscillator

Interr. Cap.

2x8 I/O’s All

I/O’s

1x8 Digital

Reset

RAM

SRAM

EPROM

C: ROM

P: OTP

MCLK

FLL

System Clock

2 Int. Vectors

E: EPROM

USART TimerA RXD,

MAB, 4 Bit

MAB, 16 Bit

MCB

Test

MDB, 8 Bit

MDB, 16 Bit

JTAG

Bus

Conv

Applications

8 Bit Timer/Port

Timer/Counter

USART

Timer

Watchdog TimerA

MPY

Multiplier

A/D Conv.

Timer, O/P

UART or

SPI Function

UTXD

URXD

PWM

16 Bit

15/16 Bit

MPYS

MACS

TXD RXD

STE

UCLK

TACLK

8x8 Bit

16x16 Bit

CIN

6

TP0.0–0.5

SOMI

SIMO

TA0–4

CPU

Incl. 16 Reg.

TDI/VPP

TDO/TDI

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS

TCK

3

MSP430C33x, MSP430P337A

I/O

DESCRIPTION

MIXED SIGNAL MICROCONTROLLERS

SLAS227A – OCTOBER 1999 – REVISED JUNE 2000

Terminal Functions

TERMINAL

NAME NO.

CIN 2 I Input port. CIN is used as an enable for counter TPCNT1 – (Timer/Port).
COM0–3 56–53 O Common outputs. COM0-3 are used for LCD backplanes – LCD
P0.0 9 I/O General-purpose digital I/O
P0.1/RXD 10 I/O General-purpose digital I/O, receive digital Input port – 8-Bit Timer/Counter
P0.2/TXD 11 I/O General-purpose digital I/O, transmit data output port – 8-Bit Timer/Counter
P0.3–P0.7 12–16 I/O Five general-purpose digital I/Os, bit 3-7
P1.0–P1.7 17–24 I/O Eight general-purpose digital I/Os, bit 0-7
P2.0–P2.7 25–27,

31–35
P3.0, P3.1 36,37 I/O Two general-purpose digital I/Os, bit 0 and bit 1
P3.2/TACLK 38 I/O General-purpose digital I/O, clock input – Timer_A
P3.3/TA0 39 I/O General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR0
P3.4/TA1 40 I/O General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR1
P3.5/TA2 41 I/O General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR2
P3.6/TA3 42 I/O General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR3
P3.7/TA4 43 I/O General-purpose digital I/O, capture I/O, or PWM output port – Timer_A CCR4
P4.0 44 I/O General-purpose digital I/O, bit 0
P4.1 45 I/O General-purpose digital I/O, bit 1
P4.2/STE 46 I/O General-purpose digital I/O, slave transmit enable – USART/SPI mode
P4.3/SIMO 47 I/O General-purpose digital I/O, slave in/master out – USART/SPI mode
P4.4/SOMI 48 I/O General-purpose digital I/O, master in/slave out – USART/SPI mode
P4.5/UCLK 49 I/O General-purpose digital I/O, external clock input – USART
P4.6/UTXD 50 I/O General-purpose digital I/O, transmit data out – USART/UART mode
P4.7/URXD 51 I/O General-purpose digital I/O, receive data in – USART/UART mode
R03 88 I Input port of fourth positive (lowest) analog LCD level (V5) – LCD
R13 89 I Input port of third most positive analog LCD level (V3 of V4) – LCD
R23 90 I Input port of second most positive analog LCD level (V2) – LCD
R33 91 O Output of most positive analog LCD level (V1) – LCD
RST/NMI 96 I Reset input or non-maskable interrupt input port
S0 57 O Segment line S0 – LCD
S1 58 O Segment line S1 – LCD
S2/O2–S5/O5 59–62 O Segment lines S2 to S5 or digital output ports, O2-O5, group 1 – LCD
S6/O6–S9/O9 63–66 O Segment lines S6 to S9 or digital output ports O6-O9, group 2 – LCD
S10/O10–S13/O13 67–70 O Segment lines S10 to S13 or digital output ports O10-O13, group 3 – LCD
S14/O14–S17/O17 71–74 O Segment lines S14 to S17 or digital output ports O14-O17, group 4 – LCD
S18/O18–S21/O21 75–78 O Segment lines S18 to S21 or digital output ports O18-O21, group 5 – LCD
S22/O22–S25/O25 79, 81–83 O Segment line S22 to S25 or digital output ports O22-O25, group 6 – LCD
S26/O26–S29/O29/CMPI 84–87 O Segment line S26 to S29 or digital output ports O26-O29, group 7 – LCD. Segment line S29

TCK 95 I Test clock. TCK is the clock input port for device programming and test.
TDI/VPP 93 I Test data input. TDI/VPP is used as a data input port or input for programming voltage.

I/O Eight general-purpose digital I/Os, bit 0-7

can be used as comparator input port CMPI – Timer/Port

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MSP430C33x, MSP430P337A

I/O

DESCRIPTION

MIXED SIGNAL MICROCONTROLLERS

SLAS227A – OCTOBER 1999 – REVISED JUNE 2000

Terminal Functions (Continued)

TERMINAL

NAME NO.

TMS 94 I Test mode select. TMS is used as an input port for device programming and test.
TDO/TDI 92 I/O Test data output port. TDO/TDI data output or programming data input terminal

TP0.0 3 O General-purpose 3-state digital output port, bit 0 – Timer/Port
TP0.1 4 O General-purpose 3-state digital output port, bit 1 – Timer/Port
TP0.2 5 O General-purpose 3-state digital output port, bit 2 – Timer/Port
TP0.3 6 O General-purpose 3-state digital output port, bit 3 – Timer/Port
TP0.4 7 O General-purpose 3-state digital output port, bit 4 – Timer/Port
TP0.5 8 I/O General-purpose 3-state digital input/output port, bit 5 – Timer/Port
V

CC1

V

CC2

V

SS1

V

SS2

V

SS3

XBUF 97 O System clock (MCLK) or crystal clock (ACLK) output
Xin 99 I Input port for crystal oscillator

Xout/TCLK 98 I/O Output terminal of crystal oscillator or test clock input

1 Positive supply voltage

29 Positive supply voltage

100 Ground reference

28 Ground reference
52 Ground reference

detailed description

processing unit

The processing unit is based on a consistent and orthogonal designed CPU and instruction set. This design
structure results in a RISC-like architecture, highly transparent to the application development, which is
distinguished by ease of programming. All operations other than program-flow instructions consequently are
performed as register operations in conjunction with seven addressing modes for source and four modes for
destination operand.

CPU registers

The CPU has sixteen registers that provide
reduced instruction execution time. This reduces
the register-to-register operation execution time
to one cycle of the processor frequency.

Four of the registers are reserved for special use
as a program counter, a stack pointer, a status
register, and a constant generator . The remaining
registers are available as general-purpose regis­ters.

Peripherals are connected to the CPU using a
data address and control bus and can be handled
easily with all instructions for memory manipula­tion.

Program Counter

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

General-Purpose Register

General-Purpose Register R14

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R4

R5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

General-Purpose Register

R15

5

MSP430C33x, MSP430P337A
MIXED SIGNAL MICROCONTROLLERS

SLAS227A – OCTOBER 1999 – REVISED JUNE 2000

detailed description (continued)

instruction set

The instruction set for this register-register architecture provides a powerful and easy-to-use assembly
language. The instruction set consists of 51 instructions with three formats and seven addressing modes.
Table 1 provides a summation and example of the three types of instruction formats; the address modes are
listed in Table 2.

Table 1. Instruction Word Formats

Dual operands, source-destination e.g. ADD R4,R5 R4 + R5 → R5
Single operands, destination only e.g. CALL R8 PC → (TOS), R8→ PC
Relative jump, un-/conditional e.g. JNE Jump-on equal bit = 0

Instructions that can operate on both word and byte data are differentiated by the suffix .B when a byte operation
is required.

Examples: Instructions for word operation: Instructions for byte operation:

MOV EDE,TONI MOV.B EDE,TONI
ADD #235h,&MEM ADD.B #35h,&MEM
PUSH R5 PUSH.B R5
SWPB R5 –––

Table 2. Address Mode Descriptions

ADDRESS MODE S D SYNTAX EXAMPLE OPERATION

Register √ √ MOV Rs,Rd MOV R10,R11 R10 → R11
Indexed √ √ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) → M(6+R6)
Symbolic (PC relative) √ √ MOV EDE,TONI M(EDE) → M(TONI)
Absolute √ √ MOV &MEM,&TCDA T M(MEM) → M(TCDAT)
Indirect √ MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) → M(T ab+R6)
Indirect autoincrement √ MOV @Rn+,Rm MOV @R10+,R11 M(R10) → R11

Immediate √ MOV #X,TONI MOV #45,TONI #45 → M(TONI)

NOTE 1: S = source, D = destination.

R10 + 2

→ R10

Computed branches (BR) and subroutine calls (CALL) instructions use the same address modes as the other
instructions. These addressing modes provide

indirect

addressing, ideally suited for computed branches and
calls. The full use of this programming capability permits a program structure different from conventional 8- and
16-bit controllers. For example, numerous routines can easily be designed to deal with pointers and stacks
instead of using flag type programs for flow control.

6

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MSP430C33x, MSP430P337A

MIXED SIGNAL MICROCONTROLLERS

SLAS227A – OCTOBER 1999 – REVISED JUNE 2000

operation modes and interrupts

The MSP430 operating modes support various advanced requirements for ultralow-power and ultralow-energy
consumption. This is achieved by the intelligent management of the operations during the different module
operation modes and CPU states. The requirements are fully supported during interrupt event handling. An
interrupt event awakens the system from each of the various operating modes and returns with the RETI
instruction to the mode that was selected before the interrupt event. The clocks used are ACLK and MCLK.
ACLK is the crystal frequency and MCLK, a multiple of ACLK, is used as the system clock.

The following five operating modes are supported:

D

Active mode (AM). The CPU is enabled with different combinations of active peripheral modules.

D

Low-power mode 0 (LPM0). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is active.

D

Low-power mode 1 (LPM1). The CPU is disabled, peripheral operation continues, ACLK and MCLK signals
are active, and loop control for MCLK is inactive.

D

Low-power mode 2 (LPM2). The CPU is disabled, peripheral operation continues, ACLK signal is active,
and MCLK and loop control for MCLK are inactive.

D

Low-power mode 3 (LPM3). The CPU is disabled, peripheral operation continues, ACLK signal is active,
MCLK and loop control for MCLK are inactive, and the dc generator for the digital controlled oscillator (DCO)
(³MCLK generator) is switched off.

D

Low-power mode 4 (LPM4). The CPU is disabled, peripheral operation continues, ACLK signal is inactive
(crystal oscillator stopped), MCLK and loop control for MCLK are inactive, and the dc generator for the DCO
is switched off.

The special function registers (SFR) include module-enable bits that stop or enable the operation of the specific
peripheral module. All registers of the peripherals may be accessed if the operational function is stopped or
enabled, however, some peripheral current-saving functions are accessed through the state of local register
bits. An example is the enable/disable of the analog voltage generator in the LCD peripheral, which is turned
on or off using one register bit.

The most general bits that influence current consumption and support fast turnon from low power operating
modes are located in the status register (SR). Four of these bits control the CPU and the system clock generator:
SCG1, SCG0, OscOff, and CPUOff.

15 9 8 7 0

Reserved For Future

Enhancements

interrupts

Software determines the activation of interrupts through the monitoring of hardware set interrupt flag status bits,
the control of specific interrupt enable bits in SRs, the establishment of interrupt vectors, and the programming
of interrupt handlers. The interrupt vectors and the power-up starting address are located in ROM address
locations 0FFFFh through 0FFE0h. Each vector contains the 16-bit address of the appropriate interrupt handler
instruction sequence. Table 3 provides a summation of interrupt functions and addresses.

V SCG1 SCG0 OscOff CPUOff GIE N Z C

rw-0

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

MSP430C33x, MSP430P337A

Timer/Port

,,

Maskable

0FFE8h

4

MIXED SIGNAL MICROCONTROLLERS

SLAS227A – OCTOBER 1999 – REVISED JUNE 2000

operation modes and interrupts (continued)

Table 3. Interrupt Functions and Addresses

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT WORD ADDRESS PRIORITY

Power up, external reset, watchdog WDTIFG Reset 0FFFEh 15, highest
NMI,

Oscillator fault
Dedicated I/O P0.0 P0IFG.0 Maskable 0FFFAh 13
Dedicated I/O P0.1 or 8-Bit Timer/Counter P0IFG.1 Maskable 0FFF8h 12

Watchdog Timer WDTIFG Maskable 0FFF4h 10
Timer_A CCIFG0 (see Note 3) Maskable 0FFF2h 9
Timer_A TAIFG (see Note 3) Maskable 0FFF0h 8
UART receive URXIFG Maskable 0FFEEh 7
UART transmit UTXIFG Maskable 0FFECh 6

I/O port P2 P2IFG.07 (see Note 2) Maskable 0FFE6h 3
I/O port P1 P1IFG.07 (see Note 2) Maskable 0FFE4h 2
Basic Timer1 BTIFG Maskable 0FFE2h 1
I/O port P0.2 – P0.7 P0IFG.27 (see Note 2) Maskable 0FFE0h 0, lowest

NOTES: 2. Multiple source flags

3. Interrupt flags are located in the individual module registers.

4. Non-maskable : neither the individual or the general interrupt enable bit will disable an interrupt event.

5. (Non)-maskable: the individual interrupt enable bit can disable an interrupt event, but the general interrupt enable bit cannot.

NMIIFG (see Notes 2 and 4)
OFIFG (see Notes 2 and 5)

RC1FG, RC2FG, EN1FG
(see Note 3)

Non-maskable

(Non)-maskable

Maskable 0FFF6h 11

0FFFCh 14

0FFEAh 5

special function registers

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits
that are not allocated to a functional purpose are not physically present in the device. Simple software access
is provided with this arrangement.

interrupt enable 1 and 2

Address
0h

7654 0

321

P0IE.1 OFIE WDTIE

rw-0 rw-0 rw-0 rw-0

P0IE.0

WDTIE: Watchdog Timer interrupt enable signal
OFIE: Oscillator fault interrupt enable signal
P0IE.0: Dedicated I/O P0.0 interrupt enable signal
P0IE.1: P0.1 or 8-Bit Timer/Counter, RXD interrupt enable signal

Address
01h BTIE

7654 0

rw-0

321

TPIE UTXIE URXIE

rw-0 rw-0 rw-0

URXIE: USART receive interrupt enable signal
UTXIE: USART transmit interrupt enable signal
TPIE: Timer/Port interrupt enable signal
BTIE: Basic Timer1 interrupt enable signal

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MIXED SIGNAL MICROCONTROLLERS

operation modes and interrupts (continued)

interrupt flag registers 1 and 2

Address
02h NMIIFG P0IFG.0

7654 0

321

P0IFG.1 OFIFG WDTIFG

MSP430C33x, MSP430P337A

SLAS227A – OCTOBER 1999 – REVISED JUNE 2000

WDTIFG: Set on overflow or security key violation

or

Reset on VCC1 power-on or reset condition at RST
OFIFG: Flag set on oscillator fault
P0IFG.0: Dedicated I/O P0.0
P0IFG.1: P0.1 or 8-Bit Timer/Counter, RXD
NMIIFG: Signal at RST/NMI-pin

Address
03h BTIFG

7654 0

rw

URXIFG: USART receive flag
UTXIFG: USART transmit flag
BTIFG: Basic Timer1 flag

module enable registers 1 and 2

Address
04h

Address
05h

7654 0321

7654 0

rw-0 rw-1 rw-0

rw-0 rw-0

/NMI-pin

321

UTXIFG URXIFG

rw-1 rw-0

321

UTXE

URXE/USPIE

Bit 0: USART mode: USART receive enable, URXE
SPI mode: SPI enable, USPIE

Bit 1: USART mode: USART transmit enable, UTXE
SPI mode: not applicable

Legend rw:

rw-0:

Bit can be read and written
Bit can be read and written. It is reset by PUC.
SFR bit not present in device

rw-0 rw-0

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

MSP430C33x, MSP430P337A
MIXED SIGNAL MICROCONTROLLERS

SLAS227A – OCTOBER 1999 – REVISED JUNE 2000

ROM memory organization

FFFFh
FFE0h

FFDFh

A000h

05FFh

0200h

01FFh

0100h

00FFh

0010h

000Fh

0000h

MSP430C336

Int. Vector

24 kB ROM

1024B RAM

16b Per.

8b Per.

SFR

FFFFh
FFE0h

FFDFh

8000h

05FFh

0200h

01FFh

0100h

00FFh

0010h
000Fh
0000h

MSP430C337

Int. Vector

32 kB ROM

1024B RAM

16b Per.

8b Per.

SFR

FFFFh
FFE0h

FFDFh

05FFh

01FFh
00FFh
000Fh

8000h

0200h

0100h
0010h
0000h

MSP430P337A
PMS430E337A

Int. Vector

32 kB OTP

or

EPROM

1024B RAM

16b Per.

8b Per.

SFR

peripherals

Peripherals that are connected to the CPU through a data, address, and controls bus can be handled easily with
instructions for memory manipulation.

oscillator and system clock

Two clocks are used in the system: the system (master) clock (MCLK) and the auxiliary clock (ACLK). The MCLK
is a multiple of the ACLK. The ACLK runs with the crystal oscillator frequency . The special design of the oscillator
supports the feature of low current consumption and the use of a 32 768 Hz crystal. The crystal is connected
across two terminals without any other external components required.

The oscillator starts after applying VCC, due to a reset of the control bit (OscOff) in the status register (SR). It
can be stopped by setting the OscOff bit to a 1. The enabled clock signals ACLK, ACLK/2, ACLK/4, or MCLK
are accessible for use by external devices at output terminal XBUF.

The controller system clocks have to deal with different requirements according to the application and system
condition. Requirements include:

D

High frequency in order to react quickly to system hardware requests or events

D

Low frequency in order to minimize current consumption, EMI, etc.

D

Stable frequency for timer applications e.g., real-time clock (RTC)

D

Enable start-stop operation with minimum delay to operation function

These requirements cannot all be met with fast frequency high-Q crystals or with RC-type low-Q oscillators. This
compromise and selected for the MSP430, uses a low-crystal frequency, which is multiplied to achieve the
desired nominal operating range:

f

(system)

+(N)1)

f

(crystal)

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MSP430C33x, MSP430P337A

MIXED SIGNAL MICROCONTROLLERS

SLAS227A – OCTOBER 1999 – REVISED JUNE 2000

oscillator and system clock (continued)

The crystal frequency multiplication is achieved with a frequency locked loop (FLL) technique. The factor N is
set to 31 after a power-up clear condition. The FLL technique, in combination with a digital controlled oscillator
(DCO), provides immediate start-up capability together with long term crystal stability . The frequency variation
of the DCO with the FLL inactive is typically 330 ppm, which means that with a cycle time of 1 µs the maximum
possible variation is 0.33 ns. For more precise timing, the FLL can be used, which forces longer cycle times if
the previous cycle time was shorter than the selected one. This switching of cycle times makes it possible to
meet the chosen system frequency over a long period of time.

The start-up operation of the system clock depends on the previous machine state. During a PUC, the DCO
is reset to its lowest possible frequency . The control logic starts operation immediately after recognition of PUC.

multiplication

The multiplication operation is supported by a dedicated peripheral module. The module performs 16x16, 16x8,
8x16, and 8x8 bit operations. The module is capable of supporting signed and unsigned multiplication as well
as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.

digital I/O

Five eight-bit I/O ports (P0 thru P4) are implemented. Port P0 has six control registers, P1 and P2 have seven
control registers, and P3 and P4 modules have four control registers to give maximum flexibility of digital
input/output to the application:

D

Individual I/O bits are independently programmable.

D

Any combination of input, output, and interrupt conditions is possible.

D

Interrupt processing of external events is fully implemented for all eight bits of the P0, P1, and P2 ports.

D

Read/write access is available to all registers by all instructions.

The seven registers are:

D

Input register contains information at the pins

D

Output register contains output information

D

Direction register controls direction

D

Interrupt edge select contains input signal change necessary for interrupt

D

Interrupt flags indicates if interrupt(s) are pending

D

Interrupt enable contains interrupt enable pins

D

Function select determines if pin(s) used by module or port

These registers contain eight bits each with the exception of the interrupt flag register and the interrupt enable
register which are 6 bits each. The two least significant bit (LSBs) of the interrupt flag and enable registers are
located in the special function register (SFR). Five interrupt vectors are implemented, one for Port P0.0, one
for Port P0.1, one commonly used for any interrupt event on Port P0.2 to Port P0.7, one commonly used for any
interrupt event on Port P1.0 to Port P1.7, and one commonly used for any interrupt event on Port P2.0 to Port
P2.7.

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MSP430C33x, MSP430P337A
MIXED SIGNAL MICROCONTROLLERS

SLAS227A – OCTOBER 1999 – REVISED JUNE 2000

LCD drive

The liquid crystal displays (LCDs) for static, 2-, 3-, and 4-MUX operation can be driven directly . The operation
of the controller LCD logic is defined by software through memory-bit manipulation. The LCD memory is part
of the LCD module, not part of data memory. Eight mode and control bits define the operation and current
consumption of the LCD drive. The information for the individual digits can be easily obtained using table
programming techniques combined with the proper addressing mode. The segment information is stored into
LCD memory using instructions for memory manipulation.

The drive capability is defined by the external resistor divider that supports analog levels for 2-, 3-, and 4-MUX
operation. Groups of the LCD segment lines can be selected for digital output signals. The MSP430x33x
configuration has four common lines, 30 segment lines, and four terminals for adjusting the analog levels.

Basic Timer1

The Basic Timer1 (BT1) divides the frequency of MCLK or ACLK, as selected with the SSEL bit, to provide
low-frequency control signals. This is done within the system by one central divider, the Basic T imer1, to support
low current applications. The BTCTL control register contains the flags which control or select the different
operational functions. When the supply voltage is applied or when a reset of the device (RST
watchdog overflow, or a watchdog security key violation occurs, all bits in the register hold undefined or
unchanged status. The user software usually configures the operational conditions on the BT during
initialization.

/NMI pin), a

The Basic Timer1 has two eight bit timers which can be cascaded to a sixteen bit timer . Both timers can be read
and written by software. Two bits in the SFR address range handle the system control interaction according to
the function implemented in the Basic Timer1. These two bits are the Basic T imer1 interrupt flag (BTIFG) and
the Basic Timer1 interrupt enable (BTIE) bit.

Watchdog Timer

The primary function of the Watchdog Timer (WDT) module is to perform a controlled system restart after a
software upset has occurred. If the selected time interval expires, a system reset is generated. If this watchdog
function is not needed in an application, the module can work as an interval timer, which generates an interrupt
after the selected time interval.

The Watchdog T imer counter (WDTCNT) is a 15/16-bit upcounter which is not directly accessible by software.
The WDTCNT is controlled using the Watchdog T imer control register (WDTCTL), which is an 8-bit read/write
register. W riting to WDTCTL, in both operating modes (watchdog or timer) is only possible by using the correct
password in the high-byte. The low-byte stores data written to the WDTCTL. The high-byte password is 05Ah.
If any value other than 05Ah is written to the high-byte of the WDTCTL, a system reset PUC is generated.
the password is read its value is 069h. This minimizes accidental write operations to the WDTCTL register. In
addition to the Watchdog T imer control bits, there are two bits included in the WDTCTL that configure the NMI
pin.

USART

The universal synchronous/asynchronous interface is a dedicated peripheral module which provides serial
communications. The USART supports synchronous SPI (3 or 4 pin) and asynchronous UART communications
protocols, using double buffered transmit and receive channels. Data streams of 7 or 8 bits in length can be
transferred at a rate determined by the program, or by a rate defined by an external clock. Low-power
applications are optimized by UART mode options which allow for the receipt of only the first byte of a complete
frame. The applications software then decides if the succeeding data is to be processed. This option reduces
power consumption.

When

Two dedicated interrupt vectors are assigned to the USAR T module, one for the receive and one for the transmit
channel.

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