ENABLE
MC3486
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLS097B – JUNE 1980 – REVSIED MA Y 1995
D
Meets or Exceeds the Requirements of
ANSI Standards EIA/TIA-422-B and
EIA/TIA-423-B and ITU Recommendations
V.10 and V.11
D
3-State, TTL-Compatible Outputs
D
Fast Transition Times
D
Operates From Single 5-V Supply
D
Designed to Be Interchangeable With
Motorola MC3486
D OR N PACKAGE
(TOP VIEW)
1B
1
1A
2
3
1Y
2Y
2A
2B
4
5
6
7
8
1,2EN
GND
16
15
14
13
12
11
10
9
V
CC
4B
4A
4Y
3,4EN
3Y
3A
3B
description
The MC3486 is a monolithic quadruple differential line receiver designed to meet the specifications of ANSI
Standards EIA/TIA-422-B and EIA/TIA-423-B and ITU Recommendations V.10 and V.11. The MC3486 offers
four independent differential-input line receivers that have TTL-compatible outputs. The outputs utilize 3-state
circuitry to provide a high-impedance state at any output when the appropriate output enable is at a low logic
level.
The MC3486 is designed for optimum performance when used with the MC3487 quadruple differential line
driver. It is supplied in a 16-pin package and operates from a single 5-V supply.
The MC3486 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each receiver)
DIFFERENTIAL INPUTS
A–B
VID ≤ 0.2 V H H
–0.2 V < VID < 0.2 V H ?
VID ≤ –0.2 V H L
Irrelevant L Z
Open H ?
H = high level, L = low level, Z = high impedance (off),
? = indeterminate
OUTPUT
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Motorola is a trademark of Motorola, Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
MC3486
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLS097B – JUNE 1980 – REVSIED MA Y 1995
4
2
1
6
7
12
10
9
14
15
†
EN
EN
logic symbol
1,2EN
1A
1B
2A
2B
3,4EN
3A
3B
4A
4B
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
schematics of inputs and outputs
EQUIVALENT OF EACH INPUT
EXCEPT OUTPUT ENABLE
V
CC
EQUIVALENT OF OUTPUT ENABLE TYPICAL OF ALL OUTPUTS
V
CC
11
13
logic diagram (positive logic)
1A
1B
2A
2B
3A
3B
4A
4B
4
2
1
6
7
12
10
9
14
15
13
3
1Y
5
2Y
11
3Y
4Y
V
85 Ω
NOM
CC
1,2EN
3
1Y
5
2Y
3,4EN
3Y
4Y
8.3 kΩ
NOM
Input
16.8 kΩ
NOM
960 Ω
NOM
960 Ω
NOM
Output
Enable
4.9 kΩ
NOM
Output
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE
A
A
MC3486
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLS097B – JUNE 1980 – REVSIED MA Y 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Differential input voltage, V
Enable input voltage 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low-level output current, I
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential-input voltage, are with respect to network ground terminal.
2. Differential-input voltage is measured at the noninverting input with respect to the corresponding inverting input.
(see Note 1) 8 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(A or B inputs) ±15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
D 950 mW 7.6 mW/°C 608 mW
N 1150 mW 9.2 mW/°C 736 mW
(see Note 2) ±25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ID
50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OL
0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
POWER RATING ABOVE TA = 25°C
A
DISSIPATION RATING TABLE
T
≤ 25°C DERATING FACTOR T
= 70°C
POWER RATING
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
Common-mode input voltage, V
Differential input voltage, V
High-level enable input voltage, V
Low-level enable input voltage, V
Operating free-air temperature, T
CC
ID
IC
IH
IL
A
4.75 5 5.25 V
±7 V
±6 V
2 V
0.8 V
0 70 °C
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
MC3486
VOHHigh-level output voltage
ID
,
O
,
2.7
V
VOLLow-level output voltage
ID
,
O
,
0.5
V
IOZHigh-impedance-state output current
A
IIBDifferential-input bias current
CC
,
mA
IIHHigh-level enable input current
A
See Figure 2
See Figure 3
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLS097B – JUNE 1980 – REVSIED MA Y 1995
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
V
Differential input high-threshold voltage VO = 2.7 V, IO = –0.4 mA 0.2 V
IT+
V
Differential input low-threshold voltage VO = 0.5 V, IO = –8 mA –0.2
IT–
V
Enable-input clamp voltage II = –10 mA –1.5 V
IK
V
p
p
p
p
I
Low-level enable input current VI = –0.5 V –100 µA
IL
I
Short-circuit output current VID = 3 V, VO = 0, See Note 4 –15 –100 mA
OS
I
Supply current VIL = 0 85 mA
CC
†
The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet for threshold
voltages only.
NOTES: 3. Refer to ANSI Standards EIA/TIA-422-B and EIA/TIA-423-B for exact conditions.
4. Only one output should be shorted at a time.
p
p
= 0.4 V, I
See Note 3 and Figure 1
V
= –0.4 V, I
See Note 3 and Figure 1
VIL = 0.8 V, VID = –3 V, VO = 2.7 V 40
VIL = 0.8 V, VID = 3 V, VO = 0.5 V –40
V
= 0 V or 5.25 V,
Other inputs at 0 V
VI = 5.25 V 100
VI = 2.7 V 20
= –0.4 mA,
= 8 mA,
VI = –10 V –3.25
VI = –3 V –1.5
VI = 3 V 1.5
VI = 10 V 3.25
†
V
µ
µ
switching characteristics, VCC = 5 V, CL = 15 pF, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PHL
t
PLH
t
PZH
t
PZL
t
PHZ
t
PLZ
Propagation delay time, high- to low-level output
Propagation delay time, low- to high-level output
Output enable time to high level 13 30 ns
Output enable time to low level
Output disable time from high level
Output disable time from low level 27 35 ns
28 35 ns
27 30 ns
20 30 ns
26 35 ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MC3486
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLS097B – JUNE 1980 – REVSIED MA Y 1995
PARAMETER MEASUREMENT INFORMATION
500 Ω
V
ID
500 Ω
V
OH
I
OL
(+)
V
2 V
Figure 1. VOH, V
Generator
(see Note A)
1.5 V
2 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, tr ≤ 6 ns,
tf ≤ 6 ns.
B. CL includes probe and stray capacitance.
51 Ω
TEST CIRCUIT VOLTAGE W AVEFORMS
Output
CL = 15 pF
(see Note B)
OL
Output
OL
Input
t
PLH
1.5 V
1.3 V
I
(–)
OH
1.5 V
t
PHL
1.3 V
3 V
0 V
Figure 2. Test Circuit and Voltage Waveforms
V
OH
V
OL
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
MC3486
QUADRUPLE DIFFERENTIAL LINE RECEIVER
WITH 3-STATE OUTPUTS
SLLS097B – JUNE 1980 – REVSIED MA Y 1995
PARAMETER MEASUREMENT INFORMATION
Generator
(see Note A)
Input
Output
–1.5 V
1.5 V
SW1
t
t
PZH
PZH
51 Ω
3 V
1.5 V
0 V
1.5 V
1.3 V
SW1 to 1.5 V
SW2 Open
SW3 Closed
V
OH
TEST CIRCUIT
Output
Input
Output
CL = 15 pF
(see Note B)
2 kΩ
5 kΩ See Note C
SW3
t
PZL
0 V
t
PZL
4.5 V
1.5 V
SW2
5 V
3 V
1.5 V
SW1 to – 1.5 V
SW2 Closed
SW3 Open
V
OL
t
t
PHZ
Input
t
PHZ
Output
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, duty cycle = 50%, tr ≤ 6 ns,
0.5 V
tf ≤ 6 ns.
B. CL includes probe and stray capacitance.
C. All diodes are 1N916 or equivalent.
3 V
0 V
1.3 V
SW1 to 1.5 V
SW2 Closed
SW3 Closed
V
OH
Input
Output
t
PLZ
PLZ
1.5 V
0.5 V
3 V
SW1 to – 1.5 V
SW2 Closed
SW3 Closed
0 V
1.3 V
V
OL
Figure 3. Test Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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