TEXAS INSTRUMENTS LM3S618 Technical data
PRELIMINARY
LM3S618 Microcontroller
DATA SHEET
Copyright © 2007 Luminary Micro, Inc.DS-LM3S618-1972
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Preliminary
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LM3S618 Microcontroller
Table of Contents
About This Document .................................................................................................................... 18
Audience .............................................................................................................................................. 18
About This Manual ................................................................................................................................ 18
Related Documents ............................................................................................................................... 18
Documentation Conventions .................................................................................................................. 18
1 Architectural Overview ...................................................................................................... 20
1.1 Product Features ...................................................................................................................... 20
1.2 Target Applications .................................................................................................................... 25
1.3 High-Level Block Diagram ......................................................................................................... 25
1.4 Functional Overview .................................................................................................................. 26
1.4.1 ARM Cortex™-M3 ..................................................................................................................... 27
1.4.2 Motor Control Peripherals .......................................................................................................... 27
1.4.3 Analog Peripherals .................................................................................................................... 28
1.4.4 Serial Communications Peripherals ............................................................................................ 29
1.4.5 System Peripherals ................................................................................................................... 30
1.4.6 Memory Peripherals .................................................................................................................. 30
1.4.7 Additional Features ................................................................................................................... 31
1.4.8 Hardware Details ...................................................................................................................... 31
1.4.9 System Block Diagram .............................................................................................................. 33
2 ARM Cortex-M3 Processor Core ...................................................................................... 34
2.1 Block Diagram .......................................................................................................................... 35
2.2 Functional Description ............................................................................................................... 35
2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 35
2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 36
2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 36
2.2.4 ROM Table ............................................................................................................................... 36
2.2.5 Memory Protection Unit (MPU) ................................................................................................... 36
2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 36
3 Memory Map ....................................................................................................................... 40
4 Interrupts ............................................................................................................................ 42
5 JTAG Interface .................................................................................................................... 44
5.1 Block Diagram .......................................................................................................................... 45
5.2 Functional Description ............................................................................................................... 45
5.2.1 JTAG Interface Pins .................................................................................................................. 46
5.2.2 JTAG TAP Controller ................................................................................................................. 47
5.2.3 Shift Registers .......................................................................................................................... 48
5.2.4 Operational Considerations ........................................................................................................ 48
5.3 Initialization and Configuration ................................................................................................... 49
5.4 Register Descriptions ................................................................................................................ 50
5.4.1 Instruction Register (IR) ............................................................................................................. 50
5.4.2 Data Registers .......................................................................................................................... 52
6 System Control ................................................................................................................... 54
6.1 Functional Description ............................................................................................................... 54
6.1.1 Device Identification .................................................................................................................. 54
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6.1.2 Reset Control ............................................................................................................................ 54
6.1.3 Power Control ........................................................................................................................... 57
6.1.4 Clock Control ............................................................................................................................ 57
6.1.5 System Control ......................................................................................................................... 60
6.2 Initialization and Configuration ................................................................................................... 60
6.3 Register Map ............................................................................................................................ 61
6.4 Register Descriptions ................................................................................................................ 62
7 Internal Memory ............................................................................................................... 113
7.1 Block Diagram ........................................................................................................................ 113
7.2 Functional Description ............................................................................................................. 113
7.2.1 SRAM Memory ........................................................................................................................ 113
7.2.2 Flash Memory ......................................................................................................................... 114
7.3 Flash Memory Initialization and Configuration ........................................................................... 116
7.3.1 Changing Flash Protection Bits ................................................................................................ 116
7.3.2 Flash Programming ................................................................................................................. 117
7.4 Register Map .......................................................................................................................... 117
7.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 118
7.6 Flash Register Descriptions (System Control Offset) .................................................................. 125
8 General-Purpose Input/Outputs (GPIOs) ....................................................................... 129
8.1 Block Diagram ........................................................................................................................ 130
8.2 Functional Description ............................................................................................................. 130
8.2.1 Data Control ........................................................................................................................... 131
8.2.2 Interrupt Control ...................................................................................................................... 132
8.2.3 Mode Control .......................................................................................................................... 133
8.2.4 Pad Control ............................................................................................................................. 133
8.2.5 Identification ........................................................................................................................... 133
8.3 Initialization and Configuration ................................................................................................. 133
8.4 Register Map .......................................................................................................................... 134
8.5 Register Descriptions .............................................................................................................. 136
9 General-Purpose Timers ................................................................................................. 168
9.1 Block Diagram ........................................................................................................................ 168
9.2 Functional Description ............................................................................................................. 169
9.2.1 GPTM Reset Conditions .......................................................................................................... 169
9.2.2 32-Bit Timer Operating Modes .................................................................................................. 170
9.2.3 16-Bit Timer Operating Modes .................................................................................................. 171
9.3 Initialization and Configuration ................................................................................................. 175
9.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 175
9.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 176
9.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 176
9.3.4 16-Bit Input Edge Count Mode ................................................................................................. 177
9.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 177
9.3.6 16-Bit PWM Mode ................................................................................................................... 178
9.4 Register Map .......................................................................................................................... 178
9.5 Register Descriptions .............................................................................................................. 179
10 Watchdog Timer ............................................................................................................... 204
10.1 Block Diagram ........................................................................................................................ 204
10.2 Functional Description ............................................................................................................. 204
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10.3 Initialization and Configuration ................................................................................................. 205
10.4 Register Map .......................................................................................................................... 205
10.5 Register Descriptions .............................................................................................................. 206
11 Analog-to-Digital Converter (ADC) ................................................................................. 227
11.1 Block Diagram ........................................................................................................................ 228
11.2 Functional Description ............................................................................................................. 228
11.2.1 Sample Sequencers ................................................................................................................ 228
11.2.2 Module Control ........................................................................................................................ 229
11.2.3 Hardware Sample Averaging Circuit ......................................................................................... 230
11.2.4 Analog-to-Digital Converter ...................................................................................................... 230
11.2.5 Test Modes ............................................................................................................................. 230
11.2.6 Internal Temperature Sensor .................................................................................................... 230
11.3 Initialization and Configuration ................................................................................................. 231
11.3.1 Module Initialization ................................................................................................................. 231
11.3.2 Sample Sequencer Configuration ............................................................................................. 231
11.4 Register Map .......................................................................................................................... 232
11.5 Register Descriptions .............................................................................................................. 233
12 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 260
12.1 Block Diagram ........................................................................................................................ 261
12.2 Functional Description ............................................................................................................. 261
12.2.1 Transmit/Receive Logic ........................................................................................................... 261
12.2.2 Baud-Rate Generation ............................................................................................................. 262
12.2.3 Data Transmission .................................................................................................................. 263
12.2.4 FIFO Operation ....................................................................................................................... 263
12.2.5 Interrupts ................................................................................................................................ 263
12.2.6 Loopback Operation ................................................................................................................ 264
12.3 Initialization and Configuration ................................................................................................. 264
12.4 Register Map .......................................................................................................................... 265
12.5 Register Descriptions .............................................................................................................. 266
13 Synchronous Serial Interface (SSI) ................................................................................ 298
13.1 Block Diagram ........................................................................................................................ 298
13.2 Functional Description ............................................................................................................. 298
13.2.1 Bit Rate Generation ................................................................................................................. 299
13.2.2 FIFO Operation ....................................................................................................................... 299
13.2.3 Interrupts ................................................................................................................................ 299
13.2.4 Frame Formats ....................................................................................................................... 300
13.3 Initialization and Configuration ................................................................................................. 307
13.4 Register Map .......................................................................................................................... 308
13.5 Register Descriptions .............................................................................................................. 309
14 Analog Comparator ......................................................................................................... 335
14.1 Block Diagram ........................................................................................................................ 335
14.2 Functional Description ............................................................................................................. 335
14.2.1 Internal Reference Programming .............................................................................................. 336
14.3 Initialization and Configuration ................................................................................................. 337
14.4 Register Map .......................................................................................................................... 338
14.5 Register Descriptions .............................................................................................................. 338
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Table of Contents
15 Pulse Width Modulator (PWM) ........................................................................................ 346
15.1 Block Diagram ........................................................................................................................ 346
15.2 Functional Description ............................................................................................................. 346
15.2.1 PWM Timer ............................................................................................................................. 346
15.2.2 PWM Comparators .................................................................................................................. 347
15.2.3 PWM Signal Generator ............................................................................................................ 348
15.2.4 Dead-Band Generator ............................................................................................................. 349
15.2.5 Interrupt/ADC-Trigger Selector ................................................................................................. 349
15.2.6 Synchronization Methods ......................................................................................................... 349
15.2.7 Fault Conditions ...................................................................................................................... 350
15.2.8 Output Control Block ............................................................................................................... 350
15.3 Initialization and Configuration ................................................................................................. 350
15.4 Register Map .......................................................................................................................... 351
15.5 Register Descriptions .............................................................................................................. 353
16 Quadrature Encoder Interface (QEI) ............................................................................... 382
16.1 Block Diagram ........................................................................................................................ 382
16.2 Functional Description ............................................................................................................. 383
16.3 Initialization and Configuration ................................................................................................. 385
16.4 Register Map .......................................................................................................................... 385
16.5 Register Descriptions .............................................................................................................. 386
17 Pin Diagram ...................................................................................................................... 399
18 Signal Tables .................................................................................................................... 400
19 Operating Characteristics ............................................................................................... 407
20 Electrical Characteristics ................................................................................................ 408
20.1 DC Characteristics .................................................................................................................. 408
20.1.1 Maximum Ratings ................................................................................................................... 408
20.1.2 Recommended DC Operating Conditions .................................................................................. 408
20.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 409
20.1.4 Power Specifications ............................................................................................................... 409
20.1.5 Flash Memory Characteristics .................................................................................................. 410
20.2 AC Characteristics ................................................................................................................... 410
20.2.1 Load Conditions ...................................................................................................................... 410
20.2.2 Clocks .................................................................................................................................... 410
20.2.3 Analog-to-Digital Converter ...................................................................................................... 411
20.2.4 Analog Comparator ................................................................................................................. 411
20.2.5 Synchronous Serial Interface (SSI) ........................................................................................... 412
20.2.6 JTAG and Boundary Scan ........................................................................................................ 413
20.2.7 General-Purpose I/O ............................................................................................................... 414
20.2.8 Reset ..................................................................................................................................... 415
21 Package Information ........................................................................................................ 418
A Serial Flash Loader .......................................................................................................... 420
A.1 Serial Flash Loader ................................................................................................................. 420
A.2 Interfaces ............................................................................................................................... 420
A.2.1 UART ..................................................................................................................................... 420
A.2.2 SSI ......................................................................................................................................... 420
A.3 Packet Handling ...................................................................................................................... 421
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A.3.1 Packet Format ........................................................................................................................ 421
A.3.2 Sending Packets ..................................................................................................................... 421
A.3.3 Receiving Packets ................................................................................................................... 421
A.4 Commands ............................................................................................................................. 422
A.4.1 COMMAND_PING (0X20) ........................................................................................................ 422
A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 422
A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 422
A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 423
A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 423
A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 423
B Register Quick Reference ............................................................................................... 425
C Ordering and Contact Information ................................................................................. 440
C.1 Ordering Information ................................................................................................................ 440
C.2 Kits ......................................................................................................................................... 440
C.3 Company Information .............................................................................................................. 440
C.4 Support Information ................................................................................................................. 441
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Table of Contents
List of Figures
Figure 1-1. Stellaris®600 Series High-Level Block Diagram ................................................................ 26
Figure 1-2. LM3S618 Controller System-Level Block Diagram ............................................................. 33
Figure 2-1. CPU Block Diagram ......................................................................................................... 35
Figure 2-2. TPIU Block Diagram ........................................................................................................ 36
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 45
Figure 5-2. Test Access Port State Machine ....................................................................................... 48
Figure 5-3. IDCODE Register Format ................................................................................................. 52
Figure 5-4. BYPASS Register Format ................................................................................................ 52
Figure 5-5. Boundary Scan Register Format ....................................................................................... 53
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 55
Figure 6-2. Main Clock Tree .............................................................................................................. 58
Figure 7-1. Flash Block Diagram ...................................................................................................... 113
Figure 8-1. GPIO Module Block Diagram .......................................................................................... 130
Figure 8-2. GPIO Port Block Diagram ............................................................................................... 131
Figure 8-3. GPIODATA Write Example ............................................................................................. 132
Figure 8-4. GPIODATA Read Example ............................................................................................. 132
Figure 9-1. GPTM Module Block Diagram ........................................................................................ 169
Figure 9-2. 16-Bit Input Edge Count Mode Example .......................................................................... 173
Figure 9-3. 16-Bit Input Edge Time Mode Example ........................................................................... 174
Figure 9-4. 16-Bit PWM Mode Example ............................................................................................ 175
Figure 10-1. WDT Module Block Diagram .......................................................................................... 204
Figure 11-1. ADC Module Block Diagram ........................................................................................... 228
Figure 11-2. Internal Temperature Sensor Characteristic ..................................................................... 231
Figure 12-1. UART Module Block Diagram ......................................................................................... 261
Figure 12-2. UART Character Frame ................................................................................................. 262
Figure 13-1. SSI Module Block Diagram ............................................................................................. 298
Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 300
Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 301
Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 302
Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 302
Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 303
Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 304
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 304
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 305
Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 306
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 307
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 307
Figure 14-1. Analog Comparator Module Block Diagram ..................................................................... 335
Figure 14-2. Structure of Comparator Unit .......................................................................................... 336
Figure 14-3. Comparator Internal Reference Structure ........................................................................ 337
Figure 15-1. PWM Module Block Diagram .......................................................................................... 346
Figure 15-2. PWM Count-Down Mode ................................................................................................ 347
Figure 15-3. PWM Count-Up/Down Mode .......................................................................................... 348
Figure 15-4. PWM Generation Example In Count-Up/Down Mode ....................................................... 348
Figure 15-5. PWM Dead-Band Generator ........................................................................................... 349
Figure 16-1. QEI Block Diagram ........................................................................................................ 382
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LM3S618 Microcontroller
Figure 16-2. Quadrature Encoder and Velocity Predivider Operation .................................................... 384
Figure 17-1. Pin Connection Diagram ................................................................................................ 399
Figure 20-1. Load Conditions ............................................................................................................ 410
Figure 20-2. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 412
Figure 20-3. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 412
Figure 20-4. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 413
Figure 20-5. JTAG Test Clock Input Timing ......................................................................................... 414
Figure 20-6. JTAG Test Access Port (TAP) Timing .............................................................................. 414
Figure 20-7. JTAG TRST Timing ........................................................................................................ 414
Figure 20-8. External Reset Timing (RST) .......................................................................................... 415
Figure 20-9. Power-On Reset Timing ................................................................................................. 416
Figure 20-10. Brown-Out Reset Timing ................................................................................................ 416
Figure 20-11. Software Reset Timing ................................................................................................... 416
Figure 20-12. Watchdog Reset Timing ................................................................................................. 417
Figure 20-13. LDO Reset Timing ......................................................................................................... 417
Figure 21-1. 48-Pin LQFP Package ................................................................................................... 418
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Table of Contents
List of Tables
Table 1. Documentation Conventions ............................................................................................ 18
Table 3-1. Memory Map ................................................................................................................... 40
Table 4-1. Exception Types .............................................................................................................. 42
Table 4-2. Interrupts ........................................................................................................................ 43
Table 5-1. JTAG Port Pins Reset State ............................................................................................. 46
Table 5-2. JTAG Instruction Register Commands ............................................................................... 50
Table 6-1. System Control Register Map ........................................................................................... 61
Table 6-2. PLL Mode Control ........................................................................................................... 76
Table 7-1. Flash Protection Policy Combinations ............................................................................. 115
Table 7-2. Flash Register Map ........................................................................................................ 118
Table 8-1. GPIO Pad Configuration Examples ................................................................................. 133
Table 8-2. GPIO Interrupt Configuration Example ............................................................................ 134
Table 8-3. GPIO Register Map ....................................................................................................... 135
Table 9-1. Available CCP Pins ........................................................................................................ 169
Table 9-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 172
Table 9-3. Timers Register Map ...................................................................................................... 178
Table 10-1. Watchdog Timer Register Map ........................................................................................ 205
Table 11-1. Samples and FIFO Depth of Sequencers ........................................................................ 228
Table 11-2. ADC Register Map ......................................................................................................... 232
Table 12-1. UART Register Map ....................................................................................................... 265
Table 13-1. SSI Register Map .......................................................................................................... 308
Table 14-1. Comparator 0 Operating Modes ...................................................................................... 336
Table 14-2. Internal Reference Voltage and ACREFCTL Field Values ................................................. 337
Table 14-3. Analog Comparators Register Map ................................................................................. 338
Table 15-1. PWM Register Map ........................................................................................................ 351
Table 16-1. QEI Register Map .......................................................................................................... 385
Table 18-1. Signals by Pin Number ................................................................................................... 400
Table 18-2. Signals by Signal Name ................................................................................................. 402
Table 18-3. Signals by Function, Except for GPIO ............................................................................. 404
Table 18-4. GPIO Pins and Alternate Functions ................................................................................. 405
Table 19-1. Temperature Characteristics ........................................................................................... 407
Table 19-2. Thermal Characteristics ................................................................................................. 407
Table 20-1. Maximum Ratings .......................................................................................................... 408
Table 20-2. Recommended DC Operating Conditions ........................................................................ 408
Table 20-3. LDO Regulator Characteristics ....................................................................................... 409
Table 20-4. Detailed Power Specifications ........................................................................................ 409
Table 20-5. Flash Memory Characteristics ........................................................................................ 410
Table 20-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 410
Table 20-7. Clock Characteristics ..................................................................................................... 410
Table 20-8. ADC Characteristics ....................................................................................................... 411
Table 20-9. Analog Comparator Characteristics ................................................................................. 411
Table 20-10. Analog Comparator Voltage Reference Characteristics .................................................... 411
Table 20-11. SSI Characteristics ........................................................................................................ 412
Table 20-12. JTAG Characteristics ..................................................................................................... 413
Table 20-13. GPIO Characteristics ..................................................................................................... 415
Table 20-14. Reset Characteristics ..................................................................................................... 415
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LM3S618 Microcontroller
Table C-1. Part Ordering Information ............................................................................................... 440
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Table of Contents
List of Registers
System Control .............................................................................................................................. 54
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 63
Register 2: Power-On and Brown-Out Reset Control (PBORCTL), offset 0x030 .................................... 65
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 66
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 67
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 68
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 70
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 71
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 72
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 77
Register 10: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 78
Register 11: Clock Verification Clear (CLKVCLR), offset 0x150 ............................................................. 79
Register 12: Allow Unregulated LDO to Reset the Part (LDOARST), offset 0x160 ................................... 80
Register 13: Device Identification 1 (DID1), offset 0x004 ....................................................................... 81
Register 14: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 83
Register 15: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 84
Register 16: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 86
Register 17: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 88
Register 18: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 90
Register 19: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 91
Register 20: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 93
Register 21: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 95
Register 22: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 97
Register 23: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................. 99
Register 24: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 101
Register 25: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 103
Register 26: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 105
Register 27: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 107
Register 28: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 109
Register 29: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 110
Register 30: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 112
Internal Memory ........................................................................................................................... 113
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 119
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 120
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 121
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 123
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 124
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 125
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 126
Register 8: Flash Memory Protection Read Enable (FMPRE), offset 0x130 ......................................... 127
Register 9: Flash Memory Protection Program Enable (FMPPE), offset 0x134 .................................... 128
General-Purpose Input/Outputs (GPIOs) ................................................................................... 129
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 137
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 138
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 139
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LM3S618 Microcontroller
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 140
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 141
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 142
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 143
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 144
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 145
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 146
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 148
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 149
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 150
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 151
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 152
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 153
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 154
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 155
Register 19: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 156
Register 20: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 157
Register 21: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 158
Register 22: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 159
Register 23: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 160
Register 24: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 161
Register 25: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 162
Register 26: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 163
Register 27: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 164
Register 28: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 165
Register 29: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 166
Register 30: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 167
General-Purpose Timers ............................................................................................................. 168
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 180
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 181
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 183
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 185
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 188
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 190
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 191
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 192
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 194
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 195
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 196
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 197
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 198
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 199
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 200
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 201
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 202
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 203
Watchdog Timer ........................................................................................................................... 204
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 207
Preliminary
13November 29, 2007
Table of Contents
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 208
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 209
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 210
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 211
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 212
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 213
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 214
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 215
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 216
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 217
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 218
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 219
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 220
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 221
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 222
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 223
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 224
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 225
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 226
Analog-to-Digital Converter (ADC) ............................................................................................. 227
Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 ............................................. 234
Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 ........................................................... 235
Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 ..................................................................... 236
Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C .................................................. 237
Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 ............................................................ 238
Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 ................................................. 239
Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 ........................................................... 242
Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 ............................................. 243
Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 ................................. 244
Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 ................................................. 245
Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 ............... 246
Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 ........................................ 248
Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 ................................ 251
Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 ................................ 251
Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 ................................ 251
Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 ............................... 251
Register 17: ADC Sample Sequence FIFO 0 Status (ADCSSFSTAT0), offset 0x04C ............................. 252
Register 18: ADC Sample Sequence FIFO 1 Status (ADCSSFSTAT1), offset 0x06C ............................. 252
Register 19: ADC Sample Sequence FIFO 2 Status (ADCSSFSTAT2), offset 0x08C ............................ 252
Register 20: ADC Sample Sequence FIFO 3 Status (ADCSSFSTAT3), offset 0x0AC ............................ 252
Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 ............... 253
Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 ............... 253
Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 ........................................ 254
Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 ........................................ 254
Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 ............... 256
Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 ........................................ 257
Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 ....................................................... 258
Preliminary
November 29, 200714
LM3S618 Microcontroller
Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 260
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 267
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 269
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 271
Register 4: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 273
Register 5: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 274
Register 6: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 275
Register 7: UART Control (UARTCTL), offset 0x030 ......................................................................... 277
Register 8: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 278
Register 9: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 280
Register 10: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 282
Register 11: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 283
Register 12: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 284
Register 13: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 286
Register 14: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 287
Register 15: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 288
Register 16: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 289
Register 17: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 290
Register 18: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 291
Register 19: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 292
Register 20: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 293
Register 21: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 294
Register 22: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 295
Register 23: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 296
Register 24: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 297
Synchronous Serial Interface (SSI) ............................................................................................ 298
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 310
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 312
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 314
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 315
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 317
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 318
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 320
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 321
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 322
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 323
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 324
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 325
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 326
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 327
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 328
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 329
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 330
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 331
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 332
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 333
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 334
Preliminary
15November 29, 2007
Table of Contents
Analog Comparator ..................................................................................................................... 335
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 339
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 340
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 341
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 342
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 343
Register 6: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 344
Pulse Width Modulator (PWM) .................................................................................................... 346
Register 1: PWM Master Control (PWMCTL), offset 0x000 ................................................................ 354
Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 ........................................................... 355
Register 3: PWM Output Enable (PWMENABLE), offset 0x008 .......................................................... 356
Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C ....................................................... 357
Register 5: PWM Output Fault (PWMFAULT), offset 0x010 ................................................................ 358
Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 ........................................................... 359
Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 ........................................................ 360
Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C ................................................ 361
Register 9: PWM Status (PWMSTATUS), offset 0x020 ...................................................................... 362
Register 10: PWM0 Control (PWM0CTL), offset 0x040 ....................................................................... 363
Register 11: PWM1 Control (PWM1CTL), offset 0x080 ....................................................................... 363
Register 12: PWM2 Control (PWM2CTL), offset 0x0C0 ...................................................................... 363
Register 13: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 .................................... 365
Register 14: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 .................................... 365
Register 15: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 .................................... 365
Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 .................................................... 367
Register 17: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 .................................................... 367
Register 18: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 ................................................... 367
Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C ........................................... 368
Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C ........................................... 368
Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC ........................................... 368
Register 22: PWM0 Load (PWM0LOAD), offset 0x050 ....................................................................... 369
Register 23: PWM1 Load (PWM1LOAD), offset 0x090 ....................................................................... 369
Register 24: PWM2 Load (PWM2LOAD), offset 0x0D0 ....................................................................... 369
Register 25: PWM0 Counter (PWM0COUNT), offset 0x054 ................................................................ 370
Register 26: PWM1 Counter (PWM1COUNT), offset 0x094 ................................................................ 370
Register 27: PWM2 Counter (PWM2COUNT), offset 0x0D4 ............................................................... 370
Register 28: PWM0 Compare A (PWM0CMPA), offset 0x058 ............................................................. 371
Register 29: PWM1 Compare A (PWM1CMPA), offset 0x098 ............................................................. 371
Register 30: PWM2 Compare A (PWM2CMPA), offset 0x0D8 ............................................................. 371
Register 31: PWM0 Compare B (PWM0CMPB), offset 0x05C ............................................................. 372
Register 32: PWM1 Compare B (PWM1CMPB), offset 0x09C ............................................................. 372
Register 33: PWM2 Compare B (PWM2CMPB), offset 0x0DC ............................................................ 372
Register 34: PWM0 Generator A Control (PWM0GENA), offset 0x060 ................................................ 373
Register 35: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 ................................................ 373
Register 36: PWM2 Generator A Control (PWM2GENA), offset 0x0E0 ................................................ 373
Register 37: PWM0 Generator B Control (PWM0GENB), offset 0x064 ................................................ 376
Register 38: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 ................................................ 376
Register 39: PWM2 Generator B Control (PWM2GENB), offset 0x0E4 ................................................ 376
Register 40: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 ................................................ 379
Preliminary
November 29, 200716
LM3S618 Microcontroller
Register 41: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 ................................................. 379
Register 42: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 ................................................ 379
Register 43: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C ............................. 380
Register 44: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC ............................. 380
Register 45: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC ............................. 380
Register 46: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 ............................. 381
Register 47: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 ............................. 381
Register 48: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 ............................. 381
Quadrature Encoder Interface (QEI) .......................................................................................... 382
Register 1: QEI Control (QEICTL), offset 0x000 ................................................................................ 387
Register 2: QEI Status (QEISTAT), offset 0x004 ................................................................................ 389
Register 3: QEI Position (QEIPOS), offset 0x008 .............................................................................. 390
Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C ....................................................... 391
Register 5: QEI Timer Load (QEILOAD), offset 0x010 ....................................................................... 392
Register 6: QEI Timer (QEITIME), offset 0x014 ................................................................................. 393
Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 ............................................................. 394
Register 8: QEI Velocity (QEISPEED), offset 0x01C .......................................................................... 395
Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 ............................................................... 396
Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 ............................................................. 397
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 ..................................................... 398
Preliminary
17November 29, 2007
About This Document
About This Document
This data sheet provides reference information for the LM3S618 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■
ARM® Cortex™-M3 Technical Reference Manual
■
ARM® CoreSight Technical Reference Manual
■
ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
■
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1 on page 18.
Table 1. Documentation Conventions
MeaningNotation
General Register Notation
REGISTER
offset 0xnnn
Register N
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
A single bit in a register.bit
Two or more consecutive and related bits.bit field
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 40.
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Preliminary
November 29, 200718
reserved
yy:xx
Register Bit/Field
Types
R/W1C
W1C
Reset Value
Pin/Signal Notation
assert a signal
SIGNAL
SIGNAL
Numbers
X
0x
LM3S618 Microcontroller
MeaningNotation
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 in
that register.
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC
Software can read this field. Always write the chip reset value.RO
Software can read or write this field.R/W
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
Only a write by software is valid; a read of the register returns no meaningful data.WO
This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/Field
Bit cleared to 0 on chip reset.0
Bit set to 1 on chip reset.1
Nondeterministic.-
Pin alternate function; a pin defaults to the signal without the brackets.[ ]
Refers to the physical connection on the package.pin
Refers to the electrical signal encoding of a pin.signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL
below).
Change the value of the signal from the logically True state to the logically False state.deassert a signal
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates that
it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1, and
so on.
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
All other numbers within register tables are assumed to be binary. Within conceptual information,
binary numbers are indicated with a b suffix, for example, 1011b, and decimal numbers are written
without a prefix or suffix.
Preliminary
19November 29, 2007
Architectural Overview
1 Architectural Overview
The Luminary Micro Stellaris®family of microcontrollers—the first ARM® Cortex™-M3 based
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
The LM3S618 microcontroller is targeted for industrial applications, including test and measurement
equipment, factory automation, HVAC and building control, motion control, medical instrumentation,
fire and security, and power/energy.
In addition, the LM3S618 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S618 microcontroller is code-compatible
to all members of the extensive Stellaris®family; providing flexibility to fit our customers' precise
needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development
boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong
support, sales, and distributor network.
1.1 Product Features
The LM3S618 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 50-MHz operation
– Hardware-division and single-cycle-multiplication
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 26 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ Internal Memory
November 29, 200720
Preliminary
LM3S618 Microcontroller
32 KB single-cycle flash–
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 8 KB single-cycle SRAM
■ General-Purpose Timers
– Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers.
Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
• To trigger analog-to-digital conversions
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
• ADC event trigger
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler
• Programmable one-shot timer
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
• ADC event trigger
– 16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
Preliminary
21November 29, 2007
Architectural Overview
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ Synchronous Serial Interface (SSI)
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ UART
– Two fully programmable 16C550-type UARTs
– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
– Programmable baud-rate generator with fractional divider
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start-bit detection
– Line-break generation and detection
■ ADC
– Single- and differential-input configurations
– Six 10-bit channels (inputs) when used as single-ended inputs
– Sample rate of 500 thousand samples/second
Preliminary
November 29, 200722
LM3S618 Microcontroller
– Flexible, configurable analog-to-digital conversion
– Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
– Each sequence triggered by software or internal event (timers, analog comparators, PWM
or GPIO)
– On-chip temperature sensor
■ Analog Comparators
– One integrated analog comparator
– Configurable for output to: drive an output pin, generate an interrupt, or initiate an ADC sample
sequence
– Compare external pin input to external pin input or to internal programmable voltage reference
■ PWM
– Three PWM generator blocks, each with one 16-bit counter, two comparators, a PWM
generator, and a dead-band generator
– One 16-bit counter
• Runs in Down or Up/Down mode
• Output frequency controlled by a 16-bit load value
• Load value updates can be synchronized
• Produces output signals at zero and load value
– Two PWM comparators
• Comparator value updates can be synchronized
• Produces output signals on match
– PWM generator
• Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
• Produces two independent PWM signals
– Dead-band generator
• Produces two PWM signals with programmable dead-band delays suitable for driving a
half-H bridge
• Can be bypassed, leaving input PWM signals unmodified
– Flexible output control block with PWM output enable of each PWM signal
Preliminary
23November 29, 2007
Architectural Overview
• PWM output enable of each PWM signal
• Optional output inversion of each PWM signal (polarity control)
• Optional fault handling for each PWM signal
• Synchronization of timers in the PWM generator blocks
• Synchronization of timer/comparator updates across the PWM generator blocks
• Interrupt status summary of the PWM generator blocks
– Can initiate an ADC sample sequence
■ QEI
– Hardware position integrator tracks the encoder position
– Velocity capture using built-in timer
– Interrupt generation on index pulse, velocity-timer expiration, direction change, and quadrature
error detection
■ GPIOs
– 0-30 GPIOs, depending on configuration
– 5-V-tolerant input/outputs
– Programmable interrupt generation as either edge-triggered or level-sensitive
– Bit masking in both read and write operations through address lines
– Can initiate an ADC sample sequence
– Programmable control for GPIO pad configuration:
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– User-enabled LDO unregulated voltage detection and automatic reset
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– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Additional Features
– Six reset sources
– Programmable clock source control
LM3S618 Microcontroller
– Clock gating to individual peripherals for power savings
– IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
– Debug access via JTAG and Serial Wire interfaces
– Full JTAG boundary scan
■ Industrial-range 48-pin RoHS-compliant LQFP package
1.2 Target Applications
■ Factory automation and control
■ Industrial control power devices
■ Building and home automation
■ Stepper motors
■ Brushless DC motors
■ AC induction motors
1.3 High-Level Block Diagram
Figure 1-1 on page 26 represents the full set of features in the Stellaris®600 series of devices; not
all features may be available on the LM3S618 microcontroller.
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Architectural Overview
Figure 1-1. Stellaris®600 Series High-Level Block Diagram
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S618 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in “Ordering and Contact Information” on page 440.
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Preliminary
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 34)
All members of the Stellaris®product family, including the LM3S618 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 34 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
LM3S618 Microcontroller
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.3 Nested Vectored Interrupt Controller (NVIC)
The LM3S618 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the ARM
Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions are
handled in Handler Mode. The processor state is automatically stored to the stack on an exception,
and automatically restored from the stack at the end of the Interrupt Service Routine (ISR). The
vector is fetched in parallel to the state saving, which enables efficient interrupt entry. The processor
supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead
of state saving and restoration. Software can set eight priority levels on 7 exceptions (system
handlers) and 26 interrupts.
“Interrupts” on page 42 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S618 controller features Pulse Width Modulation (PWM) outputs
and the Quadrature Encoder Interface (QEI).
1.4.2.1 PWM
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
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Architectural Overview
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
On the LM3S618, PWM motion control functionality can be achieved through:
■ Dedicated, flexible motion control hardware using the PWM pins
■ The motion control features of the general-purpose timers using the CCP pins
PWM Pins (see page 346)
The LM3S618 PWM module consists of three PWM generator blocks and a control block. Each
PWM generator block contains one timer (16-bit down or up/down counter), two comparators, a
PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector. The control
block determines the polarity of the PWM signals, and which signals are passed through to the pins.
Each PWM generator block produces two PWM signals that can either be independent signals or
a single pair of complementary signals with dead-band delays inserted. The output of the PWM
generation blocks are managed by the output control block before being passed to the device pins.
CCP Pins (see page 174)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
1.4.2.2 QEI (see page 382)
A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement
into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals,
you can track the position, direction of rotation, and speed. In addition, a third channel, or index
signal, can be used to reset the position counter.
The Stellaris quadrature encoder with index (QEI) module interprets the code produced by a
quadrature encoder wheel to integrate position over time and determine direction of rotation. In
addition, it can capture a running estimate of the velocity of the encoder wheel.
1.4.3 Analog Peripherals
To handle analog signals, the LM3S618 microcontroller offers an Analog-to-Digital Converter (ADC).
For support of analog signals, the LM3S618 microcontroller offers one analog comparator.
1.4.3.1 ADC (see page 227)
An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a
discrete digital number.
The LM3S618 ADC module features 10-bit conversion resolution and supports six input channels,
plus an internal temperature sensor. Four buffered sample sequences allow rapid sampling of up
to eight analog input sources without controller intervention. Each sample sequence provides flexible
programming with fully configurable input source, trigger events, interrupt generation, and sequence
priority.
1.4.3.2 Analog Comparators (see page 335)
An analog comparator is a peripheral that compares two analog voltages, and provides a logical
output that signals the comparison result.
A comparator can compare a test voltage against any one of these voltages:
Preliminary
November 29, 200728
■ An individual external reference voltage
■ A shared single external reference voltage
■ A shared internal reference voltage
The comparator can provide its output to a device pin, acting as a replacement for an analog
comparator on the board, or it can be used to signal the application via interrupts or triggers to the
ADC to cause it to start capturing a sample sequence. The interrupt generation and ADC triggering
logic is separate. This means, for example, that an interrupt can be generated on a rising edge and
the ADC triggered on a falling edge.
1.4.4 Serial Communications Peripherals
The LM3S618 controller supports both asynchronous and synchronous serial communications with:
■ Two fully programmable 16C550-type UARTs
■ One SSI module
1.4.4.1 UART (see page 260)
LM3S618 Microcontroller
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
The LM3S618 controller includes two fully programmable 16C550-type UARTs that support data
transfer speeds up to 460.8 Kbps. (Although similar in functionality to a 16C550 UART, it is not
register-compatible.)
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading.
The UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
1.4.4.2 SSI (see page 298)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The LM3S618 controller includes one SSI module that provides the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
The SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
The SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
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1.4.5 System Peripherals
1.4.5.1 Programmable GPIOs (see page 129)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.
The Stellaris®GPIO module is composed of five physical GPIO blocks, each corresponding to an
individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP
for Real-Time Microcontrollers specification) and supports 0-30 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page
400 for the signals available to each GPIO pin).
The GPIO module features programmable interrupt generation as either edge-triggered or
level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in
both read and write operations through address lines.
1.4.5.2 Three Programmable Timers (see page 168)
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris®General-Purpose Timer Module (GPTM) contains three GPTM blocks. Each GPTM
block provides two 16-bit timers/counters that can be configured to operate independently as timers
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
Timers can also be used to trigger analog-to-digital (ADC) conversions.
When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or
periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
1.4.5.3 Watchdog Timer (see page 204)
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or to the failure of an external device to respond in the expected way.
The Stellaris®Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
1.4.6 Memory Peripherals
The LM3S618 controller offers both single-cycle SRAM and single-cycle Flash memory.
1.4.6.1 SRAM (see page 113)
The LM3S618 static random access memory (SRAM) controller supports 8 KB SRAM. The internal
SRAM of the Stellaris®devices is located at offset 0x0000.0000 of the device memory map. To
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
Preliminary
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