TEXAS INSTRUMENTS LM3S2410 Technical data
PRELIMINARY
LM3S2410 Microcontroller
DATA SHEET
Copyright © 2007 Luminary Micro, Inc.DS-LM3S2410-03
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Preliminary
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LM3S2410 Microcontroller
Table of Contents
About This Document .................................................................................................................... 16
Audience .............................................................................................................................................. 16
About This Manual ................................................................................................................................ 16
Related Documents ............................................................................................................................... 16
Documentation Conventions .................................................................................................................. 16
1 Overview ............................................................................................................................. 18
1.1 Product Features ...................................................................................................................... 18
1.2 Target Applications .................................................................................................................... 22
1.3 High-Level Block Diagram ......................................................................................................... 22
1.4 Functional Overview .................................................................................................................. 23
1.4.1 ARM Cortex™-M3 ..................................................................................................................... 24
1.4.2 Motor Control Peripherals .......................................................................................................... 24
1.4.3 Serial Communications Peripherals ............................................................................................ 25
1.4.4 System Peripherals ................................................................................................................... 26
1.4.5 Memory Peripherals .................................................................................................................. 26
1.4.6 Additional Features ................................................................................................................... 27
1.4.7 Hardware Details ...................................................................................................................... 28
2 Cortex-M3 Core .................................................................................................................. 29
2.1 Block Diagram .......................................................................................................................... 30
2.2 Functional Description ............................................................................................................... 30
2.2.1 Serial Wire and JTAG Debug ..................................................................................................... 30
2.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 31
2.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 31
2.2.4 ROM Table ............................................................................................................................... 31
2.2.5 Memory Protection Unit (MPU) ................................................................................................... 31
2.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 31
3 Memory Map ....................................................................................................................... 35
4 Interrupts ............................................................................................................................ 37
5 JTAG .................................................................................................................................... 39
5.1 Block Diagram .......................................................................................................................... 40
5.2 Functional Description ............................................................................................................... 40
5.2.1 JTAG Interface Pins .................................................................................................................. 41
5.2.2 JTAG TAP Controller ................................................................................................................. 42
5.2.3 Shift Registers .......................................................................................................................... 43
5.2.4 Operational Considerations ........................................................................................................ 43
5.3 Initialization and Configuration ................................................................................................... 46
5.4 Register Descriptions ................................................................................................................ 46
5.4.1 Instruction Register (IR) ............................................................................................................. 46
5.4.2 Data Registers .......................................................................................................................... 48
6 System Control ................................................................................................................... 50
6.1 Functional Description ............................................................................................................... 50
6.1.1 Device Identification .................................................................................................................. 50
6.1.2 Reset Control ............................................................................................................................ 50
6.1.3 Power Control ........................................................................................................................... 53
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6.1.4 Clock Control ............................................................................................................................ 53
6.1.5 System Control ......................................................................................................................... 55
6.2 Initialization and Configuration ................................................................................................... 55
6.3 Register Map ............................................................................................................................ 56
6.4 Register Descriptions ................................................................................................................ 57
7 Internal Memory ................................................................................................................. 99
7.1 Block Diagram .......................................................................................................................... 99
7.2 Functional Description ............................................................................................................... 99
7.2.1 SRAM Memory ......................................................................................................................... 99
7.2.2 Flash Memory ......................................................................................................................... 100
7.3 Flash Memory Initialization and Configuration ........................................................................... 101
7.3.1 Flash Programming ................................................................................................................. 101
7.3.2 Nonvolatile Register Programming ........................................................................................... 102
7.4 Register Map .......................................................................................................................... 102
7.5 Flash Control Offset ................................................................................................................. 103
7.6 System Control Offset .............................................................................................................. 110
8 GPIO .................................................................................................................................. 123
8.1 Function Description ................................................................................................................ 123
8.1.1 Data Control ........................................................................................................................... 123
8.1.2 Interrupt Control ...................................................................................................................... 124
8.1.3 Mode Control .......................................................................................................................... 125
8.1.4 Commit Control ....................................................................................................................... 125
8.1.5 Pad Control ............................................................................................................................. 125
8.1.6 Identification ........................................................................................................................... 125
8.2 Initialization and Configuration ................................................................................................. 125
8.3 Register Map .......................................................................................................................... 126
8.4 Register Descriptions .............................................................................................................. 128
9 Timers ............................................................................................................................... 163
9.1 Block Diagram ........................................................................................................................ 164
9.2 Functional Description ............................................................................................................. 164
9.2.1 GPTM Reset Conditions .......................................................................................................... 164
9.2.2 32-Bit Timer Operating Modes .................................................................................................. 164
9.2.3 16-Bit Timer Operating Modes .................................................................................................. 166
9.3 Initialization and Configuration ................................................................................................. 170
9.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 170
9.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 171
9.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 171
9.3.4 16-Bit Input Edge Count Mode ................................................................................................. 172
9.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 172
9.3.6 16-Bit PWM Mode ................................................................................................................... 173
9.4 Register Map .......................................................................................................................... 173
9.5 Register Descriptions .............................................................................................................. 174
10 Watchdog Timer ............................................................................................................... 196
10.1 Block Diagram ........................................................................................................................ 196
10.2 Functional Description ............................................................................................................. 196
10.3 Initialization and Configuration ................................................................................................. 197
10.4 Register Map .......................................................................................................................... 197
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10.5 Register Descriptions .............................................................................................................. 198
11 UART ................................................................................................................................. 219
11.1 Block Diagram ........................................................................................................................ 220
11.2 Functional Description ............................................................................................................. 220
11.2.1 Transmit/Receive Logic ........................................................................................................... 220
11.2.2 Baud-Rate Generation ............................................................................................................. 221
11.2.3 Data Transmission .................................................................................................................. 222
11.2.4 Serial IR (SIR) ......................................................................................................................... 222
11.2.5 FIFO Operation ....................................................................................................................... 223
11.2.6 Interrupts ................................................................................................................................ 223
11.2.7 Loopback Operation ................................................................................................................ 224
11.2.8 IrDA SIR block ........................................................................................................................ 224
11.3 Initialization and Configuration ................................................................................................. 224
11.4 Register Map .......................................................................................................................... 225
11.5 Register Descriptions .............................................................................................................. 226
12 SSI ..................................................................................................................................... 259
12.1 Block Diagram ........................................................................................................................ 259
12.2 Functional Description ............................................................................................................. 259
12.2.1 Bit Rate Generation ................................................................................................................. 260
12.2.2 FIFO Operation ....................................................................................................................... 260
12.2.3 Interrupts ................................................................................................................................ 260
12.2.4 Frame Formats ....................................................................................................................... 261
12.3 Initialization and Configuration ................................................................................................. 268
12.4 Register Map .......................................................................................................................... 269
12.5 Register Descriptions .............................................................................................................. 270
13 CAN ................................................................................................................................... 293
13.1 Controller Area Network Overview ............................................................................................ 293
13.2 Controller Area Network Features ............................................................................................ 293
13.3 Controller Area Network Block Diagram .................................................................................... 294
13.4 Controller Area Network Functional Description ......................................................................... 295
13.4.1 Initialization ............................................................................................................................. 295
13.4.2 Operation ............................................................................................................................... 296
13.4.3 Transmitting Message Objects ................................................................................................. 296
13.4.4 Configuring a Transmit Message Object .................................................................................... 296
13.4.5 Updating a Transmit Message Object ....................................................................................... 297
13.4.6 Accepting Received Message Objects ...................................................................................... 297
13.4.7 Receiving a Data Frame .......................................................................................................... 298
13.4.8 Receiving a Remote Frame ...................................................................................................... 298
13.4.9 Receive/Transmit Priority ......................................................................................................... 298
13.4.10 Configuring a Receive Message Object .................................................................................... 298
13.4.11 Handling of Received Message Objects .................................................................................... 299
13.4.12 Handling of Interrupts .............................................................................................................. 299
13.4.13 Bit Timing Configuration Error Considerations ........................................................................... 300
13.4.14 Bit Time and Bit Rate ............................................................................................................... 300
13.4.15 Calculating the Bit Timing Parameters ...................................................................................... 302
13.5 Controller Area Network Register Map ...................................................................................... 304
13.6 Register Descriptions .............................................................................................................. 306
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14 Analog Comparators ....................................................................................................... 337
14.1 Block Diagram ........................................................................................................................ 337
14.2 Functional Description ............................................................................................................. 337
14.2.1 Internal Reference Programming .............................................................................................. 339
14.3 Initialization and Configuration ................................................................................................. 340
14.4 Register Map .......................................................................................................................... 340
14.5 Register Descriptions .............................................................................................................. 341
15 Pin Diagram ...................................................................................................................... 349
16 Signal Tables .................................................................................................................... 350
17 Operating Characteristics ............................................................................................... 362
18 Electrical Characteristics ................................................................................................ 363
18.1 DC Characteristics .................................................................................................................. 363
18.1.1 Maximum Ratings ................................................................................................................... 363
18.1.2 Recommended DC Operating Conditions .................................................................................. 363
18.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 364
18.1.4 Power Specifications ............................................................................................................... 364
18.1.5 Flash Memory Characteristics .................................................................................................. 365
18.2 AC Characteristics ................................................................................................................... 366
18.2.1 Load Conditions ...................................................................................................................... 366
18.2.2 Clocks .................................................................................................................................... 366
18.2.3 Analog Comparator ................................................................................................................. 367
18.2.4 Synchronous Serial Interface (SSI) ........................................................................................... 367
18.2.5 JTAG and Boundary Scan ........................................................................................................ 369
18.2.6 General-Purpose I/O ............................................................................................................... 370
18.2.7 Reset ..................................................................................................................................... 371
19 Package Information ........................................................................................................ 373
A Serial Flash Loader .......................................................................................................... 375
A.1 Serial Flash Loader ................................................................................................................. 375
A.2 Interfaces ............................................................................................................................... 375
A.2.1 UART ..................................................................................................................................... 375
A.2.2 SSI ......................................................................................................................................... 375
A.3 Packet Handling ...................................................................................................................... 376
A.3.1 Packet Format ........................................................................................................................ 376
A.3.2 Sending Packets ..................................................................................................................... 376
A.3.3 Receiving Packets ................................................................................................................... 376
A.4 Commands ............................................................................................................................. 377
A.4.1 COMMAND_PING (0X20) ........................................................................................................ 377
A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 377
A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 377
A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 378
A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 378
A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 378
B Ordering Information ....................................................................................................... 380
B.1 Ordering Information ................................................................................................................ 380
B.2 Company Information .............................................................................................................. 380
B.3 Support Information ................................................................................................................. 380
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LM3S2410 Microcontroller
List of Figures
Figure 1-1. Stellaris® Fury-class High-Level Block Diagram ................................................................ 23
Figure 2-1. CPU Block Diagram ......................................................................................................... 30
Figure 2-2. TPIU Block Diagram ........................................................................................................ 31
Figure 5-1. JTAG Module Block Diagram ............................................................................................ 40
Figure 5-2. Test Access Port State Machine ....................................................................................... 43
Figure 5-3. IDCODE Register Format ................................................................................................. 48
Figure 5-4. BYPASS Register Format ................................................................................................ 49
Figure 5-5. Boundary Scan Register Format ....................................................................................... 49
Figure 6-1. External Circuitry to Extend Reset .................................................................................... 51
Figure 7-1. Flash Block Diagram ........................................................................................................ 99
Figure 8-1. GPIODATA Write Example ............................................................................................. 124
Figure 8-2. GPIODATA Read Example ............................................................................................. 124
Figure 9-1. GPTM Module Block Diagram ........................................................................................ 164
Figure 9-2. 16-Bit Input Edge Count Mode Example .......................................................................... 168
Figure 9-3. 16-Bit Input Edge Time Mode Example ........................................................................... 169
Figure 9-4. 16-Bit PWM Mode Example ............................................................................................ 170
Figure 10-1. WDT Module Block Diagram .......................................................................................... 196
Figure 11-1. UART Module Block Diagram ......................................................................................... 220
Figure 11-2. UART Character Frame ................................................................................................. 221
Figure 11-3. IrDA Data Modulation ..................................................................................................... 223
Figure 12-1. SSI Module Block Diagram ............................................................................................. 259
Figure 12-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 262
Figure 12-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 262
Figure 12-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 263
Figure 12-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 263
Figure 12-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 264
Figure 12-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 265
Figure 12-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 265
Figure 12-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 266
Figure 12-10. MICROWIRE Frame Format (Single Frame) .................................................................... 267
Figure 12-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 268
Figure 12-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 268
Figure 13-1. CAN Module Block Diagram ........................................................................................... 294
Figure 13-2. CAN Bit Time ................................................................................................................ 301
Figure 14-1. Analog Comparator Module Block Diagram ..................................................................... 337
Figure 14-2. Structure of Comparator Unit .......................................................................................... 338
Figure 14-3. Comparator Internal Reference Structure ........................................................................ 339
Figure 15-1. Pin Connection Diagram ................................................................................................ 349
Figure 18-1. Load Conditions ............................................................................................................ 366
Figure 18-2. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 368
Figure 18-3. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 368
Figure 18-4. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 369
Figure 18-5. JTAG Test Clock Input Timing ......................................................................................... 370
Figure 18-6. JTAG Test Access Port (TAP) Timing .............................................................................. 370
Figure 18-7. JTAG TRST Timing ........................................................................................................ 370
Figure 18-8. External Reset Timing (RST) .......................................................................................... 371
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Figure 18-9. Power-On Reset Timing ................................................................................................. 372
Figure 18-10. Brown-Out Reset Timing ................................................................................................ 372
Figure 18-11. Software Reset Timing ................................................................................................... 372
Figure 18-12. Watchdog Reset Timing ................................................................................................. 372
Figure 19-1. 100-Pin LQFP Package .................................................................................................. 373
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LM3S2410 Microcontroller
List of Tables
Table 1. Documentation Conventions ............................................................................................ 16
Table 3-1. Memory Map ................................................................................................................... 35
Table 4-1. Exception Types .............................................................................................................. 37
Table 4-2. Interrupts ........................................................................................................................ 38
Table 5-1. JTAG Port Pins Reset State ............................................................................................. 41
Table 5-2. JTAG Instruction Register Commands ............................................................................... 46
Table 6-1. System Control Register Map ........................................................................................... 56
Table 6-2. VADJ to VOUT ................................................................................................................ 61
Table 6-3. Default Crystal Field Values and PLL Programming ........................................................... 68
Table 7-1. Flash Protection Policy Combinations ............................................................................. 101
Table 7-2. Flash Resident Registers ............................................................................................... 102
Table 7-3. Internal Memory Register Map ........................................................................................ 102
Table 8-1. GPIO Pad Configuration Examples ................................................................................. 126
Table 8-2. GPIO Interrupt Configuration Example ............................................................................ 126
Table 8-3. GPIO Register Map ....................................................................................................... 127
Table 9-1. 16-Bit Timer With Prescaler Configurations ..................................................................... 167
Table 9-2. Timers Register Map ...................................................................................................... 173
Table 10-1. Watchdog Timer Register Map ........................................................................................ 197
Table 11-1. UART Register Map ....................................................................................................... 225
Table 12-1. SSI Register Map .......................................................................................................... 269
Table 13-1. Transmit Message Object Bit Settings ............................................................................. 297
Table 13-2. Receive Message Object Bit Settings .............................................................................. 299
Table 13-3. CAN Protocol Ranges .................................................................................................... 301
Table 13-4. CAN Register Map ......................................................................................................... 304
Table 14-1. Comparator 0 Operating Modes ..................................................................................... 338
Table 14-2. Comparator 1 Operating Modes ...................................................................................... 339
Table 14-3. Internal Reference Voltage and ACREFCTL Field Values ................................................. 339
Table 14-4. Analog Comparators Register Map ................................................................................. 341
Table 16-1. Signals by Pin Number ................................................................................................... 350
Table 16-2. Signals by Signal Name ................................................................................................. 353
Table 16-3. Signals by Function, Except for GPIO ............................................................................. 357
Table 16-4. GPIO Pins and Alternate Functions ................................................................................. 359
Table 17-1. Temperature Characteristics ........................................................................................... 362
Table 17-2. Thermal Characteristics ................................................................................................. 362
Table 18-1. Maximum Ratings .......................................................................................................... 363
Table 18-2. Recommended DC Operating Conditions ........................................................................ 363
Table 18-3. LDO Regulator Characteristics ....................................................................................... 364
Table 18-4. Detailed Power Specifications ........................................................................................ 365
Table 18-5. Flash Memory Characteristics ........................................................................................ 365
Table 18-6. Phase Locked Loop (PLL) Characteristics ....................................................................... 366
Table 18-7. Clock Characteristics ..................................................................................................... 366
Table 18-8. Crystal Characteristics ................................................................................................... 366
Table 18-9. Analog Comparator Characteristics ................................................................................. 367
Table 18-10. Analog Comparator Voltage Reference Characteristics .................................................... 367
Table 18-11. SSI Characteristics ........................................................................................................ 367
Table 18-12. JTAG Characteristics ..................................................................................................... 369
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Table 18-13. GPIO Characteristics ..................................................................................................... 371
Table 18-14. Reset Characteristics ..................................................................................................... 371
Table B-1. Part Ordering Information ............................................................................................... 380
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LM3S2410 Microcontroller
List of Registers
System Control .............................................................................................................................. 50
Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 58
Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 60
Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 61
Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 62
Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 63
Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 64
Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 65
Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 66
Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 69
Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 70
Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 72
Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 73
Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 75
Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 76
Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 78
Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 79
Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 80
Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 81
Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 82
Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 83
Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 84
Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................. 86
Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ......................... 88
Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 .................................... 90
Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 .................................. 92
Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ......................... 94
Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................... 96
Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................... 97
Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................... 98
Internal Memory ............................................................................................................................. 99
Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 104
Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 105
Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 106
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 108
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 109
Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 110
Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 111
Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 112
Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 113
Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 114
Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 115
Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 116
Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 117
Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 118
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Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 119
Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 120
Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 121
Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 122
GPIO .............................................................................................................................................. 123
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 129
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 130
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 131
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 132
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 133
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 134
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 135
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 136
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 137
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 138
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 140
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 141
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 142
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 143
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 144
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 145
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 146
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 147
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 148
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 149
Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 151
Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 152
Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 153
Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 154
Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 155
Register 26: GPIO Peripheral Identification 1(GPIOPeriphID1), offset 0xFE4 ........................................ 156
Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 157
Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 158
Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 159
Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 160
Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 161
Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 162
Timers ........................................................................................................................................... 163
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 175
Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 176
Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 177
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 178
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 180
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 182
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 183
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 184
Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 186
Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 187
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LM3S2410 Microcontroller
Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 188
Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 189
Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 190
Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 191
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 192
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 193
Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 194
Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 195
Watchdog Timer ........................................................................................................................... 196
Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 199
Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 200
Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 201
Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 202
Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 203
Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 204
Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 205
Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 206
Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 207
Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 208
Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 209
Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 210
Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 211
Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 212
Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 213
Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 214
Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 215
Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 216
Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 217
Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 218
UART ............................................................................................................................................. 219
Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 227
Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 229
Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 231
Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 233
Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 234
Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 235
Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 236
Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 238
Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 240
Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 241
Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 243
Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 244
Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 245
Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 247
Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 248
Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 249
Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 250
Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 251
Preliminary
13June 26, 2007
Table of Contents
Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 252
Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 253
Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 254
Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 255
Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 256
Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 257
Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 258
SSI ................................................................................................................................................. 259
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 271
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 273
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 274
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 275
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 276
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 277
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 278
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 279
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 280
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 281
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 282
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 283
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 284
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 285
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 286
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 287
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 288
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 289
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 290
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 291
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 292
CAN ............................................................................................................................................... 293
Register 1: CAN Control (CANCTL), offset 0x000 ............................................................................. 307
Register 2: CAN Status (CANSTS), offset 0x004 ............................................................................... 309
Register 3: CAN Error Counter (CANERR), offset 0x008 ................................................................... 312
Register 4: CAN Bit Timing (CANBIT), offset 0x00C .......................................................................... 313
Register 5: CAN Interrupt (CANINT), offset 0x010 ............................................................................. 315
Register 6: CAN Test (CANTST), offset 0x014 .................................................................................. 316
Register 7: CAN Baud Rate Prescalar Extension (CANBRPE), offset 0x018 ....................................... 318
Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 ................................................ 319
Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 ................................................ 319
Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 .................................................. 320
Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 .................................................. 320
Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 ................................................................ 323
Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 ................................................................ 323
Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C ................................................................ 324
Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C ................................................................ 324
Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 ......................................................... 325
Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 ......................................................... 325
Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 ......................................................... 326
Preliminary
June 26, 200714
LM3S2410 Microcontroller
Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 ......................................................... 326
Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 .................................................. 327
Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 .................................................. 327
Register 22: CAN IF1 Data A1 (CANIF1DA1), offset 0x03C ................................................................. 329
Register 23: CAN IF2 Data A1 (CANIF2DA1), offset 0x09C ................................................................. 329
Register 24: CAN IF1 Data A2 (CANIF1DA2), offset 0x040 ................................................................. 330
Register 25: CAN IF2 Data A2 (CANIF2DA2), offset 0x0A0 ................................................................. 330
Register 26: CAN IF1 Data B1 (CANIF1DB1), offset 0x044 ................................................................. 331
Register 27: CAN IF2 Data B1 (CANIF2DB1), offset 0x0A4 ................................................................. 331
Register 28: CAN IF1 Data B2 (CANIF1DB2), offset 0x048 ................................................................. 332
Register 29: CAN IF2 Data B2 (CANIF2DB2), offset 0x0A8 ................................................................. 332
Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 ................................................ 333
Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 ................................................ 333
Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. 334
Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. 334
Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... 335
Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 ..................................... 335
Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 ....................................................... 336
Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 ....................................................... 336
Analog Comparators ................................................................................................................... 337
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 342
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 343
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 344
Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 345
Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 346
Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 346
Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 347
Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 347
Preliminary
15June 26, 2007
About This Document
About This Document
This data sheet provides reference information for the LM3S2410 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
Audience
This manual is intended for system software developers, hardware designers, and application
developers.
About This Manual
This document is organized into sections that correspond to each major feature.
Related Documents
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■
ARM® Cortex™-M3 Technical Reference Manual
■
ARM® CoreSight Technical Reference Manual
■
ARM® v7-M Architecture Application Level Reference Manual
The following related documents are also referenced:
■
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
Documentation Conventions
This document uses the conventions shown in Table 1 on page 16.
Table 1. Documentation Conventions
MeaningNotation
General Register Notation
REGISTER
offset 0xnnn
Register N
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
A single bit in a register.bit
Two or more consecutive and related bits.bit field
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 35.
Registers are numbered consecutively throughout the document to aid in referencing them. The
register number has no meaning to software.
Preliminary
June 26, 200716
reserved
yy:xx
Register Bit/Field
Types
R/W1C
W1C
Reset Value
Pin/Signal Notation
assert a signal
SIGNAL
SIGNAL
Numbers
X
0x
LM3S2410 Microcontroller
MeaningNotation
Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to
0; however, user software should not rely on the value of a reserved bit. To provide software
compatibility with future products, the value of a reserved bit should be preserved across a
read-modify-write operation.
The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31
in that register.
This value in the register bit diagram indicates whether software running on the controller can
change the value of the bit field.
Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC
Software can read this field. Always write the chip reset value.RO
Software can read or write this field.R/W
Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in the
register. A write of a 1 clears the value of the bit in the register; the remaining bits remain
unchanged.
This register type is primarily used for clearing interrupt status bits where the read operation
provides the interrupt status and the write of the read value clears only the interrupts being reported
at the time the register was read.
Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.
A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. A
read of the register returns no meaningful data.
This register is typically used to clear the corresponding bit in an interrupt register.
Only a write by software is valid; a read of the register returns no meaningful data.WO
This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/Field
Bit cleared to 0 on chip reset.0
Bit set to 1 on chip reset.1
Nondeterministic.-
Pin alternate function; a pin defaults to the signal without the brackets.[ ]
Refers to the physical connection on the package.pin
Refers to the electrical signal encoding of a pin.signal
Change the value of the signal from the logically False state to the logically True state. For active
High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value
is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and
SIGNAL below).
Change the value of the signal from the logically True state to the logically False state.deassert a signal
Signal names are in uppercase and in the Courier font. An overbar on a signal name indicates
that it is active Low. To assert SIGNAL is to drive it Low; to deassert SIGNAL is to drive it High.
Signal names are in uppercase and in the Courier font. An active High signal has no overbar. To
assert SIGNAL is to drive it High; to deassert SIGNAL is to drive it Low.
An uppercase X indicates any of several values is allowed, where X can be any legal pattern. For
example, a binary value of 0X00 can be either 0100 or 0000, a hex value of 0xX is 0x0 or 0x1,
and so on.
Hexadecimal numbers have a prefix of 0x. For example, 0x00FF is the hexadecimal number FF.
Binary numbers are indicated with a b suffix, for example, 1011b. Decimal numbers are written
without a prefix or suffix.
Preliminary
17June 26, 2007
Architectural Overview
1 Architectural Overview
The Luminary Micro Stellaris®family of microcontrollers—the first ARM® Cortex™-M3 based
controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller
applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to
legacy 8- and 16-bit devices, all in a package with a small footprint.
The Stellaris®family offers efficient performance and extensive integration, favorably positioning
the device into cost-conscious applications requiring significant control-processing and connectivity
capabilities. The Stellaris®LM3S2000 series, designed for Controller Area Network (CAN)
applications, extends the Stellaris family with Bosch CAN networking technology, the golden standard
in short-haul industrial networks. The Stellaris®LM3S2000 series also marks the first integration of
CAN capabilities with the revolutionary Cortex-M3 core. The Stellaris®LM3S6000 series combines
both a 10/100 Ethernet Media Access Control (MAC) and Physical (PHY) layer, marking the first
time that integrated connectivity is available with an ARM Cortex-M3 MCU and the only integrated
10/100 Ethernet MAC and PHY available in an ARM architecture MCU.
The LM3S2410 microcontroller is targeted for industrial applications, including remote monitoring,
electronic point-of-sale machines, test and measurement equipment, network appliances and
switches, factory automation, HVAC and building control, gaming equipment, motion control, medical
instrumentation, and fire and security.
In addition, the LM3S2410 microcontroller offers the advantages of ARM's widely available
development tools, System-on-Chip (SoC) infrastructure IP applications, and a large user community.
Additionally, the microcontroller uses ARM's Thumb®-compatible Thumb-2 instruction set to reduce
memory requirements and, thereby, cost. Finally, the LM3S2410 microcontroller is code-compatible
to all members of the extensive Stellaris®family; providing flexibility to fit our customers' precise
needs.
Luminary Micro offers a complete solution to get to market quickly, with evaluation and development
boards, white papers and application notes, an easy-to-use peripheral driver library, and a strong
support, sales, and distributor network.
1.1 Product Features
The LM3S2410 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
applications
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero
counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 25-MHz operation
– Hardware-division and single-cycle-multiplication
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 22 interrupts with eight priority levels
June 26, 200718
Preliminary
LM3S2410 Microcontroller
– Memory protection unit (MPU), providing a privileged mode for protected operating system
functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined
peripheral control
■ Internal Memory
– 96 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 32 KB single-cycle SRAM
■ General-Purpose Timers
– Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit
timer/counters. Each GPTM can be configured to operate independently as timers or event
counters (eight total) as a single 32-bit timer (four total), as one 32-bit Real-Time Clock (RTC)
to event capture, or for Pulse Width Modulation (PWM)
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
• User-enabled stalling in periodic and one-shot mode when the controller asserts the CPU
Halt flag during debug
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler
• Programmable one-shot timer
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
– 16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
– 16-bit PWM mode
19June 26, 2007
Preliminary
Architectural Overview
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ Controller Area Network (CAN)
– Supports CAN protocol version 2.0 part A/B
– Bit rates up to 1Mb/s
– 32 message objects, each with its own identifier mask
– Maskable interrupt
– Disable automatic retransmission mode for TTCAN
– Programmable loop-back mode for self-test operation
■ Synchronous Serial Interface (SSI)
– Master or slave operation
– Programmable clock bit rate and prescale
– Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments
synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ UART
– Fully programmable 16C550-type UART with IrDA support
– Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs to reduce CPU interrupt service
loading
– Programmable baud-rate generator with fractional divider
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
June 26, 200720
Preliminary
LM3S2410 Microcontroller
– FIFO trigger levels of 1/8, ¼, ½, ¾, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– False-start-bit detection
– Line-break generation and detection
■ Analog Comparators
– Two independent integrated analog comparators
– Configurable for output to: drive an output pin or generate an interrupt
– Compare external pin input to external pin input or to internal programmable voltage reference
■ GPIOs
– 37-60 GPIOs, depending on configuration
– 5-V-tolerant input/outputs
– Programmable interrupt generation as either edge-triggered or level-sensitive
– Bit masking in both read and write operations through address lines
– Programmable control for GPIO pad configuration:
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable
from 2.25 V to 2.75 V
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– User-enabled LDO unregulated voltage detection and automatic reset
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
Preliminary
21June 26, 2007
Architectural Overview
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Additional Features
– Six reset sources
– Programmable clock source control
– Clock gating to individual peripherals for power savings
– IEEE 1149.1-1990 compliant Test Access Port (TAP) controller
– Debug access via JTAG and Serial Wire interfaces
– Full JTAG boundary scan
■ Industrial-range 100-pin RoHS-compliant LQFP package
1.2 Target Applications
■ Remote monitoring
■ Electronic point-of-sale (POS) machines
■ Test and measurement equipment
■ Network appliances and switches
■ Factory automation
■ HVAC and building control
■ Gaming equipment
■ Motion control
■ Medical instrumentation
■ Fire and security
■ Power and energy
■ Transportation
1.3 High-Level Block Diagram
Figure 1-1 on page 23 shows the features on the Stellaris® Fury-class family of devices.
Preliminary
June 26, 200722
Figure 1-1. Stellaris® Fury-class High-Level Block Diagram
LDO Voltage
Regulator
3 Analog
Comparators
ANALOG
10-bit ADC
8 channel
1 Msps
Temp Sensor
Clocks, Reset
System Control
4 Timer/PWM/CCP
Each 32-bit or 2x16-bit
Watchdog Timer
GPIOs
SYSTEM
Battery-Backed
Hibernate
R
T
C
Systick Timer
64 KB SRAM
256 KB Flash
2 Quadrature
Encoder Inputs
6 PWM Outputs
MOTION CONTROL
Dead-Band
Generator
Comparators
PWM
Generator
PWM
Interrupt
Timer
3 UARTs
2 SSI/SPI
10/100 Ethernet
MAC + PHY
2 CAN
2 I2C
SERIAL INTERFACES
ARM
®
Cortex™-M3
50 MHz
JTAG
NVIC
SWD
32
32
LM3S2410 Microcontroller
1.4 Functional Overview
The following sections provide an overview of the features of the LM3S2410 microcontroller. The
page number in parenthesis indicates where that feature is discussed in detail. Ordering and support
information can be found in Appendix B, Ordering and Contact Information on page 380.
Preliminary
23June 26, 2007
Architectural Overview
1.4.1 ARM Cortex™-M3
1.4.1.1 Processor Core (see page 29)
All members of the Stellaris®product family, including the LM3S2410 microcontroller, are designed
around an ARM Cortex™-M3 processor core. The ARM Cortex-M3 processor provides the core for
a high-performance, low-cost platform that meets the needs of minimal memory implementation,
reduced pin count, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
“ARM Cortex-M3 Processor Core” on page 29 provides an overview of the ARM core; the core is
detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.1.2 System Timer (SysTick)
Cortex-M3 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter
can be used in several different ways, for example:
■ An RTOS tick timer which fires at a programmable rate (for example, 100 Hz) and invokes a
SysTick routine.
■ A high-speed alarm timer using the system clock.
■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock
used and the dynamic range of the counter.
■ A simple counter. Software can use this to measure time to completion and time used.
■ An internal clock source control based on missing/meeting durations. The COUNTFLAG bit-field
in the control and status register can be used to determine if an action completed within a set
duration, as part of a dynamic clock management control loop.
1.4.1.3 Nested Vectored Interrupt Controller (NVIC)
The LM3S2410 controller includes the ARM Nested Vectored Interrupt Controller (NVIC) on the
ARM Cortex-M3 core. The NVIC and Cortex-M3 prioritize and handle all exceptions. All exceptions
are handled in Handler Mode. The processor state is automatically stored to the stack on an
exception, and automatically restored from the stack at the end of the Interrupt Service Routine
(ISR). The vector is fetched in parallel to the state saving, which enables efficient interrupt entry.
The processor supports tail-chaining, which enables back-to-back interrupts to be performed without
the overhead of state saving and restoration. Software can set eight priority levels on 7 exceptions
(system handlers) and 22 interrupts.
“Interrupts” on page 37 provides an overview of the NVIC controller and the interrupt map. Exceptions
and interrupts are detailed in the ARM® Cortex™-M3 Technical Reference Manual.
1.4.2 Motor Control Peripherals
To enhance motor control, the LM3S2410 controller features Pulse Width Modulation (PWM) outputs.
1.4.2.1 PWM (see page 169)
Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels.
High-resolution counters are used to generate a square wave, and the duty cycle of the square
wave is modulated to encode an analog signal. Typical applications include switching power supplies
and motor control.
June 26, 200724
Preliminary
On the LM3S2410, PWM motion control functionality can be achieved through the motion control
features of the general-purpose timers (using the CCP pins).
CCP Pins (see page 169)
The General-Purpose Timer Module's CCP (Capture Compare PWM) pins are software programmable
to support a simple PWM mode with a software-programmable output inversion of the PWM signal.
1.4.3 Serial Communications Peripherals
The LM3S2410 controller supports both asynchronous and synchronous serial communications
with:
■ One fully programmable 16C550-type UART
■ One SSI module
■ One CAN unit
1.4.3.1 UART (see page 219)
A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C
serial communications, containing a transmitter (parallel-to-serial converter) and a receiver
(serial-to-parallel converter), each clocked separately.
LM3S2410 Microcontroller
The LM3S2410 controller includes one fully programmable 16C550-type UARTthat supports data
transfer speeds up to 460.8 Kbps. In addition, each UART is capable of supporting IrDA. (Although
similar in functionality to a 16C550 UART, it is not register-compatible.)
Separate 16x8 transmit (TX) and 16x12 receive (RX) FIFOs reduce CPU interrupt service loading.
The UART can generate individually masked interrupts from the RX, TX, modem status, and error
conditions. The module provides a single combined interrupt when any of the interrupts are asserted
and are unmasked.
1.4.3.2 SSI (see page 259)
Synchronous Serial Interface (SSI) is a four-wire bi-directional communications interface.
The LM3S2410 controller includes one SSI module that provides the functionality for synchronous
serial communications with peripheral devices, and can be configured to use the Freescale SPI,
MICROWIRE, or TI synchronous serial interface frame formats. The size of the data frame is also
configurable, and can be set between 4 and 16 bits, inclusive.
The SSI module performs serial-to-parallel conversion on data received from a peripheral device,
and parallel-to-serial conversion on data transmitted to a peripheral device. The TX and RX paths
are buffered with internal FIFOs, allowing up to eight 16-bit values to be stored independently.
The SSI module can be configured as either a master or slave device. As a slave device, the SSI
module can also be configured to disable its output, which allows a master device to be coupled
with multiple slave devices.
The SSI module also includes a programmable bit rate clock divider and prescaler to generate the
output serial clock derived from the SSI module's input clock. Bit rates are generated based on the
input clock and the maximum bit rate is determined by the connected peripheral.
1.4.3.3 Controller Area Network (see page 293)
Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic
control units (ECUs). CAN was specifically designed to be robust in electromagnetically noisy
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25June 26, 2007
Architectural Overview
environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair
wire. Originally created for automotive purposes, now it is used in many embedded control
applications (for example, industrial or medical). Bit rates up to 1Mb/s are possible at network lengths
below 40 meters. Decreased bit rates allow longer network distances (for example, 125 Kb/s at
500m).
A transmitter sends a message to all CAN nodes (broadcasting). Each node decides on the basis
of the identifier received whether it should process the message. The identifier also determines the
priority that the message enjoys in competition for bus access. Each CAN message can transmit
from 0 to 8 bytes of user information. The LM3S2410 includes one CAN units.
1.4.4 System Peripherals
1.4.4.1 Programmable GPIOs (see page 123)
General-purpose input/output (GPIO) pins offer flexibility for a variety of connections.
The Stellaris®GPIO module is composed of eight physical GPIO blocks, each corresponding to an
individual GPIO port. The GPIO module is FiRM-compliant (compliant to the ARM Foundation IP
for Real-Time Microcontrollers specification) and supports 37-60 programmable input/output pins.
The number of GPIOs available depends on the peripherals being used (see “Signal Tables” on page
350 for the signals available to each GPIO pin).
The GPIO module features programmable interrupt generation as either edge-triggered or
level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in
both read and write operations through address lines.
1.4.4.2 Three Programmable Timers (see page 163)
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris®General-Purpose Timer Module (GPTM) contains three GPTM blocks. Each GPTM
block provides two 16-bit timer/counters that can be configured to operate independently as timers
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
When configured in 32-bit mode, a timer can run as a one-shot timer, periodic timer, or Real-Time
Clock (RTC). When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
1.4.4.3 Watchdog Timer (see page 196)
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or to the failure of an external device to respond in the expected way.
The Stellaris®Watchdog Timer module consists of a 32-bit down counter, a programmable load
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
1.4.5 Memory Peripherals
The LM3S2410 controller offers both SRAM and Flash memory.
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Preliminary
1.4.5.1 SRAM (see page 99)
The LM3S2410 static random access memory (SRAM) controller supports 32 KB SRAM. The internal
SRAM of the Stellaris®devices is located at offset 0x0000.0000 of the device memory map. To
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
1.4.5.2 Flash (see page 100)
The LM3S2410 Flash controller supports 96 KB of flash memory. The flash is organized as a set
of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
1.4.6 Additional Features
LM3S2410 Microcontroller
1.4.6.1 Memory Map (see page 35)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S2410 controller can be found in “Memory Map” on page 35. Register addresses are given as
a hexadecimal increment, relative to the module's base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory
map.
1.4.6.2 JTAG TAP Controller (see page 39)
The Joint Test Action Group (JTAG) port provides a standardized serial interface for controlling the
Test Access Port (TAP) and associated test logic. The TAP, JTAG instruction register, and JTAG
data registers can be used to test the interconnects of assembled printed circuit boards, obtain
manufacturing information on the components, and observe and/or control the inputs and outputs
of the controller during normal operation. The JTAG port provides a high degree of testability and
chip-level access at a low cost.
The JTAG port is comprised of the standard five pins: TRST, TCK, TMS, TDI, and TDO. Data is
transmitted serially into the controller on TDI and out of the controller on TDO. The interpretation of
this data is dependent on the current state of the TAP controller. For detailed information on the
operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test
Access Port and Boundary-Scan Architecture.
The Luminary Micro JTAG controller works with the ARM JTAG controller built into the Cortex-M3
core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG
instructions select the ARM TDO output while Luminary Micro JTAG instructions select the Luminary
Micro TDO outputs. The multiplexer is controlled by the Luminary Micro JTAG controller, which has
comprehensive programming for the ARM, Luminary Micro, and unimplemented JTAG instructions.
1.4.6.3 System Control and Clocks (see page 50)
System control determines the overall operation of the device. It provides information about the
device, controls the clocking of the device and individual peripherals, and handles reset detection
and reporting.
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Architectural Overview
1.4.7 Hardware Details
Details on the pins and package can be found in the following sections:
■ “Pin Diagram” on page 349
■ “Signal Tables” on page 350
■ “Operating Characteristics” on page 362
■ “Electrical Characteristics” on page 363
■ “Package Information” on page 373
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June 26, 200728
2 ARM Cortex-M3 Processor Core
The ARM Cortex-M3 processor provides the core for a high-performance, low-cost platform that
meets the needs of minimal memory implementation, reduced pin count, and low power consumption,
while delivering outstanding computational performance and exceptional system response to
interrupts. Features include:
■ Compact core.
■ Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory
size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of
memory for microcontroller class applications.
■ Speedy application execution through Harvard architecture characterized by separate buses for
instruction and data.
■ Exceptional interrupt handling, by implementing the register manipulations required for handling
an interrupt in hardware.
■ Memory protection unit (MPU) to provide a privileged mode of operation for complex applications.
LM3S2410 Microcontroller
■ Migration from the ARM7™ processor family for better performance and power efficiency.
■ Full-featured debug solution with a:
– Serial Wire JTAG Debug Port (SWJ-DP)
– Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
– Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources,
and system profiling
– Instrumentation Trace Macrocell (ITM) for support of printf style debugging
– Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
The Stellaris®family of microcontrollers builds on this core to bring high-performance 32-bit computing
to cost-sensitive embedded microcontroller applications, such as factory automation and control,
industrial control power devices, building and home automation, and stepper motors.
For more information on the ARM Cortex-M3 processor core, see the ARM® Cortex™-M3 Technical
Reference Manual. For information on SWJ-DP, see the ARM® CoreSight Technical Reference
Manual.
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29June 26, 2007
Private Peripheral
Bus
(internal)
Data
Watchpoint
and Trace
Interrupts
Debug
Sleep
Instrumentation
Trace Macrocell
Trace
Port
Interface
Unit
CM3 Core
Instructions Data
Flash
Patch and
Breakpoint
Memory
Protection
Unit
Adv. High-
Perf. Bus
Access Port
Nested
Vectored
Interrupt
Controller
Serial Wire JTAG
Debug Port
Bus
Matrix
Adv. Peripheral
Bus
I-code bus
D-code bus
System bus
ROM
Table
Private
Peripheral
Bus
(external)
Serial
Wire
Output
Trace
Port
(SWO)
ARM
Cortex-M3
ARM Cortex-M3 Processor Core
2.1 Block Diagram
Figure 2-1. CPU Block Diagram
2.2 Functional Description
2.2.1 Serial Wire and JTAG Debug
Important:
Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 30. As
noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are
flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested
Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow.
Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug Port,” of the
ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris®devices.
The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the
CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP.
The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an
ARM Cortex-M3 in detail. However, these features differ based on the implementation.
This section describes the Stellaris®implementation.
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June 26, 200730
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