LM2727/LM2737 N-Channel FET Synchronous Buck Regulator Controller for Low Output
Voltages
Check for Samples: LM2727, LM2737
1
FEATURES
2
•Input Power from 2.2V to 16V
•Output Voltage Adjustable Down to 0.6V
•Power Good flag, Adjustable Soft-Start and
Output Enable for Easy Power Sequencing
•Output Over-Voltage and Under-Voltage LatchOff (LM2727)
•Output Over-Voltage and Under-Voltage Flag
(LM2737)
•Reference Accuracy: 1.5% (0°C - 125°C)
•Current Limit Without Sense Resistor
•Soft Start
•Switching Frequency from 50 kHz to 2 MHzadjusting the value of an external resistor. Current
•TSSOP-14 Package
APPLICATIONS
•Cable Modems
•Set-Top Boxes/ Home Gateways
•DDR Core Power
•High-Efficiency Distributed Power
•Local Regulation of Core Power
DESCRIPTION
TheLM2727andLM2737arehigh-speed,
synchronous, switching regulator controllers. They
are intended to control currents of 0.7A to 20A with
up to 95% conversion efficiencies. The LM2727
employs output over-voltage and under-voltage latchoff. For applications where latch-off is not desired, the
LM2737can be used.Power upand down
sequencing is achieved with the power-good flag,
adjustable soft-start and output enable features. The
LM2737 and LM2737 operate from a low-current 5V
bias and can convert from a 2.2V to 16V power rail.
Both parts utilize a fixed-frequency, voltage-mode,
PWMcontrolarchitectureandtheswitching
frequency is adjustable from 50kHz to 2MHz by
limit is achieved by monitoring the voltage drop
across the on-resistance of the low-side MOSFET,
which enhances low duty-cycle operation. The wide
range of operating frequencies gives the power
supply designer the flexibility to fine-tune component
size, cost, noise and efficiency. The adaptive, nonoverlapping MOSFET gate-drivers and high-side
bootstrapstructurehelpstofurthermaximize
efficiency. The high-side power FET drain voltage can
be from 2.2V to 16V and the output voltage is
adjustable down to 0.6V.
Typical Application
1
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
BOOT (Pin 1) - Supply rail for the N-channel MOSFET gate drive. The voltage should be at least one gate threshold above the regulator
input voltage to properly turn on the high-side N-FET.
LG (Pin 2) - Gate drive for the low-side N-channel MOSFET. This signal is interlocked with HG to avoid shoot-through problems.
PGND (Pins 3, 13) - Ground for FET drive circuitry. It should be connected to system ground.
SGND (Pin 4) - Ground for signal level circuitry. It should be connected to system ground.
VCC(Pin 5) - Supply rail for the controller.
PWGD (Pin 6) - Power Good. This is an open drain output. The pin is pulled low when the chip is in UVP, OVP, or UVLO mode. During
normal operation, this pin is connected to VCCor other voltage source through a pull-up resistor.
ISEN (Pin 7) - Current limit threshold setting. This sources a fixed 50µA current. A resistor of appropriate value should be connected
between this pin and the drain of the low-side FET.
EAO (Pin 8) - Output of the error amplifier. The voltage level on this pin is compared with an internally generated ramp signal to determine
the duty cycle. This pin is necessary for compensating the control loop.
SS (Pin 9) - Soft start pin. A capacitor connected between this pin and ground sets the speed at which the output voltage ramps up. Larger
capacitor value results in slower output voltage ramp but also lower inrush current.
FB (Pin 10) - This is the inverting input of the error amplifier, which is used for sensing the output voltage and compensating the control
loop.
FREQ (Pin 11) - The switching frequency is set by connecting a resistor between this pin and ground.
SD (Pin 12) - IC Logic Shutdown. When this pin is pulled low the chip turns off the high side switch and turns on the low side switch. While
this pin is low, the IC will not start up. An internal 20µA pull-up connects this pin to VCC.
HG (Pin 14) - Gate drive for the high-side N-channel MOSFET. This signal is interlocked with LG to avoid shoot-through problems.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Product Folder Links: LM2727 LM2737
LM2727, LM2737
www.ti.com
Absolute Maximum Ratings
V
CC
(1)(2)
SNVS205D –AUGUST 2002–REVISED MARCH 2013
BOOTV21V
Junction Temperature150°C
Storage Temperature−65°C to 150°C
Soldering Information
Lead Temperature (soldering, 10sec)260°C
Infrared or Convection (20sec)235°C
ESD Rating
(3)
2 kV
(1) Absolute maximum ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for
which the device operates correctly. Opearting Ratings do not imply ensured performance limits.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) The human body model is a 100pF capacitor discharged through a 1.5k resistor into each pin.
Operating Ratings
Supply Voltage (VCC)4.5V to 5.5V
Junction Temperature Range−40°C to +125°C
Thermal Resistance (θJA)155°C/W
Electrical Characteristics
VCC= 5V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA=TJ=+25°C. Limits appearing in
boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are ensured by design,
test, or statistical analysis.
SymbolParameterConditionsMinTypMaxUnits
VCC= 4.5V, 0°C to +125°C0.5910.60.609
VCC= 5V, 0°C to +125°C0.5910.60.609
V
FB_ADJ
V
I
Q-V5
t
PWGD1
t
PWGD2
I
I
SS-ON
I
SS-OC
I
SEN-TH
SD
ON
FB Pin VoltageV
UVLO ThresholdsRising4.2
Operating VCCCurrentmA
Shutdown VCCCurrentSD = 0V0.150.40.7mA
PWGD Pin Response TimeFB Voltage Going Up6µs
PWGD Pin Response TimeFB Voltage Going Down6µs
SD Pin Internal Pull-up Current20µA
SS Pin Source CurrentSS Voltage = 2.5V
SS Pin Sink Current During OverSS Voltage = 2.5V
Current
I
Pin Source Current Trip Point0°C to +125°C355065
SEN
VCC= 5.5V, 0°C to +125°C0.5910.60.609
VCC= 4.5V, −40°C to +125°C0.5890.60.609
VCC= 5V, −40°C to +125°C0.5890.60.609
VCC= 5.5V, −40°C to +125°C0.5890.60.609
VCC= 5V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA=TJ=+25°C. Limits appearing in
boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are ensured by design,
test, or statistical analysis.
SymbolParameterConditionsMinTypMaxUnits
ERROR AMPLIFIER
GBWError Amplifier Unity Gain
Bandwidth
GError Amplifier DC Gain60dB
SRError Amplifier Slew Rate6V/µA
I
I
EAO
V
FB
EA
FB Pin Bias CurrentFB = 0.55V015100
FB = 0.65V030155
EAO Pin Current Sourcing andV
SinkingV
= 2.5, FB = 0.55V2.8
EAO
= 2.5, FB = 0.65V0.8
EAO
Error Amplifier Maximum SwingMinimum1.2
Maximum3.2
GATE DRIVE
I
Q-BOOT
BOOT Pin Quiescent CurrentBOOTV = 12V, EN = 0
0°C to +125°C95160µA
-40°C to +125°C95215
R
DS1
R
DS2
R
DS3
R
DS4
Top FET Driver Pull-Up ON
resistance
Top FET Driver Pull-Down ON
resistance
Bottom FET Driver Pull-Up ON
resistance
Bottom FET Driver Pull-Down ON
resistance
BOOT-SW = 5V@350mA3Ω
BOOT-SW = 5V@350mA2Ω
BOOT-SW = 5V@350mA3Ω
BOOT-SW = 5V@350mA2Ω
OSCILLATOR
R
= 590kΩ50
FADJ
R
= 88.7kΩ300
FADJ
R
= 42.2kΩ, 0°C to +125°C500600700
f
OSC
PWM FrequencykHz
DMax Duty Cyclef
FADJ
R
= 42.2kΩ, -40°C to +125°C490600700
FADJ
R
= 17.4kΩ1400
FADJ
R
= 11.3kΩ2000
FADJ
= 300kHz90%
PWM
f
= 600kHz88
PWM
LOGIC INPUTS AND OUTPUTS
V
SD-IH
V
SD-IL
V
PWGD-TH-LO
SD Pin Logic High Trip Point2.63.5V
SD Pin Logic Low Trip Point0°C to +125°C1.31.6
-40°C to +125°C1.251.6
PWGD Pin Trip PointsFB Voltage Going Down
0°C to +125°C0.4130.4300.446V
-40°C to +125°C0.4100.4300.446
V
PWGD-TH-HI
PWGD Pin Trip PointsFB Voltage Going Up
0°C to +125°C0.6910.7100.734V
-40°C to +125°C0.6880.7100.734
V
PWGD-HYS
PWGD Hysteresis (LM2737 only)FB Voltage Going Down FB Voltage35
The LM2727 is a voltage-mode, high-speed synchronous buck regulator with a PWM control scheme. It is
designed for use in set-top boxes, thin clients, DSL/Cable modems, and other applications that require high
efficiency buck converters. It has power good (PWRGD), output shutdown (SD), over voltage protection (OVP)
and under voltage protection (UVP). The over-voltage and under-voltage signals are OR gated to drive the
Power Good signal and a shutdown latch, which turns off the high side gate and turns on the low side gate if
pulled low. Current limit is achieved by sensing the voltage VDSacross the low side FET. During current limit the
high side gate is turned off and the low side gate turned on. The soft start capacitor is discharged by a 95µA
source (reducing the maximum duty cycle) until the current is under control. The LM2737 does not latch off
during UVP or OVP, and uses the HIGH and LOW comparators for the powergood function only.
START UP
When VCCexceeds 4.2V and the enable pin EN sees a logic high the soft start capacitor begins charging through
an internal fixed 10µA source. During this time the output of the error amplifier is allowed to rise with the voltage
of the soft start capacitor. This capacitor, Css, determines soft start time, and can be determined approximately
by:
(1)
An application for a microprocessor might need a delay of 3ms, in which case CSSwould be 12nF. For a different
device, a 100ms delay might be more appropriate, in which case CSSwould be 400nF. (390 10%) During soft
start the PWRGD flag is forced low and is released when the voltage reaches a set value. At this point this chip
enters normal operation mode, the Power Good flag is released, and the OVP and UVP functions begin to
monitor Vo.
NORMAL OPERATION
While in normal operation mode, the LM2727/37 regulates the output voltage by controlling the duty cycle of the
high side and low side FETs. The equation governing output voltage is:
(2)
The PWM frequency is adjustable between 50kHz and 2MHz and is set by an external resistor, R
, between
FADJ
the FREQ pin and ground. The resistance needed for a desired frequency is approximately:
(3)
MOSFET GATE DRIVERS
The LM2727/37 has two gate drivers designed for driving N-channel MOSFETs in a synchronous mode. Power
for the drivers is supplied through the BOOTV pin. For the high side gate (HG) to fully turn on the top FET, the
BOOTV voltage must be at least one V
a separate, higher voltage source, or supplied from a local charge pump structure. In a system such as a
desktop computer, both 5V and 12V are usually available. Hence if Vin was 5V, the 12V supply could be used for
BOOTV. 12V is more than 2*Vin, so the HG would operate correctly. For a BOOTV of 12V, the initial gate
charging current is 2A, and the initial gate discharging current is typically 6A.
greater than Vin. (BOOTV ≥ 2*Vin) This voltage can be supplied by
In a system without a separate, higher voltage, a charge pump (bootstrap) can be built using a diode and small
capacitor, Figure 24. The capacitor serves to maintain enough voltage between the top FET gate and source to
control the device even when the top FET is on and its source has risen up to the input voltage level.
The LM2727/37 gate drives use a BiCMOS design. Unlike some other bipolar control ICs, the gate drivers have
rail-to-rail swing, ensuring no spurious turn-on due to capacitive coupling.
POWER GOOD SIGNAL
The power good signal is the or-gated flag representing over-voltage and under-voltage protection. If the output
voltage is 18% over it's nominal value, VFB= 0.7V, or falls 30% below that value, VFB= 0.41V, the power good
flag goes low. The converter then turns off the high side gate, and turns on the low side gate. Unlike the output
(LM2727 only) the power good flag is not latched off. It will return to a logic high whenever the feedback pin
voltage is between 70% and 118% of 0.6V.
UVLO
The 4.2V turn-on threshold on VCChas a built in hysteresis of 0.6V. Therefore, if VCCdrops below 3.6V, the chip
enters UVLO mode. UVLO consists of turning off the top FET, turning on the bottom FET, and remaining in that
condition until VCCrises above 4.2V. As with shutdown, the soft start capacitor is discharged through a FET,
ensuring that the next start-up will be smooth.
CURRENT LIMIT
Current limit is realized by sensing the voltage across the low side FET while it is on. The R
known value, hence the current through the FET can be determined as:
VDS= I * R
DSON
The current limit is determined by an external resistor, RCS, connected between the switch node and the ISEN
pin. A constant current of 50µA is forced through Rcs, causing a fixed voltage drop. This fixed voltage is
compared against VDSand if the latter is higher, the current limit of the chip has been reached. RCScan be found
by using the following:
RCS= R
For example, a conservative 15A current limit in a 10A design with a minimum R
DSON
(LOW) * I
/50µA(5)
LIM
of 10mΩ would require a
DSON
3.3kΩ resistor. Because current sensing is done across the low side FET, no minimum high side on-time is
necessary. In the current limit mode the LM2727/37 will turn the high side off and the keep low side on for as
long as necessary. The chip also discharges the soft start capacitor through a fixed 95µA source. In this way,
smooth ramping up of the output voltage as with a normal soft start is ensured. The output of the LM2727/37
internal error amplifier is limited by the voltage on the soft start capacitor. Hence, discharging the soft start
capacitor reduces the maximum duty cycle D of the controller. During severe current limit, this reduction in duty
cycle will reduce the output voltage, if the current limit conditions lasts for an extended time.
During the first few nanoseconds after the low side gate turns on, the low side FET body diode conducts. This
causes an additional 0.7V drop in VDS. The range of VDSis normally much lower. For example, if R
10mΩ and the current through the FET was 10A, VDSwould be 0.1V. The current limit would see 0.7V as a 70A
current and enter current limit immediately. Hence current limit is masked during the time it takes for the high
side switch to turn off and the low side switch to turn on.
The output undervoltage protection and overvoltage protection mechanisms engage at 70% and 118% of the
target output voltage, respectively. In either case, the LM2727 will turn off the high side switch and turn on the
low side switch, and discharge the soft start capacitor through a MOSFET switch. The chip remains in this state
until the shutdown pin has been pulled to a logic low and then released. The UVP function is masked only during
the first charging of the soft start capacitor, when voltage is first applied to the VCCpin. In contrast, the LM2737 is
designed to continue operating during UVP or OVP conditions, and to resume normal operation once the fault
condition is cleared. As with the LM2727, the powergood flag goes low during this time, giving a logic-level
warning signal.
SHUT DOWN
If the shutdown pin SD is pulled low, the LM2727/37 discharges the soft start capacitor through a MOSFET
switch. The high side switch is turned off and the low side switch is turned on. The LM2727/37 remains in this
state until SD is released.
DESIGN CONSIDERATIONS
The following is a design procedure for all the components needed to create the circuit shown in Figure 26 in the
Example Circuits section, a 5V in to 1.2V out converter, capable of delivering 10A with an efficiency of 85%. The
switching frequency is 300kHz. The same procedures can be followed to create the circuit shown in Figure 26,
Figure 27, and to create many other designs with varying input voltages, output voltages, and output currents.
INPUT CAPACITOR
The input capacitors in a Buck switching converter are subjected to high stress due to the input current
waveform, which is a square wave. Hence input caps are selected for their ripple current capability and their
ability to withstand the heat generated as that ripple current runs through their ESR. Input rms ripple current is
approximately:
(6)
The power dissipated by each input capacitor is:
(7)
Here, n is the number of capacitors, and indicates that power loss in each cap decreases rapidly as the number
of input caps increase. The worst-case ripple for a Buck converter occurs during full load, when the duty cycle D
= 50%.
In the 5V to 1.2V case, D = 1.2/5 = 0.24. With a 10A maximum load the ripple current is 4.3A. The Sanyo
10MV5600AX aluminum electrolytic capacitor has a ripple current rating of 2.35A, up to 105°C. Two such
capacitors make a conservative design that allows for unequal current sharing between individual caps. Each
capacitor has a maximum ESR of 18mΩ at 100 kHz. Power loss in each device is then 0.05W, and total loss is
0.1W. Other possibilities for input and output capacitors include MLCC, tantalum, OSCON, SP, and POSCAPS.
INPUT INDUCTOR
The input inductor serves two basic purposes. First, in high power applications, the input inductor helps insulate
the input power supply from switching noise. This is especially important if other switching converters draw
current from the same supply. Noise at high frequency, such as that developed by the LM2727 at 1MHz
operation, could pass through the input stage of a slower converter, contaminating and possibly interfering with
its operation.
An input inductor also helps shield the LM2727 from high frequency noise generated by other switching
converters. The second purpose of the input inductor is to limit the input current slew rate. During a change from
no-load to full-load, the input inductor sees the highest voltage change across it, equal to the full load current
times the input capacitor ESR. This value divided by the maximum allowable input current slew rate gives the
minimum input inductance:
In the case of a desktop computer system, the input current slew rate is the system power supply or "silver box"
output current slew rate, which is typically about 0.1A/µs. Total input capacitor ESR is 9mΩ, hence ΔV is
10*0.009 = 90 mV, and the minimum inductance required is 0.9µH. The input inductor should be rated to handle
the DC input current, which is approximated by:
(9)
In this case I
is about 2.8A. One possible choice is the TDK SLF12575T-1R2N8R2, a 1.2µH device that can
IN-DC
handle 8.2Arms, and has a DCR of 7mΩ.
OUTPUT INDUCTOR
The output inductor forms the first half of the power stage in a Buck converter. It is responsible for smoothing the
square wave created by the switching action and for controlling the output current ripple. (ΔIo) The inductance is
chosen by selecting between tradeoffs in efficiency and response time. The smaller the output inductor, the more
quickly the converter can respond to transients in the load current. As shown in the efficiency calculations,
however, a smaller inductor requires a higher switching frequency to maintain the same level of output current
ripple. An increase in frequency can mean increasing loss in the FETs due to the charging and discharging of the
gates. Generally the switching frequency is chosen so that conduction loss outweighs switching loss. The
equation for output inductor selection is:
(10)
Plugging in the values for output current ripple, input voltage, output voltage, switching frequency, and assuming
a 40% peak-to-peak output current ripple yields an inductance of 1.5µH. The output inductor must be rated to
handle the peak current (also equal to the peak switch current), which is (Io + 0.5*ΔIo). This is 12A for a 10A
design. The Coilcraft D05022-152HC is 1.5µH, is rated to 15Arms, and has a DCR of 4mΩ.
OUTPUT CAPACITOR
The output capacitor forms the second half of the power stage of a Buck switching converter. It is used to control
the output voltage ripple (ΔVo) and to supply load current during fast load transients.
In this example the output current is 10A and the expected type of capacitor is an aluminum electrolytic, as with
the input capacitors. (Other possibilities include ceramic, tantalum, and solid electrolyte capacitors, however the
ceramic type often do not have the large capacitance needed to supply current for load transients, and tantalums
tend to be more expensive than aluminum electrolytic.) Aluminum capacitors tend to have very high capacitance
and fairly low ESR, meaning that the ESR zero, which affects system stability, will be much lower than the
switching frequency. The large capacitance means that at switching frequency, the ESR is dominant, hence the
type and number of output capacitors is selected on the basis of ESR. One simple formula to find the maximum
ESR based on the desired output voltage ripple, ΔVoand the designed output current ripple, ΔIo, is:
(11)
In this example, in order to maintain a 2% peak-to-peak output voltage ripple and a 40% peak-to-peak inductor
current ripple, the required maximum ESR is 6mΩ. Three Sanyo 10MV5600AX capacitors in parallel will give an
equivalent ESR of 6mΩ. The total bulk capacitance of 16.8mF is enough to supply even severe load transients.
Using the same capacitors for both input and output also keeps the bill of materials simple.
MOSFETS are a critical part of any switching controller and have a direct impact on the system efficiency. In this
case the target efficiency is 85% and this is the variable that will determine which devices are acceptable. Loss
from the capacitors, inductors, and the LM2727 itself are detailed in the Efficiency section, and come to about
0.54W. To meet the target efficiency, this leaves 1.45W for the FET conduction loss, gate charging loss, and
switching loss. Switching loss is particularly difficult to estimate because it depends on many factors. When the
load current is more than about 1 or 2 amps, conduction losses outweigh the switching and gate charging losses.
This allows FET selection based on the R
of the FET. Adding the FET switching and gate-charging losses to
DSON
the equation leaves 1.2W for conduction losses. The equation for conduction loss is:
= D(I
2
* R
o
DSON
*k) + (1-D)(I
P
Cnd
The factor k is a constant which is added to account for the increasing R
1.3. The Si4442DY has a typical R
2
* R
o
DSON
*k)(12)
DSON
DSON
of 4.1mΩ. When plugged into the equation for P
of a FET due to heating. Here, k =
the result is a loss of
CND
0.533W. If this design were for a 5V to 2.5V circuit, an equal number of FETs on the high and low sides would be
the best solution. With the duty cycle D = 0.24, it becomes apparent that the low side FET carries the load
current 76% of the time. Adding a second FET in parallel to the bottom FET could improve the efficiency by
lowering the effective R
. The lower the duty cycle, the more effective a second or even third FET can be. For
DSON
a minimal increase in gate charging loss (0.054W) the decrease in conduction loss is 0.15W. What was an 85%
design improves to 86% for the added cost of one SO-8 MOSFET.
CONTROL LOOP COMPONENTS
The circuit is this design example and the others shown in the Example Circuits section have been compensated
to improve their DC gain and bandwidth. The result of this compensation is better line and load transient
responses. For the LM2727, the top feedback divider resistor, Rfb2, is also a part of the compensation. For the
10A, 5V to 1.2V design, the values are:
Cc1 = 4.7pF 10%, Cc2 = 1nF 10%, Rc = 229kΩ 1%. These values give a phase margin of 63° and a bandwidth
of 29.3kHz.
SUPPORT CAPACITORS AND RESISTORS
The Cinx capacitors are high frequency bypass devices, designed to filter harmonics of the switching frequency
and input noise. Two 1µF ceramic capacitors with a sufficient voltage rating (10V for the Circuit of Figure 26) will
work well in almost any case.
Rbypass and Cbypass are standard filter components designed to ensure smooth DC voltage for the chip supply
and for the bootstrap structure, if it is used. Use 10Ω for the resistor and a 2.2µF ceramic for the cap. Cb is the
bootstrap capacitor, and should be 0.1µF. (In the case of a separate, higher supply to the BOOTV pin, this 0.1µF
cap can be used to bypass the supply.) Using a Schottky device for the bootstrap diode allows the minimum drop
for both high and low side drivers. The On Semiconductor BAT54 or MBR0520 work well.
Rp is a standard pull-up resistor for the open-drain power good signal, and should be 10kΩ. If this feature is not
necessary, it can be omitted.
RCSis the resistor used to set the current limit. Since the design calls for a peak current magnitude (Io + 0.5 *
ΔIo) of 12A, a safe setting would be 15A. (This is well below the saturation current of the output inductor, which is
25A.) Following the equation from the Current Limit section, use a 3.3kΩ resistor.
R
is used to set the switching frequency of the chip. Following the equation in the Theory of Operation
FADJ
section, the closest 1% tolerance resistor to obtain fSW= 300kHz is 88.7kΩ.
CSSdepends on the users requirements. Based on the equation for CSSin the Theory of Operation section, for a
A reasonable estimation of the efficiency of a switching controller can be obtained by adding together the loss is
each current carrying element and using the equation:
(13)
The following shows an efficiency calculation to complement the Circuit of Figure 26. Output power for this circuit
is 1.2V x 10A = 12W.
Chip Operating Loss
Q-V
*V
CC
CC
PIQ= I
2mA x 5V = 0.01W
FET Gate Charging Loss
PGC= n * VCC* QGS* f
OSC
The value n is the total number of FETs used. The Si4442DY has a typical total gate charge, QGS, of 36nC and
an r
of 4.1mΩ. For a single FET on top and bottom: 2*5*36E-9*300,000 = 0.108W
ds-on
FET Switching Loss
PSW= 0.5 * Vin* IO* (tr+ tf)* f
OSC
The Si4442DY has a typical rise time trand fall time tfof 11 and 47ns, respectively. 0.5*5*10*58E-9*300,000 =
This circuit and the one featured on the front page have been designed to deliver high current and high efficiency
in a small package, both in area and in height The tallest component in this circuit is the inductor L1, which is
6mm tall. The compensation has been designed to tolerate input voltages from 5 to 16V.
Figure 26. 5V to 1.2V, 10A, 300kHz
This circuit design, detailed in the Design Considerations section, uses inexpensive aluminum capacitors and offthe-shelf inductors. It can deliver 10A at better than 85% efficiency. Large bulk capacitance on input and output
ensure stable operation.
The example circuit of Figure 27 has been designed for minimum component count and overall solution size. A
switching frequency of 600kHz allows the use of small input/output capacitors and a small inductor. The
availability of separate 5V and 12V supplies (such as those available from desk-top computer supplies) and the
low current further reduce component count. Using the 12V supply to power the MOSFET drivers eliminates the
bootstrap diode, D1. At low currents, smaller FETs or dual FETs are often the most efficient solutions. Here, the
Si4826DY, an asymmetric dual FET in an SO-8 package, yields 92% efficiency at a load of 2A.
Figure 28. 3.3V to 0.8V, 5A, 500kHz
The circuit of Figure 28 demonstrates the LM2727 delivering a low output voltage at high efficiency (87%) A
separate 5V supply is required to run the chip, however the input voltage can be as low as 2.2
Figure 29. 1.8V and 3.3V, 1A, 1.4MHz, Simultaneous
The circuits in Figure 29 are intended for ADSL applications, where the high switching frequency keeps noise out
of the data transmission range. In this design, the 1.8 and 3.3V outputs come up simultaneously by using the
same softstart capacitor. Because two current sources now charge the same capacitor, the capacitance must be
doubled to achieve the same softstart time. (Here, 40nF is used to achieve a 5ms softstart time.) A common
softstart capacitor means that, should one circuit enter current limit, the other circuit will also enter current limit.
In addition, if both circuits are built with the LM2727, a UVP or OVP fault on one circuit will cause both circuits to
latch off. The additional compensation components Rc2 and Cc3 are needed for the low ESR, all ceramic output
capacitors, and the wide (3x) range of Vin.
This circuit shows the LM27x7 paired with a cost effective solution to provide the 5V chip power supply, using no
extra components other than the LM78L05 regulator itself. The input voltage comes from a 'brick' power supply
which does not regulate the 12V line tightly. Additional, inexpensive 10uF ceramic capacitors (Cinx and Cox)
help isolate devices with sensitive databands, such as DSL and cable modems, from switching noise and
harmonics.
Figure 31. 12V to 5V, 1.8A, 100kHz
In situations where low cost is very important, the LM27x7 can also be used as an asynchronous controller, as
shown in the above circuit. Although a a schottky diode in place of the bottom FET will not be as efficient, it will
cost much less than the FET. The 5V at low current needed to run the LM27x7 could come from a zener diode or
inexpensive regulator, such as the one shown in Figure 30. Because the LM27x7 senses current in the low side
MOSFET, the current limit feature will not function in an asynchronous design. The ISEN pin should be left open
in this case.
Changes from Revision C (March 2013) to Revision DPage
•Changed layout of National Data Sheet to TI format .......................................................................................................... 23
LM2727MTCNRNDTSSOPPW1494TBDCall TICall TI0 to 1252727
LM2727MTC/NOPBACTIVETSSOPPW1494Green (RoHS
LM2727MTCX/NOPBACTIVETSSOPPW142500Green (RoHS
LM2737MTCNRNDTSSOPPW1494TBDCall TICall TI-40 to 1252737
LM2737MTC/NOPBACTIVETSSOPPW1494Green (RoHS
LM2737MTCXNRNDTSSOPPW142500TBDCall TICall TI-40 to 1252737
LM2737MTCX/NOPBACTIVETSSOPPW142500Green (RoHS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Package Type Package
(1)
Drawing
Pins Package
Qty
Eco Plan
(2)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
Lead/Ball Finish
(6)
CU NIPDAU | CU SNLevel-1-260C-UNLIM0 to 1252727
CU NIPDAU | CU SNLevel-1-260C-UNLIM0 to 1252727
CU NIPDAU | CU SNLevel-1-260C-UNLIM-40 to 1252737
CU NIPDAU | CU SNLevel-1-260C-UNLIM-40 to 1252737
MSL Peak Temp
(3)
Op Temp (°C)Device Marking
MTC
MTC
MTC
MTC
MTC
MTC
MTC
(4/5)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
5-Sep-2014
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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