Texas Instruments IVC102, IVC102U Datasheet
®
IVC102
PRECISION SWITCHED INTEGRATOR
TRANSIMPEDANCE AMPLIFIER
APPLICA TIONS
● PRECISION LOW CURRENT MEASUREMENT
● PHOTODIODE MEASUREMENTS
● IONIZATION CHAMBER MEASUREMENTS
● CURRENT/CHARGE-OUTPUT SENSORS
● LEAKAGE CURRENT MEASUREMENT
FEATURES
● ON-CHIP INTEGRATING CAPACITORS
● GAIN PROGRAMMED BY TIMING
● LOW INPUT BIAS CURRENT: 750fA max
● LOW NOISE
● LOW SWITCH CHARGE INJECTION
● FAST PULSE INTEGRATION
● LOW NONLINEARITY: 0.005% typ
● 14-PIN DIP, SO-14 SURFACE MOUNT
60pF
C
3
C
30pF
2
10pF
1
S
2
S
1
11 12 13
S
1
S
2
Ionization
Chamber
Photodiode
I
IN
Analog
Ground
6
5
C
4
3
2
1
Logic Low closes switches
V
B
DESCRIPTION
The IVC102 is a precision integrating amplifier with
FET op amp, integrating capacitors, and low leakage
FET switches. It integrates low-level input current for
a user-determined period, storing the resulting voltage
on the integrating capacitor. The output voltage can be
held for accurate measurement. The IVC102 provides
a precision, lower noise alternative to conventional
transimpedance op amp circuits that require a very
high value feedback resistor.
The IVC102 is ideal for amplifying low-level sensor
currents from photodiodes and ionization chambers.
The input signal current can be positive or negative.
TTL/CMOS-compatible timing inputs control the integration period, hold and reset functions to set the
effective transimpedance gain and to reset (discharge)
the integrator capacitor.
Package options include 14-Pin plastic DIP and SO-14
surface-mount packages. Both are specified for the
–40°C to 85°C industrial temperature range.
V+
14
10
9
Digital
Ground
V–
V
O
0V
Hold Integrate Hold Reset
S
1
S
2
–1
=
V
O
Positive or Negative
Signal Integration
IIN(t)
∫
C
INT
dt
SBFS009
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1996 Burr-Brown Corporation PDS-1329A Printed in U.S.A. June, 1996
1
IVC102
®
SPECIFICATIONS
At TA = +25°C, VS = ±15V, RL = 2kΩ, C
= C1 + C2 + C3, 1ms integration period
INT
PARAMETER CONDITIONS MIN TYP MAX UNITS
TRANSFER FUNCTION V
Gain Error C
vs Temperature ±25 ppm/°C
= C1 + C2 + C
INT
Nonlinearity V
Input Current Range ±100 µA
Offset Voltage
(2)
IIN = 0, CIN = 50pF –5 ±20 mV
vs Temperature ±30 µV/°C
vs Power Supply V
Droop Rate, Hold Mode –1 nV/µs
= +4.75/–10 to +18/–18V 150 750 µV/V
S
OP AMP
Input Bias Current S
vs Temperature See Typical Curve
Offset Voltage (Op Amp V
vs Temperature ±5 µV/°C
vs Power Supply V
Noise Voltage f = 1kHz 10 nV/√Hz
) ±0.5 ±5mV
OS
= +4.75/–10 to +18/–18V 10 100 µV/V
S
INTEGRATION CAPACITORS
C
+ C2 + C
1
C
1
C
2
C
3
3
vs Temperature ±25 ppm/°C
OUTPUT
Voltage Range, Positive R
Negative R
Short-Circuit Current ±20 mA
Capacitive Load Drive 500 pF
Noise Voltage See Typical Curve
DYNAMIC CHARACTERISTIC
Op Amp Gain-Bandwidth 2 MHz
Op Amp Slew Rate 3V/µs
Reset
Slew Rate 3V/µs
Settling Time, 0.01% 10V Step 6 µs
DIGITAL INPUTS (TTL/CMOS Compatible)
V
(referred to digital ground) (Logic High) 2 5.5 V
IH
V
(referred to digital ground) (Logic Low) –0.5 0.8 V
IL
I
IH
I
IL
Switching Time 100 ns
POWER SUPPLY
Voltage Range: Positive +4.75 +15 +18 V
Negative –10 –15 –18 V
Current: Positive 4.1 5.5 mA
Negative –1.6 –2.2 mA
Analog Ground –0.2 mA
Digital Ground –2.3 mA
TEMPERATURE RANGE
Operating Range –40 85 °C
Storage –55 125 °C
Thermal Resistance,
DIP 100 °C/W
θ
JA
SO-14 150 °C/W
NOTES: (1) Standard test timing: 1ms integration, 200µs hold, 100µs reset. (2) Hold mode output voltage after 1ms integration of zero input current. Includes op
amp offset voltage, integration of input error current and switch charge injection effects.
(1)
, unless otherwise specified.
IVC102P, U
= –(IIN)(T
3
= ±10V ±0.005 %
O
, S2 Open –100 ±750 fA
1
O
)/C
INT
INT
±5 +25/–17 %
80 100 120 pF
10 pF
30 pF
60 pF
= 2kΩ (V+)–3 (V+)–1.3 V
L
= 2kΩ (V–)+3 (V–)+2.6 V
L
VIH = 5V 2 µA
VIL = 0V 0 µA
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
IVC102
2
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V+ to V– .................................................................... 36V
Logic Input Voltage ...................................................................... V– to V+
Output Short Circuit to Ground ............................................... Continuous
Operating Temperature ................................................. –40°C to +125°C
Storage Temperature..................................................... –55°C to +125°C
Lead Temperature (soldering, 10s) ................................................. 300° C
PIN CONNECTIONS
Top View 14-Pin DIP/
SO-14 Surface Mount
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
14
V+
13
Digital Ground
12
S
2
11
S
1
10
V
O
9
V–
8
NC
–In
C
NC
1
2
I
IN
3
4
C
1
5
C
2
6
3
7
Analog Ground
NC = No Internal Connection
Connect to Analog Ground for Lowest Noise
PACKAGE INFORMATION
PRODUCT PACKAGE NUMBER
PACKAGE DRAWING
IVC102P 14-Pin DIP 010
IVC102U SO-14 Surface Mount 235
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
(1)
®
3
IVC102
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = ±15V, RL = 2kΩ, C
= C1 + C2 + C3, 1ms integration period, unless otherwise specified.
INT
100p
INPUT BIAS CURRENT vs TEMPERATURE
S1, S2 Open
10p
1p
100f
Input Bias Current (A)
10f
–50 –25 0 25 50 75 100 125
Temperature (°C)
30
RESET TIME vs C
25
Time Required to
Reset from ±10V
INT
to 0V.
20
0.01%
15
10
Reset Time (µs)
1%
5
0
0 100 200 300 400 500 600 700 800 900 1000
C
(pF)
INT
1000
rms Variation
of 100 Measurement
Cycles, T
100
10
Noise Voltage (µVrms)
TOTAL OUTPUT NOISE vs C
INT
= 1ms.
C
C
C
C
Reset Mode, S1 Open, S2 Closed.
INT
INT
INT
INT
= 10pF
= 30pF
= 100pF
= 300pF
C
INT
IN
= 1000pF
1
10 100 1000
C
(pF)
IN
CHARGE INJECTION vs INPUT CAPACITANCE
S
2.0
1
1.8
S
1.6
1.4
1
C
IN
1.2
1.0
0.8
0.6
Charge Injection, ∆Q (pC)
0.4
0.2
0
10 100 1000
Input Capacitance, C
IN
(pF)
100pF
∆V
∆Q
=
O
100pF
CHARGE INJECTION vs INPUT CAPACITANCE
S
1.0
0.9
2
(V+) = +18V
0.8
0.7
(V+) = +15V
0.6
0.5
0.4
(V+) = +4.75V
S
2
100pF
0.3
Charge Injection, ∆Q (pC)
0.2
C
IN
0.1
0
10 100 1000
Input Capacitance, C
®
IN
(pF)
IVC102
∆V
∆Q
=
O
100pF
4
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