Datasheet IW4027BN Datasheet (INTEGRAL)

Page 1
Dual JK Flip-Flop
High-Voltage Silicon-Gate CMOS
The IW4027B is a Dual JK Flip-Flop which is edge-triggered and features independent Set, Reset, and Clock inputs. Data is accepted when the Clock is LOW and transferred to the output on the positive­going edge of the Clock. The active HIGH asynchronous Reset and Set are independent and override the J, K, or Clock inputs. The outputs are buffered for best system performance.
•
Operating Voltage Range: 3.0 to 18 V
•
Maximum input current of 1 µA at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
•
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
TECHNICAL DATA
IW4027B
ORDERING INFORMATION
IW4027BN Plastic
IW4027BD SOIC
TA = -55° to 125° C for all packages
LOGIC DIAGRAM
PIN 16 =V
PIN 8 = GND
CC
PIN ASSIGNMENT
FUNCTION TABLE
Inputs Outputs
Set Reset Clock J K Q
LHXXXLH HLXXXHL HHXXXHH L L L L No change LL HLHL LL LHLH L L H H Qn Qn
n+1Qn+1
X = don’t care Qn+1 = State After Clock Positive Transition
19
Page 2
IW4027B
MAXIMUM RATINGS
*
Symbol Parameter Value Unit
V
CC
V
V
OUT
I
IN
P
P
DC Supply Voltage (Referenced to GND) -0.5 to +20 V DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IN
DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+
D
SOIC Package+ Power Dissipation per Output Transistor 100 mW
D
±
10
750 500
Tstg Storage Temperature -65 to +150
T
Lead Temperature, 1 mm from Case for 10 Seconds
L
260
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
VIN, V
T
CC
A
DC Supply Voltage (Referenced to GND) 3.0 18 V DC Input Voltage, Output Voltage (Referenced to GND) 0 V
OUT
Operating Temperature, All Package Types -55 +125
CC
mA
mW
°
C
°
C
V
°
C
This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V GND≤(V
IN
or V
OUT
)≤VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
and V
IN
should be constrained to the range
OUT
CC
Unused outputs must be left open.
20
).
Page 3
IW4027B
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol Parameter Test Conditions V
V
V
V
IH
IL
OH
Minimum High-Level Input Voltage
Maximum Low -Level Input Voltage
Minimum High-Level
V
=0.5 V or V
OUT
V
=1.0 V or V
OUT
V
=1.5 V or V
OUT
V
=0.5 V or V
OUT
V
=1.0 V or V
OUT
V
=1.5 V or V
OUT
VIN=GND or V
CC
CC CC CC
CC CC CC
- 0.5 V
- 1.0 V
- 1.5 V
- 0.5 V
- 1.0 V
- 1.5 V
Output Voltage
V
OL
Maximum Low-Level
VIN=GND or V
CC
Output Voltage
I
IN
Maximum Input
VIN= GND or V
CC
Leakage Current
I
CC
Maximum Quiescent
VIN= GND or V
CC
Supply Current (per Package)
I
OL
I
OH
Minimum Output Low (Sink) Current
Minimum Output High (Source) Current
VIN= GND or V VOL=0.4 V V
=0.5 V
OL
V
=1.5 V
OL
VIN= GND or V VOH=4.6 V V
=2.5 V
OH
V
=9.5 V
OH
V
=13.5 V
OH
CC
CC
V
5.0 10 15
5.0 10 15
5.0 10 15
5.0 10 15
18
5.0 10 15 20
5.0 10 15
5.0
5.0 10 15
CC
≥
14.95
Guaranteed Limit
-55°C25°C
3.5 7
11
1.5 3 4
4.95
9.95
3.5 7
11
1.5 3 4
4.95
9.95
14.95
0.05
0.05
0.05
±
0.1
1.0
2.0
4.0 20
0.64
1.6
4.2
-0.64 –2.0 –1.8 –4.2
0.05
0.05
0.05
±
0.1
1.0
2.0
4.0 20
0.51
1.3
3.4
-0.51 –1.6 –1.3 –3.4
≤
125
°
C
3.5 7
11
1.5 3 4
4.95
9.95
14.95
0.05
0.05
0.05
±
1.0
30
60 120 600
0.36
0.9
2.4
-0.36
–1.15
–0.9 –2.4
Unit
V
V
V
V
µ
A
µ
A
mA
mA
21
Page 4
IW4027B
AC ELECTRICAL CHARACTERISTICS
(CL=50pF, RL=200 kΩ, Input tr=tf=20 ns)
Symbol Parameter V
t
PLH
f
t
max
, t
PLH
Maximum Clock Frequency 5.0
Maximum Propagati on Delay, Clock to Q or Q 5.0
PHL
Maximum Propagation Delay, Set to Q or Reset to Q
t
PHL
Maximum Propagation Delay, Set to Q or Reset to Q
t
TLH
, t
C
IN
Maximum Output Transition Time, Any Output 5.0
THL
Maximum Input Capacitance - 7.5 pF
V
10 15
10 15
5.0 10 15
5.0 10 15
10 15
CC
≥
Guaranteed Limit
-55°C25°C
3.5 8
12
300 130
90
300 130
90
400 170 120
200 100
80
3.5 8
12
300 130
90
300 130
90
400 170 120
200 100
80
≤
125°C
1.75
600 260 180
600 260 180
800 340 240
400 200 160
Unit
MHz 4 6
ns
ns
ns
ns
TIMING REQUIREMENTS
(CL=50pF, RL=200 kΩ, Input tr=tf=20 ns)
Symbol Parameter V
t
t
t
tr, t
w
w
su
Minimum Pulse Width, Clock 5.0
Minimum Pulse Width, Set or Rese t 5.0
Minimum Setup Time 5.0
Maximum Input Rise or Fall Time, Clock 5.0
f
V
CC
10 15
10 15
10 15
10 15
Guaranteed Limit
≥
-55°C25°C 140
60 40
180
80 50
200
75 50
45
5 2
140
60 40
180
80 50
200
75 50
45
5 2
≤
125°C
280 120
80
360 160 100
400 150 100
90 10
Unit
ns
ns
ns
µ
s
4
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