Datasheet IW4034BN, IW4034BDW Datasheet (INTEGRAL)

TECHNICAL DATA

IW4034B

8-Stage Static Bidirectional Parallel/ Serial Input/Output Bus Register

High-Voltage Silicon-Gate CMOS

The IW4034B is a static eight-stage parallel-or serial-input

parallel-output register. It can be used to:

1) bidirectionally transfer parallel information between two buses,

2) convert serial data to parallel form and direct the parallel data to either of two buses, 3) store (recirculate) parallel data, or 4) accept parallel data from either of two buses and convert that data to serial form. Inputs that control the operations include a single-phase CLOCK (CL), A DATA ENABLE (AE), ASYNCHRONOUS/SYNCHRONOUS (A/S), A-BUS-TO-B-BUS/ BBUS-TO-A-BUS (A/B), and PARALLEL/SERIAL (P/S).

Data inputs include 16 bidirectional parallel data lines of which the eight A data lines are inputs (3-state outputs) and the B data lines are outputs (inputs) dependung on the signal level on the A/B input. In addition, an input for SERIAL DATA is also provided.

All register stages are D-type master-slave flip-flops with separate master and slave clock inputs generated internally to allow synchronous or asynchronous data transfer from master to slave.

•

Operating Voltage Range: 3.0 to 18 V

•

Maximum input current of 1 µA at 18 V over full package-

temperature range; 100 nA at 18 V and 25°C

•

Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply

ORDERING INFORMATION

IW4034BN Plastic

IW4034BDW SOIC

TA = -55° to 125° C for all packages

PIN ASSIGNMENT

76

LOGIC DIAGRAM

PIN 24=V

PIN 12= GND

CC

IW4034B

MAXIMUM RATINGS

*

Symbol Parameter Value Unit

V

CC

V

OUT

I

IN

P

DC Supply Voltage (Referenced to GND) -0.5 to +20 V DC Input Voltage (Referenced to GND) -0.5 to VCC +0.5 V

IN

DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+

D

SOIC Package+ Power Dissipation per Output Transistor 100 mW

D

±

10

750 500

Tstg Storage Temperature -65 to +150

T

Lead Temperature, 1 mm from Case for 10 Seconds

L

260

(Plastic DIP or SOIC Package)

*

Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C

SOIC Package: : - 7 mW/°C from 65° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Min Max Unit

V

VIN, V

T

CC

A

DC Supply Voltage (Referenced to GND) 3.0 18 V DC Input Voltage, Output Voltage (Referenced to GND) 0 V

OUT

Operating Temperature, All Package Types -55 +125

CC

mA

mW

°

C

°

C

V

°

C

This device c ontains p rote ction ci rcuitr y to guard a gainst damage d ue to high st atic voltages or electr ic fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, V GND≤(V

IN

or V

OUT

)≤VCC.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V

and V

IN

should be constrained to the range

OUT

CC

Unused outputs must be left open.

77

).

IW4034B

DC ELECTRICAL CHARACTERISTICS

(Voltages Referenced to GND)

Symbol Parameter Test Conditions V

V

IH

IL

OH

Minimum High-Level Input Voltage

Maximum Low -Level Input Voltage

Minimum High-Level

V

= 0.5 V or V

OUT

V

= 1.0 V or V

OUT

V

= 1.5 V V

OUT

V

= 0.5 V or V

OUT

V

= 1.0 V or V

OUT

V

= 1.5 V V

OUT

VIN=GND or V

CC

- 0.5V

CC

- 1.0 V

CC

- 1.5V

- 0.5V

CC

- 1.0 V

CC

- 1.5V

Output Voltage

V

OL

Maximum Low-Level

VIN=GND or V

CC

Output Voltage

I

IN

Maximum Input

VIN= GND or V

CC

Leakage Current

I

OZ

I

CC

Minimum Three State Leakage Current

Maximum Quiescent

Output in High-Impedance State V

= GND or V

IN

V

= GND or V

OUT

VIN= GND or V

CC

Supply Current (per Package)

I

OL

I

OH

Minimum Output Low (Sink) Current

Minimum Output High (Source) Current

VIN= GND or V UOL=0.4 V U

=0.5 V

OL

U

=1.5 V

OL

VIN= GND or V UOH=2.5 V U

=4.6 V

OH

U

=9.5 V

OH

U

=13.5 V

OH

CC

V

5.0 10 15

18

5.0 10 15 20

5.0 10 15

5.0

5.0 10 15

CC

≥

14.95

Guaranteed Limit

-55°C25°C

3.5 7

11

1.5 3 4

4.95

9.95

3.5 7

11

1.5 3 4

4.95

9.95

14.95

0.05

±

0.1

±

0.4

5 10 20

100

0.64

1.6

4.2

-2

-0.64

-1.6

-4.2

0.05

±

0.1

±

0.4

5 10 20

100

0.51

1.3

3.4

-1.6

-0.51

-1.3

-3.4

≤

125

°

C

3.5 7

11

1.5 3 4

4.95

9.95

14.95

0.05

±

1.0

±

12.0

150 300 600

3000

0.36

0.9

2.4

-1.15

-0.36

-0.9

-2.4

Unit

V

µ

A

µ

A

µ

A

mA

78

IW4034B

AC ELECTRICAL CHARACTERISTICS

(CL=50pF, RL=200kΩ, Input tr=tf=20 ns)

Symbol Parameter V

t

PHL

f

max

, t

Maximum Clock Frequency (Figur e 2) 5.0

Maximum Propagation Delay, A(B) Parallel

PLH

Data In to B(A) Parallel Data Out; Serial to Parallel Data Out (Figures 1,2)

t

PLZ

t

THL

PZL

, t

Maximum Propagation Delay, A/B or AE to

PHZ,

“A” Output (Figure 3)

PZH

Maximum Output Transition Time, Any Output

TLH

(Figures 1,2)

C

IN

TIMING REQUIREMENTS

Maximum Input Capacitance - 7.5 pF

(CL=50pF, RL=200 kΩ, Input tr=tf=20 ns)

Symbol Parameter V

t

su

Minimum Setu p Time, Serial Data to Clock (Figure 4)

t

su

Minimum Setup Time, Parallel Data to Clock (Figure 4)

t

h

t

w

Minimum Hold Time, Clock to Data (Figure 4) 5.0

Minimum Pulse Width, AE, P/S, A/S (Figure 5)

t

tr ,t

w

Minimum Pulse Width, Clock (Figure 2) 5.0

Minimum Input Rise or Fall Time, Clock

f

(Figure 2)

V

10 15

5.0 10 15

V

5.0 10 15

10 15

5.0 10 15

10 15

5.0 10 15

CC

≥

CC

≥

Guaranteed Limit

-55°C25°C 2

5 7

700 240 170

400 160 120

200 100

80

2 5 7

700 240 170

400 160 120

200 100

80

Guaranteed Limit

-55°C25°C

160

60 40

50 30 20

50 15 10

350 140

80

250 100

70 15

15 15

160

60 40

50 30 20

50 15 10

350 140

80

250 100

70 15

15 15

≤

125°C

2.5

3.5

1400

480 340

800 320 240

400 200 160

≤

125°C

320 120

80

100

60 40

100

30 20

700 280 160

500 200 140

30 30 30

Unit

1

MHz

ns

Unit

ns

79

IW4034B

TRUTH TABLE FOR REGISTER INPUT-LEVELS AND RESULTING REGISTER

OPERATION

“A”

Enable P/S A/B A/S Operation

LL LL LH

L X Serial Mode; Synch. Serial Data Input, “A” Parallel Data Outputs Disabled H X Serial Mode, Synch. Serial Data Input, “B” Parallel Data Output L L Parallel Mode; “B” Synch. Parallel Data Inputs, “A” Parallel Data Outputs

*

Disabled

LH

L H Parallel Mode; “B” Asynch. Parallel Data Inputs, “A” Parallel Data Outputs

Disabled

LH

H L Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data Outputs,

Synch. Data Recircula tion

LH

H H Parallel Mode; “A” Parallel Data Inputs Disabled, “B” Parallel Data Outputs,

Asynch. Data Recirculation

HL HL HH HH HH HH

Outputs change at positive transition of clock in the serial mode and when the A/S control input is “low”

*

L X Serial Mode; Synch. Serial Data Input, “A” Parallel Data Output H X Serial Mode; Synch. Serial Data Input, “B” Parallel Data Output L L Parallel Mode; “B” Synch. Parallel Data Input, “A” Parallel Data Output L H Parallel Mode; “B” Asynch. Parallel Data Input, “A” Parallel Data Output H L Parallel Mode; “A” Synch. Parallel Data Input, “B” Parallel Data Output H H Parallel Mode; “A” Asynch. Parallel Data Input, “B” Parallel Data Output

in the parallel mode. During transfer from parallel to serial operation A/S should remain low in oder to prevent D

transfer into Flip Flops.

S

X = Don’t Care

PARALLEL OPERATION

A high P/S input signal allows data transfer into the register via the parallel data lines synchronously with the positive transition of the clock provided the A/S input is low. If the A/S input is high the transfer is independent of the clock. The direction of data flow is controlled by the A/B input. When this signal is high the A data lines are inputs (and B data lines are outputs); a low A/B signal reverses the direction of data flow.

The AE input is an additional feature which allows many registers to feed data to a common bus. The A DATA lines are enabled only when this signal is high.

Data storage through recirculation of data in each r e gister stage is accomplished by making the A/B signal high and the AE signal low.

SERIAL OPERATION

A low P/S signal allows serial data to transfer into the register synchronously with the positive transition of the clock. The A/S input is internally disabled when the register is in the serial mode (asynchronous serial operation is not allowed).

The serial data appears as output data on either the B lines (when A/B is high) or the A lines (when A/B is low and the AE signal is high).

80

FLIP-FLOP TRUTH TABLE

Inputs Output

CL

X = don’t care

CL

M

IW4034B

S

DQ LL LL L I NVALID CONDITION XL HH HH H INVALID CONDITION

Figure 1. Asynchronous operation Figure 2. Synchronous operation

Figure 3. Switching Waveforms Figure 4. Switching Waveforms

Figure 5. Switching Waveforms

81

IW4034B

TIMING DIAGRAM

82

EXPANDED LOGIC DIAGRAM

IW4034B

Steering logic diagram

Register stage logic diagram (1/8 stages)

83