V
IN
Gnd
+V
O
A2
10kΩ
50Ω
50Ω
All resistors 30kΩ unless otherwise indicated.
V+
+Sense
–Sense
–V
O
A3
A1
10kΩ
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
DRV13x Audio-Balanced Line Drivers
1 Features 3 Description
1
• Balanced Output
• Low Distortion: 0.0005% at f = 1 kHz
• Wide Output Swing: 17Vrms into 600 Ω
• High Capacitive Load Drive
• High Slew Rate: 15 V/µs
• Wide Supply Range: ±4.5 V to ±18 V
• Low Quiescent Current: ±5.2 mA
• 8-Pin DIP, SO-8, and SOL-16 Packages
• Companion to Audio Differential Line Receivers:
INA134 and INA137
• Improved Replacement for SSM2142
2 Applications
• Audio Differential Line Drivers
• Audio Mix Consoles
• Distribution Amplifiers
• Graphic and Parametric Equalizers
• Dynamic Range Processors
• Digital Effects Processors
• Telecom Systems
• Hi-Fi Equipment
• Industrial Instrumentation
The DRV134 and DRV135 are differential output
amplifiers that convert a single-ended input to a
balanced output pair. These balanced audio drivers
consist of high performance op amps with on-chip
precision resistors. They are fully specified for high
performance audio applications and have excellent ac
specifications, including low distortion (0.0005% at 1
kHz) and high slew rate (15 V/µs).
The on-chip resistors are laser-trimmed for accurate
gain and optimum output common-mode rejection.
Wide output voltage swing and high output drive
capability allow use in a wide variety of demanding
applications. They easily drive the large capacitive
loads associated with long audio cables. Used in
combination with the INA134 or INA137 differential
receivers, they offer a complete solution for
transmitting analog audio signals without degradation.
The DRV134 is available in 8-pin DIP and SOL-16
surface-mount packages. The DRV135 comes in a
space-saving SO-8 surface-mount package. Both are
specified for operation over the extended industrial
temperature range, –40°C to +85°C and operate from
–55°C to +125°C.
Device Information
PART NUMBER PACKAGE BODY SIZE (NOM)
DRV134 SOIC (16) 10.30 mm × 7.50 mm
DRV135 SOIC (8) 4.90 mm × 3.91 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
DRV134,DRV135
(1)
4 Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV134,DRV135
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
www.ti.com
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Simplified Schematic............................................. 1
5 Revision History..................................................... 2
6 Pin Configuration and Functions......................... 3
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 Handling Ratings....................................................... 4
7.3 Recommended Operating Conditions ...................... 4
7.4 Electrical Characteristics........................................... 5
7.5 Typical Characteristics.............................................. 6
8 Detailed Description ............................................ 11
8.1 Overview................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 13
9 Application and Implementation........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
10 Power Supply Recommendations..................... 17
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Examples................................................... 18
11.3 Thermal Performance ........................................... 19
12 Device and Documentation Support................. 19
12.1 Documentation Support ........................................ 19
12.2 Related Links ........................................................ 19
12.3 Trademarks........................................................... 19
12.4 Electrostatic Discharge Caution............................ 19
12.5 Glossary................................................................ 19
13 Mechanical, Packaging, and Orderable
Information........................................................... 20
5 Revision History
Changes from Revision A (April 2007) to Revision B Page
• Added Handling Rating table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
2 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated
Product Folder Links: DRV134 DRV135
Top View 8-Pin DIP/SO-8
Top View SOL-16
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
NC
+V
O
+Sense
V+
V–
NC
NC
NC
NC
–V
O
–Sense
Gnd
V
IN
NC
NC
1
2
3
4
8
7
6
5
+V
O
+Sense
V+
V–
–V
O
–Sense
Gnd
V
IN
www.ti.com
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
6 Pin Configuration and Functions
NOTE: NC - No internal connection
Pin Functions
PIN
NAME DIP-8 and SO-8 SOL-16
Gnd 3 5 – Ground
+Sense 7 13 I Sensing, non-inverting input
–Sense 2 4 I Sensing, inverting input
V+ 6 12 – Positive supply
V– 5 11 – Negative supply
V
–V
+V
IN
o
o
4 6 I Input
1 3 O Inverted, balanced differential output
8 14 O Balanced differential output
NC – 1,2,7,8,9,10,15,16 – These pins should be left unconnected
I/O DESCRIPTION
DRV134,DRV135
Copyright © 1998–2014, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Links: DRV134 DRV135
DRV134,DRV135
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
www.ti.com
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply voltage, V+ to V– 40 V
Input voltage range V– V+
Output short-circuit (to ground) Continuous
Operating temperature –55 125 °C
Junction temperature 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
T
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Storage temperature range –55 125 °C
stg
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all –2000 2000
(1)
Electrostatic discharge V
(ESD)
pins
Charged device model (CDM), per JEDEC specification –500 500
JESD22-C101, all pins
(2)
(1)
MIN MAX UNIT
MIN MAX UNIT
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
T
T
V+ Positive supply 4.5 18 18 V
V– Negative supply –4.5 –18 –18 V
Specification temperature range –40 85 °C
spe
Operation temperature range –55 125 °C
A
4 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated
Product Folder Links: DRV134 DRV135
DRV134,DRV135
www.ti.com
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
7.4 Electrical Characteristics
At TA= +25°C, VS= ±18 V, RL= 600 Ω differential connected between +VOand –VO, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO PERFORMANCE
THD+N Total Harmonic Distortion + Noise 0.001%
(1)
RTO
RTO
Noise Floor –98 dBu
(1)
Headroom 27 dBu
INPUT
Z
IN
I
IN
Input Impedance
Input Current VIN= ±7.07 V –1000 ±700 1000 µA
(2)
GAIN
Differential
Initial 5.8 6 dB
Error –2% ±0.1% 2%
Error vs Temperature ±10 ppm/°C
Single-Ended VIN= ±5V
Initial 5.8 6 dB
Error –2% ±0.7% 2%
Error vs Temperature ±10 ppm/°C
Nonlinearity 0.0003 % of FS
OUTPUT
OCMR Common-Mode Rejection, f = 1kHz See Figure 25 46 68 dB
SBR Signal Balance Ratio, f = 1kHz See Figure 26 35 54 dB
Output Offset Voltage
(3)
V
OCM
Offset Voltage, Common-Mode VIN= 0 –250 ±50 250 mV
Offset Voltage, Common-Mode vs ±150 µV/°C
Temperature
(4)
V
OD
Offset Voltage, Differential VIN= 0 –10 ±1 10 mV
Offset Voltage, Differential vs Temperature ±5 µV/°C
PSRR Offset Voltage, Differential vs Power Supply VS= ±4.5V to ±18V 80 110 dB
Output Voltage Swing, No Load
Positive (V+) – 3 (V+) – 2.5
Negative (V–) + 2 (V–) + 1.5
Impedance 50 Ω
C
L
I
SC
Load Capacitance, Stable Operation CLTied to Ground (each output) 1 µF
Short-Circuit Current ±85 mA
FREQUENCY RESPONSE
Small-Signal Bandwidth 1.5 MHz
SR Slew Rate 15 V/µs
Settling Time: 0.01% V
Overload Recovery Output Overdriven 10% 3 µs
POWER SUPPLY
V
S
Rated Voltage ±18 V
Voltage Range ±4.5 ±18 V
I
Q
Quiescent Current IO= 0 –5.5 ±5.2 5.5 mA
(1) dBu = 20log (Vrms /0.7746); RTO = Referred-to-Output.
(2) Resistors are ratio matched but have ±20% absolute value.
(3) V
(4) VOD= (+VO) – (–VO).
= [(+VO) + (–VO)] / 2.
OCM
(5) Ensures linear operation. Includes common-mode offset.
f = 20Hz to 20kHz, VO= 10Vrms
f = 1kHz, VO= 10Vrms
0.0005%
20 kHz BW
THD+N < 1%
10 kΩ
[(+VO) – (–VO)]/V
IN
VIN= ±10V
(5)
= 10V Step 2.5 µs
OUT
V
Copyright © 1998–2014, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: DRV134 DRV135
Frequency (Hz)
THD+N (%)
20 100 1k 10k 20k
0.1
0.01
0.001
0.0001
–VOor +VOGrounded
A: R
1
= 600Ω (250 ft cable)
B: R
1
= ∞ (no cable)
Single-Ended Mode
V
O
= 10Vrms
DRV134 Output
B
A
Frequency (Hz)
THD+N (%)
20 100 1k 10k 20k
0.01
0.001
0.0001
Differential Mode
V
O
= 10Vrms
See Figure 3 for Test Circuit
A: R
1
= R2= RL= ∞ (no load)
B: R
1
= R2= ∞ RL= 600Ω
INA137 Output
A (no cable)
B (500ft cable)
Frequency (Hz)
THD+N (%)
20 100 1k 10k 20k
C
0.01
0.001
0.0001
See Figure 3 for Test Circuit
A: R
1
= R2= RL= (no load)∞
B: R
1
= R2= 600Ω, RL= ∞
C: R
1
= R2= , R∞L= 600Ω
Differential Mode
V
O
= 10Vrms
No Cable
DRV134 Output
A
B
Frequency (Hz)
THD+N (%)
20 100 1k 10k 20k
0.01
0.001
0.0001
C
See Figure 3 for Test Circuit
A: R
1
= R2= RL= (no load)∞
B: R
1
= R2= 600Ω, RL= ∞
C: R
1
= R2= , R∞L= 600Ω
Differential Mode
V
O
= 10Vrms
500 ft cable
DRV134 Output
B
A
DRV134,DRV135
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
Electrical Characteristics (continued)
At TA= +25°C, VS= ±18 V, RL= 600 Ω differential connected between +VOand –VO, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TEMPERATURE RANGE
Specification Range –40 85 °C
Operation Range –55 125 °C
Storage Range –55 125 °C
θ
JA
Thermal Resistance 8-Pin DIP 100 °C/W
SO-8 Surface mount 150 °C/W
SOL-16 Surface 80 °C/W
mount
7.5 Typical Characteristics
At TA= 25°C, VS= ±18 V, RL= 600 Ω differential connected between +VOand –VO, unless otherwise noted.
www.ti.com
Figure 1. Total Harmonic Distortion + Noise vs Frequency Figure 2. Total Harmonic Distortion + Noise vs Frequency
Figure 3. Total Harmonic Distortion + Noise Figure 4. System Total Harmonic Distortion + Noise
6 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated
vs Frequency vs Frequency
Product Folder Links: DRV134 DRV135
Frequency (Hz)
Voltage Noise (nV/√Hz)
1 10 100 1k 10k 100k 1M
10k
1k
100
10
Frequency (Hz)
Voltage Noise (µVrms)
1 10 100 1k 10k 100k
100
10
1
0.1
Frequency (Hz)
Amplitude (% of Fundamental)
20 100 1k 20k10k
0.01
0.001
0.0001
0.00001
Differential Mode
2nd Harmonic
3rd Harmonic
No Cable, RL= ∞
500 ft Cable,
R
L
= 600Ω
Frequency (Hz)
Voltage Gain (dB)
1k 10k 100k 10M1M
10
5
0
–5
–10
Output Amplitude (dBu)
THD+N (%)
5 10 15 20 3025
1
0.1
0.01
0.001
0.0001
No Cable
R
L
= ∞
500 ft Cable
R
L
= 600Ω
Single-Ended
Mode
f = 1kHz
DRV134 Output
Differential
Mode
500 ft Cable
R
L
= 600Ω
Output Amplitude (dBu)
DIM (%)
5 10 15 20 3025
1
0.1
0.01
0.001
0.0001
Differential Mode
No Cable
R
L
= ∞
500 ft Cable
R
L
= 600Ω
BW = 30kHz
www.ti.com
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
Typical Characteristics (continued)
At TA= 25°C, VS= ±18 V, RL= 600 Ω differential connected between +VOand –VO, unless otherwise noted.
Figure 5. Headroom – Total Harmonic Distortion + Noise Figure 6. Dim Intermodulation Distortion
vs Output Amplitude vs Output Amplitude
DRV134,DRV135
Figure 7. Harmonic Distortion Products vs Frequency Figure 8. Gain vs Frequency
Copyright © 1998–2014, Texas Instruments Incorporated Submit Documentation Feedback 7
Figure 9. Output Voltage Noise Spectral Density Figure 10. Output Voltage Noise
vs Frequency vs Noise Bandwidth
Product Folder Links: DRV134 DRV135
Supply Voltage (V)
Quiescent Current (mA)
±4 ±18±16±14±12±10±8±6
±5.6
±5.4
±5.2
±5
±4.8
±4.6
T = –55°C
T = +25°C
T = +125°C
Temperature ( °C)
Short-Circuit Current (mA)
–75 –50 –25 0 25 50 75 125100
±120
±100
±80
±60
±40
±20
+I
SC
–I
SC
Output Current (mA)
Output Voltage Swing (V)
0 ±20 ±40 ±60 ±80 ±100
18
16
14
12
10
8
–8
–10
–12
–14
–16
–18
–55°C
+25°C
+125°C
+125°C
+25°C –55°C
Supply Voltage (V)
Differential Output Voltage (Vrms)
±4 ±6 ±8 ±10 ±12 ±14 ±16 ±18
20
16
12
8
4
0
THD+N ≤ 0.1%
Frequency (Hz)
Power Supply Rejection (dB)
10 100 1k 1M100k10k
120
100
80
60
40
20
0
+PSRR
–PSRR
VS= ±4.5V to ±18V
Frequency (Hz)
Output Voltage Swing (Vrms)
10k 20k 100k80k50k
20
16
12
8
4
0
0.1% Distortion
0.01% Distortion
R
L
= 600Ω
Diff Mode
DRV134,DRV135
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
Typical Characteristics (continued)
At TA= 25°C, VS= ±18 V, RL= 600 Ω differential connected between +VOand –VO, unless otherwise noted.
Figure 11. Power Supply Rejection vs Frequency Figure 12. Maximum Output Voltage Swing vs Frequency
www.ti.com
Figure 13. Output Voltage Swing vs Supply Voltage
8 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated
Figure 15. Quiescent Current vs Supply Voltage Figure 16. Short-Circuit Current vs Temperature
Figure 14. Output Voltage Swing vs Output Current
Product Folder Links: DRV134 DRV135
2µs/div
5V/div
2µs/div
5V/div
2µs/div
50mV/div
2µs/div
50mV/div
Percent of Units (%)
Common-Mode Offset Voltage (mV)
–
250
–
225
–
200
–
175
–
150
–
125
–
100
–
75
–
50
–
25
0
25
50
75
100
125
150
175
200
225
250
35
30
25
20
15
10
5
0
Typical production
distribution of packaged
units. All package types
included.
Percent of Units (%)
Differential Offset Voltage (mV)
–
10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
7
8
9
10
45
40
35
30
25
20
15
10
5
0
Typical production
distribution of packaged
units. All package types
included.
www.ti.com
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
Typical Characteristics (continued)
At TA= 25°C, VS= ±18 V, RL= 600 Ω differential connected between +VOand –VO, unless otherwise noted.
DRV134,DRV135
Figure 17. Differential Offset Voltage
Production Distribution
Figure 18. Common-Mode Offset Voltage
Production Distribution
CL= 100 pF CL= 1000 pF
Figure 19. Small-Signal Step Response Figure 20. Small-Signal Step Response
Copyright © 1998–2014, Texas Instruments Incorporated Submit Documentation Feedback 9
CL= 100 pF
Figure 21. Large-Signal Step Response
CL= 1000 pF
Figure 22. Large-Signal Step Response
Product Folder Links: DRV134 DRV135
Load Capacitance (pF)
Overshoot (%)
10 1k100 10k
40
30
20
10
0
100mV Step
DRV134,DRV135
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
Typical Characteristics (continued)
At TA= 25°C, VS= ±18 V, RL= 600 Ω differential connected between +VOand –VO, unless otherwise noted.
Figure 23. Small-Signal Step Overshoot vs Load Capacitance
www.ti.com
10 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated
Product Folder Links: DRV134 DRV135
V
IN
Gnd
+V
O
A2
10kΩ
50Ω
50Ω
All resistors 30kΩ unless otherwise indicated.
+Sense
–Sense
–V
O
G = +6dB
V+
(12)6
A3
A1
10kΩ
1µF
V–
DRV134
DRV135
5 (11)
1µF
4
(6)
3
(5)
8
(14)
7
(13)
2
(4)
1
(3)
DRV134,DRV135
www.ti.com
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
8 Detailed Description
8.1 Overview
The DRV134 and DRV135 consist of an input inverter driving a cross- coupled differential output stage with 50 Ω
series output resistors. Characterized by low differential-mode output impedance (50 Ω) and high common-mode
output impedance (1.6 kΩ), the DRV134 and DRV135 are ideal for audio applications.
Excellent internal design and layout techniques provide low signal distortion, high output level (27 dBu), and a
low noise floor (–98 dBu). Laser trimming of thin film resistors assures excellent output common-mode rejection
(OCMR) and signal balance ratio (SBR). In addition, low dc voltage offset reduces errors and minimizes load
currents.
The Functional Block Diagram section shows a detailed block diagram of the DRV134 and DRV135.
8.2 Functional Block Diagram
8.3 Feature Description
OCM
errors have virtually no effect on performance.
8.3.1 Audio Performance
The DRV134 and DRV135 were designed for enhanced ac performance. Very low distortion, low noise, and wide
bandwidth provide superior performance in high quality audio applications. Laser-trimmed matched resistors
provide optimum output common-mode rejection (typically 68dB), especially when compared to circuits
implemented with op amps and discrete precision resistors. In addition, high slew rate (15 V/μs) and fast settling
time (2.5 μs to 0.01%) ensure excellent dynamic response.
The DRV134 and DRV135 have excellent distortion characteristics. As shown in the distortion data provided in
the Typical Characteristics section, THD+Noise is below 0.003% throughout the audio frequency range under
various output conditions. Both differential and single-ended modes of operation are shown. In addition, the
optional 10μF blocking capacitors used to minimize V
Measurements were taken with an Audio Precision System One (with the internal 80 kHz noise filter) using the
THD test circuit shown in Figure 24.
Copyright © 1998–2014, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: DRV134 DRV135
600Ω
V
CM
= 10Vp-p
300Ω
(1)
300Ω
(1)
V
IN
Gnd
+V
O
V
OD
–V
O
DRV134
1µF
+18V
6
8
1
7
2
1µF
–18V
5
4
3
R
1
R
2
R
L
V
OUT
INA137
1µF
V
IN
+V
O
–In
+In
–V
O
+18V
7
2
3
6
1
5
1µF
–18V
4
DRV134
1µF
+18V
6
8
1
7
2
1µF
–18V
5
4
3
Test Point
or
DRV134,DRV135
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
www.ti.com
Feature Description (continued)
Up to approximately 10 kHz, distortion is below the measurement limit of commonly used test equipment.
Furthermore, distortion remains relatively constant over the wide output voltage swing range (approximately 2.5
V from the positive supply and 1.5 V from the negative supply). A special output stage topology yields a design
with minimum distortion variation from lot-to-lot and unit-to-unit. Furthermore, the small and large signal transient
response curves demonstrate the stability under load of the DRV134 and DRV135.
Figure 24. Distortion Test Circuit
8.3.2 Output Common-Mode Rejection
Output common-mode rejection (OCMR) is defined as the change in differential output voltage due to a change
in output common-mode voltage. When measuring OCMR, VINis grounded and a common-mode voltage, VCM,
is applied to the output as shown in Figure 25. Ideally no differential mode signal (VOD) should appear.
However, a small mode-conversion effect causes an error signal whose magnitude is quantified by OCMR.
Figure 25. Output Common-Mode Rejection Test Circuit
8.3.3 Signal Balance Ratio
Signal balance ratio (SBR) measures the symmetry of the output signals under loaded conditions. To measure
SBR an input signal is applied and the outputs are summed as shown in Figure 26. V
each output ideally is exactly equal and opposite. However, an error signal results from any imbalance in the
outputs. This error is quantified by SBR. The impedances of the DRV134 and DRV135’s output stages are
closely matched by laser trimming to minimize SBR errors. In an application, SBR also depends on the balance
of the load network.
12 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated
Product Folder Links: DRV134 DRV135
should be zero since
OUT
V
IN
Gnd
+V
O
A2
10kΩ
50Ω
50Ω
All resistors 30kΩ unless otherwise indicated.
+Sense
–Sense
–V
O
G = +6dB
V+
(12)6
A3
A1
10kΩ
1µF
V–
DRV134
DRV135
5 (11)
1µF
4
(6)
3
(5)
8
(14)
7
(13)
2
(4)
1
(3)
600Ω
300Ω
(1)
300Ω
(1)
V
OUT
V
IN
= 10Vp-p
+V
O
O
–V
DRV134
1µF
+18V
6
8
1
7
2
1µF
–18V
Gnd
5
4
3
DRV134,DRV135
www.ti.com
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
Feature Description (continued)
Figure 26. Signal Balance Ratio Test Circuit
8.4 Device Functional Modes
8.4.1 Differential-Output Mode
In differential-output mode, the DRV134 (and DRV135 in SO-8 package) converts a single-ended, groundreferenced input to a floating differential output with +6 dB gain (G = 2). Figure 27 shows the basic connections
required for operation in differential-output mode.
Normally, +VOis connected to +Sense, –VOis connected to –Sense, and the outputs are taken from these
junctions as shown in Figure 27.
Copyright © 1998–2014, Texas Instruments Incorporated Submit Documentation Feedback 13
Figure 27. Basic Connections for Differential-Output Mode
Product Folder Links: DRV134 DRV135
600Ω
V
OUT
= 2V
IN
V
IN
V+
DRV134
8
1
7
2
G = +6dB
4
5
6
3
DRV134,DRV135
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
www.ti.com
Device Functional Modes (continued)
8.4.2 Single-Ended Mode
The DRV134 can be operated in single-ended mode without degrading output drive capability. Single-ended
operation requires that the unused side of the output pair be grounded (both the VOand Sense pins) to a low
impedance return path. Gain remains +6 dB. Grounding the negative outputs as shown in Figure 28 results in a
non-inverted output signal (G = +2) while grounding the positive outputs gives an inverted output signal (G = –2).
Figure 28. Typical Single-Ended Application
For best rejection of line noise and hum differential mode operation is recommended. However, single-ended
performance is adequate for many applications. In general single ended performance is comparable to
differential mode (see THD+N typical performance curves), but the common mode and noise rejection inherent in
balanced-pair systems is lost.
14 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated
Product Folder Links: DRV134 DRV135
V
IN
Gnd
A2
10kΩ
50Ω
50Ω
All resistors 30kΩ unless otherwise indicated.
INA134 (G = 1): VO= 2V
IN
INA137 (G = 1/2): VO= V
IN
A3
A1
10kΩ
DRV134
DRV135
4
3
8
+V
O
–V
O
+V
O
–V
O
7
2
1
INA134, INA137
RECEIVER
DRIVER
BALANCED
CABLE PAIR
V
O
5
6
1
2
3
10µF
(1)
10µF
(1)
DRV134,DRV135
www.ti.com
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
Decoupling capacitors placed close to the device pins are strongly recommended in applications with noisy or
high impedance power supplies.
For best system performance, it is recommended that a high input-impedance difference amplifier be used as the
receiver. Used with the INA134 (G = 0 dB) or the INA137 (G = ±6 dB) differential line receivers, the DRV134
forms a complete solution for driving and receiving audio signals, replacing input and output coupling
transformers commonly used in professional audio systems (Figure 29). When used with the INA137 (G = –6 dB)
overall system gain is unity.
9.2 Typical Application
9.2.1 Cable Driving Application
The DRV134 is capable of driving large signals into 600-Ω loads over long cables. Low impedance shielded
audio cables such as the standard Belden 8451 or 9452 (or similar) are recommended, especially in applications
where long cable lengths are required.
For applications with large dc cable offset errors, a 10-µF electrolytic nonpolarized blocking capacitor at each
sense pin is recommended as shown in Figure 29.
Figure 29. Complete Audio Driver and Receiver Circuit
9.2.1.1 Design Requirements
Consider a design with the goal of differentially transmitting a single ended signal of up to 22.2 dBu through 500
ft of cable with no load at the receiving side. The signal at the end of the cable should have no more than 0.002
percent of total harmonic distortion plus noise (THD+N) at 10 kHz and less than 0.0005 percent of THD+N for
frequencies between 20 Hz and 1 kHz.
The system is required to put out a single ended signal 0 dB with respect to the input signal and accommodate
inputs with peak to RMS ratios of up to 1.5 for the maximum 22.2 dBu range established above.
Copyright © 1998–2014, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: DRV134 DRV135
R
1
R
2
R
L
V
OUT
INA137
1µF
V
IN
+V
O
–In
+In
–V
O
+18V
7
2
3
6
1
5
1µF
–18V
4
DRV134
1µF
+18V
6
8
1
7
2
1µF
–18V
5
4
3
Test Point
or
PEAKPEAK_IN
V97.1498.95.1V
RMS
20
L
IN
V98.910775.0V
u
¸
¸
¹
·
¨
¨
©
§
¸
¹
·
¨
©
§
775.0
x
log20L
10u
DRV134,DRV135
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
www.ti.com
Typical Application (continued)
9.2.1.2 Detailed Design Procedure
The dBu is a common unit of measurement for input sensitivity and output level of professional audio equipment.
A 0 dBu signal dissipates 1 mW into a 600-Ω resistive load; therefore, a 0 dBu signal corresponds to
approximately 0.775 V
and the signal level in V
For this design, the single ended input signal of 22.2 dBu corresponds to 9.98 V
Given that the system must accommodate for 22.2 dBu signals with up to 1.5 of peak to RMS ratio, the
maximum peak input signal is 14.97 V
The DRV134 is chosen to convert the single ended input signal into a differential signal and the outputs of the
DRV134 will be connected to one end of the 500 ft cable. In order to prevent clipping and distortion of the input
signal, the power supply rails for the DRV134 are chosen as 3 V above and below the peak calculated in
Equation 3. The 3 V margin is derived from the output voltage swing specification given in the Electrical
Characteristics table. The supplies selected are 18 V for V+ and –18 V for V–.
Finally, the INA137 is used at the end of the 500 ft cable in order to convert the differential signal output of the
DRV134 into a single ended signal that is 0 dB with respect to the input signal.
Figure 30 shows the system diagram.
. Equation 1 shows the relationship between the signal level in dBu (denoted by Lu)
RMS
(denoted by x).
RMS
as shown in Equation 2.
RMS
as calculated in Equation 3.
PEAK
(1)
(2)
(3)
Figure 30. Diagram of System Based on DRV134 and INA137
16 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated
Product Folder Links: DRV134 DRV135
Frequency (Hz)
THD+N (%)
20 100 1k 10k 20k
0.01
0.001
0.0001
C
See Figure 3 for Test Circuit
A: R
1
= R2= RL= (no load)∞
B: R
1
= R2= 600Ω, RL= ∞
C: R
1
= R2= , R∞L= 600Ω
Differential Mode
V
O
= 10Vrms
500 ft cable
DRV134 Output
B
A
www.ti.com
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
Typical Application (continued)
9.2.1.3 Application Curve
Figure 31 shows the performance obtained with the system depicted in Figure 30.
Figure 31. Measured Performance of a System Based on DRV134
10 Power Supply Recommendations
DRV134,DRV135
The DRV134 and DRV135 are designed to operate from an input voltage supply range between ±4.5 V and ±18
V. This input supply should be well regulated. If the input supply is located more than a few inches from the
DRV134 or DRV135 additional bulk capacitance may be required in addition to the ceramic bypass capacitors.
11 Layout
11.1 Layout Guidelines
A driver/receiver balanced-pair (such as the DRV134 and INA137) rejects the voltage differences between the
grounds at each end of the cable, which can be caused by ground currents, supply variations, etc. In addition to
proper bypassing (as shown in Figure 32 and Figure 33), the suggestions below should be followed to achieve
optimal OCMR and noise rejection.
• The DRV134 input should be driven by a low impedance source such as an op amp or buffer.
• As is the case for any single-ended system, the source’s common should be connected as close as possible
to the DRV134’s ground. Any ground offset errors in the source will degrade system performance.
• Symmetry on the outputs should be maintained.
• Shielded twisted-pair cable is recommended for all applications. Physical balance in signal wiring should be
maintained. Capacitive differences due to varying wire lengths may result in unequal noise pickup between
the pair and degrade OCMR. Follow industry practices for proper system grounding of the cables.
Copyright © 1998–2014, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: DRV134 DRV135
DRV135
-Vo
+Vo
+Sense
V-
-Sense
1
8
Top View
LEGEND
TOP layer:
copper pour & traces
PCB
via to ground plane
V
IN
V+
1 µF
SMD
0603
4
5
1 µF
SMD
0603
Gnd
DRV134
NC
-Vo
NC
+Vo
+Sense
V-
NC
-Sense
1
16
Top View
LEGEND
TOP layer:
copper pour & traces
PCB
via to ground plane
V
IN
NC
V+
NC
NC
NC
NC
1 µF
SMD
0603
8
9
1 µF
SMD
0603
Gnd
DRV134,DRV135
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
11.2 Layout Examples
www.ti.com
18 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated
Figure 32. DRV134 Layout Example
Figure 33. DRV135 Layout Example
Product Folder Links: DRV134 DRV135
DRV134,DRV135
www.ti.com
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
11.3 Thermal Performance
The DRV134 and DRV135 have robust output drive capability and excellent performance over temperature. In
most applications there is no significant difference between the DIP, SOL-16, and SO-8 packages. However, for
applications with extreme temperature and load conditions, the SOL-16 (DRV134UA) or DIP (DRV134PA)
packages are recommended. Under these conditions, such as loads greater than 600 Ω or very long cables,
performance may be degraded in the SO-8 (DRV135UA) package.
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Audio Differential Line Receivers 0dB (G = 1), INA134
• Audio Differential Line Receivers ±6dB (G = 1/2 or 2), INA137
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
PARTS PRODUCT FOLDER SAMPLE & BUY
DRV134 Click here Click here Click here Click here Click here
DRV135 Click here Click here Click here Click here Click here
TECHNICAL TOOLS & SUPPORT &
DOCUMENTS SOFTWARE COMMUNITY
12.3 Trademarks
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
Copyright © 1998–2014, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: DRV134 DRV135
DRV134,DRV135
SBOS094B –JANUARY 1998–REVISED DECEMBER 2014
www.ti.com
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
20 Submit Documentation Feedback Copyright © 1998–2014, Texas Instruments Incorporated
Product Folder Links: DRV134 DRV135
PACKAGE OPTION ADDENDUM
www.ti.com
PACKAGING INFORMATION
Orderable Device Status
DRV134PA ACTIVE PDIP P 8 50 Green (RoHS
DRV134PAG4 ACTIVE PDIP P 8 50 Green (RoHS
DRV134UA ACTIVE SOIC DW 16 40 Green (RoHS
DRV134UA/1K ACTIVE SOIC DW 16 1000 Green (RoHS
DRV134UAE4 ACTIVE SOIC DW 16 40 Green (RoHS
DRV135UA ACTIVE SOIC D 8 75 Green (RoHS
DRV135UA/2K5 ACTIVE SOIC D 8 2500 Green (RoHS
DRV135UA/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS
DRV135UAG4 ACTIVE SOIC D 8 75 Green (RoHS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Package Type Package
(1)
Drawing
Pins Package
Qty
Eco Plan
(2)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
Lead/Ball Finish
(6)
NIPDAU N / A for Pkg Type -55 to 125 DRV134PA
NIPDAU N / A for Pkg Type -55 to 125 DRV134PA
NIPDAU Level-3-260C-168 HR DRV134UA
NIPDAU Level-3-260C-168 HR DRV134UA
NIPDAU Level-3-260C-168 HR DRV134UA
NIPDAU Level-3-260C-168 HR -55 to 125 DRV
NIPDAU Level-3-260C-168 HR -55 to 125 DRV
NIPDAU Level-3-260C-168 HR -55 to 125 DRV
NIPDAU Level-3-260C-168 HR -55 to 125 DRV
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
135UA
135UA
135UA
135UA
(4/5)
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
6-Feb-2020
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
6-Feb-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Sep-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
DRV134UA/1K SOIC DW 16 1000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
DRV135UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)B0(mm)K0(mm)P1(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Sep-2014
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DRV134UA/1K SOIC DW 16 1000 367.0 367.0 38.0
DRV135UA/2K5 SOIC D 8 2500 367.0 367.0 35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
SOIC - 2.65 mm max heightDW 16
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
SMALL OUTLINE INTEGRATED CIRCUIT
Refer to the product data sheet for package details.
www.ti.com
4224780/A
PACKAGE OUTLINE
A
10.5
10.1
NOTE 3
SCALE 1.500
10.63
TYP
9.97
PIN 1 ID
AREA
1
8
B
7.6
7.4
NOTE 4
16
9
14X 1.27
2X
8.89
0.51
16X
0.31
0.25 C A B
SOIC - 2.65 mm max heightDW0016A
SOIC
C
SEATING PLANE
0.1 C
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
GAGE PLANE
0 - 8
0.25
1.27
0.40
(1.4)
DETAIL A
TYPICAL
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
0.3
0.1
www.ti.com
EXAMPLE BOARD LAYOUT
SOIC - 2.65 mm max heightDW0016A
SOIC
16X (2)
16X (0.6)
14X (1.27)
R0.05 TYP
SYMM
1
8
(9.3)
SEE
DETAILS
16
SYMM
9
LAND PATTERN EXAMPLE
SCALE:7X
METAL
0.07 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
4220721/A 07/2016
www.ti.com
EXAMPLE STENCIL DESIGN
SOIC - 2.65 mm max heightDW0016A
SOIC
16X (2)
16X (0.6)
14X (1.27)
R0.05 TYP
SYMM
1
8
(9.3)
16
SYMM
9
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SCALE:7X
4220721/A 07/2016
www.ti.com
PACKAGE OUTLINE
A
.189-.197
[4.81-5.00]
NOTE 3
.228-.244 TYP
[5.80-6.19]
1
4
B .150-.157
[3.81-3.98]
PIN 1 ID AREA
NOTE 4
SCALE 2.800
6X .050
[1.27]
8
2X
.150
[3.81]
5
8X .012-.020
[0.31-0.51]
.010 [0.25] C A B
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.004 [0.1] C
4X (0 -15 )
.069 MAX
[1.75]
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
0 - 8
.016-.050
[0.41-1.27]
(.041)
[1.04]
DETAIL A
TYPICAL
.004-.010
[0.11-0.25]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
8X (.061 )
8X (.024)
6X (.050 )
[1.27]
[0.6]
[1.55]
SYMM
1
4
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
EXAMPLE BOARD LAYOUT
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
SEE
DETAILS
8
SYMM
(R.002 ) TYP
5
[0.05]
EXPOSED
METAL
METAL
NON SOLDER MASK
SOLDER MASK
OPENING
.0028 MAX
[0.07]
ALL AROUND
DEFINED
SOLDER MASK
OPENING
EXPOSED
METAL
.0028 MIN
[0.07]
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL UNDER
SOLDER MASK
4214825/C 02/2019
www.ti.com
8X (.061 )
8X (.024)
[0.6]
6X (.050 )
[1.27]
[1.55]
EXAMPLE STENCIL DESIGN
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
SYMM
1
8
SYMM
(R.002 ) TYP
4
(.213)
[5.4]
5
[0.05]
BASED ON .005 INCH [0.125 MM] THICK STENCIL
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SCALE:8X
4214825/C 02/2019
SOLDER PASTE EXAMPLE
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
Loading...