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DM3725
PRODUCT PREVIEW
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User Manual
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Texas instruments DM3725, DM3730 PRODUCT PREVIEW

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PRODUCTPREVIEW
DM3730, DM3725
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1.1 Features

12345
• DM3730/25 Digital Media Processor: – Compatible with OMAP™ 3 Architecture – ARM®microprocessor (MPU) Subsystem
• Up to 1-GHz ARM®Cortex™-A8 Core See Processor Clocks OPP table.
• NEON SIMD Coprocessor
– High Performance Image, Video, Audio
(IVA2.2TM) Accelerator Subsystem
• Up to 800-MHz TMS320C64x+TMDSP Core
• Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
• Video Hardware Accelerators
– POWERVR SGX™ Graphics Accelerator
(DM3730 only)
• Tile Based Architecture Delivering up to 20 MPoly/sec
• Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality • 8-Bit Overflow Protection
• Industry Standard API Support: • Bit-Field Extract, Set, Clear OpenGLES 1.1 and 2.0, OpenVG1.0
• Fine Grained Task Switching, Load Balancing, and Power Management
• Programmable High Quality Image Anti-Aliasing
– Advanced Very-Long-Instruction-Word
(VLIW) TMS320C64x+TMDSP Core
• Eight Highly Independent Functional Units
• Six ALUs (32-/40-Bit); Each Supports Single 32- bit, Dual 16-bit, or Quad 8-bit, Arithmetic per Clock Cycle
• Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
• Load-Store Architecture With Non-Aligned Support
• 64 32-Bit General-Purpose Registers
• Instruction Packing Reduces Code Size
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2POWERVR SGX is a trademark of Imagination Technologies Ltd. 3OMAP is a trademark of Texas Instruments. 4Cortex is a trademark of ARM Limited. 5ARM is a registered trademark of ARM Ltd.
PRODUCT PREVIEW information concernsproducts in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change ordiscontinue these products withoutnotice.
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
DM3730, DM3725
Digital Media Processor
Check for Samples: DM3730, DM3725
• All Instructions Conditional
• Additional C64x+TMEnhancements – Protected Mode Operation – Expectations Support for Error
Detection and Program Redirection
– Hardware Support for Modulo Loop
Operation
– C64x+TML1/L2 Memory Architecture
• 32K-Byte L1P Program RAM/Cache (Direct Mapped)
• 80K-Byte L1D Data RAM/Cache (2-Way Set- Associative)
• 64K-Byte L2 Unified Mapped RAM/Cache (4- Way Set-Associative)
• 32K-Byte L2 Shared SRAM and 16K-Byte L2 ROM
– C64x+TMInstruction Set Features
• Byte-Addressable (8-/16-/32-/64-Bit Data)
• Normalization, Saturation, Bit-Counting
• Compact 16-Bit Instructions
• Additional Instructions to Support Complex Multiplies
– External Memory Interfaces:
• SDRAM Controller (SDRC) – 16, 32-bit Memory Controller With
1G-Byte Total Address Space – Interfaces to Low-Power SDRAM – SDRAM Memory Scheduler (SMS) and
Rotation Engine
• General Purpose Memory Controller (GPMC)
– 16-bit Wide Multiplexed Address/Data
Bus
– Up to 8 Chip Select Pins With
128M-Byte Address Space per Chip Select Pin
– Glueless Interface to NOR Flash,
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PRODUCTPREVIEW
DM3730, DM3725
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
NAND Flash (With ECC Hamming – System Direct Memory Access (SDMA) Code Calculation), SRAM and Controller (32 Logical Channels With Pseudo-SRAM Configurable Priority)
– Flexible Asynchronous Protocol – Comprehensive Power, Reset, and Clock
Control for Interface to Custom Logic Management (FPGA, CPLD, ASICs, etc.)
– Nonmultiplexed Address/Data Mode
(Limited 2K-Byte Address Space)
– 1.8-V I/O and 3.0-V (MMC1 only),
0.9-V to 1.2-V Adaptive Processor Core Voltage
0.9-V to 1.1-V Adaptive Core Logic Voltage Note: These are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex AVS.
– Commercial and Extended Temperature
Grades
– Serial Communication
• 5 Multichannel Buffered Serial Ports (McBSPs)
– 512 Byte Transmit/Receive Buffer
(McBSP1/3/4/5)
– 5K-Byte Transmit/Receive Buffer
(McBSP2)
– SIDETONE Core Support (McBSP2 and
3 Only) For Filter, Gain, and Mix Operations
– Direct Interface to I2S and PCM Device
and T Buses
– 128 Channel Transmit/Receive Mode
• Four Master/Slave Multichannel Serial Port Interface (McSPI) Ports
• High-Speed/Full-Speed/Low-Speed USB OTG Subsystem (12-/8-Pin ULPI Interface)
• High-Speed/Full-Speed/Low-Speed Multiport USB Host Subsystem
– 12-/8-Pin ULPI Interface or 6-/4-/3-Pin
Serial Interface
• One HDQ/1-Wire Interface
• Four UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
• Three Master/Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
– Camera Image Signal Processing (ISP)
• CCD and CMOS Imager Interface
• Memory Data Input
• BT.601/BT.656 Digital YCbCr 4:2:2 (8-/10-Bit) Interface
• Glueless Interface to Common Video Decoders
• Resize Engine – Resize Images From 1/4x to 4x – Separate Horizontal/Vertical Control
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• SmartReflexTMTechnology
• Dynamic Voltage and Frequency Scaling (DVFS)
– ARM®Cortex™-A8 Core
• ARMv7 Architecture – Trust Zone – Thumb®-2 – MMU Enhancements
• In-Order, Dual-Issue, Superscalar Microprocessor Core
• NEON Multimedia Architecture
• Over 2x Performance of ARMv6 SIMD
• Supports Both Integer and Floating Point SIMD
• Jazelle®RCT Execution Environment Architecture
• Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
• Embedded Trace Macrocell (ETM) Support for Non-Invasive Debug
– ARM Cortex-A8 Memory Architecture:
• 32K-Byte Instruction Cache (4-Way Set-Associative)
• 32K-Byte Data Cache (4-Way Set-Associative)
• 256K-Byte L2 Cache
– 32K-Byte ROM – 64K-Byte Shared SRAM – Endianess:
• ARM Instructions - Little Endian
• ARM Data – Configurable
• DSP Instructions/Data - Little Endian
• Removable Media Interfaces: – Three Multimedia Card (MMC)/ Secure Digital
(SD) With Secure Data I/O (SDIO)
• Test Interfaces – IEEE-1149.1 (JTAG) Boundary-Scan
Compatible – Embedded Trace Macro Interface (ETM) – Serial Data Transport Interface (SDTI)
• 12 32-bit General Purpose Timers
• 2 32-bit Watchdog Timers
• 1 32-bit Secure Watchdog Timer
• 1 32-bit 32-kHz Sync Timer
• Up to 188 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
• 45-nm CMOS Technology
2 DM3730, DM3725 Digital Media Processor Copyright © 2010, Texas Instruments Incorporated
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
• Package-On-Package (POP) Implementation for – 515-pin s-PBGA package (CBC Suffix), Memory Stacking (Not Available in CUS .65mm Ball Pitch (Top), .5mm Ball Pitch Package) (Bottom)
• Packages: – 423-pin s-PBGA package (CUS Suffix), – 515-pin s-PBGA package (CBP Suffix), .5mm
.65mm Ball Pitch
Ball Pitch (Top), .4mm Ball Pitch (Bottom)
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1.2 Description

The DM37x generation of high-performance, digital media processors are based on the enhanced device architecture and are integrated on TI's advanced 45-nm process technology. This architecture is designed to provide best in class ARM and Graphics performance while delivering low power consumption. This balance of performance and power allow the device to support the following example applications:
• Portable Data Terminals
• Navigation
• Auto Infotainment
• Gaming
• Medical Imaging
• Home Automation
• Human Interface
• Industrial Control
• Test and Measurement
• Single board Computers The device can support numerous HLOS and RTOS solutions including Linux and Windows Embedded
CE which are available directly from TI. Additionally, the device is fully backward compatible with previous Cortex™-A8 processors and OMAP™ processors.
This DM3730/25 Digital Media Processor data manual presents the electrical and mechanical specifications for the DM3730/25 Digital Media Processor. The information contained in this data manual applies to both the commercial and extended temperature versions of the DM3730/25 Digital Media Processor unless otherwise indicated. It consists of the following sections:
• A description of the DM3730/25 terminals: assignment, electrical characteristics, multiplexing, and functional description
• A presentation of the electrical characteristics requirements: power domains, operating conditions, power consumption, and dc characteristics
• The clock specifications: input and output clocks, DPLL and DLL
• A description of thermal characteristics, device nomenclature, and mechanical data about the available packaging
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PRODUCTPREVIEW
64
64
Async
64
64
L2$
256K
MPU
Subsystem
POWERVR
SGX
Graphics
Accelerator
TM
32
32
32
Channel
System
DMA
3232
Parallel
TV
Amp
LCD Panel
CVBS
or
S-Video
Dual Output 3-Layer
Display Processor
(1xGraphics, 2xVideo)
Temporal Dithering
SDTV QCIF Support®
32
Camera
ISP
Image
Capture
Hardware
Image
Pipeline
Camera
(Parallel)
64
HS USB
Host
HS USB OTG
32
L3 Interconnect Network-Hierarchial, Performance, and Power Driven
64KB
On-Chip
RAM
32
32KB
On-Chip
ROM
32
SMS:
SDRAM
Memory
Scheduler/
Rotation
64
SDRC:
SDRAM
Memory
Controller
L4 Interconnect
32
System
Controls
PRCM
2xSmartReflex
TM
Control Module
External
Peripherals
Interfaces
Peripherals: 4xUART,
3xHigh-Speed I2C, 5xMcBSP
(2x with Sidetone/Audio Buffer)
4xMcSPI, 6xGPIO 3xHigh-Speed MMC/SDIO HDQ/1 Wire, 6xMailboxes
12xGPTimers, 2xWDT,
32K Sync Timer
GPMC:
General Purpose Memory
Controller
NAND/
NOR Flash, SRAM
32
Emulation
Debug: SDTI, ETM, JTAG
External and
Stacked Memories
32
IVA 2.2 Subsystem
TMS320DM64x+ DSP
Imaging Video and
Audio Processor
32K/32K L1$
48K L1D RAM
64K L2$ 32K L2 RAM 16K L2 ROM
Video Hardware
64
32
Async
64
32
ARM
Cortex™- A8
®
Core
TrustZone
32K/32K L1$
DM3730, DM3725
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1.3 Functional Block Diagram

The functional block diagram of the DM3730/25 Digital Media Processor is shown below.
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
Copyright © 2010, Texas Instruments Incorporated DM3730, DM3725 Digital Media Processor 5
Figure 1-1. DM3730/25 Functional Block Diagram
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data sheet revision history highlights the technical changes made from the previous to the current revision.
SECTION ADDITIONS/CHANGES/DELETIONS
Terminal Description
Electrical Characteristics • Table 3-2 . Maximum Current Ratings at Ball Level
Clock Specifications
Timing Requirements and Switching Characteristics
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Revision History

Revision History
Updated/changed:
• Table 2-1. Ball Characteristics (CBP Pkg.)
• Table 2-2. Ball Characteristics (CBC Pkg.)
• Table 2-3. Ball Characteristics (CUS Pkg.) Updated/changed:
• Table 3-1. Absolute Maximum Rating over Junction Temperature Range
• Table 3-4. Recommended Operating Conditions
• Table 3-5. DC Electrical Characteristics Added/updated:
• Section 4.3.3. DPLL and DLL Noise Isolation
• Section 4.3.6. SGX Clock
• Table 4-2. Crystal Electrical Characteristics
• Table 4-13. sys_clkout2 Output Clock Switch Characteristics
• Table 4-18. Processor Voltages Without SmartReflex
• Table 4-19. Processor Voltages With SmartReflex
• Figure 4-8. DPLL and DLL Noise Filter Added/updated:
• Section 5.4.2.2. Placement
• Section 5.4.2.3. LPDDR Keep Out Region
• Section 5.4.2.4. Net Classes
• Section 5.4.2.5. LPDDR Signal Termination
• Section 5.4.2.6. LPDDR CK and ADDR_CTRL Routing
• Section 5.6.7.1. UART
• Table 5-22. ISP2P cam_xclka and cam_xclkb Output Clocks Switching Characteristics
TM
TM
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2
3
4
5
6
7
8
9
10
11
121314
15
16
17
18
19
20
21
22
23
A
B
C
D
E
F
G
H
J
K
L
M
N
P
T
R
U
V
W
Y
AA
AB
AC
24
25
26
27
28
AD
AE
AF
AG
AH
1
030-001
DM3730, DM3725
www.ti.com

2 TERMINAL DESCRIPTION

2.1 Terminal Assignment

Figure 2-1 through Figure 2-5 show the ball locations for the 515- and 423- ball plastic ball grid array
(s-PBGA) packages. Table 2-1 through Table 2-25 indicate the signal names and ball grid numbers for both packages.
Note: There are no balls present on the top of the 423-ball s-PBGA package.
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 7
Figure 2-1. DM3730/25 Digital Media Processor CBP s-PBGA-N515 Package (Bottom View)
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A
C
D
E
G
K
L
M
N
P
T
R
U
V
W
Y
AB
B
F
H
J
AA
AC
22
21
20
18
17
16
15
13
12 10
9
8
7
6
5
4
3
2
111
14
19
23
030-002
DM3730, DM3725
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
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8 TERMINAL DESCRIPTION Copyright © 2010, Texas Instruments Incorporated
Figure 2-2. DM3730/25 Digital Media Processor CBP s-PBGA-N515 Package (Top View)
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AF
AE AD AC AB AA
Y
W
V U
T R P N
M
L K
J H
G
F E D C B A
1 2 3 4 56789
10 11
12 13 14 15 16 17 18 19 20 21 22 23
24 25 26
DM3730, DM3725
www.ti.com
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
Figure 2-3. DM3730/25 Digital Media Processor CBC s-PBGA-515 Package (Bottom View)
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AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
DM3730, DM3725
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
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Figure 2-4. DM3730/25 Digital Media Processor CBC s-PBGA-515 Package (Top View)
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AD
AC
AB
AA
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1 2
3
4
5 6
7
8 9
10
11 121314
15 16
17
18 19
20
21 22
23
24
DM3730, DM3725
www.ti.com
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
Figure 2-5. DM3730/25 Digital Media Processor CUS s-PBGA-N423 Package (Bottom View)

2.2 Pin Assignments

2.2.1 Pin Map (Top View)

The following pin maps show the top views of the 515-pin sPBGA package [CBP], the 515-pin sPBGA package [CBC], and the 423-pin sPBGA package [CUS] pin assignments in four quadrants (A, B, C, and D).
Note: A pin with an "NC" designator indicates No Connection. For proper device operation, these pins must be left unconnected.
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A
98
vdds_mem
765432
NC
1
B
vdds_mem
vss
C
D
E
F
G
H
J
K
vdds_mem
NC
vdds_mem
NC
vss
vss
vdd_corevdd_core
vssvss
gpmc_nwe
gpmc_nadv
_ale
vdds_memvdds_mem
NC
gpmc_nbe0
_cle
gpmc_noe
NC
gpmc_wait3
vdd_core
gpmc_ncs1gpmc_d8
gpmc_nwp
vss
vdd_core
vss
vdds_memvdds_mem
vdd_mpu
_iva
gpmc_wait1
gpmc_a10gpmc_d9gpmc_d0
gpmc_a4
gpmc_wait2
vdd_mpu
_iva
gpmc_ncs0
vss
L
M
N
P
vdd_mpu
_iva
gpmc_wait0
gpmc_a9gpmc_d2
gpmc_d1
gpmc_ncs7
gpmc_a2
gpmc_a8
pop_k2
_m2
vss
gpmc_a1
gpmc_a7
pop_l2
_n2
pop_u1
_n1
vss
gpmc_d3gpmc_d10
vss
gpmc_ncs6
vss
gpmc_a3
14
NC
13
NC
121110
NC
vdds_mem
NC
vdds_mem
vssvss
vssvss
NCNC
NCNC
vssvss
vdd_mpu
_iva
vdd_mpu
_iva
vdd_mpu
_iva
vss
vdd_mpu
_iva
vdd_mpu
_iva
vss
vdd_mpu
_iva
NC
vdd_mpu
_iva
vdd_mpu
_iva
vdd_mpu
_iva
vss
pop_y23
_m1
NC NC
NC
NC
NC
NC
NC
NC
NC
NCNC
NCNCNC NCNCNC
NC
NC
NC NC
NC
NC NC
NC
NC
NC
NC NC
NC
NCNCNC
NC NC
DM3730, DM3725
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
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A. Top Views are provided to assist in hardware debugging efforts.
Figure 2-6. CBP Pin Map [Quadrant A - Top View]
12 TERMINAL DESCRIPTION Copyright © 2010, Texas Instruments Incorporated
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A
20 21 22 23 24 25
cam_d5
26 27
pop_a22
_a27
28
B
cam_d2 cam_d10
vss
C
D
dss_hsync
E
F
G
H
J
K
vdds_mem
cam_vs
cam_hs
pop_a23
_a28
vdds_mem
cam_wen
cam_xclkb
pop_b23
_b28
vss
cam_fld
cam_d3
vss
cam_xclka
cam_d11
cam_pclk vdds_mem
vss
vdd_core cam_d4
dss_vsync
dss_pclk
vdd_core
dss_data6
dss_acbias
dss_data20
vdds
dss_data8
dss_data7
uart3_rx
_irrx
dss_data9
vss
vdds_mem
dss_data19 dss_data18 dss_data17
vdds
vdd_core
hdq_sio
dss_data21
pop_k1
_j28
vss
mcbsp1_fsx
cam_d8 cam_d6
vdds_ mmc1
vdd_core
dss_data16
cam_strobevdd_core
L
M
N
P
vss
vss
cam_d9
cam_d7
vdd_core
mmc1
_cmd
vss
vdd_core
mmc1
_dat2
mmc1 _dat1
mmc1
_dat0
mmc1
_clk
gpio_127
gpio_126
mmc1 _dat3
vdds_x
vdd_core
vdd_core
15
pop_a12 _a15
16
NC
17 18 19
NC
NC
vdds_mem
NC NC
vdds_mem
vdds_mem
NC
vss
vdd_core vdds_mem
NC
vss
NC
NC
uart3_cts
_rctx
uart3_rts
_sd
vss vss
vdd_core
vdda_dplls
_dll
vdd_core
vss
vss
vss vss
vdd_mpu
_iva
NC
NC
vdd_core
vdd_core
vdd_core
vss
i2c1_sda
cap_vdd
_sram_core
i2c1_scl
mcbsp2_dx
mcbsp2
_clkx
mcbsp2_fsx
uart3_tx
_irtx
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
pop_b12
_b15
vdds
pop_h22
_j27
pop_k22
_m26
DM3730, DM3725
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
Figure 2-7. CBP Pin Map [Quadrant B - Top View]
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AH
9
etk_d5
8
etk_d15
7654
mmc2 _dat1
3
2
pop_ac2
_ah2
1
AG
mmc2 _cmd
mmc2 _dat2
vss
AF
etk_d8
AE
mmc2 _dat7
AD
AC
AB
AA
Y
W
etk_d13
vdds_mem
mmc2 _dat0
etk_d9etk_d14etk_d12
vssvss
pop_ab1
_ag1
etk_d11mcbsp3_dx
mcbsp3
_clkx
mmc2 _dat5
mmc2 _dat3
mmc2 _dat6
vdd_core
mcbsp3_dr
mcbsp3_fsx
mmc2
_clk
mcbsp4
_clkx
mcbsp4_dxmcbsp4_dr
vdd_core
mcspi1_cs1
mcspi1
_cs0
mcbsp4
_fsx
mcspi1_clk
mcspi1
_cs3
mcspi1
_cs2
uart1_tx
mcspi1
_somi
mcspi2_clk
pop_aa1
_aa1
vdd_mpu
_iva
mcspi2
_cs0
mcspi2
_somi
mcspi2_
simo
gpmc_d15
vdd_mpu
_iva
uart1_cts
vss
gpmc_d7
gpmc_d14
vdds
uart1_rx
uart1_rts
mcspi1
_simo
mmc2 _dat4
etk_d10
V
U
T
R
vss
gpmc_ncs2
mcspi2
_cs1
gpmc_d6
gpmc_d5
gpmc_ncs3
cap_vdd
_bb_mpu
_iva
gpmc_nbe1
vss
vdds_mem
vdd_mpu
_iva
gpmc_clk
gpmc_a5
gpmc_d13
gpmc_d4
vdd_mpu
_iva
gpmc_ncs5
gpmc_a6gpmc_d12gpmc_d11
vdds_mem
gpmc_ncs4
vss
cap_vdd
_sram
_mpu_iva
14
etk_d7
13121110
i2c3_scl
etk_d2
pop_ac9
_ah11
i2c3_sda
pop_ab11
_ag13
etk_d1
pop_ab9
_ag11
etk_d6
vss
etk_d0
etk_clk
sys_boot2
etk_d3
etk_d4etk_ctl
jtag_tckjtag_rtck
jtag_emu1
vdd_mpu
_iva
vdd_mpu
_iva
vdd_mpu
_iva
vss
vssvss
vdda_wkup
_bg_bb
vss
jtag_emu0
vss
vdd_mpu
_iva
vdd_mpu
_iva
vdd_mpu
_iva
vss
vdd_mpu
_iva
vss
vdd_mpu
_iva
pop_aa2
_aa2
vdds vdds
vdds
vdds
pop_u2
_af2
pop_ac8
_af1
pop_ab8
_ag10
pop_ac11
_ah13
pop_ac13
_ah10
pop_ac1
_ah1
DM3730, DM3725
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
www.ti.com
Figure 2-8. CBP Pin Map [Quadrant C - Top View]
14 TERMINAL DESCRIPTION Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): DM3730 DM3725
PRODUCTPREVIEW
AH
20
cap_vddu
_array
21
vss
22 23 24 25
sys
_nrespwron
26
27
pop_ac22
_ah27
28
AG
dss_data4 sys_clkout1
vdds
AF
vss
AE
i2c4_sda
AD
AC
AB
AA
Y
W
dss_data1
dss_data3
dss_data5
vdds
dss_data0
dss_data2
sys_boot1
pop_ab23
_ag28
sys_boot6
sys_off _mode
sys
_nreswarm
sys_boot0
sys_clkreq
sys_nirq
vss
sys_boot5
vdds vdd_core
uart2_rx
i2c4_scl
dss_data11
dss_data10
vss vss
dss_
data22
dss_
data23
uart2_cts
dss_data13
dss_data12
uart2_tx
dss_
data15
dss_
data14
vss
vssa_dac
cvideo1
_out
cvideo1
_rset
cvideo2
_vfb
cvideo2
_out
vss
uart2_rts
sys_32ksys_clkout2
V
U
T
R
hsusb0 _data7
hsusb0
_data6
hsusb0
_data5
hsusb0 _data4
hsusb0
_data3
hsusb0
_data2
hsusb0 _data1
hsusb0_stp hsusb0_nxt
hsusb0
_data0
hsusb0_clk
vss
gpio_128
hsusb0_dir
gpio_129
vdda_dac
15 16
pop_ac14
_ah16
17 18 19
i2c2_scl
cam_d1
gpio_115
pop_ab13
_ag15
cam_d0
vdds
sys_xtalout sys_boot3
sys_boot4
i2c2_sda
vdd_core
vdd_core
sys_xtalin
jtag_tdi
mcbsp1
_clkr
vdd_core
vdd_core
mcbsp1_dx
mcbsp1
_clkx
vdd_core
vdd_core
mcbsp1_dr
mcbsp_clks
vss
mcbsp2_dr
vss
cap_vddu
_wkup
_logic
vdda_dpll
_per
jtag_tms
_tmsc
jtag_tdo
vdd_core
sys_
xtalgnd
vdd_core
vdd_mpu
_iva
vdd_core
vss
vss
vdds_sram
vss
vdd_mpu
_iva
jtag_ntrst
vdd_core
vdd_core
vdd_core
vss
mcbsp1_fsr
NC
NC
cvideo1
_vfb
pop_aa23
_ae28
vdds
pop_h23
_af28
pop_aa22
_af27
vdds
pop_l1 _ah15
gpio_113
pop_ac23
_ah28
vss
gpio_114
gpio_112
vdds
DM3730, DM3725
www.ti.com
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
Figure 2-9. CBP Pin Map [Quadrant D - Top View]
Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 15
Product Folder Link(s): DM3730 DM3725
Submit Documentation Feedback
PRODUCTPREVIEW
A
98765432
NC
1
B
vss
C
D
E
F
G
H
J
K
gpmc _a11
pop_a1
_a1
NC
gpmc_
ncs2
vdds
uart1
_rx
vdd_mpu
_iva
mmc2 _dat7
vss
L
M
N
gpmc _d14
pop_j1
_l1
mcbsp3
_dr
cap_vdd
_sram
_mpu_iva
vdds
13121110
vdd_mpu
_iva
vss
vdd_mpu
_iva
vdda_ dplls_
dll
vdd_mpu
_iva
gpmc_
ncs4
gpmc_
wait2
NC vss
cap_
vdd_bb
_mpu_iva
NC
sys_
boot6
i2c2_scl vss
vss
NC vss NC NC NC NC vss
NC
vdd_
core
gpmc_
ncs6
gpmc_
ncs3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
vdds
NC
NC
NC
NC
gpmc_
wait3
gpmc_
ncs7
gpmc_
ncs5
sys_
boot2
sys_
boot1
I2C2_SDA
gpmc
_a9
gpmc _a10
gpmc
_a7
gpmc
_a8
sys_
boot3
sys_
boot4
gpmc
_a5
gpmc
_a6
sys_
boot0
NC
vss
gpmc
_a4
sys_
boot5
vdds
gpmc
_a2
gpmc
_a3
vss
gpmc
_nbe1
gpmc
_a1
NC NC
vss
gpmc
_nbe0
_cle
NC
mmc2 _dat6
gpmc
_nwe
gpmc _d15
mmc2 _dat5
uart1
_tx
gpmc
_clk
gpmc _noe
vss
NC
vdd_mpu
_iva
vss
vdd_mpu
_iva
NC vss
vdd_mpu
_iva
NC NC NC NC NC
NC
NC
NC
NC
vssNC
vdd_ core
vdds
NC
NCNCNC
NC
NC
NC
vdd_mpu
_iva
vdd_mpu
_iva
NC
NC
vss
vdd_mpu
_iva
DM3730, DM3725
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
www.ti.com
A. Top Views are provided to assist in hardware debugging efforts.
Figure 2-10. CBC Pin Map [Quadrant A - Top View]
16 TERMINAL DESCRIPTION Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): DM3730 DM3725
PRODUCTPREVIEW
A
18 19 20 21 22 23
cam_wen
24 25 26
B
NC
cam_d2
C
D
E
F
G
H
J
K
pop_b16
_a20
NC NC
NC
NC
pop_
b21_b26
NC
NC
NC
cam_ xclka
NC
NC NC
NC
uart3_ rts_sd
dss_
data20
dss_
acbias
dss_
data7
hdq_sio
vdd_ core
L
M
N
vdds_ mmc1
cam_d9
14
NC
15 16 17
NC
NC
NC NC
NC
NC
NC
NC
vss
NC
vss
cap_vddu_
wkup_
logic
vss
vdd_
core
i2c1_scl
NC
NC
NC
vdds
NC
NC
NCNC
NC
vss
vss
NC NC
NC vss
cam_d3
cam_d5
cam_d4
vdds
cam_fld
cam_hs
cam_vs
vss
pop_
a20_a25
pop_
a21_a26
cam_
pclk
cam_d10
cam_
strobe
cam_d11
dss_
pclk
cam_
xclkb
dss_
data6
uart3_
cts_
rctx
uart3_
tx_ irtx
vss
NC
uart3_
rx_ irrx
dss_
data8
dss_
data9
i2c1_sda
pop_
h21_k26
vss
dss_
hsync
NC
vss
vdds
dss_
data16
dss_
data17
dss_
data19
dss_
vsync
dss_
data18
NC
cam_d8
dss_
data21
NC NC
gpio_126
vdd_
core
NC vss
vdd_ core
NCNCNCNCNCNC
NCNC
vdds
NCNC
vdds
NC
NC NC
mmc1_
dat2
NC
cap_vdd
_sram_
core
vdds
vss
mmc1_
cmd
mmc1_
dat0
mmc1_
dat1
mmc1_
dat3
mmc1_
clk
NCvss
DM3730, DM3725
www.ti.com
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
Figure 2-11. CBC Pin Map [Quadrant B - Top View]
Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 17
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Product Folder Link(s): DM3730 DM3725
PRODUCTPREVIEW
AF
9
etk_d14
87654321
AE
AD
AC
AB
AA
Y
W
V
U
etk_d13
sys_ nres
warm
pop_t2
_y2
NC
etk_d9
gpmc
_d8
vdd_mpu
_iva
T
R
P
pop_n2
_t2
gpmc _d10
mcbsp4
_dx
uart1
_rts
mcspi1
_clk
NC
mcbsp3
_dx
gpmc _d13
mcspi1
_simo
13121110
gpmc_
nadv_ale
jtag_
rtck
NC
vdd_mpu
_iva
sys_
nresp
wron
sys_off _mode
vdd_mpu
_iva
vdd_mpu
_iva
vdds_
sram
vss
i2c3_scl
pop_aa11
_af13
pop_y9_
_af10
NC
uart1
_cts
vdd_
core
mcspi1
_cs0
mcspi1
_somi
jtag_
tdo
vdd_
core
vss
NC
vss vss
mcspi1
_cs1
mcspi1
_cs2
mmc2
_cmd
mmc2
_dat0
mmc2
_dat1
mcspi1
_cs3
vdds
mcbsp4
_fsx
gpmc
_d12
gpmc
_d11
mcbsp3
_clkx
mcbsp4
_dr
vdd_
core
mcspi2
_somi
mmc2 _dat3
mmc2
_dat2
vdd_mpu
_iva
mmc2
_dat4
mcspi2
_cs1
mcspi2
_cs0
vdd_mpu
_iva
mcbsp4
_clkx
mcbsp3
_fsx
vss
mcspi2
_clk
mcspi2
_simo
vdd_mpu
_iva
mmc2
_clk
sys_
clkout2
vdd_mpu
_iva
vdd_mpu
_iva
vdd_ core
vss
vdds
etk_d4
gpmc
_d9
gpmc
_d1
gpmc
_d0
etk_d3
etk_d8
etk_d5
etk_clk
etk_ctl
vss
gpmc
_d3
gpmc
_d2
etk_d0 i2c3_sda
gpmc
_d7
gpmc _nwp
vdds
gpmc
_wait1
NC vss
gpmc
_wait0
NC NC
NCNCNCNC
gpmc
_ncs0
gpmc
_d5
etk_d1etk_d2
etk_d7
gpmc _ncs1
gpmc
_d6
NC
pop_w2
_ae2
etk_d6 etk_d10
gpmc
_d4
etk_d12
vss NC
etk_d15
vdds
NC NC NC
pop_aa10
_af12
NC
pop_y7_
_af8
etk_d11
pop_aa6
_af5
pop_y2
_af4
NCNC
DM3730, DM3725
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
www.ti.com
Figure 2-12. CBC Pin Map [Quadrant C - Top View]
18 TERMINAL DESCRIPTION Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): DM3730 DM3725
PRODUCTPREVIEW
AF
18
19
sys_
xtalin
20 21 22
23
sys
_xtalgnd
24
25 26
AE
dss_
data1
AD
AC
AB
AA
Y
W
V
U
pop_y21
_ae26
vdd_ core
uart2
_cts
dss_
data13
dss_
data12
cvideo1
_rset
vssa_
dac
cvideo2
_out
cvideo2
_vfb
pop_
p21_u26
T
R
P
vdds
vdds_x
NC
cam_d7
14
pop_aa12
_af14
15 16 17
cam_d1 cam_d0
gpio_113
mcbsp1
_clkr
hsusb0 _data2
mcbsp2
_dx
gpio_129
gpio_128
vdda_ wkup_ bg_bb
i2c4_sda
jtag_tms
_tmsc
jtag_tdi
vss
vdda_
dpll_per
jtag_
ntrst
sys_nirq
gpio_127
vss
pop_aa21
_af26
sys_
clkout1
cap _vddu _array
mcbsp1
_dr
hsusb0
_stp
mcbsp2
_clkx
mcbsp1
_fsx
jtag_ emu1
cam_d6
NC NCNCNC
vdd_
core
mcbsp1
_clkx
mcbsp2
_dr
mcbsp
_clks
vss NC NC
vssNC
mcbsp2
_fsx
mcbsp1
_dx
jtag_tck
mcbsp1
_fsr
hsusb0
_dir
hsusb0
_data0
vdda_
dac
cvideo1
_out
cvideo1
_vfb
vdds
vss
hsusb0
_data3
hsusb0
_clk
hsusb0
_nxt
hsusb0 _data4
sys_
clkreq
jtag_
emu0
vss
hsusb0 _data7
hsusb0 _data5
hsusb0
_data6
hsusb0
_data1
NC vss
dss_
data14
uart2
_rts
NC
NC
vdds
dss_
data23
dss_
data15
dss_
data10
dss_
data22
vdds
NCNC
sys_32k
vss
vdds
NC
vss
NC
vdds
NC
vss
i2c4_scl gpio_112
vdds
vdds
vdds
uart2
_rts
uart2
_rx
uart2
_tx
dss_
data4
dss_
data5
vss
dss_
data11
pop_y20
_ae25
pop_aa20
_af25
pop_y19
_af24
pop_
aa19_af22
pop_y17
_af21
dss_
data3
dss_
data2
dss_
data0
gpio_114gpio_115
pop_aa13
_af15
pop_aa14
_af16
pop_y14
_af17
pop_aa17
_af18
sys_
xtalout
DM3730, DM3725
www.ti.com
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
Figure 2-13. CBC Pin Map [Quadrant D - Top View]
Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 19
Submit Documentation Feedback
Product Folder Link(s): DM3730 DM3725
PRODUCTPREVIEW
A
987654321
B
C
D
E
F
G
H
J
K
sdrc_a0
NC
NC
L
M
gpmc
_d0
mcspi2
_cs1
121110
sdrc
_dqs0
sdrc
_dm2
vdds_x
gpmc
_ncs3
gpmc _nwp
gpmc
_nadv
_ale
gpmc _noe
gpmc _a10
gpmc
_a8
gpmc
_a9
gpmc
_a6
gpmc
_d2
vdd_mpu
_iva
vss
vss
vdd_mpu
_iva
gpmc_
nbe0_cle
vdd_mpu
_iva
vdd_mpu
_iva
NC
sdrc
_dqs2
sdrc _clk
sdrc
_nclk
sdrc_a4 sdrc_a3 sdrc_a1 sdrc_d3
sdrc
_dm0
sdrc_d7 sdrc_d18 sdrc_d19 sdrc_d21 sdrc_d8 sdrc_d10
sdrc_d9sdrc_d20sdrc_d16sdrc_d6sdrc_d2sdrc_d1sdrc_a5
gpmc
_wait3
gpmc
_wait0
sdrc_a2 sdrc_d0 sdrc_d4 sdrc_d5 sdrc_d22
sdrc_d17sdrc_a8sdrc_a9sdrc_a10
sdrc_a6
gpmc
_ncs0
gpmc _ncs6
gpmc
_ncs4
sdrc_a7 sdrc_a13
sdrc_a14
vdd_ core
vdd_mpu
_iva
sdrc_a12sdrc_a11
gpmc _ncs5
gpmc
_ncs7
gpmc _nwe
vdd_mpu
_iva
vdd_mpu
_iva
vdd_ core
vdd_ core
vssvss
vdd_mpu
_iva
vdd_mpu
_iva
vdds
_mem
vdds
_mem
vdds
_mem
gpmc
_a4
gpmc
_a5
gpmc
_a7
gpmc
_a3
gpmc
_a2
gpmc
_a1
vdds
_mem
vdds
_mem
vdds
_mem
vss
vss
vdd_mpu
_iva
vssvss
gpmc_
nbe1
gpmc
_d1
gpmc
_d4
mcspi2
_cs0
vdd_mpu
_iva
vdd_mpu
_iva
vdd_mpu
_iva
vss
vss
DM3730, DM3725
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
www.ti.com
A. Top Views are provided to assist in hardware debugging efforts.
Figure 2-14. CUS Pin Map [Quadrant A - Top View]
20 TERMINAL DESCRIPTION Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): DM3730 DM3725
PRODUCTPREVIEW
A
16 17 18 19 20 21 22 23 24
B
cam_hs
C
D
E
F
G
H
J
K
dss_
data9
dss_
data19
dss_
acbias
L
M
13 14 15
sdrc_
dqs1
vdd_
core
cam_ xclka
uart3_
_cts_
rctx
hdq_si0
dss_
data6
dss_
data18
i2c1_sda
mmc1_
cmd
vdda
_dplls
_dll
cap_vdd
_sram
_core
vdds_
mem
cam_vs
vdd_
core
vss
cam_
strobe
cam_
pclk
vss
sdrc_
d14
sdrc_
dm3
sdrc_
dqs3
sdrc_
ncs0
sdrc_
nwe
uart3_
_rx_
irrx
uart3_
_rts_
sd
cam_d5
sdrc_
cke0
sdrc_
ncs1
sdrc_
d31
sdrc_
d30
sdrc_
d27
sdrc_
d15
sdrc_
d13
sdrc_
dm1
sdrc_
d12
sdrc_
d26
sdrc_
d28
sdrc_
ba0
sdrc_
ncas
sdrc_
cke1
cam_ xclkb
uart3_
_tx_
irtx
dss_
data20
sdrc_
nras
sdrc_
ba1
sdrc_
d29
sdrc_
d25
sdrc_
d11
sdrc_
d23
sdrc_
d24
vdds
dss_
hsync
dss_
data7
dss_
data8
dss_
vsync
cam_d10
cam_d3cam_wen
vdds_
mem
vdds_
mem
vdd_
core
vdds_
mem
vdds_
mem
cam_d2 cam_d4 cam_d11
dss_
pclk
dss_
data17
cam_fld
vdds_
mem
vss
vdd_
core
vss vss vss vss
vdd_
core
vdd_
core
dss_
data16
cam_d8
cam_d7cam_d9
dss_
data21
i2c1_scl
vdd_ core
vdd_
core
vdd_
core
vssvss
vss
vdd_
core
vdd_
core
vss
cam_d6
mmc1_
clk
mmc1_
dat0
mmc1_
dat1
mmc1_
dat2
vdds
vdds
vss
vdd_
core
DM3730, DM3725
www.ti.com
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
Figure 2-15. CUS Pin Map [Quadrant B - Top View]
Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 21
Submit Documentation Feedback
Product Folder Link(s): DM3730 DM3725
PRODUCTPREVIEW
AD
9
etk_d14
87654321
AC
AB
AA
Y
W
V
U
T
R
sys_ nres
warm
vdd_mpu
_iva
P
N
gpmc
_d3
uart1
_rx
121110
vdd_mpu
_iva
vss
NC
uart1
_rts
vss
mcspi2
_clk
mmc2
_dat3
gpmc
_d7
gpmc
_d8
mcspi2
_simo
mcspi1
_cs0
vdd_mpu
_iva
sys_
clkout1
etk_d4
gpmc
_d14
gpmc
_clk
etk_clk
sys_
clkout2
vdds
jtag_tms
_tmsc
vdds_
sram
sys_
boot0
uart1_
cts
etk_d10 etk_d8 etk_d1 etk_d12
i2c3_sda
etk_d0
mcbsp3
_dx
mcspi1
_simo
mcbsp1
_cs3
cap_vddu_ wkup_logic
vdd_mpu
_iva
vdd_mpu
_iva
mcspi2
_somi
vdd_mpu
_iva
vss
vss
vss
vss
vdd_mpu
_iva
vss
vss
vss
vss
vss
gpmc
_d11
gpmc
_d5
gpmc
_d6
vdd_mpu
_iva
vdd_mpu
_iva
mcspi1
_clk
gpmc
_d9
gpmc
_d12
mcspi1
_somi
vssvssvss
vssvss
cap_vdd
_sram_
mpu_iva
gpmc
_d13
gpmc
_d10
vdd_mpu
_iva
vddsvdds
mcbsp3
_fsx
gpmc
_d15
mcbsp3
_dr
vdd_mpu
_iva
vddsvdds
uart1
_tx
mcbsp3
_clkx
mmc2
_dat2
vdds
mmc2
_dat1
mmc2 _dat6
mmc2
_clk
mmc2 _dat7
mmc2 _dat5
jtag_
rtck
sys_
nres
pwron
jtag_
tdi
jtag_
tdo
jtag_
ntrst
jtag_
tck
mmc2 _cmd
mmc2
_dat0
mmc2 _dat4
etk_d2 etk_d11etk_d6
etk_d5
etk_ctl
etk_d9
etk_d3 etk_d7 etk_d13 etk_d15
DM3730, DM3725
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
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Figure 2-16. CUS Pin Map [Quadrant C - Top View]
22 TERMINAL DESCRIPTION Copyright © 2010, Texas Instruments Incorporated
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AD
16
17
sys_
xtalin
18 19 20
21 22 23 24
AC
dss_
data3
AB
AA
Y
W
V
U
T
R
dss_
data15
dss_
data14
cvideo1
_rset
P
N
13 14 15
mcbsp1
_clkx
vdds
vss
hsusb0
_stp
mmc1_
dat3
gpio_126
cap_vdd
_bb_mpu
_iva
vdd_
core
hsusb0
_dir
hsusb0
_data0
cvideo2
_out
cvideo1
_vfb
sys_
clkreq
dss_
data23
sys_32k
sys_
boot6
vdda_ wkup _bg_bb
i2c3_scl
vssa_dac
cam_d0
dss_
data12
sys_off
_mode
dss_
data10
dss_
data5
dss_
data0
cap_vddu
_array
sys_
xtalgnd
jtag_
emu0
i2c4_scl
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vss
vdds
vdds
vdds_ mmc1
gpio_129
vss
hsusb0
_clk
mcbsp2
_dx
vdd_
core
vdd_ core
hsusb0
_nxt
hsusb0 _data1
hsusb0
_data7
mcbsp2
_clkx
vdd_
core
vdd_
core
vdd_
core
vdd_ core
hsusb0
_data2
hsusb0 _data3
vdda_
dpll
_per
vdd_mpu
_iva
vdd_mpu
_iva
mcbsp2
_dr
mcbsp2
_fsx
dss_
data22
hsusb0 _data5
hsusb0 _data6
hsusb0
_data4
mcbsp1
_clkr
sys_
nirq
mcbsp1
_dx
vdd_mpu
_iva
cvideo2
_vfb
dss_
data13
mcbsp1
_dr
i2c4_sda
mcbsp
_clks
mcbsp1
_fsx
cvideo1
_out
mcbsp1
_fsr
dss_
data1
sys_
boot5
vdda_
dac
i2c2_sda i2c2_scl
sys_
boot1
sys_
boot4
cam_d1
dss_
data11
jtag_
emu1
dss_
data4
dss_
data2
sys_
boot3
sys_
boot2
sys_
xtaout
DM3730, DM3725
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
Figure 2-17. CUS Pin Map [Quadrant D - Top View]
Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 23
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010

2.3 Ball Characteristics

Table 2-1 through Table 2-3 describe the terminal characteristics and the signals multiplexed on each pin
for the CBP, CBC, and CUS packages, respectively. The following list describes the table column headers.
1. BALL BOTTOM: Ball number(s) on the bottom side associated with each signal(s) on the bottom.
2. BALL TOP: Ball number(s) on the top side associated with each signal(s) on the top.
3. PIN NAME: Names of signals multiplexed on each ball (also notice that the name of the pin is the signal name in mode 0). Note: Table 2-1 through Table 2-3 do not take into account subsystem pin multiplexing options. Subsystem pin multiplexing options are described in Section 2.5, Signal Descriptions.
4. MODE: Multiplexing mode number. (a) Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the pin
corresponds to the name of the pin. There is always a function mapped on the primary mode. Notice that primary mode is not necessarily the default mode.
Note: The default mode is the mode at the release of the reset; also see the RESET REL. MODE column.
(b) Modes 1 to 7 are possible modes for alternate functions. On each pin, some modes are effectively
used for alternate functions, while some modes are not used and do not correspond to a functional configuration.
5. TYPE: Signal direction – I = Input
– O = Output – I/O = Input/Output – D = Open drain – DS = Differential – A = Analog – PWR = Power – GND = Ground
Note: In the safe_mode, the buffer is configured in high-impedance.
6. BALL RESET STATE: The state of the terminal at the power-on reset. – 0: The buffer drives VOL(pulldown/pullup resistor not activated)
0(PD): The buffer drives VOLwith an active pulldown resistor.
– 1: The buffer drives VOH(pulldown/pullup resistor not activated)
1(PU): The buffer drives VOHwith an active pullup resistor. – Z: High-impedance – L: High-impedance with an active pulldown resistor – H : High-impedance with an active pullup resistor
7. BALL RESET REL. STATE: The state of the terminal at the release of the System Control Module reset (PRCM CORE_RSTPWRON_RET reset signal).
– 0: The buffer drives VOL(pulldown/pullup resistor not activated)
0(PD): The buffer drives VOLwith an active pulldown resistor.
– 1: The buffer drives VOH(pulldown/pullup resistor not activated)
1(PU): The buffer drives VOHwith an active pullup resistor. – Z: High-impedance – L: High-impedance with an active pulldown resistor – H : High-impedance with an active pullup resistor
8. RESET REL. MODE: The mode is automatically configured at the release of the System Control Module reset (PRCM CORE_RSTPWRON_RET reset signal).
9. POWER: The voltage supply that powers the terminal’s I/O buffers.
10. HYS: Indicates if the input buffer is with hysteresis.
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11. BUFFER STRENGTH: Drive strength of the associated output buffer.
12. PULL U/D - TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software. Note: The pullup/pulldown drive strength is equal to minimum = 50mA, typical = 100 mA, maximum = 250 mA (unless otherwise specified), except for CBP balls P27, P26, R27, and R25, and CUS balls N22 and P24, which the pulldown drive strength is equal to 1.8 kΩ.
13. IO CELL: IO cell information. Note: Configuring two pins to the same input signal is not supported as it can yield unexpected results.
This can be easily prevented with the proper software configuration.
In the DM3730/25 device, new Far End load Settings registers are added for some IOs. This new feature configures the IO according to the transmission line and the application/peripheral load. For a full description on these registers, see the System Control Module / SCM Functional Description / Functional Register Description / Signal Integrity Parameter Control Registers with Pad Group Assignment section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).
BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
NA J2 sdrc_d0 0 IO L Z 0 vdds_mem Yes 4 NA J1 sdrc_d1 0 IO L Z 0 vdds_mem Yes 4 NA G2 sdrc_d2 0 IO L Z 0 vdds_mem Yes 4 NA G1 sdrc_d3 0 IO L Z 0 vdds_mem Yes 4 NA F2 sdrc_d4 0 IO L Z 0 vdds_mem Yes 4 NA F1 sdrc_d5 0 IO L Z 0 vdds_mem Yes 4 NA D2 sdrc_d6 0 IO L Z 0 vdds_mem Yes 4 NA D1 sdrc_d7 0 IO L Z 0 vdds_mem Yes 4 NA B13 sdrc_d8 0 IO L Z 0 vdds_mem Yes 4 NA A13 sdrc_d9 0 IO L Z 0 vdds_mem Yes 4 NA B14 sdrc_d10 0 IO L Z 0 vdds_mem Yes 4 NA A14 sdrc_d11 0 IO L Z 0 vdds_mem Yes 4 NA B16 sdrc_d12 0 IO L Z 0 vdds_mem Yes 4 NA A16 sdrc_d13 0 IO L Z 0 vdds_mem Yes 4 NA B19 sdrc_d14 0 IO L Z 0 vdds_mem Yes 4 NA A19 sdrc_d15 0 IO L Z 0 vdds_mem Yes 4 NA B3 sdrc_d16 0 IO L Z 0 vdds_mem Yes 4 NA A3 sdrc_d17 0 IO L Z 0 vdds_mem Yes 4 NA B5 sdrc_d18 0 IO L Z 0 vdds_mem Yes 4 NA A5 sdrc_d19 0 IO L Z 0 vdds_mem Yes 4 NA B8 sdrc_d20 0 IO L Z 0 vdds_mem Yes 4 NA A8 sdrc_d21 0 IO L Z 0 vdds_mem Yes 4 NA B9 sdrc_d22 0 IO L Z 0 vdds_mem Yes 4 NA A9 sdrc_d23 0 IO L Z 0 vdds_mem Yes 4 NA B21 sdrc_d24 0 IO L Z 0 vdds_mem Yes 4 NA A21 sdrc_d25 0 IO L Z 0 vdds_mem Yes 4 NA D22 sdrc_d26 0 IO L Z 0 vdds_mem Yes 4 NA D23 sdrc_d27 0 IO L Z 0 vdds_mem Yes 4 NA E22 sdrc_d28 0 IO L Z 0 vdds_mem Yes 4 NA E23 sdrc_d29 0 IO L Z 0 vdds_mem Yes 4 NA G22 sdrc_d30 0 IO L Z 0 vdds_mem Yes 4 NA G23 sdrc_d31 0 IO L Z 0 vdds_mem Yes 4
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
NOTE
Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BUFFER
STATE [7] [11]
(3)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
(10)
PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS
Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 25
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BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
NA AB21 sdrc_ba0 0 O 0 0 0 vdds_mem No 4 NA AC21 sdrc_ba1 0 O 0 0 0 vdds_mem No 4 NA N22 sdrc_a0 0 O 0 0 0 vdds_mem No 4 NA N23 sdrc_a1 0 O 0 0 0 vdds_mem No 4 NA P22 sdrc_a2 0 O 0 0 0 vdds_mem No 4 NA P23 sdrc_a3 0 O 0 0 0 vdds_mem No 4 NA R22 sdrc_a4 0 O 0 0 0 vdds_mem No 4 NA R23 sdrc_a5 0 O 0 0 0 vdds_mem No 4 NA T22 sdrc_a6 0 O 0 0 0 vdds_mem No 4 NA T23 sdrc_a7 0 O 0 0 0 vdds_mem No 4 NA U22 sdrc_a8 0 O 0 0 0 vdds_mem No 4 NA U23 sdrc_a9 0 O 0 0 0 vdds_mem No 4 NA V22 sdrc_a10 0 O 0 0 0 vdds_mem No 4 NA V23 sdrc_a11 0 O 0 0 0 vdds_mem No 4 NA W22 sdrc_a12 0 O 0 0 0 vdds_mem No 4 NA W23 sdrc_a13 0 O 0 0 0 vdds_mem No 4 NA Y22 sdrc_a14 0 O 0 0 0 vdds_mem No 4 NA M22 sdrc_ncs0 0 O 1 1 0 vdds_mem No 4 NA M23 sdrc_ncs1 0 O 1 1 0 vdds_mem No 4 NA A11 sdrc_clk 0 IO L 0 0 vdds_mem Yes 4 NA B11 sdrc_nclk 0 O 1 1 0 vdds_mem No 4 NA J22 sdrc_cke0 0 O H 1 7 vdds_mem Yes 4
NA J23 sdrc_cke1 0 O H 1 7 vdds_mem NA 4
NA L23 sdrc_nras 0 O 1 1 0 vdds_mem No 4 NA L22 sdrc_ncas 0 O 1 1 0 vdds_mem No 4 NA K23 sdrc_nwe 0 O 1 1 0 vdds_mem No 4 NA C1 sdrc_dm0 0 O 0 0 0 vdds_mem No 4 NA A17 sdrc_dm1 0 O 0 0 0 vdds_mem No 4 NA A6 sdrc_dm2 0 O 0 0 0 vdds_mem No 4 NA A20 sdrc_dm3 0 O 0 0 0 vdds_mem No 4 NA C2 sdrc_dqs0 0 IO L Z 0 vdds_mem Yes 4 NA B17 sdrc_dqs1 0 IO L Z 0 vdds_mem Yes 4 NA B6 sdrc_dqs2 0 IO L Z 0 vdds_mem Yes 4 NA B20 sdrc_dqs3 0 IO L Z 0 vdds_mem Yes 4 N4 AC15 gpmc_a1 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS
M4 AB15 gpmc_a2 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS
L4 AC16 gpmc_a3 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS
K4 AB16 gpmc_a4 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS
T3 AC17 gpmc_a5 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS
R3 AB17 gpmc_a6 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
safe_mode_out1
safe_mode_out1
gpio_34 4 IO safe_mode 7
gpio_35 4 IO safe_mode 7
gpio_36 4 IO safe_mode 7
gpio_37 4 IO safe_mode 7
gpio_38 4 IO safe_mode 7
gpio_39 4 IO safe_mode 7
Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BUFFER
STATE [7] [11]
(13)
7
(13)
7
(3)
(continued)
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(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
(12)
NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS PU/ PD LVCMOS NA LVCMOS PU/ PD LVCMOS
PU/ PD LVCMOS
NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS NA LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS
26 TERMINAL DESCRIPTION Copyright © 2010, Texas Instruments Incorporated
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Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
N3 AC18 gpmc_a7 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
M3 AB18 gpmc_a8 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
L3 AC19 gpmc_a9 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
K3 AB19 gpmc_a10 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
NA AC20 gpmc_a11 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS
K1 M2 gpmc_d0 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS L1 M1 gpmc_d1 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS L2 N2 gpmc_d2 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS P2 N1 gpmc_d3 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS T1 R2 gpmc_d4 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS V1 R1 gpmc_d5 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS V2 T2 gpmc_d6 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS W2 T1 gpmc_d7 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS H2 AB3 gpmc_d8 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS
K2 AC3 gpmc_d9 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS
P1 AB4 gpmc_d10 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS
R1 AC4 gpmc_d11 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS
R2 AB6 gpmc_d12 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS
T2 AC6 gpmc_d13 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS
W1 AB7 gpmc_d14 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS
Y1 AC7 gpmc_d15 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS
G4 Y2 gpmc_ncs0 0 O 1 1 0 vdds_mem NA 8 NA LVCMOS H3 Y1 gpmc_ncs1 0 O H 1 0 vdds_mem Yes 8 PU/ PD LVCMOS
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
gpio_40 4 IO safe_mode 7
gpio_41 4 IO safe_mode 7
sys_ndmareq2 1 I gpio_42 4 IO safe_mode 7
sys_ndmareq3 1 I gpio_43 4 IO safe_mode 7
safe_mode 7
gpio_44 4 IO safe_mode 7
gpio_45 4 IO safe_mode 7
gpio_46 4 IO safe_mode 7
gpio_47 4 IO safe_mode 7
gpio_48 4 IO safe_mode 7
gpio_49 4 IO safe_mode 7
gpio_50 4 IO safe_mode 7
gpio_51 4 IO safe_mode 7
gpio_52 4 IO safe_mode 7
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(3)
(continued)
BALL BUFFER
STATE [7] [11]
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
V8 NA gpmc_ncs2 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
U8 NA gpmc_ncs3 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
T8 NA gpmc_ncs4 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
R8 NA gpmc_ncs5 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
P8 NA gpmc_ncs6 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
N8 NA gpmc_ncs7 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
T4 W2 gpmc_clk 0 O L 0 0 vdds_mem Yes 8 PU/ PD LVCMOS
F3 W1 gpmc_nadv_ale 0 O 0 0 0 vdds_mem NA 8 PU/ PD LVCMOS G2 V2 gpmc_noe 0 O 1 1 0 vdds_mem NA 8 PU/ PD LVCMOS F4 V1 gpmc_nwe 0 O 1 1 0 vdds_mem NA 8 PU/ PD LVCMOS G3 AC12 gpmc_nbe0_cle 0 O L 0 0 vdds_mem Yes 8 PU/ PD LVCMOS
U3 NA gpmc_nbe1 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS
H1 AB10 gpmc_nwp 0 O L 0 0 vdds_mem Yes 8 PU/ PD LVCMOS
M8 AB12 gpmc_wait0 0 I H H 0 vdds_mem Yes NA PU/PD LVCMOS L8 AC10 gpmc_wait1 0 I H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
K8 NA gpmc_wait2 0 I H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
gpio_53 4 IO safe_mode 7
sys_ndmareq0 1 I gpio_54 4 IO safe_mode 7
sys_ndmareq1 1 I mcbsp4_clkx 2 IO gpt_9_pwm_evt 3 IO gpio_55 4 IO safe_mode 7
sys_ndmareq2 1 I mcbsp4_dr 2 I gpt_10_pwm_evt 3 IO gpio_56 4 IO safe_mode 7
sys_ndmareq3 1 I mcbsp4_dx 2 IO gpt_11_pwm_evt 3 IO gpio_57 4 IO safe_mode 7
gpmc_io_dir 1 O mcbsp4_fsx 2 IO gpt_8_pwm_evt 3 IO gpio_58 4 IO safe_mode 7
gpio_59 4 IO safe_mode 7
gpio_60 4 IO safe_mode 7
gpio_61 4 IO safe_mode 7
gpio_62 4 IO safe_mode 7
gpio_63 4 IO safe_mode 7
uart4_tx 2 O gpio_64 4 IO safe_mode 7
Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BUFFER
STATE [7] [11]
(3)
(continued)
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Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
J8 NA gpmc_wait3 0 I H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
D28 NA dss_pclk 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
D26 NA dss_hsync 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
D27 NA dss_vsync 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
E27 NA dss_acbias 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS
AG22 NA dss_data0 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
AH22 NA dss_data1 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
AG23 NA dss_data2 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
AH23 NA dss_data3 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
AG24 NA dss_data4 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
AH24 NA dss_data5 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
E26 NA dss_data6 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
F28 NA dss_data7 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
sys_ndmareq1 1 I uart4_rx 2 I gpio_65 4 IO safe_mode 7
gpio_66 4 IO hw_dbg12 5 O safe_mode 7
gpio_67 4 IO hw_dbg13 5 O safe_mode 7
gpio_68 4 IO safe_mode 7
gpio_69 4 IO safe_mode 7
uart1_cts 2 I NA gpio_70 4 IO 8 safe_mode 7 8
uart1_rts 2 O 8 gpio_71 4 IO 8 safe_mode 7 8
gpio_72 4 IO 8 safe_mode 7 8
gpio_73 4 IO 8 safe_mode 7 8
uart3_rx_irrx 2 I NA gpio_74 4 IO 8 safe_mode 7 8
uart3_tx_irtx 2 O 8 gpio_75 4 IO 8 safe_mode 7 8
uart1_tx 2 O gpio_76 4 IO hw_dbg14 5 O safe_mode 7
uart1_rx 2 I gpio_77 4 IO hw_dbg15 5 O safe_mode 7
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(3)
(continued)
BALL BUFFER
STATE [7] [11]
Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 29
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
F27 NA dss_data8 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
G26 NA dss_data9 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
AD28 NA dss_data10 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
AD27 NA dss_data11 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
AB28 NA dss_data12 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
AB27 NA dss_data13 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
AA28 NA dss_data14 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
AA27 NA dss_data15 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
G25 NA dss_data16 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
H27 NA dss_data17 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
H26 NA dss_data18 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
H25 NA dss_data19 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
E28 NA dss_data20 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
J26 NA dss_data21 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
uart3_rx_irrx 2 I gpio_78 4 IO hw_dbg16 5 O safe_mode 7
uart3_tx_irtx 2 O gpio_79 4 IO hw_dbg17 5 O safe_mode 7
gpio_80 4 IO safe_mode 7
gpio_81 4 IO safe_mode 7
gpio_82 4 IO safe_mode 7
gpio_83 4 IO safe_mode 7
gpio_84 4 IO safe_mode 7
gpio_85 4 IO safe_mode 7
gpio_86 4 IO safe_mode 7
gpio_87 4 IO safe_mode 7
mcspi3_clk 2 IO dss_data0 3 IO gpio_88 4 IO safe_mode 7
mcspi3_simo 2 IO dss_data1 3 IO gpio_89 4 IO safe_mode 7
mcspi3_somi 2 IO dss_data2 3 IO gpio_90 4 IO safe_mode 7
mcspi3_cs0 2 IO dss_data3 3 IO gpio_91 4 IO safe_mode 7
Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BUFFER
STATE [7] [11]
(3)
(continued)
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Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
AC27 NA dss_data22 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS
AC28 NA dss_data23 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS
W28 NA cvideo2_out 0 AO 0 0 0 vdda_dac NA NA Y28 NA cvideo1_out 0 AO 0 0 0 vdda_dac NA NA Y27 NA cvideo1_vfb 0 AO 0 NA 0 vdda_dac NA NA W27 NA cvideo2_vfb 0 AO 0 NA 0 vdda_dac NA NA W26 NA cvideo1_rset 0 AIO 0 NA 0 vdda_dac No NA NA 10-bit DAC A24 NA cam_hs 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
A23 NA cam_vs 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
C25 NA cam_xclka 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
C27 NA cam_pclk 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
C23 NA cam_fld 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
AG17 NA cam_d0 0 I L L 7 vdds Yes NA PU/PD LVCMOS
AH17 NA cam_d1 0 I L L 7 vdds Yes NA PU/PD LVCMOS
B24 NA cam_d2 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
C24 NA cam_d3 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
D24 NA cam_d4 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
A25 NA cam_d5 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
mcspi3_cs1 2 O dss_data4 3 IO gpio_92 4 IO safe_mode 7
dss_data5 3 IO gpio_93 4 IO safe_mode 7
gpio_94 4 IO hw_dbg0 5 O safe_mode 7
gpio_95 4 IO hw_dbg1 5 O safe_mode 7
gpio_96 4 IO safe_mode 7
gpio_97 4 IO hw_dbg2 5 O safe_mode 7
cam_global_reset 2 IO gpio_98 4 IO hw_dbg3 5 O safe_mode 7
gpio_99 4 I safe_mode 7
gpio_100 4 I safe_mode 7
gpio_101 4 IO hw_dbg4 5 O safe_mode 7
gpio_102 4 IO hw_dbg5 5 O safe_mode 7
gpio_103 4 IO hw_dbg6 5 O safe_mode 7
gpio_104 4 IO
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(3)
(continued)
BALL BUFFER
STATE [7] [11]
(4)
(4)
(10)
(10)
NA 10-bit DAC NA 10-bit DAC NA 10-bit DAC NA 10-bit DAC
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BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
K28 NA cam_d6 0 I L L 7 vdds Yes NA PU/ PD LVCMOS
L28 NA cam_d7 0 I L L 7 vdds Yes NA PU/ PD LVCMOS
K27 NA cam_d8 0 I L L 7 vdds Yes NA PU/ PD LVCMOS
L27 NA cam_d9 0 I L L 7 vdds Yes NA PU/ PD LVCMOS
B25 NA cam_d10 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
C26 NA cam_d11 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
B26 NA cam_xclkb 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
B23 NA cam_wen 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
D25 NA cam_strobe 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
AG19 NA gpio_112 4 I L L 7 vdds Yes NA PU/PD LVCMOS
AH19 NA gpio_113 4 I L L 7 vdds Yes NA PU/PD LVCMOS
AG18 NA gpio_114 4 I L L 7 vdds Yes NA PU/PD LVCMOS
AH18 NA gpio_115 4 I L L 7 vdds Yes NA PU/PD LVCMOS
P21 NA mcbsp2_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
N21 NA mcbsp2_clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
R21 NA mcbsp2_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
M21 NA mcbsp2_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
hw_dbg7 5 O safe_mode 7
gpio_105 4 I safe_mode 7
gpio_106 4 I safe_mode 7
gpio_107 4 I safe_mode 7
gpio_108 4 I safe_mode 7
gpio_109 4 IO hw_dbg8 5 O safe_mode 7
gpio_110 4 IO hw_dbg9 5 O safe_mode 7
gpio_111 4 IO safe_mode 7
cam_shutter 2 O gpio_167 4 IO hw_dbg10 5 O safe_mode 7
gpio_126 4 IO hw_dbg11 5 O safe_mode 7
safe_mode 7
safe_mode 7
safe_mode 7 -
safe_mode 7 -
gpio_116 4 IO safe_mode 7
gpio_117 4 IO safe_mode 7
gpio_118 4 IO safe_mode 7
gpio_119 4 IO safe_mode 7
Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BUFFER
STATE [7] [11]
(3)
(continued)
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Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
N28 NA mmc1_clk 0 IO L L 7 vdds_mmc1(Yes 1 PU/ PD
M27 NA mmc1_cmd 0 O L L 7 vdds_mmc1(Yes 1 PU/ PD
N27 NA mmc1_dat0 0 IO L L 7 vdds_mmc1(Yes 1 PU/ PD
N26 NA mmc1_dat1 0 IO L L 7 vdds_mmc1(Yes 1 PU/ PD
N25 NA mmc1_dat2 0 IO L L 7 vdds_mmc1(Yes 1 PU/ PD
P28 NA mmc1_dat3 0 IO L L 7 vdds_mmc1(Yes 1 PU/ PD
P27 NA gpio_126
P26 NA gpio_127
R27 NA gpio_128
R25 NA gpio_129
AE2 NA mmc2_clk 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
AG5 NA mmc2_cmd 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
AH5 NA mmc2_dat0 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
AH4 NA mmc2_dat1 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
AG4 NA mmc2_dat2 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
AF4 NA mmc2_dat3 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
AE4 NA mmc2_dat4 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
(1)
gpio_120 safe_mode 7
(1)
gpio_121 safe_mode 7
(1)
gpio_122 safe_mode 7
(1)
gpio_123 safe_mode 7
(1)
gpio_124 safe_mode 7
(1)
gpio_125 safe_mode 7
(1)
safe_mode 7
(1)
safe_mode 7
(1)
safe_mode 7
(1)
safe_mode 7
mcspi3_clk 1 IO gpio_130 4 IO safe_mode 7
mcspi3_simo 1 IO gpio_131 4 IO safe_mode 7
mcspi3_somi 1 IO gpio_132 4 IO safe_mode 7
gpio_133 4 IO safe_mode 7
mcspi3_cs1 1 O gpio_134 4 IO safe_mode 7
mcspi3_cs0 1 IO gpio_135 4 IO safe_mode 7
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(3)
(continued)
BALL BUFFER
STATE [7] [11]
15)
4 IO
15)
4 IO
15)
4 IO
15)
4 IO
15)
4 IO
15)
4 IO
4 IO L L 7 vdds_x Yes 1 PU/ PD
4 IO L L 7 vdds_x Yes 1 PU/ PD
4 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
4 IO L L 7 vdds_x Yes 1 PU/ PD
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
(5)
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
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BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
AH3 NA mmc2_dat5 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
AF3 NA mmc2_dat6 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
AE3 NA mmc2_dat7 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
AF6 NA mcbsp3_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
AE6 NA mcbsp3_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
AF5 NA mcbsp3_clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
AE5 NA mcbsp3_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
AB26 NA uart2_cts 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS
AB25 NA uart2_rts 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
AA25 NA uart2_tx 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
mmc2_dir_dat0 1 O mmc3_dat0 3 IO gpio_136 4 IO safe_mode 7
mmc2_dir_dat1 1 O cam_global_reset 2 IO mmc3_dat1 3 IO gpio_137 4 IO mm3_rxdp 6 IO safe_mode 7
mmc2_dir_cmd 1 O cam_shutter 2 O mmc3_dat2 3 IO gpio_138 4 IO safe_mode 7
mmc2_clkin 1 I mmc3_dat3 3 IO gpio_139 4 IO mm3_rxdm 6 IO safe_mode 7
uart2_cts 1 I gpio_140 4 IO safe_mode 7
uart2_rts 1 O gpio_141 4 IO safe_mode 7
uart2_tx 1 O gpio_142 4 IO safe_mode 7
uart2_rx 1 I gpio_143 4 IO safe_mode 7
mcbsp3_dx 1 IO gpt_9_pwm_evt 2 IO gpio_144 4 IO safe_mode 7
mcbsp3_dr 1 I gpt_10_pwm_evt 2 IO gpio_145 4 IO safe_mode 7
mcbsp3_clkx 1 IO gpt_11_pwm_evt 2 IO gpio_146 4 IO safe_mode 7
Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BUFFER
STATE [7] [11]
(3)
(continued)
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Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
AD25 NA uart2_rx 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS
AA8 NA uart1_tx 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
AA9 NA uart1_rts 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
W8 NA uart1_cts 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
Y8 NA uart1_rx 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
AE1 NA mcbsp4_clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
AD1 NA mcbsp4_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
AD2 NA mcbsp4_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
AC1 NA mcbsp4_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
Y21 NA mcbsp1_clkr 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
AA21 NA mcbsp1_fsr 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
V21 NA mcbsp1_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
U21 NA mcbsp1_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
T21 NA mcbsp_clks 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
mcbsp3_fsx 1 IO gpt_8_pwm_evt 2 IO gpio_147 4 IO safe_mode 7
gpio_148 4 IO safe_mode 7
gpio_149 4 IO safe_mode 7
gpio_150 4 IO safe_mode 7
mcbsp1_clkr 2 IO mcspi4_clk 3 IO gpio_151 4 IO safe_mode 7
gpio_152 4 IO mm3_txse0 6 IO safe_mode 7
gpio_153 4 IO mm3_rxrcv 6 IO safe_mode 7
gpio_154 4 IO mm3_txdat 6 IO safe_mode 7
gpio_155 4 IO mm3_txen_n 6 IO safe_mode 7
mcspi4_clk 1 IO gpio_156 4 IO safe_mode 7
cam_global_reset 2 IO gpio_157 4 IO safe_mode 7
mcspi4_simo 1 IO mcbsp3_dx 2 IO gpio_158 4 IO safe_mode 7
mcspi4_somi 1 IO mcbsp3_dr 2 I gpio_159 4 IO safe_mode 7
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(3)
(continued)
BALL BUFFER
STATE [7] [11]
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
K26 NA mcbsp1_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
W21 NA mcbsp1_clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
H18 NA uart3_cts_rctx 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
H19 NA uart3_rts_sd 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
H20 NA uart3_rx_irrx 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS
H21 NA uart3_tx_irtx 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
T28 NA hsusb0_clk 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
T25 NA hsusb0_stp 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
R28 NA hsusb0_dir 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
T26 NA hsusb0_nxt 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
T27 NA hsusb0_data0 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
U28 NA hsusb0_data1 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
U27 NA hsusb0_data2 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
U26 NA hsusb0_data3 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
cam_shutter 2 O gpio_160 4 IO uart1_cts 5 I safe_mode 7
mcspi4_cs0 1 IO mcbsp3_fsx 2 IO gpio_161 4 IO safe_mode 7
mcbsp3_clkx 2 IO gpio_162 4 IO safe_mode 7
gpio_163 4 IO safe_mode 7
gpio_164 4 IO safe_mode 7
gpio_165 4 IO safe_mode 7
gpio_166 4 IO safe_mode 7
gpio_120 4 IO safe_mode 7
gpio_121 4 IO safe_mode 7
gpio_122 4 IO safe_mode 7
gpio_124 4 IO safe_mode 7
uart3_tx_irtx 2 O gpio_125 4 IO uart2_tx 5 O safe_mode 7
uart3_rx_irrx 2 I gpio_130 4 IO uart2_rx 5 I safe_mode 7
uart3_rts_sd 2 O gpio_131 4 IO uart2_rts 5 O safe_mode 7
uart3_cts_rctx 2 IO
Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BUFFER
STATE [7] [11]
(3)
(continued)
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Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
U25 NA hsusb0_data4 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
V28 NA hsusb0_data5 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
V27 NA hsusb0_data6 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
V26 NA hsusb0_data7 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
K21 NA i2c1_scl 0 OD H H 0 vdds NA 3 PU/ PD J21 NA i2c1_sda 0 IOD H H 0 vdds Yes 3 PU/ PD AF15 NA i2c2_scl 0 OD H H 7 vdds Yes 3 PU/ PD
AE15 NA i2c2_sda 0 IOD H H 7 vdds Yes 3 PU/ PD
AF14 NA i2c3_scl 0 OD H H 7 vdds Yes 3 PU/ PD
AG14 NA i2c3_sda 0 IOD H H 7 vdds Yes 3 PU/ PD
AD26 NA i2c4_scl 0 OD H H 0 vdds Yes 3 PU/ PD
AE26 NA i2c4_sda 0 IOD H H 0 vdds Yes 3 PU/ PD
J25 NA hdq_sio 0 IOD H H 7 vdds Yes 4 PU/ PD LVCMOS
AB3 NA mcspi1_clk 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
AB4 NA mcspi1_ simo 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
AA4 NA mcspi1_ somi 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
AC2 NA mcspi1_cs0 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
gpio_169 4 IO uart2_cts 5 I safe_mode 7
gpio_188 4 IO safe_mode 7
gpio_189 4 IO safe_mode 7
gpio_190 4 IO safe_mode 7
gpio_191 4 IO safe_mode 7
gpio_168 4 IO 4 safe_mode 7
gpio_183 4 IO 4 safe_mode 7
gpio_184 4 IO 4 safe_mode 7
gpio_185 4 IO 4 safe_mode 7
sys_ nvmode1 1 O 4 safe_mode 7
sys_ nvmode2 1 O 4 safe_mode 7
sys_altclk 1 I i2c2_sccbe 2 OD i2c3_sccbe 3 OD gpio_170 4 IO safe_mode 7
mmc2_dat4 1 IO gpio_171 4 IO safe_mode 7
mmc2_dat5 1 IO gpio_172 4 IO safe_mode 7
mmc2_dat6 1 IO gpio_173 4 IO safe_mode 7
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(3)
(continued)
BALL BUFFER
STATE [7] [11]
(6)(7)
(6)(7)
(6) (8)
(6) (8)
(6) (8)
(6) (8)
(6)(7)
(6)(7)
Open Drain Open Drain Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
Open Drain
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BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
AC3 NA mcspi1_cs1 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
AB1 NA mcspi1_cs2 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
AB2 NA mcspi1_cs3 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
AA3 NA mcspi2_clk 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
Y2 NA mcspi2_ simo 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
Y3 NA mcspi2_ somi 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
Y4 NA mcspi2_cs0 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
V3 NA mcspi2_cs1 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
AE25 NA sys_32k 0 I Z Z 0 vdds Yes NA PU/ PD LVCMOS AE17 NA sys_xtalin 0 AI Z Z 0 vdds Yes NA No LVCMOS
AF17 NA sys_xtalout 0 AO Z 0 0 vdds NA NA NA LVCMOS
AF25 NA sys_clkreq 0 IO 0 See
AF26 NA sys_nirq 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS
AH25 NA sys_nrespwron 0 I Z Z 0 vdds Yes NA No LVCMOS AF24 NA sys_nreswarm 0 IOD 0 1 0 vdds Yes 4 PU/ PD LVCMOS
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
mmc2_dat7 1 IO gpio_174 4 IO safe_mode 7
mmc3_cmd 3 O gpio_175 4 IO safe_mode 7
mmc3_clk 3 IO gpio_176 4 IO safe_mode 7
hsusb2_ data2 3 IO gpio_177 4 IO mm2_txdat 5 IO safe_mode 7
hsusb2_ data7 3 IO gpio_178 4 IO safe_mode 7
gpt_9_pwm_evt 1 IO hsusb2_ data4 3 IO gpio_179 4 IO safe_mode 7
gpt_10_pwm_evt 1 IO hsusb2_ data5 3 IO gpio_180 4 IO safe_mode 7
gpt_11_pwm_evt 1 IO hsusb2_ data6 3 IO gpio_181 4 IO safe_mode 7
gpt_8_pwm_evt 1 IO hsusb2_ data3 3 IO gpio_182 4 IO mm2_txen_n 5 IO safe_mode 7
gpio_1 4 IO safe_mode 7
gpio_0 4 IO safe_mode 7
gpio_30 4 IO Open Drain
Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BUFFER
STATE [7] [11]
(11)
0 vdds Yes 4 PU/ PD LVCMOS
(3)
(continued)
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Analog
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Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
AH26 NA sys_boot0 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
AG26 NA sys_boot1 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
AE14 NA sys_boot2 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
AF18 NA sys_boot3 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
AF19 NA sys_boot4 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
AE21 NA sys_boot5 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
AF21 NA sys_boot6 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
AF22 NA sys_off_mode 0 O 0 L 7 vdds Yes 4 PU/ PD LVCMOS
AG25 NA sys_clkout1 0 O L L 7
AE22 NA sys_clkout2 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
AA17 NA jtag_ntrst 0 I L L 0 vdds Yes NA PU/ PD LVCMOS AA13 NA jtag_tck 0 I L L 0 vdds Yes NA PU/ PD LVCMOS AA12 NA jtag_rtck 0 O L 0 0 vdds NA 4 PU/ PD LVCMOS AA18 NA jtag_tms_tmsc 0 IO H H 0 vdds Yes 4 PU/ PD LVCMOS AA20 NA jtag_tdi 0 I H H 0 vdds Yes NA PU/ PD LVCMOS AA19 NA jtag_tdo 0 O L Z 0 vdds NA 4 PU/ PD LVCMOS AA11 NA jtag_emu0 0 IO H H 0 vdds Yes 4 PU/ PD LVCMOS
AA10 NA jtag_emu1 0 IO H H 0 vdds Yes 4 PU/ PD LVCMOS
AF10 NA etk_clk 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
safe_mode 7
dss_data18 3 IO gpio_2 4 IO safe_mode 7
dss_data19 3 IO gpio_3 4 IO safe_mode 7
gpio_4 4 IO safe_mode 7
dss_data20 3 O gpio_5 4 IO safe_mode 7
mmc2_dir_dat2 1 O dss_data21 3 O gpio_6 4 IO safe_mode 7
mmc2_dir_dat3 1 O dss_data22 3 O gpio_7 4 IO safe_mode 7
dss_data23 3 O gpio_8 4 IO safe_mode 7
gpio_9 4 IO safe_mode 7
gpio_10 4 IO safe_mode 7
gpio_186 4 IO safe_mode 7
gpio_11 4 IO safe_mode 7
gpio_31 4 IO safe_mode 7
mcbsp5_ clkx 1 IO mmc3_clk 2 IO
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(3)
(continued)
BALL BUFFER
STATE [7] [11]
(14)
vdds Yes 4 PU/ PD LVCMOS
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BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
AE10 NA etk_ctl 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS
AF11 NA etk_d0 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS
AG12 NA etk_d1 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS
AH12 NA etk_d2 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS
AE13 NA etk_d3 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS
AE11 NA etk_d4 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
AH9 NA etk_d5 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
AF13 NA etk_d6 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
AH14 NA etk_d7 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
hsusb1_stp 3 O gpio_12 4 IO mm1_rxdp 5 IO hw_dbg0 7 O
mmc3_cmd 2 O hsusb1_clk 3 O gpio_13 4 IO hw_dbg1 7 O
mcspi3_ simo 1 IO mmc3_dat4 2 IO hsusb1_ data0 3 IO gpio_14 4 IO mm1_rxrcv 5 IO hw_dbg2 7 O
mcspi3_ somi 1 IO hsusb1_ data1 3 IO gpio_15 4 IO mm1_txse0 5 IO hw_dbg3 7 O
mcspi3_cs0 1 IO hsusb1_ data2 3 IO gpio_16 4 IO mm1_txdat 5 IO hw_dbg4 7 O
mcspi3_clk 1 IO mmc3_dat3 2 IO hsusb1_ data7 3 IO gpio_17 4 IO hw_dbg5 7 O
mcbsp5_dr 1 I mmc3_dat0 2 IO hsusb1_ data4 3 IO gpio_18 4 IO hw_dbg6 7 O
mcbsp5_fsx 1 IO mmc3_dat1 2 IO hsusb1_ data5 3 IO gpio_19 4 IO hw_dbg7 7 O
mcbsp5_dx 1 O mmc3_dat2 2 IO hsusb1_ data6 3 IO gpio_20 4 IO hw_dbg8 7 O
mcspi3_cs1 1 O
Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BUFFER
STATE [7] [11]
(3)
(continued)
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Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
AF9 NA etk_d8 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
AG9 NA etk_d9 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
AE7 NA etk_d10 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
AF7 NA etk_d11 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
AG7 NA etk_d12 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
AH7 NA etk_d13 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
AG8 NA etk_d14 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
AH8 NA etk_d15 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
AH21 NA vss 0 GND - - - - - - - ­AG16 NA vss 0 GND - - - - - - - ­M28 NA vss 0 GND - - - - - - - ­AH20 NA cap_vddu_array 0 PWR - - - - - - - ­AG20 NA vdds 0 PWR - - - - - - - ­AG21 NA vdds 0 PWR - - - - - - - ­H28 NA vdds 0 PWR - - - - - - - ­P25 NA vdds_x 0 PWR - - - - - - - -
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
mmc3_dat7 2 IO hsusb1_ data3 3 IO gpio_21 4 IO mm1_txen_n 5 IO hw_dbg9 7 O
mmc3_dat6 2 IO hsusb1_dir 3 I gpio_22 4 IO hw_dbg10 7 O
mmc3_dat5 2 IO hsusb1_nxt 3 I gpio_23 4 IO mm1_rxdm 5 IO hw_dbg11 7 O
uart1_rx 2 I hsusb2_clk 3 O gpio_24 4 IO hw_dbg12 7 O
hsusb2_stp 3 O gpio_25 4 IO mm2_rxdp 5 IO hw_dbg13 7 O
hsusb2_dir 3 I gpio_26 4 IO hw_dbg14 7 O
hsusb2_nxt 3 I gpio_27 4 IO mm2_rxdm 5 IO hw_dbg15 7 O
hsusb2_ data0 3 IO gpio_28 4 IO mm2_rxrcv 5 IO hw_dbg16 7 O
hsusb2_ data1 3 IO gpio_29 4 IO mm2_txse0 5 IO hw_dbg17 7 O
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(3)
(continued)
BALL BUFFER
STATE [7] [11]
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BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
AE9, AE18, NA vdd_core 0 PWR - - - - - - - ­AE19, AE24, AC4, Y16, Y18, Y19, Y20, W18, W20, V20, U19, U20, T19, P20, N19, N20, M19, M25, L25, K18, K20, J4, J18, J19, J20, H4, E25, D8, D9, D15, D22, D23
Y9, Y10, NA vdd_mpu_iva 0 PWR - - - - - - - ­Y11, Y14, Y15, W9, W11, W12, W15, U10, T9, T10, R9, R10, N10, M9, M10, L9, L10, K11, K14, K13, J9, J10, J11, J14, J15
AH6, U1, AC5, P1, vdds_mem 0 PWR - - - - - - - ­R4, J1, J2, H1, F23, E1, G28, F1, F2, C23, A4, A7, D16, C16, A10, A15, C28, B5, B8, A18 B12, B18, B22, A5, A8, A12, A18, A22
AG27, AF8, NA vdds 0 PWR - - - - - - - ­AF16, AF23, AE8, AE16, AE23, AD3, AD4, W4, F25, F26
W16 NA vdds_sram 0 PWR K15 NA vdda_dplls_dll 0 PWR - - - - - - - ­AA16 NA vdda_dpll_per 0 PWR - - - - - - - ­AA14 NA vdda_wkup_ 0 PWR - - - - - - - -
K25 NA vdds_mmc1 0 PWR - - - - - - - ­V25 NA vdda_dac 0 PWR - - - - - - - ­Y26 NA vssa_dac 0 GND - - - - - - - -
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
bg_bb
Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BUFFER
STATE [7] [11]
(3)
(continued)
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Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
AG2, AG3, B4, B7, B10, vss 0 GND - - - - - - - ­AG6, AF12, B15, B18, AF20, AE12, C22, E2, AE20, F22, H2, P2, AC25, AB5, AB14, AC26, Y12, AB20 Y13, Y25, W3, W10, W13, W14, W17, W19, W25, V9, V10, V19, U2, U9, T20, R19, R20, R26, P3, P4, P9, P10, P19, N9, M20, L19, L20, L26, K9, K10, K12, K16, K17, K19, J3, J12, J13, J16, J17, G27, E3,E4, D7, D10, D13, D19, D21, C7, C10, C13, C19, C22, B2, B27, A3, A26
AA15 NA cap_vddu_wkup_ 0 PWR - - - - - - - -
AH10, A12, AA1, Feed-Through - - - - - - - - - ­AH11, AA23, AB11, Pins AH13, AB9, AC11, AH15, AC13, AH16, AC14, AC8, AG11, AC9, H23, AG13, AF1, K1, L1, U1, AF28, AE28, Y23, A1, A2, AA1, N1, A22, A23, M1, J28, AB1, AB23, A15, M2, AC1, AC2, N2, A1, A2, AC22, A27, A28, AC23, B1, AG1, AG28, B23, AA2, AH1, AH2, U2, AA22, AH27, AB8, AB13, AH28, B1, B12, H22, B28, AA2, K2, K22, L2 AF2, AF27, AG10, AG15, B15, J27, M26
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
logic
(9)
BALL BUFFER
STATE [7] [11]
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(3)
(continued)
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
BALL BALL RESET PULLUP BOTTOM PIN NAME [3] MODE [4] TYPE [5] RESET REL. MODE POWER [9] HYS [10] /DOWN
[1] STATE [6] [8] TYPE [12]
G1, A13, AB2, AB22, No Connect A14,A16, B2, B22 A17, B14, B16, B17, C14, C15, C17, D17, D18, H9, H10, H11, H12, H13, H14, H15, H16, H17, A4, A6, A7, A9, A10, A11, A19, A20, A21, B3, B4, B6, B7, B9, B10, B11, B13, B19, B20, B21, C1,C2, C3, C4,C5, C6, C8,C9, C11, C12, C18, C20, C21, D1, D2, D3, D4, D5,D6, D11, D12,D14, D20, E1,E2, AA26,AE27, A27, A28, B28, AG1, AG28, AH1, AH2,AH27, AH28
Y17 NA sys_xtalgnd 0 GND U4 NA cap_vdd_bb_ 0 PWR
V4 NA cap_vdd_sram 0 PWR
L21 NA cap_vdd_sram_core 0 PWR
BALL TOP RESET STRENG IO CELL
[2] REL. TH (mA) [13]
(2)
mpu_iva
_mpu_iva
(1) The usage of this GPIO is strongly restricted. For more information, see the GPIO chapter of the AM/DM37x Multimedia Device
Technical Reference Manual (literature number SPRUGN4). (2) Pins labeled as "No connect" must be left unconnected. Any connections to these pins may result in unpredictable behavior. (3) NA in this table stands for "Not Applicable". (4) The drive strength is fixed regardless of the load. The driver is designed to drive 75-ohm for video applications. (5) PU = [50 to 100 kΩ] per default or [10 to 50 kΩ] according to the selected mode.
For a full description of the pull-up drive strength programming, see the PRG_SDMMC_PUSTRENGTH configuration register bit field in
the System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).
PD: 30 to 150 kΩ. (6) The pullup and pulldown can be either the standard LVCMOS 100-mA drive strength or the I2C pullup and pulldown described below:
Nominal resistance = 1.66 kΩ in high-speed mode with a load range of 5 pF to 12 pF, 4.5 kΩ in standard / fast mode with a load range
of 5 pF to 15 pF. (7) The default buffer configuration is High-Speed I2C point-to-point mode using internal pullup. For a full description of the pull drive
strength programming, see prg_i2c1_pullupresx, prg_i2c1_lb1lb0, and prg_sr_pullupresx, prg_sr_lb bits of the CONTROL_PROG_IO1,
CONTROL_PROG_IO_WKUP1 control modules in the System Control Module / SCM Programming Model / Feature Settings section
and the System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number
SPRUGN4) to modify the IO settings if required by the targeted interface application.
(8) The default buffer configuration is standard LVCMOS mode (non-I2C). For a full description of the pull drive strength programming, see
PADCONFS bits of CONTROL_PADCONF_X control modules (standard LVCMOS mode), or prg_i2c2_pullupresx, prg_i2c2_lb1lb0, and
prg_i2c3_pullupresx, prg_i2c3_lb1lb0 bits of the CONTROL_PROG_IO2, CONTROL_PROG_IO3 control modules (I2C mode) in the
System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4) to
modify the IO settings if required by the targeted interface application. (9) These signals are feed-through balls. For more information, see Table 2-28. (10) In buffer mode, the drive strength is fixed regardless of the load. The driver is designed to drive 75Ω for video applications. In bypass
mode, the drive strength is 0.47 mA. (11) Depending on the sys_clkreq direction the corresponding reset released state value can be:
– Z if sys_clkreq is used as input
– 1 if sys_clkreq is used as output
Table 2-1. Ball Characteristics (CBP Pkg.)
BALL BUFFER
STATE [7] [11]
- -
(3)
(continued)
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For a full description of the sys_clkreq control, see Power, Reset, and Clock Management chapter of the AM/DM37x Multimedia Device
Technical Reference Manual (literature number SPRUGN4).
(12) The drive strength of these IOs is set according to the programmable load range: 2 pF to 4 pF per default or 4 pF to 12 pF. For a full
description of the drive strength programming, see the System Control Module chapter of the AM/DM37x Multimedia Device Technical
Reference Manual (literature number SPRUGN4). (13) In the safe_mode_out1, the buffer is configured to drive 1. (14) Mux0 if sys_boot6 is pulled down (clock master). (15) If MMC1 functional signals are enabled, vdds_mmc1 for MMC1 must be supplied by a dedicated power source.
If MMC1 functional signals are disabled, other multiplexed CMOS signals of the interface can be enabled. The interface can be supplied
by the same power source as vdds. The vdds power source supplies the vdds_mmc1 ball.
If neither MMC1 functional balls or CMOS signals are enabled, the interface balls are left unconnected with its associated power supply
(vdda/vssa) grounded.
For the corresponding setting of the PBIASLITEPWRDNZ0 bit, see the System Control Module / SCM Programming Model /
Extended-Drain I/Os and PBIAS Cells Programming Guide section of the AM/DM37x Multimedia Device Technical Reference Manual
(literature number SPRUGN4).
BALL BALL TOP PIN NAME [3] MODE [4] TYPE [5] BALL BALL RESET RESET POWER [9] HYS [10] BUFFER PULLUP IO CELL BOTTOM [2] RESET REL. STATE REL. MODE STRENGTH /DOWN [13]
[1] STATE [6] [7] [8] (mA) [11] TYPE [12]
AE16 NA cam_d0 0 I L L 7 vdda Yes NA PU/ PD LVCMOS
gpio_99 4 I safe_mode 7 -
AE15 NA cam_d1 0 I L L 7 vdda Yes NA PU/ PD LVCMOS
gpio_100 4 I safe_mode 7 -
AD17 NA gpio_112 4 I L L 7 vdda Yes NA PU/ PD LVCMOS
safe_mode 7 -
AE18 NA gpio_114 4 I L L 7 vdda Yes NA PU/ PD LVCMOS
safe_mode 7 -
AD16 NA gpio_113 4 I L L 7 vdda Yes NA PU/ PD LVCMOS
safe_mode 7 -
gpio_115 4 I AE17 NA safe_mode 7 - L L 7 vdda Yes NA PU/ PD LVCMOS NA G20 sdrc_a0 0 O 0 0 0 vdds NA 4 NA K20 sdrc_a1 0 O 0 0 0 vdds NA 4 NA J20 sdrc_a2 0 O 0 0 0 vdds NA 4 NA J21 sdrc_a3 0 O 0 0 0 vdds NA 4 NA U21 sdrc_a4 0 O 0 0 0 vdds NA 4 NA R20 sdrc_a5 0 O 0 0 0 vdds NA 4 NA M21 sdrc_a6 0 O 0 0 0 vdds NA 4 NA M20 sdrc_a7 0 O 0 0 0 vdds NA 4 NA N20 sdrc_a8 0 O 0 0 0 vdds NA 4 NA K21 sdrc_a9 0 O 0 0 0 vdds NA 4 NA Y16 sdrc_a10 0 O 0 0 0 vdds NA 4 NA N21 sdrc_a11 0 O 0 0 0 vdds NA 4 NA R21 sdrc_a12 0 O 0 0 0 vdds NA 4 NA AA15 sdrc_a13 0 O 0 0 0 vdds NA 4 NA Y12 sdrc_a14 0 O 0 0 0 vdds NA 4 NA AA18 sdrc_ba0 0 O 0 0 0 vdds NA 4 NA V20 sdrc_ba1 0 O 0 0 0 vdds NA 4 NA Y15 sdrc_cke0 0 O H 1 7 vdds NA 4
safe_mode_out1 NA Y13 sdrc_cke1 0 O H 1 7 vdds NA 4
safe_mode_out1 NA A12 sdrc_clk 0 IO L 0 0 vdds Yes 4 NA D1 sdrc_d0 0 IO L Z 0 vdds Yes 4 NA G1 sdrc_d1 0 IO L Z 0 vdds Yes 4 NA G2 sdrc_d2 0 IO L Z 0 vdds Yes 4
(6)
(6)
Table 2-2. Ball Characteristics (CBC Pkg.)
7
7
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(5)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS
PU/ PD LVCMOS
PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS
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BALL BALL TOP PIN NAME [3] MODE [4] TYPE [5] BALL BALL RESET RESET POWER [9] HYS [10] BUFFER PULLUP IO CELL BOTTOM [2] RESET REL. STATE REL. MODE STRENGTH /DOWN [13]
[1] STATE [6] [7] [8] (mA) [11] TYPE [12]
NA E1 sdrc_d3 0 IO L Z 0 vdds Yes 4 NA D2 sdrc_d4 0 IO L Z 0 vdds Yes 4 NA E2 sdrc_d5 0 IO L Z 0 vdds Yes 4 NA B3 sdrc_d6 0 IO L Z 0 vdds Yes 4 NA B4 sdrc_d7 0 IO L Z 0 vdds Yes 4 NA A10 sdrc_d8 0 IO L Z 0 vdds Yes 4 NA B11 sdrc_d9 0 IO L Z 0 vdds Yes 4 NA A11 sdrc_d10 0 IO L Z 0 vdds Yes 4 NA B12 sdrc_d11 0 IO L Z 0 vdds Yes 4 NA A16 sdrc_d12 0 IO L Z 0 vdds Yes 4 NA A17 sdrc_d13 0 IO L Z 0 vdds Yes 4 NA B17 sdrc_d14 0 IO L Z 0 vdds Yes 4 NA B18 sdrc_d15 0 IO L Z 0 vdds Yes 4 NA B7 sdrc_d16 0 IO L Z 0 vdds Yes 4 NA A5 sdrc_d17 0 IO L Z 0 vdds Yes 4 NA B6 sdrc_d18 0 IO L Z 0 vdds Yes 4 NA A6 sdrc_d19 0 IO L Z 0 vdds Yes 4 NA A8 sdrc_d20 0 IO L Z 0 vdds Yes 4 NA B9 sdrc_d21 0 IO L Z 0 vdds Yes 4 NA A9 sdrc_d22 0 IO L Z 0 vdds Yes 4 NA B10 sdrc_d23 0 IO L Z 0 vdds Yes 4 NA C21 sdrc_d24 0 IO L Z 0 vdds Yes 4 NA D20 sdrc_d25 0 IO L Z 0 vdds Yes 4 NA B19 sdrc_d26 0 IO L Z 0 vdds Yes 4 NA C20 sdrc_d27 0 IO L Z 0 vdds Yes 4 NA D21 sdrc_d28 0 IO L Z 0 vdds Yes 4 NA E20 sdrc_d29 0 IO L Z 0 vdds Yes 4 NA E21 sdrc_d30 0 IO L Z 0 vdds Yes 4 NA G21 sdrc_d31 0 IO L Z 0 vdds Yes 4 NA H1 sdrc_dm0 0 O 0 0 0 vdds NA 4 NA A14 sdrc_dm1 0 O 0 0 0 vdds NA 4 NA A4 sdrc_dm2 0 O 0 0 0 vdds NA 4 NA A18 sdrc_dm3 0 O 0 0 0 vdds NA 4 NA C2 sdrc_dqs0 0 IO L Z 0 vdds Yes 4 NA B15 sdrc_dqs1 0 IO L Z 0 vdds Yes 4 NA B8 sdrc_dqs2 0 IO L Z 0 vdds Yes 4 NA A19 sdrc_dqs3 0 IO L Z 0 vdds Yes 4 NA U20 sdrc_ncas 0 O 1 1 0 vdds NA 4 NA B13 sdrc_nclk 0 O 1 1 0 vdds NA 4 NA T21 sdrc_ncs0 0 O 1 1 0 vdds NA 4 NA T20 sdrc_ncs1 0 O 1 1 0 vdds NA 4 NA V21 sdrc_nras 0 O 1 1 0 vdds NA 4 NA Y18 sdrc_nwe 0 O 1 1 0 vdds NA 4 AE21 NA dss_data0 0 IO L L 7 vdda Yes 8 PU/ PD LVCMOS
uart1_cts 2 I NA
gpio_70 4 IO 8
safe_mode 7 - 8 AE22 NA dss_data1 0 IO L L 7 vdda Yes 8 PU/ PD LVCMOS
uart1_rts 2 O 8
gpio_71 4 IO 8
safe_mode 7 - 8 AE23 NA dss_data2 0 IO L L 7 vdda Yes 8 PU/ PD LVCMOS
gpio_72 4 IO 8
safe_mode 7 - 8 AE24 NA dss_data3 0 IO L L 7 vdda Yes 8 PU/ PD LVCMOS
Table 2-2. Ball Characteristics (CBC Pkg.)
(5)
(continued)
www.ti.com
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS
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Table 2-2. Ball Characteristics (CBC Pkg.)
BALL BALL TOP PIN NAME [3] MODE [4] TYPE [5] BALL BALL RESET RESET POWER [9] HYS [10] BUFFER PULLUP IO CELL BOTTOM [2] RESET REL. STATE REL. MODE STRENGTH /DOWN [13]
[1] STATE [6] [7] [8] (mA) [11] TYPE [12]
gpio_73 4 IO 8
safe_mode 7 - 8 AD23 NA dss_data4 0 IO L L 7 vdda Yes 8 PU/ PD LVCMOS
uart3_rx_irrx 2 I NA
gpio_74 4 IO 8
safe_mode 7 - 8 AD24 NA dss_data5 0 IO L L 7 vdda Yes 8 PU/ PD LVCMOS
uart3_tx_irtx 2 O 8
gpio_75 4 IO 8
safe_mode 7 - 8 AC26 NA dss_data10 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_80 4 IO
safe_mode 7 ­AD26 NA dss_data11 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_81 4 IO
safe_mode 7 ­AA25 NA dss_data12 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_82 4 IO
safe_mode 7 ­Y25 NA dss_data13 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_83 4 IO
safe_mode 7 ­AA26 NA dss_data14 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_84 4 IO
safe_mode 7 ­AB26 NA dss_data15 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_85 4 IO
safe_mode 7 ­F25 NA dss_data20 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
mcspi3_somi 2 IO
dss_data2 3 IO
gpio_90 4 IO
safe_mode 7 ­AC25 NA dss_data22 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS
mcspi3_cs1 2 O
dss_data4 3 IO
gpio_92 4 IO
safe_mode 7 ­AB25 NA dss_data23 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS
dss_data5 3 IO
gpio_93 4 IO
safe_mode 7 ­G25 NA dss_pclk 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
gpio_66 4 IO
hw_dbg12 5 O
safe_mode 7 ­J2 NA gpmc_a1 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_34 4 IO
safe_mode 7 ­H1 NA gpmc_a2 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_35 4 IO
safe_mode 7 ­H2 NA gpmc_a3 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_36 4 IO
safe_mode 7 -
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(5)
(continued)
Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 47
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
BALL BALL TOP PIN NAME [3] MODE [4] TYPE [5] BALL BALL RESET RESET POWER [9] HYS [10] BUFFER PULLUP IO CELL BOTTOM [2] RESET REL. STATE REL. MODE STRENGTH /DOWN [13]
[1] STATE [6] [7] [8] (mA) [11] TYPE [12]
G2 NA gpmc_a4 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_37 4 IO
safe_mode 7 ­F1 NA gpmc_a5 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_38 4 IO
safe_mode 7 ­F2 NA gpmc_a6 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
gpio_39 4 IO
safe_mode 7 ­E1 NA gpmc_a7 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
gpio_40 4 IO
safe_mode 7 ­E2 NA gpmc_a8 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
gpio_41 4 IO
safe_mode 7 ­D1 NA gpmc_a9 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
sys_ndmareq2 1 I
gpio_42 4 IO
safe_mode 7 ­D2 NA gpmc_a10 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
sys_ndmareq3 1 I
gpio_43 4 IO
N1 L1 gpmc_clk 0 O L 0 0 vdds Yes 8 PU/ PD LVCMOS
AA2 U2 gpmc_d0 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AA1 U1 gpmc_d1 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AC2 V2 gpmc_d2 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AC1 V1 gpmc_d3 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AE5 AA3 gpmc_d4 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AD6 AA4 gpmc_d5 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AD5 Y3 gpmc_d6 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS AC5 Y4 gpmc_d7 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS V1 R1 gpmc_d8 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS
Y1 T1 gpmc_d9 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS
T1 N1 gpmc_d10 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS
U2 P2 gpmc_d11 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS
U1 P1 gpmc_d12 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS
P1 M1 gpmc_d13 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS
L2 J2 gpmc_d14 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS
safe_mode 7 -
gpio_59 4 IO
safe_mode 7 -
gpio_44 4 IO
safe_mode 7 -
gpio_45 4 IO
safe_mode 7 -
gpio_46 4 IO
safe_mode 7 -
gpio_47 4 IO
safe_mode 7 -
gpio_48 4 IO
safe_mode 7 -
gpio_49 4 IO
safe_mode 7 -
gpio_50 4 IO
safe_mode 7 -
Table 2-2. Ball Characteristics (CBC Pkg.)
(5)
(continued)
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Table 2-2. Ball Characteristics (CBC Pkg.)
BALL BALL TOP PIN NAME [3] MODE [4] TYPE [5] BALL BALL RESET RESET POWER [9] HYS [10] BUFFER PULLUP IO CELL BOTTOM [2] RESET REL. STATE REL. MODE STRENGTH /DOWN [13]
[1] STATE [6] [7] [8] (mA) [11] TYPE [12]
M2 K2 gpmc_d15 0 IO H H 0 vdds Yes 8 PU/ PD LVCMOS
gpio_51 4 IO
safe_mode 7 ­AD10 AA9 gpmc_nadv_ale 0 O 0 0 0 vdds NA 8 NA LVCMOS K2 NA gpmc_nbe0_cle 0 O L 0 0 vdds Yes 8 PU/ PD LVCMOS
gpio_60 4 IO
safe_mode 7 ­J1 NA gpmc_nbe1 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_61 4 IO
safe_mode 7 ­AD8 AA8 gpmc_ncs0 0 O 1 1 0 vdds NA 8 NA LVCMOS AD1 W1 gpmc_ncs1 0 O H 1 0 vdds Yes 8 PU/ PD LVCMOS
gpio_52 4 IO
safe_mode 7 ­A3 NA gpmc_ncs2 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
gpio_53 4 IO
safe_mode 7 ­B6 NA gpmc_ncs3 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
sys_ndmareq0 1 I
gpio_54 4 IO
safe_mode 7 ­B4 NA gpmc_ncs4 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
sys_ndmareq1 1 I
mcbsp4_clkx 2 IO
gpt_9_pwm_evt 3 IO
gpio_55 4 IO
safe_mode 7 ­C4 NA gpmc_ncs5 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
sys_ndmareq2 1 I
mcbsp4_dr 2 I
gpt_10_pwm_evt 3 IO
gpio_56 4 IO
safe_mode 7 ­B5 NA gpmc_ncs6 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
sys_ndmareq3 1 I
mcbsp4_dx 2 IO
gpt_11_pwm_evt 3 IO
gpio_57 4 IO
C5 NA gpmc_ncs7 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
N2 L2 gpmc_noe 0 O 1 1 0 vdds NA 8 NA LVCMOS M1 K1 gpmc_nwe 0 O 1 1 0 vdds NA 8 NA LVCMOS AC6 Y5 gpmc_nwp 0 O L 0 0 vdds Yes 8 PU/ PD LVCMOS
AC11 Y10 gpmc_wait0 0 I H H 0 vdds Yes NA PU/ PD LVCMOS AC8 Y8 gpmc_wait1 0 I H H 7 vdds Yes 8 PU/ PD LVCMOS
B3 NA gpmc_wait2 0 I H H 7 vdds Yes 8 PU/ PD LVCMOS
safe_mode 7 -
gpmc_io_dir 1 O
mcbsp4_fsx 2 IO
gpt_8_pwm_evt 3 IO
gpio_58 4 IO
safe_mode 7 -
gpio_62 4 IO
safe_mode 7 -
gpio_63 4 IO
safe_mode 7 -
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(5)
(continued)
Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 49
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
BALL BALL TOP PIN NAME [3] MODE [4] TYPE [5] BALL BALL RESET RESET POWER [9] HYS [10] BUFFER PULLUP IO CELL BOTTOM [2] RESET REL. STATE REL. MODE STRENGTH /DOWN [13]
[1] STATE [6] [7] [8] (mA) [11] TYPE [12]
uart4_tx 2 O
gpio_64 4 IO
safe_mode 7 ­C6 NA gpmc_wait3 0 I H H 7 vdds Yes 8 PU/ PD LVCMOS
sys_ndmareq1 1 I
uart4_rx 2 I
gpio_65 4 IO
safe_mode 7 ­W19 NA hsusb0_clk 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_120 4 IO
safe_mode 7 ­V20 NA hsusb0_data0 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
uart3_tx_irtx 2 O
gpio_125 4 IO
uart2_tx 5 O
safe_mode 7 ­Y20 NA hsusb0_data1 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
uart3_rx_irrx 2 I
gpio_130 4 IO
uart2_rx 5 I
safe_mode 7 ­V18 NA hsusb0_data2 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
W20 NA hsusb0_data3 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
W17 NA hsusb0_data4 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
Y18 NA hsusb0_data5 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
Y19 NA hsusb0_data6 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
Y17 NA hsusb0_data7 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
V19 NA hsusb0_dir 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
W18 NA hsusb0_nxt 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
U20 NA hsusb0_stp 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
U15 NA jtag_ntrst 0 I L L 0 vdds Yes NA PU/ PD LVCMOS W13 NA jtag_rtck 0 O L 0 0 vdds NA 4 PU/ PD LVCMOS V14 NA jtag_tck 0 I L L 0 vdds Yes NA PU/ PD LVCMOS
uart3_rts_sd 2 O
gpio_131 4 IO
uart2_rts 5 O
safe_mode 7 -
uart3_cts_rctx 2 IO
gpio_169 4 IO
uart2_cts 5 I
safe_mode 7 -
gpio_188 4 IO
safe_mode 7 -
gpio_189 4 IO
safe_mode 7 -
gpio_190 4 IO
safe_mode 7 -
gpio_191 4 IO
safe_mode 7 -
gpio_122 4 IO
safe_mode 7 -
gpio_124 4 IO
safe_mode 7 -
gpio_121 4 IO
safe_mode 7 -
Table 2-2. Ball Characteristics (CBC Pkg.)
(5)
(continued)
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50 TERMINAL DESCRIPTION Copyright © 2010, Texas Instruments Incorporated
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Table 2-2. Ball Characteristics (CBC Pkg.)
BALL BALL TOP PIN NAME [3] MODE [4] TYPE [5] BALL BALL RESET RESET POWER [9] HYS [10] BUFFER PULLUP IO CELL BOTTOM [2] RESET REL. STATE REL. MODE STRENGTH /DOWN [13]
[1] STATE [6] [7] [8] (mA) [11] TYPE [12]
U16 NA jtag_tdi 0 I H H 0 vdds Yes NA PU/ PD LVCMOS Y13 NA jtag_tdo 0 O L Z 0 vdds NA 4 PU/ PD LVCMOS V15 NA jtag_tms_tmsc 0 IO H H 0 vdds Yes 4 PU/ PD LVCMOS N19 NA mmc1_clk 0 IO L L 7 vdds_mmc1(Yes 1 PU/ PD
(8)
gpio_120
safe_mode 7 ­L18 NA mmc1_cmd 0 O L L 7 vdds_mmc1(Yes 1 PU/ PD
(8)
gpio_121
safe_mode 7 ­M19 NA mmc1_dat0 0 IO L L 7 vdds_mmc1(Yes 1 PU/ PD
(8)
gpio_122
safe_mode 7 ­M18 NA mmc1_dat1 0 IO L L 7 vdds_mmc1(Yes 1 PU/ PD
(8)
gpio_123
safe_mode 7 ­K18 NA mmc1_dat2 0 IO L L 7 vdds_mmc1(Yes 1 PU/ PD
(8)
gpio_124
safe_mode 7 ­N20 NA mmc1_dat3 0 IO L L 7 vdds_mmc1(Yes 1 PU/ PD
(8)
gpio_125
safe_mode 7 ­M20 NA gpio_126
P17 NA gpio_127
P18 NA gpio_128
P19 NA gpio_129
J25 NA i2c1_scl 0 OD H H 0 vdds NA 3 PU/ PD J24 NA i2c1_sda 0 IOD H H 0 vdds Yes 3 PU/ PD
C2 NA i2c2_scl 0 OD H H 7 vdds Yes 3 PU/ PD
C1 NA i2c2_sda 0 IOD H H 7 vdds Yes 3 PU/ PD
AB4 NA i2c3_scl 0 OD H H 7 vdds Yes 3 PU/ PD
AC4 NA i2c3_sda 0 IOD H H 7 vdds Yes 3 PU/ PD
U19 NA mcbsp1_clkr 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
T17 NA mcbsp1_clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
(8)
safe_mode 7 -
(8)
safe_mode 7 -
(8)
safe_mode 7 -
(8)
safe_mode 7 -
gpio_168 4 IO 4
safe_mode 7 - 4
gpio_183 4 IO 4
safe_mode 7 - 4
gpio_184 4 IO 4
safe_mode 7 - 4
gpio_185 4 IO 4
safe_mode 7 - 4
mcspi4_clk 1 IO
gpio_156 4 IO
safe_mode 7 -
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(5)
(continued)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(9) (10)
(9) (10)
(9)(11)
(9)(11)
(9)(11)
(9)(11)
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Open Drain LVCMOS
Open Drain LVCMOS
Open Drain
LVCMOS Open Drain
LVCMOS Open Drain
LVCMOS Open Drain
10)
4 IO
10)
4 IO
10)
4 IO
10)
4 IO
10)
4 IO
10)
4 IO
4 IO L L 7 vdds_x Yes 1 PU/PD
4 IO L L 7 vdds_x Yes 1 PU/PD
4 IO L L 7 vdds Yes 4 PU/PD LVCMOS
4 IO L L 7 vdds_x Yes 1 PU/PD
Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 51
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
BALL BALL TOP PIN NAME [3] MODE [4] TYPE [5] BALL BALL RESET RESET POWER [9] HYS [10] BUFFER PULLUP IO CELL BOTTOM [2] RESET REL. STATE REL. MODE STRENGTH /DOWN [13]
[1] STATE [6] [7] [8] (mA) [11] TYPE [12]
mcbsp3_clkx 2 IO
gpio_162 4 IO
safe_mode 7 ­T20 NA mcbsp1_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
mcspi4_somi 1 IO
mcbsp3_dr 2 I
gpio_159 4 IO
safe_mode 7 ­U17 NA mcbsp1_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
mcspi4_simo 1 IO
mcbsp3_dx 2 IO
gpio_158 4 IO
safe_mode 7 ­V17 NA mcbsp1_fsr 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
cam_global_reset 2 IO
gpio_157 4 IO
safe_mode 7 ­P20 NA mcbsp1_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
mcspi4_cs0 1 IO
mcbsp3_fsx 2 IO
gpio_161 4 IO
safe_mode 7 ­R18 NA mcbsp2_clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_117 4 IO
safe_mode 7 ­T18 NA mcbsp2_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_118 4 IO
safe_mode 7 ­R19 NA mcbsp2_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_119 4 IO
safe_mode 7 ­U18 NA mcbsp2_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_116 4 IO
safe_mode 7 ­P9 NA mcspi1_clk 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
mmc2_dat4 1 IO
gpio_171 4 IO
safe_mode 7 ­R7 NA mcspi1_cs0 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
mmc2_dat7 1 IO
gpio_174 4 IO
safe_mode 7 ­R9 NA mcspi1_cs2 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
mmc3_clk 3 IO
gpio_176 4 IO
safe_mode 7 ­P8 NA mcspi1_simo 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
mmc2_dat5 1 IO
gpio_172 4 IO
safe_mode 7 ­P7 NA mcspi1_somi 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
mmc2_dat6 1 IO
gpio_173 4 IO
safe_mode 7 ­W7 NA mcspi2_clk 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
Table 2-2. Ball Characteristics (CBC Pkg.)
(5)
(continued)
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52 TERMINAL DESCRIPTION Copyright © 2010, Texas Instruments Incorporated
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Table 2-2. Ball Characteristics (CBC Pkg.)
BALL BALL TOP PIN NAME [3] MODE [4] TYPE [5] BALL BALL RESET RESET POWER [9] HYS [10] BUFFER PULLUP IO CELL BOTTOM [2] RESET REL. STATE REL. MODE STRENGTH /DOWN [13]
[1] STATE [6] [7] [8] (mA) [11] TYPE [12]
hsusb2_data7 3 IO
gpio_178 4 IO
safe_mode 7 ­V8 NA mcspi2_cs0 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
gpt_11_pwm_evt 1 IO
hsusb2_data6 3 IO
gpio_181 4 IO
safe_mode 7 ­W8 NA mcspi2_simo 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
gpt_9_pwm_evt 1 IO
hsusb2_data4 3 IO
gpio_179 4 IO
safe_mode 7 ­U8 NA mcspi2_somi 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
gpt_10_pwm_evt 1 IO
hsusb2_data5 3 IO
gpio_180 4 IO
safe_mode 7 ­W10 NA mmc2_clk 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
mcspi3_clk 1 IO
gpio_130 4 IO
safe_mode 7 ­R10 NA mmc2_cmd 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
mcspi3_simo 1 IO
gpio_131 4 IO
safe_mode 7 ­T10 NA mmc2_dat0 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
mcspi3_somi 1 IO
gpio_132 4 IO
safe_mode 7 ­T9 NA mmc2_dat1 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
gpio_133 4 IO
safe_mode 7 ­U10 NA mmc2_dat2 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
mcspi3_cs1 1 O
gpio_134 4 IO
safe_mode 7 ­U9 NA mmc2_dat3 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
V10 NA mmc2_dat4 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
R2 NA uart1_rts 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
H3 NA uart1_rx 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
L4 NA uart1_tx 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
mcspi3_cs0 1 IO
gpio_135 4 IO
safe_mode 7 -
mmc2_dir_dat0 1 O
mmc3_dat0 3 IO
gpio_136 4 IO
safe_mode 7 -
gpio_149 4 IO
safe_mode 7 -
mcbsp1_clkr 2 IO
mcspi4_clk 3 IO
gpio_151 4 IO
safe_mode 7 -
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(5)
(continued)
Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 53
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
BALL BALL TOP PIN NAME [3] MODE [4] TYPE [5] BALL BALL RESET RESET POWER [9] HYS [10] BUFFER PULLUP IO CELL BOTTOM [2] RESET REL. STATE REL. MODE STRENGTH /DOWN [13]
[1] STATE [6] [7] [8] (mA) [11] TYPE [12]
gpio_148 4 IO
safe_mode 7 ­Y24 NA uart2_cts 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS
mcbsp3_dx 1 IO
gpt_9_pwm_evt 2 IO
gpio_144 4 IO
safe_mode 7 ­AA24 NA uart2_rts 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
mcbsp3_dr 1 I
gpt_10_pwm_evt 2 IO
gpio_145 4 IO
safe_mode 7 ­AD21 NA uart2_rx 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS
mcbsp3_fsx 1 IO
gpt_8_pwm_evt 2 IO
gpio_147 4 IO
safe_mode 7 ­AD22 NA uart2_tx 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
mcbsp3_clkx 1 IO
gpt_11_pwm_evt 2 IO
gpio_146 4 IO
safe_mode 7 ­F23 NA uart3_cts_rctx 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
gpio_163 4 IO
safe_mode 7 ­F24 NA uart3_rts_sd 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
gpio_164 4 IO
safe_mode 7 ­H24 NA uart3_rx_irrx 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS
gpio_165 4 IO
safe_mode 7 ­G24 NA uart3_tx_irtx 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
gpio_166 4 IO
safe_mode 7 ­J23 NA hdq_sio 0 IOD H H 7 vdds Yes 4 PU/ PD LVCMOS
sys_altclk 1 I
i2c2_sccbe 2 OD
i2c3_sccbe 3 OD
gpio_170 4 IO
safe_mode 7 ­AD15 NA i2c4_scl 0 OD H H 0 vdds Yes 3 PU/ PD
sys_nvmode1 1 O 4
safe_mode 7 - 4 W16 NA i2c4_sda 0 IOD H H 0 vdds Yes 3 PU/ PD
sys_nvmode2 1 O 4
safe_mode 7 - 4 F3 NA sys_boot0 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
dss_data18 3 IO
gpio_2 4 IO
safe_mode 7 ­D3 NA sys_boot1 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
dss_data19 3 IO
gpio_3 4 IO
Table 2-2. Ball Characteristics (CBC Pkg.)
(5)
(continued)
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Open Drain
(9) (10)
LVCMOS Open Drain
(9) (10)
LVCMOS Open Drain
54 TERMINAL DESCRIPTION Copyright © 2010, Texas Instruments Incorporated
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Table 2-2. Ball Characteristics (CBC Pkg.)
BALL BALL TOP PIN NAME [3] MODE [4] TYPE [5] BALL BALL RESET RESET POWER [9] HYS [10] BUFFER PULLUP IO CELL BOTTOM [2] RESET REL. STATE REL. MODE STRENGTH /DOWN [13]
[1] STATE [6] [7] [8] (mA) [11] TYPE [12]
safe_mode 7 ­C3 NA sys_boot2 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
gpio_4 4 IO
safe_mode 7 ­E3 NA sys_boot3 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
dss_data20 3 O
gpio_5 4 IO
safe_mode 7 ­E4 NA sys_boot4 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
mmc2_dir_dat2 1 O
dss_data21 3 O
gpio_6 4 IO
safe_mode 7 ­G3 NA sys_boot5 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
mmc2_dir_dat3 1 O
dss_data22 3 O
gpio_7 4 IO
safe_mode 7 ­D4 NA sys_boot6 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
dss_data23 3 O
gpio_8 4 IO
safe_mode 7 ­AE14 NA sys_clkout1 0 O L L 7
gpio_10 4 IO
safe_mode 7 ­W11 NA sys_clkout2 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_186 4 IO
safe_mode 7 ­W15 NA sys_clkreq 0 IO 0 see
gpio_1 4 IO
safe_mode 7 ­V16 NA sys_nirq 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS
gpio_0 4 IO
safe_mode 7 ­V13 NA sys_nrespwron 0 I Z Z 0 vdds Yes NA No LVCMOS AD7 AA5 sys_nreswarm 0 IOD 0 1 0 vdds Yes 4 PU/ PD LVCMOS
gpio_30 4 IO Open Drain
safe_mode 7 ­V12 NA sys_off_mode 0 O 0 L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_9 4 IO
safe_mode 7 ­AF19 NA sys_xtalin 0 AI Z Z 0 vdds Yes NA NA LVCMOS
AF20 NA sys_xtalout 0 AO Z 0 0 vdds NA NA NA Analog W26 NA cvideo1_out 0 AO 0 0 0 vdda_dac NA NA NA 10-bit DAC V26 NA cvideo2_out 0 AO 0 0 0 vdda_dac NA NA NA 10-bit DAC W25 NA cvideo1_vfb 0 AO 0 NA 0 vdda_dac NA NA NA 10-bit DAC U24 NA cvideo2_vfb 0 AO 0 NA 0 vdda_dac NA NA NA 10-bit DAC V23 NA cvideo1_rset 0 AIO Z NA 0 vdda_dac No NA NA 10-bit DAC AE20 NA sys_32k 0 I Z Z 0 vdds Yes NA PU/ PD LVCMOS A24 NA cam_d2 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_101 4 IO
hw_dbg4 5 O
safe_mode 7 ­B24 NA cam_d3 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(5)
(continued)
(12)
(7)
0 vdds Yes 4 PU/ PD LVCMOS
vdds Yes 4 PU/ PD LVCMOS
Analog
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BALL BALL TOP PIN NAME [3] MODE [4] TYPE [5] BALL BALL RESET RESET POWER [9] HYS [10] BUFFER PULLUP IO CELL BOTTOM [2] RESET REL. STATE REL. MODE STRENGTH /DOWN [13]
[1] STATE [6] [7] [8] (mA) [11] TYPE [12]
gpio_102 4 IO
hw_dbg5 5 O
safe_mode 7 ­D24 NA cam_d4 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_103 4 IO
hw_dbg6 5 O
safe_mode 7 ­C24 NA cam_d5 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_104 4 IO
hw_dbg7 5 O
safe_mode 7 ­D25 NA cam_d10 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_109 4 IO
hw_dbg8 5 O
safe_mode 7 ­E26 NA cam_d11 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_110 4 IO
hw_dbg9 5 O
safe_mode 7 ­B23 NA cam_fld 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
cam_global_reset 2 IO
gpio_98 4 IO
C23 NA cam_hs 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
C26 NA cam_pclk 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
D26 NA cam_strobe 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
C25 NA cam_xclka 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
E25 NA cam_xclkb 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
P25 NA cam_d6 0 I L L 7 vdds Yes NA PU/ PD SubLVDS
P26 NA cam_d7 0 I L L 7 vdds Yes NA PU/ PD SubLVDS
N25 NA cam_d8 0 I L L 7 vdds NA NA PU/ PD SubLVDS
N26 NA cam_d9 0 I L L 7 vdds NA NA PU/ PD SubLVDS
D23 NA cam_vs 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
hw_dbg3 5 O
safe_mode 7 -
gpio_94 4 IO
hw_dbg0 5 O
safe_mode 7 -
gpio_97 4 IO
hw_dbg2 5 O
safe_mode 7 -
gpio_126 4 IO
hw_dbg11 5 O
safe_mode 7 -
gpio_96 4 IO
safe_mode 7 -
gpio_111 4 IO
safe_mode 7 -
gpio_105 4 I
safe_mode 7 -
gpio_106 4 I
safe_mode 7 -
gpio_107 4 I
safe_mode 7 -
gpio_108 4 I
safe_mode 7 -
Table 2-2. Ball Characteristics (CBC Pkg.)
(5)
(continued)
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Table 2-2. Ball Characteristics (CBC Pkg.)
BALL BALL TOP PIN NAME [3] MODE [4] TYPE [5] BALL BALL RESET RESET POWER [9] HYS [10] BUFFER PULLUP IO CELL BOTTOM [2] RESET REL. STATE REL. MODE STRENGTH /DOWN [13]
[1] STATE [6] [7] [8] (mA) [11] TYPE [12]
gpio_95 4 IO
hw_dbg1 5 O
safe_mode 7 ­A23 NA cam_wen 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
cam_shutter 2 O
gpio_167 4 IO
hw_dbg10 5 O
safe_mode 7 ­F26 NA dss_acbias 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_69 4 IO
safe_mode 7 ­G26 NA dss_data6 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
uart1_tx 2 O
gpio_76 4 IO
hw_dbg14 5 O
safe_mode 7 ­H25 NA dss_data7 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
uart1_rx 2 I
gpio_77 4 IO
hw_dbg15 5 O
safe_mode 7 ­H26 NA dss_data8 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
uart3_rx_irrx 2 I
gpio_78 4 IO
hw_dbg16 5 O
safe_mode 7 ­J26 NA dss_data9 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
uart3_tx_irtx 2 O
gpio_79 4 IO
hw_dbg17 5 O
safe_mode 7 ­L25 NA dss_data16 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_86 4 IO
safe_mode 7 ­L26 NA dss_data17 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_87 4 IO
safe_mode 7 ­M24 NA dss_data18 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
M26 NA dss_data19 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
N24 NA dss_data21 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS
K24 NA dss_hsync 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
mcspi3_clk 2 IO
dss_data0 3 IO
gpio_88 4 IO
safe_mode 7 -
mcspi3_simo 2 IO
dss_data1 3 IO
gpio_89 4 IO
safe_mode 7 -
mcspi3_cs0 2 IO
dss_data3 3 IO
gpio_91 4 IO
safe_mode 7 -
gpio_67 4 IO
hw_dbg13 5 O
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(5)
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BALL BALL TOP PIN NAME [3] MODE [4] TYPE [5] BALL BALL RESET RESET POWER [9] HYS [10] BUFFER PULLUP IO CELL BOTTOM [2] RESET REL. STATE REL. MODE STRENGTH /DOWN [13]
[1] STATE [6] [7] [8] (mA) [11] TYPE [12]
safe_mode 7 ­M25 NA dss_vsync 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
gpio_68 4 IO
safe_mode 7 ­R8 NA mcspi1_cs1 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
mmc3_cmd 3 O
gpio_175 4 IO
safe_mode 7 ­T8 NA mcspi1_cs3 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
hsusb2_data2 3 IO
gpio_177 4 IO
mm2_txdat 5 IO
safe_mode 7 ­V9 NA mcspi2_cs1 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
gpt_8_pwm_evt 1 IO
hsusb2_data3 3 IO
gpio_182 4 IO
mm2_txen_n 5 IO
safe_mode 7 ­T19 NA mcbsp_clks 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
cam_shutter 2 O
gpio_160 4 IO
AB2 NA etk_clk 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS
AB3 NA etk_ctl 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS
AC3 NA etk_d0 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS
AD4 NA etk_d1 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS
AD3 NA etk_d2 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS
uart1_cts 5 I
safe_mode 7 -
mcbsp5_clkx 1 IO
mmc3_clk 2 IO
hsusb1_stp 3 O
gpio_12 4 IO
mm1_rxdp 5 IO
hw_dbg0 7 O
mmc3_cmd 2 O
hsusb1_clk 3 O
gpio_13 4 IO
hw_dbg1 7 O
mcspi3_simo 1 IO
mmc3_dat4 2 IO
hsusb1_data0 3 IO
gpio_14 4 IO
mm1_rxrcv 5 IO
hw_dbg2 7 O
mcspi3_somi 1 IO
hsusb1_data1 3 IO
gpio_15 4 IO
mm1_txse0 5 IO
hw_dbg3 7 O
mcspi3_cs0 1 IO
hsusb1_data2 3 IO
gpio_16 4 IO
mm1_txdat 5 IO
hw_dbg4 7 O
Table 2-2. Ball Characteristics (CBC Pkg.)
(5)
(continued)
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Table 2-2. Ball Characteristics (CBC Pkg.)
BALL BALL TOP PIN NAME [3] MODE [4] TYPE [5] BALL BALL RESET RESET POWER [9] HYS [10] BUFFER PULLUP IO CELL BOTTOM [2] RESET REL. STATE REL. MODE STRENGTH /DOWN [13]
[1] STATE [6] [7] [8] (mA) [11] TYPE [12]
AA3 NA etk_d3 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS
mcspi3_clk 1 IO
mmc3_dat3 2 IO
hsusb1_data7 3 IO
gpio_17 4 IO
hw_dbg5 7 O Y3 NA etk_d4 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
mcbsp5_dr 1 I
mmc3_dat0 2 IO
hsusb1_data4 3 IO
gpio_18 4 IO
hw_dbg6 7 O AB1 NA etk_d5 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
mcbsp5_fsx 1 IO
mmc3_dat1 2 IO
hsusb1_data5 3 IO
gpio_19 4 IO
hw_dbg7 7 O AE3 NA etk_d6 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
mcbsp5_dx 1 O
mmc3_dat2 2 IO
hsusb1_data6 3 IO
gpio_20 4 IO
hw_dbg8 7 O AD2 NA etk_d7 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
mcspi3_cs1 1 O
mmc3_dat7 2 IO
hsusb1_data3 3 IO
gpio_21 4 IO
mm1_txen_n 5 IO
hw_dbg9 7 O AA4 NA etk_d8 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
mmc3_dat6 2 IO
hsusb1_dir 3 I
gpio_22 4 IO
hw_dbg10 7 O V2 NA etk_d9 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
mmc3_dat5 2 IO
AE4 NA etk_d10 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
AF6 NA etk_d11 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
AE6 NA etk_d12 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
hsusb1_nxt 3 I
gpio_23 4 IO
mm1_rxdm 5 IO
hw_dbg11 7 O
uart1_rx 2 I
hsusb2_clk 3 O
gpio_24 4 IO
hw_dbg12 7 O
hsusb2_stp 3 O
gpio_25 4 IO
mm2_rxdp 5 IO
hw_dbg13 7 O
hsusb2_dir 3 I
gpio_26 4 IO
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(5)
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
BALL BALL TOP PIN NAME [3] MODE [4] TYPE [5] BALL BALL RESET RESET POWER [9] HYS [10] BUFFER PULLUP IO CELL BOTTOM [2] RESET REL. STATE REL. MODE STRENGTH /DOWN [13]
[1] STATE [6] [7] [8] (mA) [11] TYPE [12]
hw_dbg14 7 O AF7 NA etk_d13 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
hsusb2_nxt 3 I
gpio_27 4 IO
mm2_rxdm 5 IO
hw_dbg15 7 O AF9 NA etk_d14 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
hsusb2_data0 3 IO
gpio_28 4 IO
mm2_rxrcv 5 IO
hw_dbg16 7 O AE9 NA etk_d15 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
hsusb2_data1 3 IO
gpio_29 4 IO
mm2_txse0 5 IO
hw_dbg17 7 O Y15 NA jtag_emu0 0 IO H H 0 vdds Yes 4 PU/ PD LVCMOS
gpio_11 4 IO
safe_mode 7 ­Y14 NA jtag_emu1 0 IO H H 0 vdds Yes 4 PU/ PD LVCMOS
gpio_31 4 IO
safe_mode 7 ­U3 NA mcbsp3_clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
uart2_tx 1 O
gpio_142 4 IO
safe_mode 7 ­N3 NA mcbsp3_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
uart2_rts 1 O
gpio_141 4 IO
safe_mode 7 ­P3 NA mcbsp3_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
uart2_cts 1 I
gpio_140 4 IO
safe_mode 7 ­W3 NA mcbsp3_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
uart2_rx 1 I
gpio_143 4 IO
safe_mode 7 ­V3 NA mcbsp4_clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_152 4 IO
mm3_txse0 6 IO
safe_mode 7 ­U4 NA mcbsp4_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_153 4 IO
mm3_rxrcv 6 IO
safe_mode 7 ­R3 NA mcbsp4_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_154 4 IO
mm3_txdat 6 IO
safe_mode 7 ­T3 NA mcbsp4_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_155 4 IO
mm3_txen_n 6 IO
safe_mode 7 ­M3 NA mmc2_dat5 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
Table 2-2. Ball Characteristics (CBC Pkg.)
(5)
(continued)
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Table 2-2. Ball Characteristics (CBC Pkg.)
BALL BALL TOP PIN NAME [3] MODE [4] TYPE [5] BALL BALL RESET RESET POWER [9] HYS [10] BUFFER PULLUP IO CELL BOTTOM [2] RESET REL. STATE REL. MODE STRENGTH /DOWN [13]
[1] STATE [6] [7] [8] (mA) [11] TYPE [12]
mmc2_dir_dat1 1 O
cam_global_reset 2 IO
mmc3_dat1 3 IO
gpio_137 4 IO
mm3_rxdp 6 IO
safe_mode 7 ­L3 NA mmc2_dat6 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
mmc2_dir_cmd 1 O
cam_shutter 2 O
mmc3_dat2 3 IO
gpio_138 4 IO
safe_mode 7 ­K3 NA mmc2_dat7 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
mmc2_clkin 1 I
mmc3_dat3 3 IO
gpio_139 4 IO
mm3_rxdm 6 IO
safe_mode 7 ­W2 NA uart1_cts 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_150 4 IO
safe_mode 7 ­AC16 NA vss 0 GND AD18 NA vdds 0 PWR L19 NA vss 0 GND AC19 NA vss 0 GND AD19 NA vdds 0 PWR L20 NA vdds 0 PWR P23 NA vdds_x 0 PWR AE19 NA cap_vddu_array 0 PWR AC21, D15, NA vdd_core 0 PWR - - - - - - - -
G11, G18, H20, M7, M17, R20, T7, Y8, Y12
D13, G9, NA vdd_mpu_iva 0 PWR - - - - - - - ­G12, H7, K11, L9, M9, M10, N7, N8, P10, U7, U11, U13, V7, V11, W9, Y9, Y11
A18, AC7, A3, A15, B5, vdds 0 PWR - - - - - - - ­AC15, F2, F21, AC18, L20, W21 AC24, AD20, AE10, C11, D9, E24, G4, J15, J18, L7, L24, M4, T4, T24, W24, Y4, AB24
U12 NA vdds_sram 0 PWR - - - - - - - ­K13 NA vdda_dplls_dll 0 PWR - - - - - - - ­U14 NA vdda_dpll_per 0 PWR - - - - - - - ­W14 NA vdda_wkup_bg_bb 0 PWR - - - - - - - ­N23 NA vdds_mmc1 0 PWR - - - - - - - ­V25 NA vdda_dac 0 PWR - - - - - - - ­V24 NA vssa_dac 0 GND - - - - - - - -
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(5)
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BALL BALL TOP PIN NAME [3] MODE [4] TYPE [5] BALL BALL RESET RESET POWER [9] HYS [10] BUFFER PULLUP IO CELL BOTTOM [2] RESET REL. STATE REL. MODE STRENGTH /DOWN [13]
[1] STATE [6] [7] [8] (mA) [11] TYPE [12]
A6, A8, A13, A7, A13, vss 0 GND - - - - - - - ­AB5, AB22, B14, C1, F1, AC10, F20, H2, AD14, H20, L21, AD25, AE7, M2, P20, B2, B25, R2, W20 Y6, C12, D7, Y11, AA7, D10, D12, AA16 D14, D18, D20, E22, G1, G8, G10, G20, G23, H4, K1, K15, K25, L10, L17, L23, N4, N10, N17, R1, R4, R17, T23, U25, W1, W4, W23, Y7, Y10, Y16, Y26
K14 NA cap_vddu_wkup_log 0 PWR - - - - - - - -
A1, L1, T2, A1, J1, N2, Feed-Through - - - - - - - - - ­Y2, AE2, T2, W2, Y2, Pins AF4, AF5, AA6, Y7, AF8, AF10, Y9, AA10, AF12, AF13, AA11, AF14, AF15, AA12, AF17, AF16, AA13, Y14, A20, AF21, AA14, B16, AF18, AF24, Y17, AA17, AF22, A25, Y19, AA19, AE25, AF25, A20, Y20, A26, B26, AA20, A21, K26, U26, B21, H21, AE26, AF26 P21, Y21,
AA21
ic
(4)
Table 2-2. Ball Characteristics (CBC Pkg.)
(5)
(continued)
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Table 2-2. Ball Characteristics (CBC Pkg.)
BALL BALL TOP PIN NAME [3] MODE [4] TYPE [5] BALL BALL RESET RESET POWER [9] HYS [10] BUFFER PULLUP IO CELL BOTTOM [2] RESET REL. STATE REL. MODE STRENGTH /DOWN [13]
[1] STATE [6] [7] [8] (mA) [11] TYPE [12]
A2, AF1, A2, AA1, No Connect B1,D5, K23, AA2,B1, B2, A5, A7, A9, B20, Y1 A10, A11, A12, A14, A15, A16, A17, A19, A21, A22, AA23, AB23, AC9, AC12, AC13, AC14, AC17, AC20, AC22, AC23, AD9, AD11, AD12, AD13, AE1, AE8, AE11, AE12, AE13, AF2, AF3, AF11, B7, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, B19, B20, B21, B22, C7, C8, C9, C10, C13, C14, C15, C16, C17 C18, C19, C20, C21, C22, D8, D11, D16, D17, D19, D21, D22, E23, F4, G7, G13, G14, G15, G16, G17, G19, H8, H9, H10, H11, H12, H13, H14, H15, H16, H17, H18, H19, H23, J3, J4, J7, J8, J9, J10, J11, J12, J13, J14, J16, J17, J19, J20, K4, K7, K8, K9, K10, K12, K16, K17, K19, L8, M8, M23, N18, P2, P4, P24, R23, R24, R25, R26, T25, T26, U23, V4, W12, Y23
AF23 NA sys_xtalgnd 0 GND A4 NA gpmc_a11 0 O L L 7 vdds Yes 8 PU/PD LVCMOS
safe_mode 7 D6 NA cap_vdd_bb_mpu_i 0 PWR
N9 NA cap_vdd_sram_mpu 0 PWR
K20 NA cap_vdd_sram_core 0 PWR
va
_iva
(2)
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(5)
(continued)
- - - - - - - - - -
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(1) The drive strength of these IOs is set according to the programmable load range: 2 pF to 4 pF per default or 4 pF to 12 pF. For a full
description of the drive strength programming, see the System Control Module chapter of the AM/DM37x Multimedia Device Technical
Reference Manual (literature number SPRUGN4). (2) Pins labeled as "No connect" must be left unconnected. Any connections to these pins may result in unpredictable behavior. (3) PU = [50 to 100 kΩ] per default or [10 to 50 kΩ] according to the selected mode.
For a full description of the pull-up drive strength programming, see the PRG_SDMMC_PUSTRENGTH configuration register bit field in
the System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).
PD: 30 to 150 kΩ. (4) These signals are feed-through balls. For more information, see Table 2-27. (5) NA in this table stands for "Not Applicable". (6) In the safe_mode_out1, the buffer is configured to drive 1. (7) Depending on the sys_clkreq direction the corresponding reset released state value can be:
– Z if sys_clkreq is used as input
– 1 if sys_clkreq is used as output
For a full description of the sys_clkreq control, see Power, Reset, and Clock Management chapter of the AM/DM37x Multimedia Device
Technical Reference Manual (literature number SPRUGN4). (8) The usage of this GPIO is strongly restricted. For more information, see the General-Purpose Interface chapter of the AM/DM37x
Multimedia Device Technical Reference Manual (literature number SPRUGN4). (9) The pullup and pulldown can be either the standard LVCMOS 100-mA drive strength or the I2C pullup and pulldown described as
follows: Nominal resistance = 1.66 kΩ in high-speed mode with a load range of 5 pF to 12 pF, 4.5 kΩ in standard / fast mode with a load
range of 5 pF to 15 pF. (10) The default buffer configuration is High-Speed I2C point-to-point mode using internal pullup. For a full description of the pull drive
strength programming, see prg_i2c1_pullupresx, prg_i2c1_lb1lb0, and prg_sr_pullupresx, prg_sr_lb bits of the CONTROL_PROG_IO1,
CONTROL_PROG_IO_WKUP1 control modules in the System Control Module chapter of the AM/DM37x Multimedia Device Technical
Reference Manual (literature number SPRUGN4) to modify the IO settings if required by the targeted interface application. (11) The default buffer configuration is standard LVCMOS mode (non-I2C). For a full description of the pull drive strength programming, see
PADCONFS bits of CONTROL_PADCONF_X control modules (standard LVCMOS mode), or prg_i2c2_pullupresx, prg_i2c2_lb1lb0, and
prg_i2c3_pullupresx, prg_i2c3_lb1lb0 bits of the CONTROL_PROG_IO2, CONTROL_PROG_IO3 control modules (I2C mode) in the
System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4) to
modify the IO settings if required by the targeted interface application. (12) Mux0 if sys_boot6 is pulled down (clock master). (13) If MMC1 functional signals are enabled, vdds_mmc1 for MMC1 must be supplied by a dedicated power source.
If MMC1 functional signals are disabled, other multiplexed CMOS signals of the interface can be enabled. The interface can be supplied
by the same power source as vdds. The vdds power source supplies the vdds_mmc1 ball.
If neither MMC1 functional balls or CMOS signals are enabled, the interface balls are left unconnected with its associated power supply
(vdda/vssa) grounded.
For the corresponding setting of the PBIASLITEPWRDNZ0 bit, see the System Control Module / SCM Programming Model /
Extended-Drain I/Os and PBIAS Cells Programming Guide section of the AM/DM37x Multimedia Device Technical Reference Manual
(literature number SPRUGN4).
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Table 2-3. Ball Characteristics (CUS Pkg.)
BALL BALL TOP [2] PIN NAME MODE [4] TYPE [5] BALL RESET BALL RESET RESET REL. POWER [9] HYS [10] BUFFER PULLUP BOTTOM [1] [3] STATE [6] REL. STATE MODE [8] STRENGTH /DOWN
D7 sdrc_d0 0 IO L Z 0 vdds_mem Yes 4 C5 sdrc_d1 0 IO L Z 0 vdds_mem Yes 4 C6 sdrc_d2 0 IO L Z 0 vdds_mem Yes 4 B5 sdrc_d3 0 IO L Z 0 vdds_mem Yes 4 D9 sdrc_d4 0 IO L Z 0 vdds_mem Yes 4 D10 sdrc_d5 0 IO L Z 0 vdds_mem Yes 4 C7 sdrc_d6 0 IO L Z 0 vdds_mem Yes 4 B7 sdrc_d7 0 IO L Z 0 vdds_mem Yes 4 B11 sdrc_d8 0 IO L Z 0 vdds_mem Yes 4 C12 sdrc_d9 0 IO L Z 0 vdds_mem Yes 4 B12 sdrc_d10 0 IO L Z 0 vdds_mem Yes 4 D13 sdrc_d11 0 IO L Z 0 vdds_mem Yes 4 C13 sdrc_d12 0 IO L Z 0 vdds_mem Yes 4 B14 sdrc_d13 0 IO L Z 0 vdds_mem Yes 4 A14 sdrc_d14 0 IO L Z 0 vdds_mem Yes 4 B15 sdrc_d15 0 IO L Z 0 vdds_mem Yes 4 C9 sdrc_d16 0 IO L Z 0 vdds_mem Yes 4
[7] (mA) [11] TYPE [12]
(1)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS
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Table 2-3. Ball Characteristics (CUS Pkg.)
BALL BALL TOP [2] PIN NAME MODE [4] TYPE [5] BALL RESET BALL RESET RESET REL. POWER [9] HYS [10] BUFFER PULLUP BOTTOM [1] [3] STATE [6] REL. STATE MODE [8] STRENGTH /DOWN
E12 sdrc_d17 0 IO L Z 0 vdds_mem Yes 4 B8 sdrc_d18 0 IO L Z 0 vdds_mem Yes 4 B9 sdrc_d19 0 IO L Z 0 vdds_mem Yes 4 C10 sdrc_d20 0 IO L Z 0 vdds_mem Yes 4 B10 sdrc_d21 0 IO L Z 0 vdds_mem Yes 4 D12 sdrc_d22 0 IO L Z 0 vdds_mem Yes 4 E13 sdrc_d23 0 IO L Z 0 vdds_mem Yes 4 E15 sdrc_d24 0 IO L Z 0 vdds_mem Yes 4 D15 sdrc_d25 0 IO L Z 0 vdds_mem Yes 4 C15 sdrc_d26 0 IO L Z 0 vdds_mem Yes 4 B16 sdrc_d27 0 IO L Z 0 vdds_mem Yes 4 C16 sdrc_d28 0 IO L Z 0 vdds_mem Yes 4 D16 sdrc_d29 0 IO L Z 0 vdds_mem Yes 4 B17 sdrc_d30 0 IO L Z 0 vdds_mem Yes 4 B18 sdrc_d31 0 IO L Z 0 vdds_mem Yes 4 C18 sdrc_ba0 0 O 0 0 0 vdds_mem NA 4 D18 sdrc_ba1 0 O 0 0 0 vdds_mem NA 4 A4 sdrc_a0 0 O 0 0 0 vdds_mem NA 4 B4 sdrc_a1 0 O 0 0 0 vdds_mem NA 4 D6 sdrc_a2 0 O 0 0 0 vdds_mem NA 4 B3 sdrc_a3 0 O 0 0 0 vdds_mem NA 4 B2 sdrc_a4 0 O 0 0 0 vdds_mem NA 4 C3 sdrc_a5 0 O 0 0 0 vdds_mem NA 4 E3 sdrc_a6 0 O 0 0 0 vdds_mem NA 4 F6 sdrc_a7 0 O 0 0 0 vdds_mem NA 4 E10 sdrc_a8 0 O 0 0 0 vdds_mem NA 4 E9 sdrc_a9 0 O 0 0 0 vdds_mem NA 4 E7 sdrc_a10 0 O 0 0 0 vdds_mem NA 4 G6 sdrc_a11 0 O 0 0 0 vdds_mem NA 4 G7 sdrc_a12 0 O 0 0 0 vdds_mem NA 4 F7 sdrc_a13 0 O 0 0 0 vdds_mem NA 4 F9 sdrc_a14 0 O 0 0 0 vdds_mem NA 4 A19 sdrc_ncs0 0 O 1 1 0 vdds_mem NA 4 B19 sdrc_ncs1 0 O 1 1 0 vdds_mem NA 4 A10 sdrc_clk 0 IO L 0 0 vdds_mem Yes 4 A11 sdrc_nclk 0 O 1 1 0 vdds_mem NA 4 B20 sdrc_cke0 0 O H 1 7 vdds_mem NA 4
safe_mode_out1
C20 sdrc_cke1 0 O H 1 7 vdds_mem NA 4
safe_mode_out1 D19 sdrc_nras 0 O 1 1 0 vdds_mem NA 4 C19 sdrc_ncas 0 O 1 1 0 vdds_mem NA 4 A20 sdrc_nwe 0 O 1 1 0 vdds_mem NA 4 B6 sdrc_dm0 0 O 0 0 0 vdds_mem NA 4 B13 sdrc_dm1 0 O 0 0 0 vdds_mem NA 4 A7 sdrc_dm2 0 O 0 0 0 vdds_mem NA 4 A16 sdrc_dm3 0 O 0 0 0 vdds_mem NA 4 A5 sdrc_dqs0 0 IO L Z 0 vdds_mem Yes 4 A13 sdrc_dqs1 0 IO L Z 0 vdds_mem Yes 4 A8 sdrc_dqs2 0 IO L Z 0 vdds_mem Yes 4 A17 sdrc_dqs3 0 IO L Z 0 vdds_mem Yes 4 K4 gpmc_a1 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS
gpio_34 4 IO
safe_mode 7 K3 gpmc_a2 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS
(9)
7
(9)
7
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(1)
(continued)
[7] (mA) [11] TYPE [12]
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
(8)
PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS
PU/ PD LVCMOS
PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS PU/ PD LVCMOS
Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 65
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
BALL BALL TOP [2] PIN NAME MODE [4] TYPE [5] BALL RESET BALL RESET RESET REL. POWER [9] HYS [10] BUFFER PULLUP BOTTOM [1] [3] STATE [6] REL. STATE MODE [8] STRENGTH /DOWN
gpio_35 4 IO
safe_mode 7 K2 gpmc_a3 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS
gpio_36 4 IO
safe_mode 7 J4 gpmc_a4 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS
gpio_37 4 IO
safe_mode 7 J3 gpmc_a5 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS
gpio_38 4 IO
safe_mode 7 J2 gpmc_a6 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
gpio_39 4 IO
safe_mode 7 J1 gpmc_a7 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
gpio_40 4 IO
safe_mode 7 H1 gpmc_a8 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
gpio_41 4 IO
safe_mode 7 H2 gpmc_a9 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
sys_ndmareq2 1 I
G2 gpmc_a10 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
L2 gpmc_d0 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS M1 gpmc_d1 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS M2 gpmc_d2 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS N2 gpmc_d3 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS M3 gpmc_d4 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS P1 gpmc_d5 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS P2 gpmc_d6 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS R1 gpmc_d7 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS R2 gpmc_d8 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS
T2 gpmc_d9 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS
U1 gpmc_d10 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS
R3 gpmc_d11 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS
T3 gpmc_d12 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS
U2 gpmc_d13 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS
V1 gpmc_d14 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS
gpio_42 4 IO
safe_mode 7
sys_ndmareq3 1 I
gpio_43 4 IO
safe_mode 7
gpio_44 4 IO
safe_mode 7
gpio_45 4 IO
safe_mode 7
gpio_46 4 IO
safe_mode 7
gpio_47 4 IO
safe_mode 7
gpio_48 4 IO
safe_mode 7
gpio_49 4 IO
safe_mode 7
Table 2-3. Ball Characteristics (CUS Pkg.)
[7] (mA) [11] TYPE [12]
(1)
(continued)
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Table 2-3. Ball Characteristics (CUS Pkg.)
BALL BALL TOP [2] PIN NAME MODE [4] TYPE [5] BALL RESET BALL RESET RESET REL. POWER [9] HYS [10] BUFFER PULLUP BOTTOM [1] [3] STATE [6] REL. STATE MODE [8] STRENGTH /DOWN
gpio_50 4 IO
safe_mode 7 V2 gpmc_d15 0 IO H H 0 vdds_mem Yes 8 PU/ PD LVCMOS
gpio_51 4 IO
safe_mode 7 E2 gpmc_ncs0 0 O 1 1 0 vdds_mem NA 8 NA LVCMOS D2 gpmc_ncs3 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
sys_ndmareq0 1 I
gpio_54 4 IO
safe_mode 7 F4 gpmc_ncs4 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
sys_ndmareq1 1 I
mcbsp4_ clkx 2 IO
gpt_9_pwm_evt 3 IO
gpio_55 4 IO
safe_mode 7 G5 gpmc_ncs5 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
sys_ndmareq2 1 I
mcbsp4_dr 2 I
gpt_10_pwm_evt 3 IO
gpio_56 4 IO
safe_mode 7 F3 gpmc_ncs6 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
sys_ndmareq3 1 I
mcbsp4_dx 2 IO
gpt_11_pwm_evt 3 IO
gpio_57 4 IO
safe_mode 7 G4 gpmc_ncs7 0 O H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
gpmc_io_dir 1 O
mcbsp4_fsx 2 IO
gpt_8_pwm_evt 3 IO
gpio_58 4 IO
safe_mode 7 W2 gpmc_clk 0 O L 0 0 vdds_mem Yes 8 PU/ PD LVCMOS
gpio_59 4 IO
safe_mode 7 F1 gpmc_nadv_ale 0 O 0 0 0 vdds_mem NA 8 PU/ PD LVCMOS F2 gpmc_noe 0 O 1 1 0 vdds_mem NA 8 PU/ PD LVCMOS G3 gpmc_nwe 0 O 1 1 0 vdds_mem NA 8 PU/ PD LVCMOS K5 gpmc_nbe0_cle 0 O L 0 0 vdds_mem Yes 8 PU/ PD LVCMOS
gpio_60 4 IO
safe_mode 7 L1 gpmc_nbe1 0 O L L 7 vdds_mem Yes 8 PU/ PD LVCMOS
gpio_61 4 IO
safe_mode 7 E1 gpmc_nwp 0 O L 0 0 vdds_mem Yes 8 PU/ PD LVCMOS
gpio_62 4 IO
safe_mode 7 C1 gpmc_wait0 0 I H H 0 vdds_mem Yes NA PU/ PD LVCMOS C2 gpmc_wait3 0 I H H 7 vdds_mem Yes 8 PU/ PD LVCMOS
sys_ndmareq1 1 I
uart4_rx 2 I
gpio_65 4 IO
safe_mode 7
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(1)
(continued)
[7] (mA) [11] TYPE [12]
Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 67
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
BALL BALL TOP [2] PIN NAME MODE [4] TYPE [5] BALL RESET BALL RESET RESET REL. POWER [9] HYS [10] BUFFER PULLUP BOTTOM [1] [3] STATE [6] REL. STATE MODE [8] STRENGTH /DOWN
G22 dss_pclk 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
gpio_66 4 IO
hw_dbg12 5 O
safe_mode 7 E22 dss_hsync 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
gpio_67 4 IO
hw_dbg13 5 O
safe_mode 7 F22 dss_vsync 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
gpio_68 4 IO
safe_mode 7 J21 dss_acbias 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_69 4 IO
safe_mode 7 AC19 dss_data0 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
uart1_cts 2 I NA
gpio_70 4 IO 8
safe_mode 7 8 AB19 dss_data1 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
uart1_rts 2 O 8
gpio_71 4 IO 8
safe_mode 7 8 AD20 dss_data2 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_72 4 IO 8
safe_mode 7 8 AC20 dss_data3 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_73 4 IO 8
safe_mode 7 8 AD21 dss_data4 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
uart3_rx_ irrx 2 I NA
gpio_74 4 IO 8
safe_mode 7 8 AC21 dss_data5 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
uart3_tx_ irtx 2 O 8
gpio_75 4 IO 8
safe_mode 7 8 D24 dss_data6 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
uart1_tx 2 O
gpio_76 4 IO
hw_dbg14 5 O
safe_mode 7 E23 dss_data7 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
uart1_rx 2 I
gpio_77 4 IO
hw_dbg15 5 O
safe_mode 7 E24 dss_data8 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
uart3_rx_irrx 2 I
gpio_78 4 IO
hw_dbg16 5 O
safe_mode 7 F23 dss_data9 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
uart3_tx_irtx 2 O
gpio_79 4 IO
hw_dbg17 5 O
Table 2-3. Ball Characteristics (CUS Pkg.)
[7] (mA) [11] TYPE [12]
(1)
(continued)
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68 TERMINAL DESCRIPTION Copyright © 2010, Texas Instruments Incorporated
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www.ti.com
Table 2-3. Ball Characteristics (CUS Pkg.)
BALL BALL TOP [2] PIN NAME MODE [4] TYPE [5] BALL RESET BALL RESET RESET REL. POWER [9] HYS [10] BUFFER PULLUP BOTTOM [1] [3] STATE [6] REL. STATE MODE [8] STRENGTH /DOWN
safe_mode 7 AC22 dss_data10 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_80 4 IO
safe_mode 7 AC23 dss_data11 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_81 4 IO
safe_mode 7 AB22 dss_data12 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_82 4 IO
safe_mode 7 Y22 dss_data13 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_83 4 IO
safe_mode 7 W22 dss_data14 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_84 4 IO
safe_mode 7 V22 dss_data15 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_85 4 IO
safe_mode 7 J22 dss_data16 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_86 4 IO
safe_mode 7 G23 dss_data17 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_87 4 IO
safe_mode 7 G24 dss_data18 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
mcspi3_clk 2 IO
dss_data0 3 IO
gpio_88 4 IO
safe_mode 7 H23 dss_data19 0 IO L L 7 vdds Yes 8 PU/ PD LVCMOS
mcspi3_simo 2 IO
dss_data1 3 IO
gpio_89 4 IO
safe_mode 7 D23 dss_data20 0 O H H 7 vdds Yes 8 PU/ PD LVCMOS
mcspi3_somi 2 IO
dss_data2 3 IO
K22 dss_data21 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS
V21 dss_data22 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS
W21 dss_data23 0 O L L 7 vdds Yes 8 PU/ PD LVCMOS
AA23 cvideo2_out 0 AO 0 0 0 vdda_dac NA NA
gpio_90 4 IO
safe_mode 7
mcspi3_cs0 2 IO
dss_data3 3 IO
gpio_91 4 IO
safe_mode 7
mcspi3_cs1 2 O
dss_data4 3 IO
gpio_92 4 IO
safe_mode 7
dss_data5 3 IO
gpio_93 4 IO
safe_mode 7
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(1)
(continued)
[7] (mA) [11] TYPE [12]
(6)
NA 10-bit DAC
Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 69
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DM3730, DM3725
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
BALL BALL TOP [2] PIN NAME MODE [4] TYPE [5] BALL RESET BALL RESET RESET REL. POWER [9] HYS [10] BUFFER PULLUP BOTTOM [1] [3] STATE [6] REL. STATE MODE [8] STRENGTH /DOWN
AB24 cvideo1_out 0 AO 0 0 0 vdda_dac NA NA AB23 cvideo1_vfb 0 AO 0 NA 0 vdda_dac NA NA Y23 cvideo2_vfb 0 AO 0 NA 0 vdda_dac NA NA Y24 cvideo1_rset 0 AIO 0 NA 0 vdda_dac No NA NA 10-bit DAC A22 cam_hs 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_94 4 IO
hw_dbg0 5 O
safe_mode 7 E18 cam_vs 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_95 4 IO
hw_dbg1 5 O
safe_mode 7 B22 cam_ xclka 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_96 4 IO
safe_mode 7 J19 cam_pclk 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_97 4 IO
hw_dbg2 5 O
safe_mode 7 H24 cam_fld 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
cam_global_reset 2 IO
hw_dbg3 5 O
AB18 cam_d0 0 I L L 7 vdds Yes NA PU/ PD LVCMOS
AC18 cam_d1 0 I L L 7 vdds Yes NA PU/ PD LVCMOS
G19 cam_d2 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
F19 cam_d3 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
G20 cam_d4 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
B21 cam_d5 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
L24 cam_d6 0 I L L 7 vdds Yes NA PU/ PD LVCMOS
K24 cam_d7 0 I L L 7 vdds Yes NA PU/ PD LVCMOS
J23 cam_d8 0 I L L 7 vdds Yes NA PU/ PD LVCMOS
gpio_98 4 IO
safe_mode 7
gpio_99 4 I
safe_mode 7
gpio_100 4 I
safe_mode 7
gpio_101 4 IO
hw_dbg4 5 O
safe_mode 7
gpio_102 4 IO
hw_dbg5 5 O
safe_mode 7
gpio_103 4 IO
hw_dbg6 5 O
safe_mode 7
gpio_104 4 IO
hw_dbg7 5 O
safe_mode 7
gpio_105 4 I
safe_mode 7
gpio_106 4 I
safe_mode 7
gpio_107 4 I
safe_mode 7
Table 2-3. Ball Characteristics (CUS Pkg.)
[7] (mA) [11] TYPE [12]
(1)
(continued)
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(6)
(7)
(7)
NA 10-bit DAC NA 10-bit DAC NA 10-bit DAC
70 TERMINAL DESCRIPTION Copyright © 2010, Texas Instruments Incorporated
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Table 2-3. Ball Characteristics (CUS Pkg.)
BALL BALL TOP [2] PIN NAME MODE [4] TYPE [5] BALL RESET BALL RESET RESET REL. POWER [9] HYS [10] BUFFER PULLUP BOTTOM [1] [3] STATE [6] REL. STATE MODE [8] STRENGTH /DOWN
K23 cam_d9 0 I L L 7 vdds Yes NA PU/ PD LVCMOS
gpio_108 4 I
safe_mode 7 F21 cam_d10 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_109 4 IO
hw_dbg8 5 O
safe_mode 7 G21 cam_d11 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_110 4 IO
hw_dbg9 5 O
safe_mode 7 C22 cam_ xclkb 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_111 4 IO
safe_mode 7 F18 cam_wen 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
cam_ shutter 2 O
gpio_167 4 IO
hw_dbg10 5 O
safe_mode 7 J20 cam_ strobe 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_126 4 IO
hw_dbg11 5 O
safe_mode 7 V20 mcbsp2_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_116 4 IO
safe_mode 7 T21 mcbsp2_ clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_117 4 IO
safe_mode 7 V19 mcbsp2_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_118 4 IO
safe_mode 7 R20 mcbsp2_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_119 4 IO
safe_mode 7 M23 mmc1_clk 0 IO L L 7 vdds_mmc1(1Yes 1 PU/ PD
(5)
gpio_120
L23 mmc1_cmd 0 O L L 7 vdds_mmc1(1Yes 1 PU/ PD
M22 mmc1_dat0 0 IO L L 7 vdds_mmc1(1Yes 1 PU/ PD
M21 mmc1_dat1 0 IO L L 7 vdds_mmc1(1Yes 1 PU/ PD
M20 mmc1_dat2 0 IO L L 7 vdds_mmc1(1Yes 1 PU/ PD
N23 mmc1_dat3 0 IO L L 7 vdds_mmc1(1Yes 1 PU/ PD
safe_mode 7
(5)
gpio_121
safe_mode 7
(5)
gpio_122
safe_mode 7
(5)
gpio_123
safe_mode 7
(5)
gpio_124
safe_mode 7
4 IO
4 IO
4 IO
4 IO
4 IO
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(1)
(continued)
[7] (mA) [11] TYPE [12]
(4)
4)
4)
4)
4)
4)
4)
LVCMOS
(4)
LVCMOS
(4)
LVCMOS
(4)
LVCMOS
(4)
LVCMOS
(4)
LVCMOS
Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 71
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
BALL BALL TOP [2] PIN NAME MODE [4] TYPE [5] BALL RESET BALL RESET RESET REL. POWER [9] HYS [10] BUFFER PULLUP BOTTOM [1] [3] STATE [6] REL. STATE MODE [8] STRENGTH /DOWN
(5)
gpio_125
safe_mode 7 N22 gpio_126
P24 gpio_129
Y1 mmc2_clk 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
AB5 mmc2_ cmd 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
AB3 mmc2_ dat0 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
Y3 mmc2_ dat1 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
W3 mmc2_ dat2 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
V3 mmc2_ dat3 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
AB2 mmc2_ dat4 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
AA2 mmc2_ dat5 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
Y2 mmc2_dat6 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
AA1 mmc2_dat7 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
V6 mcbsp3_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
(5)
safe_mode 7
(5)
safe_mode 7
mcspi3_clk 1 IO
gpio_130 4 IO
safe_mode 7
mcspi3_ simo 1 IO
gpio_131 4 IO
safe_mode 7
mcspi3_ somi 1 IO
gpio_132 4 IO
safe_mode 7
gpio_133 4 IO
safe_mode 7
mcspi3_cs1 1 O
gpio_134 4 IO
safe_mode 7
mcspi3_cs0 1 IO
gpio_135 4 IO
safe_mode 7
mmc2_dir_dat0 1 O
mmc3_dat0 3 IO
gpio_136 4 IO
safe_mode 7
mmc2_dir_dat1 1 O
cam_global_reset 2 IO
mmc3_dat1 3 IO
gpio_137 4 IO
mm3_rxdp 6 IO
safe_mode 7
mmc2_dir_cmd 1 O
cam_shutter 2 O
mmc3_dat2 3 IO
gpio_138 4 IO
safe_mode 7
mmc2_clkin 1 I
mmc3_dat3 3 IO
gpio_139 4 IO
mm3_rxdm 6 IO
safe_mode 7
uart2_cts 1 I
4 IO
4 IO L L 7 vdds_x Yes 1 PU/ PD
4 IO L L 7 vdds_x Yes 1 PU/ PD
Table 2-3. Ball Characteristics (CUS Pkg.)
[7] (mA) [11] TYPE [12]
(1)
(continued)
(4)
(4)
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LVCMOS
LVCMOS
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Table 2-3. Ball Characteristics (CUS Pkg.)
BALL BALL TOP [2] PIN NAME MODE [4] TYPE [5] BALL RESET BALL RESET RESET REL. POWER [9] HYS [10] BUFFER PULLUP BOTTOM [1] [3] STATE [6] REL. STATE MODE [8] STRENGTH /DOWN
gpio_140 4 IO
safe_mode 7 V5 mcbsp3_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
uart2_rts 1 O
gpio_141 4 IO
safe_mode 7 W4 mcbsp3_ clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
uart2_tx 1 O
gpio_142 4 IO
safe_mode 7 V4 mcbsp3_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
uart2_rx 1 I
gpio_143 4 IO
safe_mode 7 W7 uart1_tx 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_148 4 IO
safe_mode 7 W6 uart1_rts 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_149 4 IO
safe_mode 7 AC2 uart1_cts 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_150 4 IO
safe_mode 7 V7 uart1_rx 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
mcbsp1_ clkr 2 IO
mcspi4_clk 3 IO
gpio_151 4 IO
safe_mode 7 W19 mcbsp1_ clkr 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
mcspi4_clk 1 IO
gpio_156 4 IO
safe_mode 7 AB20 mcbsp1_fsr 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
cam_global_reset 2 IO
gpio_157 4 IO
safe_mode 7 W18 mcbsp1_dx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
mcspi4_ simo 1 IO
Y18 mcbsp1_dr 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
AA18 mcbsp_clks 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
AA19 mcbsp1_fsx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
mcbsp3_dx 2 IO
gpio_158 4 IO
safe_mode 7
mcspi4_ somi 1 IO
mcbsp3_dr 2 I
gpio_159 4 IO
safe_mode 7
cam_ shutter 2 O
gpio_160 4 IO
uart1_cts 5 I
safe_mode 7
mcspi4_cs0 1 IO
mcbsp3_fsx 2 IO
gpio_161 4 IO
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(1)
(continued)
[7] (mA) [11] TYPE [12]
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
BALL BALL TOP [2] PIN NAME MODE [4] TYPE [5] BALL RESET BALL RESET RESET REL. POWER [9] HYS [10] BUFFER PULLUP BOTTOM [1] [3] STATE [6] REL. STATE MODE [8] STRENGTH /DOWN
safe_mode 7 V18 mcbsp1_ clkx 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
mcbsp3_ clkx 2 IO
gpio_162 4 IO
safe_mode 7 A23 uart3_cts_ rctx 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
gpio_163 4 IO
safe_mode 7 B23 uart3_rts_ sd 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
gpio_164 4 IO
safe_mode 7 B24 uart3_rx_ irrx 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS
gpio_165 4 IO
safe_mode 7 C23 uart3_tx_ irtx 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
gpio_166 4 IO
safe_mode 7 R21 hsusb0_clk 0 I L L 7 vdds Yes 8 PU/ PD LVCMOS
gpio_120 4 IO
safe_mode 7 R23 hsusb0_stp 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
gpio_121 4 IO
P23 hsusb0_dir 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
R22 hsusb0_nxt 0 I L L 7 vdds Yes 4 PU/ PD LVCMOS
T24 hsusb0_ data0 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
T23 hsusb0_ data1 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
U24 hsusb0_ data2 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
U23 hsusb0_ data3 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
W24 hsusb0_ data4 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
V23 hsusb0_ data5 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
safe_mode 7
gpio_122 4 IO
safe_mode 7
gpio_124 4 IO
safe_mode 7
uart3_tx_ irtx 2 O
gpio_125 4 IO
uart2_tx 5 O
safe_mode 7
uart3_rx_ irrx 2 I
gpio_130 4 IO
uart2_rx 5 I
safe_mode 7
uart3_rts_ sd 2 O
gpio_131 4 IO
uart2_rts 5 O
safe_mode 7
uart3_cts_ rctx 2 IO
gpio_169 4 IO
uart2_cts 5 I
safe_mode 7
gpio_188 4 IO
safe_mode 7
gpio_189 4 IO
safe_mode 7
Table 2-3. Ball Characteristics (CUS Pkg.)
[7] (mA) [11] TYPE [12]
(1)
(continued)
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Table 2-3. Ball Characteristics (CUS Pkg.)
BALL BALL TOP [2] PIN NAME MODE [4] TYPE [5] BALL RESET BALL RESET RESET REL. POWER [9] HYS [10] BUFFER PULLUP BOTTOM [1] [3] STATE [6] REL. STATE MODE [8] STRENGTH /DOWN
W23 hsusb0_ data6 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_190 4 IO
safe_mode 7 T22 hsusb0_ data7 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_191 4 IO
safe_mode 7 K20 i2c1_scl 0 OD H H 0 vdds NA 3 PU/ PD K21 i2c1_sda 0 IOD H H 0 vdds Yes 3 PU/ PD AC15 i2c2_scl 0 OD H H 7 vdds Yes 3 PU/ PD
gpio_168 4 IO 4
safe_mode 7 AC14 i2c2_sda 0 IOD H H 7 vdds Yes 3 PU/ PD
gpio_183 4 IO 4
safe_mode 7 AC13 i2c3_scl 0 OD H H 7 vdds Yes 3 PU/ PD
gpio_184 4 IO 4
safe_mode 7 AC12 i2c3_sda 0 IOD H H 7 vdds Yes 3 PU/ PD
gpio_185 4 IO 4
safe_mode 7 Y16 i2c4_scl 0 OD H H 0 vdds Yes 3 PU/ PD
sys_nvmode1 1 O 4
safe_mode 7 Y15 i2c4_sda 0 IOD H H 0 vdds Yes 3 PU/ PD
sys_nvmode2 1 O 4
safe_mode 7 A24 hdq_sio 0 IOD H H 7 vdds Yes 4 PU/ PD LVCMOS
sys_altclk 1 I
i2c2_sccbe 2 OD
i2c3_sccbe 3 OD
gpio_170 4 IO
safe_mode 7 T5 mcspi1_clk 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
mmc2_dat4 1 IO
gpio_171 4 IO
safe_mode 7 R4 mcspi1_ simo 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
mmc2_dat5 1 IO
T4 mcspi1_ somi 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
T6 mcspi1_cs0 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
R5 mcspi1_cs3 0 O H H 7 vdds Yes 4 PU/ PD LVCMOS
N5 mcspi2_clk 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_172 4 IO
safe_mode 7
mmc2_dat6 1 IO
gpio_173 4 IO
safe_mode 7
mmc2_dat7 1 IO
gpio_174 4 IO
safe_mode 7
hsusb2_ data2 3 IO
gpio_177 4 IO
mm2_txdat 5 IO
safe_mode 7
hsusb2_ data7 3 IO
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(1)
(continued)
[7] (mA) [11] TYPE [12]
(10)(11)
Open Drain
(10)(11)
Open Drain
(10)(12)
Open Drain
(10)(12)
Open Drain
(10)(12)
Open Drain
(10)(12)
Open Drain
(10)(11)
Open Drain
(10)(11)
Open Drain
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BALL BALL TOP [2] PIN NAME MODE [4] TYPE [5] BALL RESET BALL RESET RESET REL. POWER [9] HYS [10] BUFFER PULLUP BOTTOM [1] [3] STATE [6] REL. STATE MODE [8] STRENGTH /DOWN
gpio_178 4 IO
safe_mode 7 N4 mcspi2_ simo 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
gpt_9_pwm_evt 1 IO
hsusb2_ data4 3 IO
gpio_179 4 IO
safe_mode 7 N3 mcspi2_ somi 0 IO L L 7 vdds Yes 4 PU/ PD LVCMOS
gpt_10_pwm_evt 1 IO
hsusb2_ data5 3 IO
gpio_180 4 IO
safe_mode 7 M5 mcspi2_cs0 0 IO H H 7 vdds Yes 4 PU/ PD LVCMOS
gpt_11_pwm_evt 1 IO
hsusb2_ data6 3 IO
gpio_181 4 IO
safe_mode 7 M4 mcspi2_cs1 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
gpt_8_pwm_evt 1 IO
hsusb2_ data3 3 IO
gpio_182 4 IO
mm2_txen_n 5 IO
AA16 sys_32k 0 I Z Z 0 vdds Yes NA PU/ PD LVCMOS AD15 sys_xtalin 0 AI Z Z 0 vdds Yes NA No Analog AD14 sys_xtalout 0 AO Z 0 0 vdds NA NA NA Analog Y13 sys_clkreq 0 IO 0 see
W16 sys_nirq 0 I H H 7 vdds Yes 4 PU/ PD LVCMOS
AA10 sys_nrespwron 0 I Z Z 0 vdds Yes NA No LVCMOS Y10 sys_nreswarm 0 IOD 0 1 0 vdds Yes 4 PU/ PD LVCMOS
AB12 sys_boot0 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
AC16 sys_boot1 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
AD17 sys_boot2 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
AD18 sys_boot3 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
AC17 sys_boot4 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
safe_mode 7
gpio_1 4 IO
safe_mode 7
gpio_0 4 IO
safe_mode 7
gpio_30 4 IO
safe_mode 7
dss_data18 3 IO
gpio_2 4 IO
safe_mode 7
dss_data19 3 IO
gpio_3 4 IO
safe_mode 7
gpio_4 4 IO
safe_mode 7
dss_data20 3 O
gpio_5 4 IO
safe_mode 7
mmc2_dir_dat2 1 O
dss_data21 3 O
gpio_6 4 IO
Table 2-3. Ball Characteristics (CUS Pkg.)
[7] (mA) [11] TYPE [12]
(3)
0 vdds Yes 4 PU/ PD LVCMOS
(1)
(continued)
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Table 2-3. Ball Characteristics (CUS Pkg.)
BALL BALL TOP [2] PIN NAME MODE [4] TYPE [5] BALL RESET BALL RESET RESET REL. POWER [9] HYS [10] BUFFER PULLUP BOTTOM [1] [3] STATE [6] REL. STATE MODE [8] STRENGTH /DOWN
safe_mode 7 AB16 sys_boot5 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
mmc2_dir_dat3 1 O
dss_data22 3 O
gpio_7 4 IO
safe_mode 7 AA15 sys_boot6 0 I Z Z 0 vdds Yes 8 PU/ PD LVCMOS
dss_data23 3 O
gpio_8 4 IO
safe_mode 7 AD23 sys_off_ mode 0 O 0 L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_9 4 IO
safe_mode 7 Y7 sys_clkout1 0 O L L 7
gpio_10 4 IO
safe_mode 7 AA6 sys_clkout2 0 O L L 7 vdds Yes 4 PU/ PD LVCMOS
gpio_186 4 IO
safe_mode 7 AB7 jtag_ntrst 0 I L L 0 vdds Yes NA PU/ PD LVCMOS AB6 jtag_tck 0 I L L 0 vdds Yes NA PU/ PD LVCMOS AA7 jtag_rtck 0 O L 0 0 vdds NA 4 PU/ PD LVCMOS AA9 jtag_tms_tmsc 0 IO H H 0 vdds Yes 4 PU/ PD LVCMOS AB10 jtag_tdi 0 I H H 0 vdds Yes NA PU/ PD LVCMOS AB9 jtag_tdo 0 O L Z 0 vdds NA 4 PU/ PD LVCMOS AC24 jtag_emu0 0 IO H H 0 vdds Yes 4 PU/ PD LVCMOS
gpio_11 4 IO
safe_mode 7 AD24 jtag_emu1 0 IO H H 0 vdds Yes 4 PU/ PD LVCMOS
gpio_31 4 IO
safe_mode 7 AC1 etk_clk 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS
mcbsp5_ clkx 1 IO
mmc3_clk 2 IO
hsusb1_stp 3 O
gpio_12 4 IO
mm1_rxdp 5 IO
hw_dbg0 7 O AD3 etk_ctl 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS
mmc3_cmd 2 O
hsusb1_clk 3 O
gpio_13 4 IO
hw_dbg1 7 O AD6 etk_d0 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS
mcspi3_ simo 1 IO
mmc3_dat4 2 IO
hsusb1_ data0 3 IO
gpio_14 4 IO
mm1_rxrcv 5 IO
hw_dbg2 7 O AC6 etk_d1 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS
mcspi3_ somi 1 IO
hsusb1_ data1 3 IO
gpio_15 4 IO
mm1_txse0 5 IO
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(1)
(continued)
[7] (mA) [11] TYPE [12]
(13)
vdds Yes 4 PU/ PD LVCMOS
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
BALL BALL TOP [2] PIN NAME MODE [4] TYPE [5] BALL RESET BALL RESET RESET REL. POWER [9] HYS [10] BUFFER PULLUP BOTTOM [1] [3] STATE [6] REL. STATE MODE [8] STRENGTH /DOWN
hw_dbg3 7 O AC7 etk_d2 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS
mcspi3_cs0 1 IO
hsusb1_ data2 3 IO
gpio_16 4 IO
mm1_txdat 5 IO
hw_dbg4 7 O AD8 etk_d3 0 O H H 4 vdds Yes 4 PU/ PD LVCMOS
mcspi3_clk 1 IO
mmc3_dat3 2 IO
hsusb1_ data7 3 IO
gpio_17 4 IO
hw_dbg5 7 O AC5 etk_d4 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
mcbsp5_dr 1 I
mmc3_dat0 2 IO
hsusb1_ data4 3 IO
gpio_18 4 IO
hw_dbg6 7 O AD2 etk_d5 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
mcbsp5_fsx 1 IO
mmc3_dat1 2 IO
AC8 etk_d6 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
AD9 etk_d7 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
AC4 etk_d8 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
AD5 etk_d9 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
AC3 etk_d10 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
AC9 etk_d11 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
hsusb1_ data5 3 IO
gpio_19 4 IO
hw_dbg7 7 O
mcbsp5_dx 1 O
mmc3_dat2 2 IO
hsusb1_ data6 3 IO
gpio_20 4 IO
hw_dbg8 7 O
mcspi3_cs1 1 O
mmc3_dat7 2 IO
hsusb1_ data3 3 IO
gpio_21 4 IO
mm1_txen_n 5 IO
hw_dbg9 7 O
mmc3_dat6 2 IO
hsusb1_dir 3 I
gpio_22 4 IO
hw_dbg10 7 O
mmc3_dat5 2 IO
hsusb1_nxt 3 I
gpio_23 4 IO
mm1_rxdm 5 IO
hw_dbg11 7 O
uart1_rx 2 I
hsusb2_clk 3 O
gpio_24 4 IO
hw_dbg12 7 O
Table 2-3. Ball Characteristics (CUS Pkg.)
[7] (mA) [11] TYPE [12]
(1)
(continued)
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Table 2-3. Ball Characteristics (CUS Pkg.)
BALL BALL TOP [2] PIN NAME MODE [4] TYPE [5] BALL RESET BALL RESET RESET REL. POWER [9] HYS [10] BUFFER PULLUP BOTTOM [1] [3] STATE [6] REL. STATE MODE [8] STRENGTH /DOWN
hsusb2_stp 3 O
gpio_25 4 IO
mm2_rxdp 5 IO
hw_dbg13 7 O AC10 etk_d12 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
hsusb2_dir 3 I
gpio_26 4 IO
hw_dbg14 7 O AD11 etk_d13 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
hsusb2_nxt 3 I
gpio_27 4 IO
mm2_rxdm 5 IO
hw_dbg15 7 O AC11 etk_d14 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
hsusb2_ data0 3 IO
gpio_28 4 IO
mm2_rxrcv 5 IO
hw_dbg16 7 O AD12 etk_d15 0 O L L 4 vdds Yes 4 PU/ PD LVCMOS
hsusb2_ data1 3 IO
gpio_29 4 IO
mm2_txse0 5 IO
hw_dbg17 7 O E16, F15, vdds_mem 0 PWR - - - - - - - -
F16, G15, G16, H15, J6, J7, J8, K6, K7, K8
F12, F13, vdd_core 0 PWR - - - - - - - ­G12, G13, H12, H13, J17, J18, K17, K18, K19, L14, L15, M14, M15, R17, R18, R19, T17, T18, T19, T20
F10, G9, vdd_mpu_iva 0 PWR - - - - - - - ­G10, H9, H10, J9, J10, L11, L12, M6, M7, M8, M12, N6, N7, N8, R6, R7, R8, T7, T8, U12, U13, V12, V13, W12, W13
H8 vdds_x 0 PWR - - - - - - - ­M17, M18, vdds 0 PWR - - - - - - - -
M19, N17, N18, N19, U10, V9, V10, W9, W10, Y9
N24 vdds_mmc1 0 PWR - - - - - - - ­Y12 cap_vddu_ 0 PWR - - - - - - - -
U8 cap_vdd_sram_mpu_ 0 PWR - - - - - - - -
H17 cap_vdd_sram_core 0 PWR - - - - - - - ­G18 vdda_dplls_dll 0 PWR - - - - - - - ­U17 vdda_dpll_per 0 PWR - - - - - - - ­AA12 vdds_sram 0 PWR - - - - - - - ­AA13 vdda_wkup_bg_bb 0 PWR - - - - - - - -
wkup_logic
iva
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(1)
(continued)
[7] (mA) [11] TYPE [12]
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SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
BALL BALL TOP [2] PIN NAME MODE [4] TYPE [5] BALL RESET BALL RESET RESET REL. POWER [9] HYS [10] BUFFER PULLUP BOTTOM [1] [3] STATE [6] REL. STATE MODE [8] STRENGTH /DOWN
N21 cap_vdd_bb_mpu_iv 0 PWR - - - - - - - -
N20 cap_vddu_array 0 PWR - - - - - - - ­AB15 vssa_dac 0 GND - - - - - - - ­AB13 vdda_dac 0 PWR - - - - - - - ­H11, H14, vss 0 GND - - - - - - - -
H16, J11, J12, J13, J14, J15, J16, K10, K11, K14, K15, L8, L10, L13, L17, M9, M10, M11, M13, M16, N9, N10, N11, N12, N13, N14, N15, N16, P8, P10, P11, P12, P13, P14, P15, P17, R10, R11, R14, R15, T9, T10, T11, T12, T13, T14, T15, T16, U9, U11, U14, U15, U16, V15, V16
AD1, A1, A2, No Connect B1
W15 sys_xtalgnd 0 GND - - - - - - - -
a
(2)
- - - - - - - - - -
(1) NA in this table stands for "Not Applicable". (2) Pins labeled as "No connect" must be left unconnected. Any connections to these pins may result in unpredictable behavior. (3) Depending on the sys_clkreq direction the corresponding reset released state value can be:
– Z if sys_clkreq is used as input – 1 if sys_clkreq is used as output For a full description of the sys_clkreq control, see Power, Reset, and Clock Management chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).
(4) PU = [50 to 100 kΩ] per default or [10 to 50 kΩ] according to the selected mode. For a full description of the pull-up drive strength
programming, see the PRG_SDMMC_PUSTRENGTH configuration register bit field in the System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4). PD: 30 to 150 kΩ.
(5) The usage of this GPIO is strongly restricted. For more information, see the General-Purpose Interface chapter of the AM/DM37x
Multimedia Device Technical Reference Manual (literature number SPRUGN4). (6) The drive strength is fixed regardless of the load. The driver is designed to drive 75Ω for video applications. (7) In buffer mode, the drive strength is fixed regardless of the load. The driver is designed to drive 75Ω for video applications. In bypass
mode, the drive strength is 0.47 mA. (8) The drive strength of these IOs is set according to the programmable load range: 2 pF to 4 pF per default or 4 pF to 12 pF. For a full
description of the drive strength programming, see the System Control Module chapter of the AM/DM37x Multimedia Device Technical
Reference Manual (literature number SPRUGN4). (9) In the safe_mode_out1, the buffer is configured to drive 1. (10) The pullup and pulldown can be either the standard LVCMOS 100-mA drive strength or the I2C pullup and pulldown described below:
Nominal resistance = 1.66 kΩ in high-speed mode with a load range of 5 pF to 12 pF, 4.5 kΩ in standard / fast mode with a load range
of 5 pF to 15 pF. (11) The default buffer configuration is High-Speed I2C point-to-point mode using internal pullup. For a full description of the pull drive
strength programming, see prg_i2c1_pullupresx, prg_i2c1_lb1lb0, and prg_sr_pullupresx, prg_sr_lb bits of the CONTROL_PROG_IO1,
CONTROL_PROG_IO_WKUP1 control modules in the System Control Module / SCM Programming Model / Feature Settings section
and the System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number
SPRUGN4) to modify the IO settings if required by the targeted interface application.
(12) The default buffer configuration is standard LVCMOS mode (non-I2C). For a full description of the pull drive strength programming, see
PADCONFS bits of CONTROL_PADCONF_X control modules (standard LVCMOS mode), or prg_i2c2_pullupresx, prg_i2c2_lb1lb0, and
prg_i2c3_pullupresx, prg_i2c3_lb1lb0 bits of the CONTROL_PROG_IO2, CONTROL_PROG_IO3 control modules (I2C mode) in the
System Control Module chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4) to
modify the IO settings if required by the targeted interface application. (13) Mux0 if sys_boot6 is pulled down (clock master).
80 TERMINAL DESCRIPTION Copyright © 2010, Texas Instruments Incorporated
Table 2-3. Ball Characteristics (CUS Pkg.)
[7] (mA) [11] TYPE [12]
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(1)
(continued)
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(14) If MMC1 functional signals are enabled, vdds_mmc1 for MMC1 must be supplied by a dedicated power source.
If MMC1 functional signals are disabled, other multiplexed CMOS signals of the interface can be enabled. The interface can be supplied
by the same power source as vdds. The vdds power source supplies the vdds_mmc1 ball.
If neither MMC1 functional balls or CMOS signals are enabled, the interface balls are left unconnected with its associated power supply
(vdda/vssa) grounded.
For the corresponding setting of the PBIASLITEPWRDNZ0 bit, see the System Control Module / SCM Programming Model /
Extended-Drain I/Os and PBIAS Cells Programming Guide section of the AM/DM37x Multimedia Device Technical Reference Manual
(literature number SPRUGN4).
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 81
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2.4 Multiplexing Characteristics

provides a description of the multiplexing on the CBP, CBC, and CUS packages, respectively. Note: The following does not take into account subsystem pin multiplexing options. Subsystem pin
multiplexing options are described in Section 2.5, Signal Description. For more information, see the System Control Module / System Control Module Functional Description / Pad Functional Multiplexing and Configuration section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number
SPRUGN4).
CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE
Bottom Top Bottom Top
NA J2 NA D1 D7 sdrc_d0 NA J1 NA G1 C5 sdrc_d1 NA G2 NA G2 C6 sdrc_d2 NA G1 NA E1 B5 sdrc_d3 NA F2 NA D2 D9 sdrc_d4 NA F1 NA E2 D10 sdrc_d5 NA D2 NA B3 C7 sdrc_d6 NA D1 NA B4 B7 sdrc_d7 NA B13 NA A10 B11 sdrc_d8 NA A13 NA B11 C12 sdrc_d9 NA B14 NA A11 B12 sdrc_d10 NA A14 NA B12 D13 sdrc_d11 NA B16 NA A16 C13 sdrc_d12 NA A16 NA A17 B14 sdrc_d13 NA B19 NA B17 A14 sdrc_d14 NA A19 NA B18 B15 sdrc_d15 NA B3 NA B7 C9 sdrc_d16 NA A3 NA A5 E12 sdrc_d17 NA B5 NA B6 B8 sdrc_d18 NA A5 NA A6 B9 sdrc_d19 NA B8 NA A8 C10 sdrc_d20 NA A8 NA B9 B10 sdrc_d21 NA B9 NA A9 D12 sdrc_d22 NA A9 NA B10 E13 sdrc_d23 NA B21 NA C21 E15 sdrc_d24 NA A21 NA D20 D15 sdrc_d25 NA D22 NA B19 C15 sdrc_d26 NA D23 NA C20 B16 sdrc_d27 NA E22 NA D21 C16 sdrc_d28 NA E23 NA E20 D16 sdrc_d29 NA G22 NA E21 B17 sdrc_d30 NA G23 NA G21 B18 sdrc_d31 NA AB21 NA AA18 C18 sdrc_ba0 NA AC21 NA V20 D18 sdrc_ba1 NA N22 NA G20 A4 sdrc_a0 NA N23 NA K20 B4 sdrc_a1 NA P22 NA J20 D6 sdrc_a2 NA P23 NA J21 B3 sdrc_a3 NA R22 NA U21 B2 sdrc_a4 NA R23 NA R20 C3 sdrc_a5 NA T22 NA M21 E3 sdrc_a6 NA T23 NA M20 F6 sdrc_a7 NA U22 NA N20 E10 sdrc_a8 NA U23 NA K21 E9 sdrc_a9
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Table 2-4. Multiplexing Characteristics
7
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CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE
Bottom Top Bottom Top
NA V22 NA Y16 E7 sdrc_a10 NA V23 NA N21 G6 sdrc_a11 NA W22 NA R21 G7 sdrc_a12 NA W23 NA AA15 F7 sdrc_a13 NA Y22 NA Y12 F9 sdrc_a14 NA M22 NA T21 A19 sdrc_ncs0 NA M23 NA T20 B19 sdrc_ncs1 NA A11 NA A12 A10 sdrc_clk NA B11 NA B13 A11 sdrc_nclk NA J22 NA Y15 B20 sdrc_cke0 safe_mo
NA J23 NA Y13 C20 sdrc_cke1 safe_mo
NA L23 NA V21 D19 sdrc_nras NA L22 NA U20 C19 sdrc_ncas NA K23 NA Y18 A20 sdrc_nwe NA C1 NA H1 B6 sdrc_dm0 NA A17 NA A14 B13 sdrc_dm1 NA A6 NA A4 A7 sdrc_dm2 NA A20 NA A18 A16 sdrc_dm3 NA C2 NA C2 A5 sdrc_dqs0 NA B17 NA B15 A13 sdrc_dqs1 NA B6 NA B8 A8 sdrc_dqs2 NA B20 NA A19 A17 sdrc_dqs3 N4 AC15 J2 NA K4 gpmc_a1 gpio_34 safe_mo
M4 AB15 H1 NA K3 gpmc_a2 gpio_35 safe_mo
L4 AC16 H2 NA K2 gpmc_a3 gpio_36 safe_mo
K4 AB16 G2 NA J4 gpmc_a4 gpio_37 safe_mo
T3 AC17 F1 NA J3 gpmc_a5 gpio_38 safe_mo
R3 AB17 F2 NA J2 gpmc_a6 gpio_39 safe_mo
N3 AC18 E1 NA J1 gpmc_a7 gpio_40 safe_mo
M3 AB18 E2 NA H1 gpmc_a8 gpio_41 safe_mo
L3 AC19 D1 NA H2 gpmc_a9 sys_ndmareq gpio_42 safe_mo
K3 AB19 D2 NA G2 gpmc_a10 sys_ndmareq gpio_43 safe_mo
NA AC20 A4 NA NA gpmc_a11 safe_mo
K1 M2 AA2 U2 L2 gpmc_d0 L1 M1 AA1 U1 M1 gpmc_d1 L2 N2 AC2 V2 M2 gpmc_d2 P2 N1 AC1 V1 N2 gpmc_d3 T1 R2 AE5 AA3 M3 gpmc_d4 V1 R1 AD6 AA4 P1 gpmc_d5 V2 T2 AD5 Y3 P2 gpmc_d6 W2 T1 AC5 Y4 R1 gpmc_d7 H2 AB3 V1 R1 R2 gpmc_d8 gpio_44 safe_mo
K2 AC3 Y1 T1 T2 gpmc_d9 gpio_45 safe_mo
P1 AB4 T1 N1 U1 gpmc_d10 gpio_46 safe_mo
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
Table 2-4. Multiplexing Characteristics (continued)
7
de_out1
de_out1
de
de
de
de
de
de
de
de
2 de
3 de
de
de
de
de
Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 83
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CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE
Bottom Top Bottom Top
R1 AC4 U2 P2 R3 gpmc_d11 gpio_47 safe_mo
R2 AB6 U1 P1 T3 gpmc_d12 gpio_48 safe_mo
T2 AC6 P1 M1 U2 gpmc_d13 gpio_49 safe_mo
W1 AB7 L2 J2 V1 gpmc_d14 gpio_50 safe_mo
Y1 AC7 M2 K2 V2 gpmc_d15 gpio_51 safe_mo
G4 Y2 AD8 AA8 E2 gpmc_ncs0 H3 Y1 AD1 W1 NA gpmc_ncs1 gpio_52 safe_mo
V8 NA A3 NA NA gpmc_ncs2 gpio_53 safe_mo
U8 NA B6 NA D2 gpmc_ncs3 sys_ndmareq gpio_54 safe_mo
T8 NA B4 NA F4 gpmc_ncs4 sys_ndmareq mcbsp4_clkx gpt_9_pwm gpio_55 safe_mo
R8 NA C4 NA G5 gpmc_ncs5 sys_ndmareq mcbsp4_dr gpt_10_pw gpio_56 safe_mo
P8 NA B5 NA F3 gpmc_ncs6 sys_ndmareq mcbsp4_dx gpt_11_pw gpio_57 safe_mo
N8 NA C5 NA G4 gpmc_ncs7 gpmc_io_dir mcbsp4_fsx gpt_8_pwm gpio_58 safe_mo
T4 W2 N1 L1 W2 gpmc_clk gpio_59 safe_mo
F3 W1 AD10 AA9 F1 gpmc_nadv_a
G2 V2 N2 L2 F2 gpmc_noe F4 V1 M1 K1 G3 gpmc_nwe G3 AC12 K2 NA K5 gpmc_nbe0_c gpio_60 safe_mo
U3 NA J1 NA L1 gpmc_nbe1 gpio_61 safe_mo
H1 AB10 AC6 Y5 E1 gpmc_nwp gpio_62 safe_mo
M8 AB12 AC11 Y10 C1 gpmc_wait0 L8 AC10 AC8 Y8 NA gpmc_wait1 gpio_63 safe_mo
K8 NA B3 NA NA gpmc_wait2 uart4_tx gpio_64 safe_mo
J8 NA C6 NA C2 gpmc_wait3 sys_ndmareq uart4_rx
D28 NA G25 NA G22 dss_pclk gpio_66 hw_dbg12 safe_mo
D26 NA K24 NA E22 dss_hsync gpio_67 hw_dbg13 safe_mo
D27 NA M25 NA F22 dss_vsync gpio_68 safe_mo
E27 NA F26 NA J21 dss_acbias gpio_69 safe_mo
AG22 NA AE21 NA AC19 dss_data0 uart1_cts gpio_70 safe_mo
AH22 NA AE22 NA AB19 dss_data1 uart1_rts gpio_71 safe_mo
AG23 NA AE23 NA AD20 dss_data2 gpio_72 safe_mo
AH23 NA AE24 NA AC20 dss_data3 gpio_73 safe_mo
AG24 NA AD23 NA AD21 dss_data4 uart3_rx_irrx gpio_74 safe_mo
AH24 NA AD24 NA AC21 dss_data5 uart3_tx_irtx gpio_75 safe_mo
E26 NA G26 NA D24 dss_data6 uart1_tx gpio_76 hw_dbg14 safe_mo
Table 2-4. Multiplexing Characteristics (continued)
0 de
1 _evt de
2 m_evt de
3 m_evt de
_evt de
le
le de
(3)
1 de
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7
de
de
de
de
de
de
de
de
de
de
de
de
gpio_65 safe_mo
de
de
de
de
de
de
de
de
de
de
de
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CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE
Bottom Top Bottom Top
F28 NA H25 NA E23 dss_data7 uart1_rx gpio_77 hw_dbg15 safe_mo
F27 NA H26 NA E24 dss_data8 uart3_rx_irrx gpio_78 hw_dbg16 safe_mo
G26 NA J26 NA F23 dss_data9 uart3_tx_irtx gpio_79 hw_dbg17 safe_mo
AD28 NA AC26 NA AC22 dss_data10 gpio_80 safe_mo
AD27 NA AD26 NA AC23 dss_data11 gpio_81 safe_mo
AB28 NA AA25 NA AB22 dss_data12 gpio_82 safe_mo
AB27 NA Y25 NA Y22 dss_data13 gpio_83 safe_mo
AA28 NA AA26 NA W22 dss_data14 gpio_84 safe_mo
AA27 NA AB26 NA V22 dss_data15 gpio_85 safe_mo
G25 NA L25 NA J22 dss_data16 gpio_86 safe_mo
H27 NA L26 NA G23 dss_data17 gpio_87 safe_mo
H26 NA M24 NA G24 dss_data18 mcspi3_clk dss_data0 gpio_88 safe_mo
H25 NA M26 NA H23 dss_data19 mcspi3_simo dss_data1 gpio_89 safe_mo
E28 NA F25 NA D23 dss_data20 mcspi3_somi dss_data2 gpio_90 safe_mo
J26 NA N24 NA K22 dss_data21 mcspi3_cs0 dss_data3 gpio_91 safe_mo
AC27 NA AC25 NA V21 dss_data22 mcspi3_cs1 dss_data4 gpio_92 safe_mo
AC28 NA AB25 NA W21 dss_data23 dss_data5 gpio_93 safe_mo
W28 NA V26 NA AA23 cvideo2_out Y28 NA W26 NA AB24 cvideo1_out Y27 NA W25 NA AB23 cvideo1_vfb W27 NA U24 NA Y23 cvideo2_vfb W26 NA V23 NA Y24 cvideo1_rset A24 NA C23 NA A22 cam_hs gpio_94 hw_dbg0 safe_mo
A23 NA D23 NA E18 cam_vs gpio_95 hw_dbg1 safe_mo
C25 NA C25 NA B22 cam_xclka gpio_96 safe_mo
C27 NA C26 NA J19 cam_pclk gpio_97 hw_dbg2 safe_mo
C23 NA B23 NA H24 cam_fld cam_global_res gpio_98 hw_dbg3 safe_mo
AG17 NA AE16 NA AB18 cam_d0 gpio_99
AH17 NA AE15 NA AC18 cam_d1 gpio_100
B24 NA A24 NA G19 cam_d2 gpio_101 hw_dbg4 safe_mo
C24 NA B24 NA F19 cam_d3 gpio_102 hw_dbg5 safe_mo
D24 NA D24 NA G20 cam_d4 gpio_103 hw_dbg6 safe_mo
A25 NA C24 NA B21 cam_d5 gpio_104 hw_dbg7 safe_mo
K28 NA P25 NA L24 cam_d6 gpio_105
L28 NA P26 NA K24 cam_d7 gpio_106
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
Table 2-4. Multiplexing Characteristics (continued)
et de
7
de
de
de
de
de
de
de
de
de
de
de
de
de
de
de
de
de
de
de
de
de
(1)
(1)
(1)
(1)
safe_mo de
safe_mo de
de
de
de
de safe_mo
de safe_mo
de
Copyright © 2010, Texas Instruments Incorporated TERMINAL DESCRIPTION 85
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CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE
Bottom Top Bottom Top
K27 NA N25 NA J23 cam_d8 gpio_107
L27 NA N26 NA K23 cam_d9 gpio_108
B25 NA D25 NA F21 cam_d10 gpio_109 hw_dbg8 safe_mo
C26 NA E26 NA G21 cam_d11 gpio_110 hw_dbg9 safe_mo
B26 NA E25 NA C22 cam_xclkb gpio_111 safe_mo
B23 NA A23 NA F18 cam_wen cam_shutter gpio_167 hw_dbg10 safe_mo
D25 NA D26 NA J20 cam_strobe gpio_126 hw_dbg11 safe_mo
AG19 NA AD17 NA NA gpio_112
AH19 NA AD16 NA NA gpio_113
AG18 NA AE18 NA NA gpio_114
AH18 NA AE17 NA NA gpio_115
P21 NA U18 NA V20 mcbsp2_fsx gpio_116 safe_mo
N21 NA R18 NA T21 mcbsp2_clkx gpio_117 safe_mo
R21 NA T18 NA V19 mcbsp2_dr gpio_118 safe_mo
M21 NA R19 NA R20 mcbsp2_dx gpio_119 safe_mo
N28 NA N19 NA M23 mmc1_clk gpio_120
M27 NA L18 NA L23 mmc1_cmd gpio_121
N27 NA M19 NA M22 mmc1_dat0 gpio_122
N26 NA M18 NA M21 mmc1_dat1 gpio_123
N25 NA K18 NA M20 mmc1_dat2 gpio_124
P28 NA N20 NA N23 mmc1_dat3 gpio_125
P27 NA M20 NA N22 gpio_126
P26 NA P17 NA NA gpio_127
R27 NA P18 NA NA gpio_128
R25 NA P19 NA P24 gpio_129
AE2 NA W10 NA Y1 mmc2_clk mcspi3_clk gpio_130 safe_mo
AG5 NA R10 NA AB5 mmc2_cmd mcspi3_simo gpio_131 safe_mo
AH5 NA T10 NA AB3 mmc2_dat0 mcspi3_somi gpio_132 safe_mo
AH4 NA T9 NA Y3 mmc2_dat1 gpio_133 safe_mo
AG4 NA U10 NA W3 mmc2_dat2 mcspi3_cs1 gpio_134 safe_mo
AF4 NA U9 NA V3 mmc2_dat3 mcspi3_cs0 gpio_135 safe_mo
AE4 NA V10 NA AB2 mmc2_dat4 mmc2_dir_dat mmc3_dat0 gpio_136 safe_mo
AH3 NA M3 NA AA2 mmc2_dat5 mmc2_dir_dat cam_global_res mmc3_dat1 gpio_137 mm3_rxdp safe_mo
Table 2-4. Multiplexing Characteristics (continued)
0 de
1 et de
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7
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
safe_mo de
safe_mo de
de
de
de
de
de safe_mo
de safe_mo
de safe_mo
de safe_mo
de
de
de
de
de safe_mo
de safe_mo
de safe_mo
de safe_mo
de safe_mo
de safe_mo
de safe_mo
de safe_mo
de safe_mo
de safe_mo
de
de
de
de
de
de
de
86 TERMINAL DESCRIPTION Copyright © 2010, Texas Instruments Incorporated
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CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE
Bottom Top Bottom Top
AF3 NA L3 NA Y2 mmc2_dat6 mmc2_dir_cm cam_shutter mmc3_dat2 gpio_138 safe_mo
AE3 NA K3 NA AA1 mmc2_dat7 mmc2_clkin mmc3_dat3 gpio_139 mm3_rxdm safe_mo
AF6 NA P3 NA V6 mcbsp3_dx uart2_cts gpio_140 safe_mo
AE6 NA N3 NA V5 mcbsp3_dr uart2_rts gpio_141 safe_mo
AF5 NA U3 NA W4 mcbsp3_clkx uart2_tx gpio_142 safe_mo
AE5 NA W3 NA V4 mcbsp3_fsx uart2_rx gpio_143 safe_mo
AB26 NA Y24 NA NA uart2_cts mcbsp3_dx gpt_9_pwm_evt gpio_144 safe_mo
AB25 NA AA24 NA NA uart2_rts mcbsp3_dr gpt_10_pwm_e gpio_145 safe_mo
AA25 NA AD22 NA NA uart2_tx mcbsp3_clkx gpt_11_pwm_e gpio_146 safe_mo
AD25 NA AD21 NA NA uart2_rx mcbsp3_fsx gpt_8_pwm_evt gpio_147 safe_mo
AA8 NA L4 NA W7 uart1_tx gpio_148 safe_mo
AA9 NA R2 NA W6 uart1_rts gpio_149 safe_mo
W8 NA W2 NA AC2 uart1_cts gpio_150 safe_mo
Y8 NA H3 NA V7 uart1_rx mcbsp1_clkr mcspi4_clk gpio_151 safe_mo
AE1 NA V3 NA NA mcbsp4_clkx gpio_152 mm3_txse0 safe_mo
AD1 NA U4 NA NA mcbsp4_dr gpio_153 mm3_rxrcv safe_mo
AD2 NA R3 NA NA mcbsp4_dx gpio_154 mm3_txdat safe_mo
AC1 NA T3 NA NA mcbsp4_fsx gpio_155 mm3_txen_ safe_mo
Y21 NA U19 NA W19 mcbsp1_clkr mcspi4_clk gpio_156 safe_mo
AA21 NA V17 NA AB20 mcbsp1_fsr cam_global_res gpio_157 safe_mo
V21 NA U17 NA W18 mcbsp1_dx mcspi4_simo mcbsp3_dx gpio_158 safe_mo
U21 NA T20 NA Y18 mcbsp1_dr mcspi4_somi mcbsp3_dr gpio_159 safe_mo
T21 NA T19 NA AA18 mcbsp_clks cam_shutter gpio_160 uart1_cts safe_mo
K26 NA P20 NA AA19 mcbsp1_fsx mcspi4_cs0 mcbsp3_fsx gpio_161 safe_mo
W21 NA T17 NA V18 mcbsp1_clkx mcbsp3_clkx gpio_162 safe_mo
H18 NA F23 NA A23 uart3_cts_rctx gpio_163 safe_mo
H19 NA F24 NA B23 uart3_rts_sd gpio_164 safe_mo
H20 NA H24 NA B24 uart3_rx_irrx gpio_165 safe_mo
H21 NA G24 NA C23 uart3_tx_irtx gpio_166 safe_mo
T28 NA W19 NA R21 hsusb0_clk gpio_120 safe_mo
T25 NA U20 NA R23 hsusb0_stp gpio_121 safe_mo
R28 NA V19 NA P23 hsusb0_dir gpio_122 safe_mo
T26 NA W18 NA R22 hsusb0_nxt gpio_124 safe_mo
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
Table 2-4. Multiplexing Characteristics (continued)
7
d de
de
de
de
de
de
de
vt de
vt de
de
de
de
de
de
de
de
de
n de
de
et de
de
de
de
de
de
de
de
de
de
de
de
de
de
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CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE
Bottom Top Bottom Top
T27 NA V20 NA T24 hsusb0_data0 uart3_tx_irtx gpio_125 uart2_tx safe_mo
U28 NA Y20 NA T23 hsusb0_data1 uart3_rx_irrx gpio_130 uart2_rx safe_mo
U27 NA V18 NA U24 hsusb0_data2 uart3_rts_sd gpio_131 uart2_rts safe_mo
U26 NA W20 NA U23 hsusb0_data3 uart3_cts_rctx gpio_169 uart2_cts safe_mo
U25 NA W17 NA W24 hsusb0_data4 gpio_188 safe_mo
V28 NA Y18 NA V23 hsusb0_data5 gpio_189 safe_mo
V27 NA Y19 NA W23 hsusb0_data6 gpio_190 safe_mo
V26 NA Y17 NA T22 hsusb0_data7 gpio_191 safe_mo
K21 NA J25 NA K20 i2c1_scl J21 NA J24 NA K21 i2c1_sda AF15 NA C2 NA AC15 i2c2_scl gpio_168 safe_mo
AE15 NA C1 NA AC14 i2c2_sda gpio_183 safe_mo
AF14 NA AB4 NA AC13 i2c3_scl gpio_184 safe_mo
AG14 NA AC4 NA AC12 i2c3_sda gpio_185 safe_mo
AD26 NA AD15 NA Y16 i2c4_scl sys_nvmode1 safe_mo
AE26 NA W16 NA Y15 i2c4_sda sys_nvmode2 safe_mo
J25 NA J23 NA A24 hdq_sio sys_altclk i2c2_sccbe i2c3_sccbe gpio_170 safe_mo
AB3 NA P9 NA T5 mcspi1_clk mmc2_dat4 gpio_171 safe_mo
AB4 NA P8 NA R4 mcspi1_simo mmc2_dat5 gpio_172 safe_mo
AA4 NA P7 NA T4 mcspi1_somi mmc2_dat6 gpio_173 safe_mo
AC2 NA R7 NA T6 mcspi1_cs0 mmc2_dat7 gpio_174 safe_mo
AC3 NA R8 NA NA mcspi1_cs1 mmc3_cmd gpio_175 safe_mo
AB1 NA R9 NA NA mcspi1_cs2 mmc3_clk gpio_176 safe_mo
AB2 NA T8 NA R5 mcspi1_cs3 hsusb2_dat gpio_177 mm2_txdat safe_mo
AA3 NA W7 NA N5 mcspi2_clk hsusb2_dat gpio_178 safe_mo
Y2 NA W8 NA N4 mcspi2_simo gpt_9_pwm_e hsusb2_dat gpio_179 safe_mo
Y3 NA U8 NA N3 mcspi2_somi gpt_10_pwm_ hsusb2_dat gpio_180 safe_mo
Y4 NA V8 NA M5 mcspi2_cs0 gpt_11_pwm_ hsusb2_dat gpio_181 safe_mo
V3 NA V9 NA M4 mcspi2_cs1 gpt_8_pwm_e hsusb2_dat gpio_182 mm2_txen_ safe_mo
AE25 NA AE20 NA AA16 sys_32k AE17 NA AF19 NA AD15 sys_xtalin AF17 NA AF20 NA AD14 sys_xtalout AF25 NA W15 NA Y13 sys_clkreq gpio_1 safe_mo
AF26 NA V16 NA W16 sys_nirq gpio_0 safe_mo
AH25 NA V13 NA AA10 sys_nrespwro
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Table 2-4. Multiplexing Characteristics (continued)
7
de
de
de
de
de
de
de
de
de
de
de
de
de
de
de
de
de
de
de
de
de
a2 de
a7 de
vt a4 de
evt a5 de
evt a6 de
vt a3 n de
de
de
n
88 TERMINAL DESCRIPTION Copyright © 2010, Texas Instruments Incorporated
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CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE
Bottom Top Bottom Top
AF24 NA AD7 AA5 Y10 sys_nreswar gpio_30 safe_mo
AH26 NA F3 NA AB12 sys_boot0 dss_data18 gpio_2 safe_mo
AG26 NA D3 NA AC16 sys_boot1 dss_data19 gpio_3 safe_mo
AE14 NA C3 NA AD17 sys_boot2 gpio_4 safe_mo
AF18 NA E3 NA AD18 sys_boot3 dss_data20 gpio_5 safe_mo
AF19 NA E4 NA AC17 sys_boot4 mmc2_dir_dat dss_data21 gpio_6 safe_mo
AE21 NA G3 NA AB16 sys_boot5 mmc2_dir_dat dss_data22 gpio_7 safe_mo
AF21 NA D4 NA AA15 sys_boot6 dss_data23 gpio_8 safe_mo
AF22 NA V12 NA AD23 sys_off_mode gpio_9 safe_mo
AG25 NA AE14 NA Y7 sys_clkout1 gpio_10 safe_mo
AE22 NA W11 NA AA6 sys_clkout2 gpio_186 safe_mo
AA17 NA U15 NA AB7 jtag_ntrst AA13 NA V14 NA AB6 jtag_tck AA12 NA W13 NA AA7 jtag_rtck AA18 NA V15 NA AA9 jtag_tms_tms
AA20 NA U16 NA AB10 jtag_tdi AA19 NA Y13 NA AB9 jtag_tdo AA11 NA Y15 NA AC24 jtag_emu0 gpio_11 safe_mo
AA10 NA Y14 NA AD24 jtag_emu1 gpio_31 safe_mo
AF10 NA AB2 NA AC1 etk_clk mcbsp5_clkx mmc3_clk hsusb1_stp gpio_12 mm1_rxdp hw_dbg
AE10 NA AB3 NA AD3 etk_ctl mmc3_cmd hsusb1_clk gpio_13 hw_dbg
AF11 NA AC3 NA AD6 etk_d0 mcspi3_simo mmc3_dat4 hsusb1_dat gpio_14 mm1_rxrcv hw_dbg
AG12 NA AD4 NA AC6 etk_d1 mcspi3_somi hsusb1_dat gpio_15 mm1_txse0 hw_dbg
AH12 NA AD3 NA AC7 etk_d2 mcspi3_cs0 hsusb1_dat gpio_16 mm1_txdat hw_dbg
AE13 NA AA3 NA AD8 etk_d3 mcspi3_clk mmc3_dat3 hsusb1_dat gpio_17 hw_dbg
AE11 NA Y3 NA AC5 etk_d4 mcbsp5_dr mmc3_dat0 hsusb1_dat gpio_18 hw_dbg
AH9 NA AB1 NA AD2 etk_d5 mcbsp5_fsx mmc3_dat1 hsusb1_dat gpio_19 hw_dbg
AF13 NA AE3 NA AC8 etk_d6 mcbsp5_dx mmc3_dat2 hsusb1_dat gpio_20 hw_dbg
AH14 NA AD2 NA AD9 etk_d7 mcspi3_cs1 mmc3_dat7 hsusb1_dat gpio_21 mm1_txen_ hw_dbg
AF9 NA AA4 NA AC4 etk_d8 mmc3_dat6 hsusb1_dir gpio_22 hw_dbg
AG9 NA V2 NA AD5 etk_d9 mmc3_dat5 hsusb1_nxt gpio_23 mm1_rxdm hw_dbg
AE7 NA AE4 NA AC3 etk_d10 uart1_rx hsusb2_clk gpio_24 hw_dbg
AF7 NA AF6 NA AC9 etk_d11 hsusb2_stp gpio_25 mm2_rxdp hw_dbg
AG7 NA AE6 NA AC10 etk_d12 hsusb2_dir gpio_26 hw_dbg
AH7 NA AF7 NA AD11 etk_d13 hsusb2_nxt gpio_27 mm2_rxdm hw_dbg
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
Table 2-4. Multiplexing Characteristics (continued)
7
m de
de
de
de
de
2 de
3 de
de
de
de
de
c
de
de
0
1
a0 2
a1 3
a2 4
a7 5
a4 6
a5 7
a6 8
a3 n 9
10
11
12
13
14
15
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CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE
Bottom Top Bottom Top
AG8 NA AF9 NA AC11 etk_d14 hsusb2_dat gpio_28 mm2_rxrcv hw_dbg
AH8 NA AE9 NA AD12 etk_d15 hsusb2_dat gpio_29 mm2_txse0 hw_dbg
AC4, J4, H4, NA AC21, D15, NA F12, F13, vdd_core D8, AE9, D9, G11, G18, G12, G13, D15, Y16, H20, M7, H12, H13, AE18, Y18, M17, R20, T7, J17, J18, W18, K18, Y8, Y12 K17, K18, J18, AE19, K19, L14, Y19, U19, L15, M14, T19, N19, M15, R17, M19, J19, R18, R19, Y20, W20, T17, T18, V20, U20, T19, T20 P20, N20, K20, J20, D22, D23, AE24, M25, L25, E25
Y9, W9, T9, NA D13, G9, NA F10, G9, G10, vdd_mpu_iva R9, M9, L9, G12, H7, K11, H9, H10, J9, J9, Y10, U10, L9, M9, M10, J10, L11, L12, T10, R10, N7, N8, P10, M6, M7,M8, N10, M10, U7, U11, U13, M12, N6, N7, L10, J10, V7, V11, W9, N8,R6, R7, Y11, W11, Y9, Y11 R8, T7, T8, K11, J11, U12, U13, W12, K13, V12, V13, Y14, K14, W12, W13 J14, Y15, W15, J15
U4 NA D6 NA N21 cap_vdd_bb_
AA15 NA K14 NA Y12 cap_vddu_wk
K15 NA K13 NA G18 vdda_dplls_dll W16 NA U12 NA AA12 vdds_sram AD3, AD4, NA A18, AC7, A3,A15,B5,F2 M17, M18, vdds
W4, AF8, AC15, AC18, ,F21,L20,W21 M19, N17, AE8, AF16, AC24, AD20, N18, N19, AE16, AF23, AE10, C11, U10, V9, V10, AE23, F25, D9, E24, G4, W9, W10, Y9 F26, AG27 J15, J18, L7,
U1, J1, F1, AC5, P1, H1, NA NA E16, F15, vdds_mem J2, F2, R4, F23, E1, C23, F16, G15, B5, A5, AH6, A4, A7, A10, G16, H15, J6, B8, A8, B12, A15, A18 J7, J8, K6, A12, D16, K7, K8 C16, B18, A18, B22, A22, G28, C28
AA16 NA U14 NA U17 vdda_dpll_per AA14 NA W14 NA AA13 vdda_wkup_b
L24, M4, T4, T24, W24, Y4, AB24
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Table 2-4. Multiplexing Characteristics (continued)
7
a0 16
a1 17
mpu_iva
up_logic
g_bb
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CBP CBC CUS MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE
Bottom Top Bottom Top
AG2, U2, B2, B4, B7, B10, A6,A8, A13, A7, A13, B14, H11, H14, vss
AG3, W3, P3, B15, B18, AB5, AB22, C1, F1, F20, H16, J11,
J3, E3, A3, C22, E2, F22, AC10, AD14, H2, H20, L21, J12, J13, J14,
P4, E4, AG6, H2, P2,AB5, AD25, AE7, M2, P20, R2, J15, J16,
D7, C7, V9, AB14, AB20 B2, B25, C12, W20 Y6, Y11, K10, K11, U9, P9, N9, D7, D10, D12, AA7, AA16 K14, K15, L8,
K9, W10, D14, D18, L10, L13, V10, P10, D20, E22, G1, L17, M9, K10, D10, G8, G10, M10, M11,
C10, AF12, G20, G23, M13, M16, AE12, Y12, H4, K1, K15, N9, N10, N11,
K12, J12, K25, L10, N12, N13,
Y13, W13, L17, L23, N4, N14, N15,
J13, D13, N10, N17, R1, N16, P8, P10,
C13, W14, R4, R17, T23, P11, P12,
K16, J16, U25, W1, W4, P13, P14,
W17, K17, W23, Y7, P15, P17,
J17, W19, Y10, Y16, R10, R11,
V19, R19, Y26 R14, R15, T9,
P19, L19, T10, T11, K19, D19, T12, T13,
C19, AF20, T14, T15, AE20, T20, T16, U9, U11,
AG15, AF2, U14, U15,
AF27, B15, U16, V15,
J27, M2, M26, V16
N2, AA2,
AG10, AC25,
AC26, Y25,
W25, M20,
L20, L26,
G27, D21,
C22, B27, A26, R20,
R26 V25 NA V25 NA AB13 vdda_dac Y26 NA V24 NA AB15 vssa_dac K25 NA N23 NA N24 vdds_mmc1 P25 NA P23 NA H8 vdds_x AG21 NA AD19 NA NA vdds AH20 NA AE19 NA N20 cap_vddu_arr
AH21 NA AC19 NA NA vss AG16 NA AC16 NA NA vss AG20 NA AD18 NA NA vdds M28 NA L19 NA NA vss H28 NA L20 NA NA vdds V4 NA N9 NA U8 cap_vdd_sra
L21 NA K20 NA H17 cap_vdd_sra
Y17 NA AF23 NA W15 sys_xtalgnd
(1) This GPIO is only an input (and not an output). (2) The usage of this GPIO is strongly restricted. For more information, see the General-Purpose Interface chapter of the AM/DM37x
Multimedia Device Technical Reference Manual (literature number SPRUGN4).
(3) UART4 is only available on CBP and CBC packages.
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
Table 2-4. Multiplexing Characteristics (continued)
7
ay
m_mpu_iva
m_core
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2.5 Signal Description

Many signals are available on multiple pins according to the software configuration of the pin multiplexing options.
1. SIGNAL NAME: The signal name
2. DESCRIPTION: Description of the signal
3. TYPE: Type = Ball type for this specific function: – I = Input
– O = Output – Z = High-impedance – D = Open Drain – DS = Differential – A = Analog
4. BALL BOTTOM: Associated ball(s) bottom
5. BALL TOP: Associated ball(s) top
6. SUBSYSTEM PIN MULTIPLEXING: Contains a list of the pin multiplexing options at the module/subsystem level. The pin function is selected at the module/system level.
Note: The Subsystem Multiplexing Signals are not described in the following tables. For more information, see the System Control Module / System Control Module Functional Description / Pad Functional Multiplexing and Configuration section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).
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2.5.1 External Memory Interfaces

For more information, see Memory Subsystem / General-Purpose Memory Controller / GPMC Environment section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).
Table 2-5. External Memory Interfaces – GPMC Signals Description
SIGNAL NAME DESCRIPTION [2] TYPE BALL BALL BALL BOTTOM BALL TOP BALL SUBSYSTEM
[1] [3] BOTTOM TOP (CBC Pkg.) [4] (CBC Pkg.) [5] BOTTOM PIN
gpmc_a1 GPMC output address bit 1 / O N4 / K1 AC15 / M2 J2 / AA2 NA / U2 K4 / L2 - / gpmc_d0
extended multiplexed address gpmc_a17
gpmc_a2 GPMC output address bit 2 / O M4 / L1 AB15 / M1 H1 / AA1 NA / U1 K3 / M1 - / gpmc_d1
extended multiplexed address gpmc_a18
gpmc_a3 GPMC output address bit 3 / O L4 / L2 AC16 / N2 H2 / AC2 NA / V2 K2 / M2 - / gpmc_d2
extended multiplexed address gpmc_a19
gpmc_a4 GPMC output address bit 4 / O K4 / P2 AB16 / N1 G2 / AC1 NA / V1 J4 / N2 - / gpmc_d3
extended multiplexed address gpmc_a20
gpmc_a5 GPMC output address bit 5 / O T3 / T1 AC17 / R2 F1 / AE5 NA / AA3 J3 / M3 - / gpmc_d4
extended multiplexed address gpmc_a21
gpmc_a6 GPMC output address bit 6 / O R3 / V1 AB17 / R1 F2 / AD6 NA / AA4 J2/ P1 - / gpmc_d5
extended multiplexed address gpmc_a22
gpmc_a7 GPMC output address bit 7 / O N3 / V2 AC18 / T2 E1 / AD5 NA / Y3 J1/ P2 - / gpmc_d6
extended multiplexed address gpmc_a23
gpmc_a8 GPMC output address bit 8 / O M3 / W2 AB18 / T1 E2 / AC5 NA / Y4 H1/ R1 - / gpmc_d7
extended multiplexed address gpmc_a24
NOTE
(1)
(CBP (CBP (CUS MULTIPLEXING
Pkg.) [4] Pkg.) [5] Pkg.) [4] [6]
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Table 2-5. External Memory Interfaces – GPMC Signals Description
SIGNAL NAME DESCRIPTION [2] TYPE BALL BALL BALL BOTTOM BALL TOP BALL SUBSYSTEM
[1] [3] BOTTOM TOP (CBC Pkg.) [4] (CBC Pkg.) [5] BOTTOM PIN
gpmc_a9 GPMC output address bit 9 / O L3 / H2 AC19 / D1 / V1 NA / R1 H2/ R2 - / gpmc_d8
gpmc_a10 GPMC output address bit 10 / O K3 / K2 AB19 / D2 / Y1 T1 G2/ T2 - / gpmc_d9
gpmc_a11 GPMC output address bit 11 / O NC / P1 AC20 / A4 / T1 - / N1 NA - / gpmc_d10
gpmc_a12 General-purpose memory address O R1 AC4 U2 P2 R3 gpmc_d11
gpmc_a13 General-purpose memory address O R2 AB6 U1 P1 T3 gpmc_d12
gpmc_a14 General-purpose memory address O T2 AC6 P1 M1 U2 gpmc_d13
gpmc_a15 General-purpose memory address O W1 AB7 L2 J2 V1 gpmc_d14
gpmc_a16 General-purpose memory address O Y1 AC7 M2 K2 V2 gpmc_d15
gpmc_a17 General-purpose memory address O N4 AC15 J2 NA K4 gpmc_a1
gpmc_a18 General-purpose memory address O M4 AB15 H1 NA K3 gpmc_a2
gpmc_a19 General-purpose memory address O L4 AC16 H2 NA K2 gpmc_a3
gpmc_a20 General-purpose memory address O K4 AB16 G2 NA J4 gpmc_a4
gpmc_a21 General-purpose memory address O T3 AC17 F1 NA J3 gpmc_a5
gpmc_a22 General-purpose memory address O R3 AB17 F2 NA J2 gpmc_a6
gpmc_a23 General-purpose memory address O N3 AC18 E1 NA J1 gpmc_a7
gpmc_a24 General-purpose memory address O M3 AB18 E2 NA H1 gpmc_a8
gpmc_a25 General-purpose memory address O L3 AC19 D1 NA H2 gpmc_a9
gpmc_a26 General-purpose memory address O K3 AB19 D2 NA G2 gpmc_a10
gpmc_d0 GPMC data bit 0 / multiplexed IO K1 M2 AA2 U2 L2 gpmc_d0
gpmc_d1 GPMC data bit 1 / multiplexed IO L1 M1 AA1 U1 M1 gpmc_d1
gpmc_d2 GPMC data bit 2 / multiplexed IO L2 N2 AC2 V2 M2 gpmc_d2
gpmc_d3 GPMC data bit 3 / multiplexed IO P2 N1 AC1 V1 N2 gpmc_d3
gpmc_d4 GPMC data bit 4 / multiplexed IO T1 R2 AE5 AA3 M3 gpmc_d4
gpmc_d5 GPMC data bit 5 / multiplexed IO V1 R1 AD6 AA4 P1 gpmc_d5
gpmc_d6 GPMC data bit 6 / multiplexed IO V2 T2 AD5 Y3 P2 gpmc_d6
gpmc_d7 GPMC data bit 7 / multiplexed IO W2 T1 AC5 Y4 R1 gpmc_d7
gpmc_d8 GPMC data bit 8 / multiplexed IO H2 AB3 V1 R1 R2 gpmc_d8
gpmc_d9 GPMC data bit 9 / multiplexed IO K2 AC3 Y1 T1 T2 gpmc_d9
extended multiplexed address AB3 gpmc_a25
extended multiplexed address AC3 gpmc_a26
extended multiplexed address AB4 gpmc_a27
bit 12
bit 13
bit 14
bit 15
bit 16
bit 17
bit 18
bit 19
bit 20
bit 21
bit 22
bit 23
bit 24
bit 25
bit 26
address gpmc_a1
address gpmc_a2
address gpmc_a3
address gpmc_a4
address gpmc_a5
address gpmc_a6
address gpmc_a7
address gpmc_a8
address gpmc_a9
address gpmc_a10
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(1)
(continued)
(CBP (CBP (CUS MULTIPLEXING
Pkg.) [4] Pkg.) [5] Pkg.) [4] [6]
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Table 2-5. External Memory Interfaces – GPMC Signals Description
SIGNAL NAME DESCRIPTION [2] TYPE BALL BALL BALL BOTTOM BALL TOP BALL SUBSYSTEM
[1] [3] BOTTOM TOP (CBC Pkg.) [4] (CBC Pkg.) [5] BOTTOM PIN
gpmc_d10 GPMC data bit 10 / multiplexed IO P1 AB4 T1 N1 U1 gpmc_d10
gpmc_d11 GPMC data bit 11 / multiplexed IO R1 AC4 U2 P2 R3 gpmc_d11
gpmc_d12 GPMC data bit 12 / multiplexed IO R2 AB6 U1 P1 T3 gpmc_d12
gpmc_d13 GPMC data bit 13 / multiplexed IO T2 AC6 P1 M1 U2 gpmc_d13
gpmc_d14 GPMC data bit 14 / multiplexed IO W1 AB7 L2 J2 V1 gpmc_d14
gpmc_d15 GPMC data bit 15 / multiplexed IO Y1 AC7 M2 K2 V2 gpmc_d15
gpmc_ncs0 GPMC Chip Select bit 0 O G4 Y2 AD8 AA8 E2 NA gpmc_ncs1 GPMC Chip Select bit 1 O H3 Y1 AD1 W1 NA NA gpmc_ncs2 GPMC Chip Select bit 2 O V8 NA A3 NA NA NA gpmc_ncs3 GPMC Chip Select bit 3 O U8 NA B6 NA D2 NA gpmc_ncs4 GPMC Chip Select bit 4 O T8 NA B4 NA F4 NA gpmc_ncs5 GPMC Chip Select bit 5 O R8 NA C4 NA G5 NA gpmc_ncs6 GPMC Chip Select bit 6 O P8 NA B5 NA F3 NA gpmc_ncs7 GPMC Chip Select bit 7 O N8 NA C5 NA G4 NA gpmc_io_dir GPMC IO direction control for use O N8 NA C5 NA G4 gpmc_ncs7
gpmc_clk GPMC clock O T4 W2 N1 L1 W2 NA gpmc_nadv_ale Address Valid or Address Latch O F3 W1 AD10 AA9 F1 NA
gpmc_noe Output Enable O G2 V2 N2 L2 F2 NA gpmc_nwe Write Enable O F4 V1 M1 K1 G3 NA gpmc_nbe0_cle Lower Byte Enable. Also used for O G3 AC12 K2 NA K5 NA
gpmc_nbe1 Upper Byte Enable O U3 NA J1 NA L1 NA gpmc_nwp Flash Write Protect O H1 AB10 AC6 Y5 E1 NA gpmc_wait0 External indication of wait I M8 AB12 AC11 Y10 C1 NA gpmc_wait1 External indication of wait I L8 AC10 AC8 Y8 NA NA gpmc_wait2 External indication of wait I K8 NA B3 NA NA NA gpmc_wait3 External indication of wait I J8 NA C6 NA C2 NA
(1) NA in table stands for "Not Applicable".
address gpmc_a11
address gpmc_a12
address gpmc_a13
address gpmc_a14
address gpmc_a15
address gpmc_a16
with external transceivers
Enable
Command Latch Enable
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(1)
(continued)
(CBP (CBP (CUS MULTIPLEXING
Pkg.) [4] Pkg.) [5] Pkg.) [4] [6]
NOTE
For more information, see Memory Subsystem / SDRAM Controller (SDRC) Subsystem / SDRC Subsystem Environment section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).
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Table 2-6. External Memory Interfaces – SDRC Signals Description
SIGNAL DESCRIPTION TYPE
NAME BOTTOM (CBP Pkg.) (CBC Pkg.) (CBC Pkg.) (CUS Pkg.)
sdrc_d0 SDRAM data bit 0 IO NA J2 NA D1 D7 sdrc_d1 SDRAM data bit 1 IO NA J1 NA G1 C5 sdrc_d2 SDRAM data bit 2 IO NA G2 NA G2 C6 sdrc_d3 SDRAM data bit 3 IO NA G1 NA E1 B5 sdrc_d4 SDRAM data bit 4 IO NA F2 NA D2 D9 sdrc_d5 SDRAM data bit 5 IO NA F1 NA E2 D10 sdrc_d6 SDRAM data bit 6 IO NA D2 NA B3 C7 sdrc_d7 SDRAM data bit 7 IO NA D1 NA B4 B7 sdrc_d8 SDRAM data bit 8 IO NA B13 NA A10 B11 sdrc_d9 SDRAM data bit 9 IO NA A13 NA B11 C12 sdrc_d10 SDRAM data bit 10 IO NA B14 NA A11 B12 sdrc_d11 SDRAM data bit 11 IO NA A14 NA B12 D13 sdrc_d12 SDRAM data bit 12 IO NA B16 NA A16 C13 sdrc_d13 SDRAM data bit 13 IO NA A16 NA A17 B14 sdrc_d14 SDRAM data bit 14 IO NA B19 NA B17 A14 sdrc_d15 SDRAM data bit 15 IO NA A19 NA B18 B15 sdrc_d16 SDRAM data bit 16 IO NA B3 NA B7 C9 sdrc_d17 SDRAM data bit 17 IO NA A3 NA A5 E12 sdrc_d18 SDRAM data bit 18 IO NA B5 NA B6 B8 sdrc_d19 SDRAM data bit 19 IO NA A5 NA A6 B9 sdrc_d20 SDRAM data bit 20 IO NA B8 NA A8 C10 sdrc_d21 SDRAM data bit 21 IO NA A8 NA B9 B10 sdrc_d22 SDRAM data bit 22 IO NA B9 NA A9 D12 sdrc_d23 SDRAM data bit 23 IO NA A9 NA B10 E13 sdrc_d24 SDRAM data bit 24 IO NA B21 NA C21 E15 sdrc_d25 SDRAM data bit 25 IO NA A21 NA D20 D15 sdrc_d26 SDRAM data bit 26 IO NA D22 NA B19 C15 sdrc_d27 SDRAM data bit 27 IO NA D23 NA C20 B16 sdrc_d28 SDRAM data bit 28 IO NA E22 NA D21 C16 sdrc_d29 SDRAM data bit 29 IO NA E23 NA E20 D16 sdrc_d30 SDRAM data bit 30 IO NA G22 NA E21 B17 sdrc_d31 SDRAM data bit 31 IO NA G23 NA G21 B18 sdrc_ba0 SDRAM bank select 0 O NA AB21 NA AA18 C18 sdrc_ba1 SDRAM bank select 1 O NA AC21 NA V20 D18 sdrc_a0 SDRAM address bit 0 O NA N22 NA G20 A4 sdrc_a1 SDRAM address bit 1 O NA N23 NA K20 B4 sdrc_a2 SDRAM address bit 2 O NA P22 NA J20 D6 sdrc_a3 SDRAM address bit 3 O NA P23 NA J21 B3 sdrc_a4 SDRAM address bit 4 O NA R22 NA U21 B2 sdrc_a5 SDRAM address bit 5 O NA R23 NA R20 C3 sdrc_a6 SDRAM address bit 6 O NA T22 NA M21 E3 sdrc_a7 SDRAM address bit 7 O NA T23 NA M20 F6 sdrc_a8 SDRAM address bit 8 O NA U22 NA N20 E10 sdrc_a9 SDRAM address bit 9 O NA U23 NA K21 E9 sdrc_a10 SDRAM address bit 10 O NA V22 NA Y16 E7 sdrc_a11 SDRAM address bit 11 O NA V23 NA N21 G6 sdrc_a12 SDRAM address bit 12 O NA W22 NA R21 G7 sdrc_a13 SDRAM address bit 13 O NA W23 NA AA15 F7 sdrc_a14 SDRAM address bit 14 O NA Y22 NA Y12 F9 sdrc_ncs0 Chip select 0 O NA M22 NA T21 A19
SPRS685A–AUGUST 2010–REVISED SEPTEMBER 2010
(1)
(2)
BALL BALL TOP BALL BOTTOM BALL TOP BALL BOTTOM
(CBP Pkg.)
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Table 2-6. External Memory Interfaces – SDRC Signals Description
SIGNAL DESCRIPTION TYPE
NAME BOTTOM (CBP Pkg.) (CBC Pkg.) (CBC Pkg.) (CUS Pkg.)
sdrc_ncs1 Chip select 1 O NA M23 NA T20 B19 sdrc_clk Clock IO NA A11 NA A12 A10 sdrc_nclk Clock Invert O NA B11 NA B13 A11 sdrc_cke0 Clock Enable 0 O NA J22 NA Y15 B20 sdrc_cke1 Clock Enable 1 O NA J23 NA Y13 C20 sdrc_nras SDRAM Row Access O NA L23 NA V21 D19 sdrc_ncas SDRAM column O NA L22 NA U20 C19
address strobe sdrc_nwe SDRAM write enable O NA K23 NA Y18 A20 sdrc_dm 0 Data Mask 0 O NA C1 NA H1 B6 sdrc_ dm1 Data Mask 1 O NA A17 NA A14 B13 sdrc_ dm2 Data Mask 2 O NA A6 NA A4 A7 sdrc_dm 3 Data Mask 3 O NA A20 NA A18 A16 sdrc_dqs0 Data Strobe 0 IO NA B17 NA C2 A5 sdrc_dqs1 Data Strobe 1 IO NA NA NA B15 A13 sdrc_dqs2 Data Strobe 2 IO NA NA NA B8 A8 sdrc_dqs3 Data Strobe 3 IO NA B20 NA A19 A17
(2)
BALL BALL TOP BALL BOTTOM BALL TOP BALL BOTTOM
(CBP Pkg.)
(1)
(continued)
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(1) NA in this table stands for "Not Applicable". (2) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog). (3) For a list of pins not supported on a particular package, see
Table 2-4
.
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2.5.2 Video Interfaces

Table 2-7. Video Interfaces – CAM Signals Description
SIGNAL NAME DESCRIPTION TYPE
cam_hs Camera Horizontal Synchronization IO A24 C23 A22 cam_vs Camera Vertical Synchronization IO A23 D23 E18 cam_xclka Camera Clock Output a O C25 C25 B22 cam_xclkb Camera Clock Output b O B26 E25 C22 cam_d0 Camera digital image data bit 0 I AG17 AE16 AB18 cam_d1 Camera digital image data bit 1 I AH17 AE15 AC18 cam_d2 Camera digital image data bit 2 I B24 A24 G19 cam_d3 Camera digital image data bit 3 I C24 B24 F19 cam_d4 Camera digital image data bit 4 I D24 D24 G20 cam_d5 Camera digital image data bit 5 I A25 C24 B21 cam_d6 Camera digital image data bit 6 I K28 P25 L24 cam_d7 Camera digital image data bit 7 I L28 P26 K24 cam_d8 Camera digital image data bit 8 I K27 N25 J23 cam_d9 Camera digital image data bit 9 I L27 N26 K23 cam_d10 Camera digital image data bit 10 I B25 D25 F21 cam_d11 Camera digital image data bit 11 I C26 E26 G21 cam_fld Camera field identification IO C23 B23 H24 cam_pclk Camera pixel clock I C27 C26 J19 cam_wen Camera Write Enable I B23 A23 F18 cam_strobe Flash strobe control signal O D25 D26 J20 cam_global_reset Global reset is used strobe IO C23 / AH3 / AA21 B23/M3/V17 H24/ AA2/ AB20
synchronization
cam_shutter Mechanical shutter control signal O B23 / AF3 / T21 A23 / T19/ L3 F18/ Y2/ AA18
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog).
(1)
BALL BOTTOM BALL BOTTOM BALL BOTTOM
(CBP Pkg.) (CBC Pkg.) (CUS Pkg.)
For more information, see Display Subsystem / Display Subsystem Environment section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number
SPRUGN4).
Table 2-8. Video Interfaces – DSS Signals Description
SIGNAL NAME DESCRIPTION TYPE
dss_pclk LCD Pixel Clock O D28 G25 G22 dss_hsync LCD Horizontal Synchronization O D26 K24 E22 dss_vsync LCD Vertical Synchronization O D27 M25 F22 dss_acbias AC bias control (STN) or pixel data enable (TFT) output O E27 F26 J21 dss_data0 LCD Pixel Data bit 0 O AG22 / H26 AE21 / M24 AC19 / G24 dss_data1 LCD Pixel Data bit 1 O AH22 / H25 AE22 / M26 AB19 / H23 dss_data2 LCD Pixel Data bit 2 O AG23 / E28 AE23 / F25 AD20 / D23 dss_data3 LCD Pixel Data bit 3 O AH23 / J26 AE24 / N24 AC20 / K22 dss_data4 LCD Pixel Data bit 4 O AG24 / AC27 AD23 / AC25 AD21 / V21 dss_data5 LCD Pixel Data bit 5 O AH24 / AC28 AD24 / AB25 AC21 / W21 dss_data6 LCD Pixel Data bit 6 O E26 G26 D24 dss_data7 LCD Pixel Data bit 7 O F28 H25 E23 dss_data8 LCD Pixel Data bit 8 O F27 H26 E24
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog).
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NOTE
(1)
BALL BOTTOM BALL BOTTOM BALL BOTTOM
(CBP Pkg.) (CBC Pkg.) (CUS Pkg.)
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Table 2-8. Video Interfaces – DSS Signals Description (continued)
SIGNAL NAME DESCRIPTION TYPE
dss_data9 LCD Pixel Data bit 9 O G26 J26 F23 dss_data10 LCD Pixel Data bit 10 O AD28 AC26 AC22 dss_data11 LCD Pixel Data bit 11 O AD27 AD26 AC23 dss_data12 LCD Pixel Data bit 12 O AB28 AA25 AB22 dss_data13 LCD Pixel Data bit 13 O AB27 Y25 Y22 dss_data14 LCD Pixel Data bit 14 O AA28 AA26 W22 dss_data15 LCD Pixel Data bit 15 O AA27 AB26 V22 dss_data16 LCD Pixel Data bit 16 O G25 L25 J22 dss_data17 LCD Pixel Data bit 17 O H27 L26 G23 dss_data18 LCD Pixel Data bit 18 O H26 / AH26 M24 / F3 G24 / AB12 dss_data19 LCD Pixel Data bit 19 O H25 / AG26 M26 / D3 H23 / AC16 dss_data20 LCD Pixel Data bit 20 O E28 / AF18 F25 / E3 D23 / AD18 dss_data21 LCD Pixel Data bit 21 O J26 / AF19 N24 / E4 K22 / AC17 dss_data22 LCD Pixel Data bit 22 O AC27 / AE21 AC25 / G23 V21 / AB16 dss_data23 LCD Pixel Data bit 23 O AC28 / AF21 AB25 / D4 W21 / AA15
SIGNAL DESCRIPTION TYPE
NAME (CBP Pkg.) (CBC Pkg.) (CUS Pkg.) MULTIPLEXING
rfbi_a0 RFBI command/data control O E27 F26 J21 dss_acbias rfbi_cs0 1st LCD chip select O D26 K24 E22 dss_hsync rfbi_da0 RFBI data bus 0 IO AG22 / H26 AE21 / M24 AC19 / G24 dss_data0 rfbi_da1 RFBI data bus 1 IO AH22 / H25 AE22 / M26 AB19 / H23 dss_data1 rfbi_da2 RFBI data bus 2 IO AG23 / E28 AE23 / F25 AD20 / D23 dss_data2 rfbi_da3 RFBI data bus 3 IO AH23 / J26 AE24 / N24 AC20 / K22 dss_data3 rfbi_da4 RFBI data bus 4 IO AG24 / AC27 AD23 / AC25 AD21 / V21 dss_data4 rfbi_da5 RFBI data bus 5 IO AH24 / AC28 AD24 / AB25 AC21 / W21 dss_data5 rfbi_da6 RFBI data bus 6 IO E26 G26 D24 dss_data6 rfbi_da7 RFBI data bus 7 IO F28 H25 E23 dss_data7 rfbi_da8 RFBI data bus 8 IO F27 H26 E24 dss_data8 rfbi_da9 RFBI data bus 9 IO G26 J26 F23 dss_data9 rfbi_da10 RFBI data bus 10 IO AD28 AC26 AC22 dss_data10 rfbi_da11 RFBI data bus 11 IO AD27 AD26 AC23 dss_data11 rfbi_da12 RFBI data bus 12 IO AB28 AA25 AB22 dss_data12 rfbi_da13 RFBI data bus 13 IO AB27 Y25 Y22 dss_data13 rfbi_da14 RFBI data bus 14 IO AA28 AA26 W22 dss_data14 rfbi_da15 RFBI data bus 15 IO AA27 AB26 V22 dss_data15 rfbi_rd Read enable for RFBI O D28 G25 G22 dss_pclk rfbi_wr Write Enable for RFBI O D27 M25 F22 dss_vsync rfbi_te_vsync tearing effect removal and Vsync input I G25 L25 J22 dss_data16
0 from 1st LCD rfbi_hsync0 Hsync for 1st LCD I H27 L26 G23 dss_data17 rfbi_te_vsync tearing effect removal and Vsync input I H26 / AH26 M24 / F3 G24 / AB12 dss_data18
1 from 2nd LCD rfbi_hsync1 Hsync for 2nd LCD I H25 / AG26 M26 / D3 H23 / AC16 dss_data19 rfbi_cs1 2nd LCD chip select O E28 / AF18 F25 / E3 D23 / AD18 dss_data20
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog). (2) The subsystem pin multiplexing options are not described in Table 2-1 and Table 2-4.
(1)
BALL BOTTOM BALL BOTTOM BALL BOTTOM
(CBP Pkg.) (CBC Pkg.) (CUS Pkg.)
Table 2-9. Video Interfaces – RFBI Signals Description
(1)
BALL BOTTOM BALL BOTTOM BALL BOTTOM SUBSYSTEM PIN
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(2)
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Table 2-10. Video Interfaces – TV Signals Description
SIGNAL NAME DESCRIPTION TYPE
cvideo1_out TV analog output Composite: AO Y28 W26 AB24
cvideo1_out
cvideo2_out TV analog output S-VIDEO: cvideo2_out AO W28 V26 AA23
cvideo1_vfb cvideo1_vfb: Feedback through external AO Y27 W25 AB23
resistor to composite
cvideo2_vfb cvideo2_vfb: Feedback through external AO W27 U24 Y23
resistor to S-VIDEO
cvideo1_rset cvideo1 input reference current resistor AIO W26 V23 Y24
setting
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog).
(1)
BALL BOTTOM BALL BOTTOM BALL BOTTOM
(CBP Pkg.) (CBC Pkg.) (CUS Pkg.)
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2.5.3 Serial Communication Interfaces

For more information, see HDQ/1-Wire / HDQ/1-Wire Environment section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).
Table 2-11. Serial Communication Interfaces – HDQ/1-Wire Signals Description
SIGNAL DESCRIPTION TYPE
NAME (CBP Pkg.) (CBC Pkg.) (CUS Pkg.)
hdq_sio Bidirectional HDQ 1-Wire control and data IOD J25 J23 A24
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog).
SIGNAL NAME DESCRIPTION TYPE
INTER-INTEGRATED CIRCUIT INTERFACE (I2C1)
i2c1_scl OD K21 J25 K20
i2c1_sda IOD J21 J24 K21
INTER-INTEGRATED CIRCUIT INTERFACE (I2C3)
i2c3_scl OD AF14 AB4 AC13
i2c3_sda IOD AG14 AC4 AC12
i2c3_sccbe Serial Camera Control Bus Enable OD J25 J23 A24
INTER-INTEGRATED CIRCUIT INTERFACE (I2C2)
i2c2_scl OD AF15 C2 AC15
i2c2_sda IOD AE15 C1 AC14
i2c2_sccbe Serial Camera Control Bus Enable OD J25 J23 A24
(1) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog).
Interface. Output is open drain.
For more information, see Multimaster High-Speed I2C Controller / HS I2C Environment section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).
Table 2-12. Serial Communication Interfaces – I2C Signals Description
I2C Master Serial clock. Output is open drain.
I2C Serial Bidirectional Data. Output is open drain.
I2C Master Serial clock. Output is open drain.
I2C Serial Bidirectional Data. Output is open drain.
I2C Master Serial clock. Output is open drain.
I2C Serial Bidirectional Data. Output is open drain.
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(1)
(1)
BALL BOTTOM BALL BOTTOM BALL BOTTOM
BALL BOTTOM BALL BOTTOM BALL BOTTOM
(CBP Pkg.) (CBC Pkg.) (CUS Pkg.)
For more information, see Power Reset and Clock Management / PRCM Introduction to Power Management / SmartReflex Voltage-Control Overview section of the AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).
Table 2-13. Serial Communication Interfaces – SmartReflex Signals Description
SIGNAL NAME DESCRIPTION TYPE
INTER-INTEGRATED CIRCUIT INTERFACE (I2C4)
i2c4_scl OD AD26 AD15 Y16
i2c4_sda IOD AE26 W16 Y15
I2C Master Serial clock. Output is open drain.
I2C Serial Bidirectional Data. Output is open drain.
(1) For more information on SmartReflex voltage control, see the PRCM chapter of the AM/DM37x Multimedia Device Technical Reference
Manual (literature number SPRUGN4).
(2) Type = Ball type for this specific function (I = Input, O = Output, Z = High-impedance, D = Open Drain, DS = Differential, A = Analog).
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(2)
BALL BOTTOM BALL BOTTOM BALL BOTTOM
(CBP Pkg.) (CBC Pkg.) (CUS Pkg.)
(1)
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