DEMĆDAI3010
User’s Guide
April 2003 DAV Digital Audio/Speaker
SLEU036
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty . Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. T o minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party , or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EV ALUA TION
PURPOSES ONL Y and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED,
IMPLIED, OR ST ATUT ORY, INCLUDING ANY WARRANTY OF MERCHANT ABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER P ARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any
machine, process, or combination in which such TI products or services might be or are used.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of ±15 V and the output
voltage range of ±15 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
55°C. The EVM is designed to operate properly with certain components above 55°C as long
as the input and output ranges are maintained. These components include but are not limited
to linear regulators, switching transistors, pass transistors, and current sense resistors. These
types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
When placing measurement probes near these devices during operation, please be aware
that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
Contents
Contents
1 Description 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Block Diagram 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Use of the DEM-DAI3010 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1 Initial Settings of the DEM-DAI3010 (at shipping) 1-3. . . . . . . . . . . . . . . . . . . . . . . .
1.2.2 How to Connect Power Supplies to the DEM-DAI3010 1-3. . . . . . . . . . . . . . . . . . .
1.3 Settings and Connections for Basic Operation 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Setting Functions 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.1 Function Setting Switches and Header Pins 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4.2 Detailed Explanation of Function Setting Switches and Header Pins 1-6. . . . . . . .
2 Printed-Circuit Board and Schematic 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 DEM-DAI3010 Printed-Circuit Board 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 DEM-DAI3010 Schematics 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures
1–1 DEM-DAI3010 Block DIagram 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–1 DEM-DAI3010 Silkscreen 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 DEM-DAI3010—Top View 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 DEM-DAI3010—Bottom View 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 DEM-DAI3010 Analog Section 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 DEM-DAI3010 Regulator , Connector and Ext.-I/F 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 DEM-DAI3010 Digital Section (Digital Audio Interface) 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
1–1 Initial Settings of the DEM-DAI3010 at Shipping 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1–2 Power Supply Terminals and Supply Voltage (Depending on CN057 Setting) 1-3. . . . . . . . . .
1–3 Switches and Header Pins of the DEM-DAI3010 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
Contents
vi
Chapter 1
Description
The DEM-DAI3010 is an evaluation board for the PCM3010 (24-bit, 96-kHz
ADC and 192-kHz DAC, stereo codec). This board includes not only the
PCM3010 but also analog I/O terminals, analog filter circuits, and an S/PDIF
digital I/O circuit that is useful for codec evaluation. S/PDIF I/O circuits consist
of a 24-bit/96-kHz digital audio interface receiver (DIR1703) and a digital audio
interface transmitter (DIT4096), and include optical (TOSLINK) and coaxial
S/PDIF digital I/O connectors. Removing shorting plugs from the pins of a
header breaks the connection between the S/PDIF I/O circuits and the
PCM3010for easier PCM3010 device evaluation.
Topic Page
1.1 Block Diagram 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Use of the DEM-DAI3010 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Settings and Connections for Basic Operation 1-4. . . . . . . . . . . . . . . . . .
1.4 Setting Functions 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1
Block Diagram
1.1 Block Diagram
Figure 1–1.DEM-DAI3010 Block DIagram
System Clock
Data Format
Clock Mode
X’tal Frequency
System Clock
S/PDIF Input
OPT. IN
COAX. IN
S/PDIF Output
OPT. OUT
COAX. OUT
SW003
SW001
24.576 MHz
SW051
SW005 SW006
System Clock
Data Format
SW004
DIR1703
DIT4096
Channel Status System Clock
74HCT244
JP107
JP001
PCM3010
(Slave Only)
SW101
Data Format
Power Down
JP105
JP106
DAC Output
L-ch Output
LPF
R-ch Output
LPF
ADC Input
L-ch 1Vrms
L-ch 2Vrms
LPF
R-ch 1Vrms
R-ch 2Vrms
LPF
±15 V
5 V
3.3 V
3.3 V
CN057
LPF Circuits
PCM3010 VCC and DIR1703, DIT4096, TOSLINK
PCM3010 V
DD
1-2
Use of the DEM-DAI3010
1.2 Use of the DEM-DAI3010
The DEM-DAI3010 is shipped with standard settings preset. Therefore,
connecting power supplies (15-V, –15-V and 5-V) is the only requirement to
prepare the board for use, unless nonstandard settings are desired.
1.2.1 Initial Settings of the DEM-DAI3010 (at shipping)
Table 1–1.Initial Settings of the DEM-DAI3010 at Shipping
Item Initial Setting (at shipping)
Power supply voltage 15 V, –15 V, and 5 V (close CN57)
Power supply terminals CN51–CN55 (open CN56)
Connection of PCM3010 and S/PDIF I/O DIR1703 and DIT4096 connected with JP107
DIR1703 system clock (SCK) 256 f
DIR1703 output audio data format I2S
DIR1703 crystal clock frequency 24.576 MHz (load capacitance: 18 pF)
DIT4096 system clock (SCLK) 256 f
DIT4096 input audio data format I2S
PCM3010 system clock Automatic selection (no setting required)
PCM3010 I/O audio data format I2S
PCM3010 power-down function Disabled
PCM3010 de-emphasis function (DAC) Disabled
PCM3010 DAC cutoff frequency 54 kHz (JP101–JP104 are closed)
PCM3010 ADC input terminal selection CN101, CN102: 2-V rms input (with LPF)
S
S
1.2.2 How to Connect Power Supplies to the DEM-DAI3010
The DEM-DAI3010 requires 5-V, 15-V, and –15-V power supplies. Power is
supplied to this board by five binding posts (one each for V
= +15 V , –AV
(3.3 V) for the PCM3010 is normally generated by an onboard
V
DD
= –15 V , and two for ground) from stabilized dc power supplies.
CC
= +5 V , +AV
CC
voltage-regulator IC from VCC (5 V), but it is possible to supply 3.3 V directly .
To do so, open CN057, then supply 3.3 V to CN056 and 5 V to CN054. If 3.3
V is supplied externally , 5 V must still be provided to CN054 in order to supply
the analog section of the PCM3010. T o avoid latch-up of the PCM3010, ensure
that V
and VDD are powered up simultaneously.
CC
Table 1–2.Power Supply Terminals and Supply Voltage (Depending on CN057 Setting)
Power Terminal CN057 Closed (Default) CN057 Open
CN051 (orange) 15 V 15 V
CN052 (green) 0 V (ground) 0 V (ground)
CN053 (blue) –15 V –15 V
CN054 (red) 5 V 5 V
CN055 (black) 0 V (ground) 0 V (ground)
CN056 (2-pin connector) Open (no connection) 3.3 V
CC
Description
1-3
Settings and Connections for Basic Operation
1.3 Settings and Connections for Basic Operation
The PCM3010 is an LSI codec containing an ADC and a DAC. Connections
and settings depend on the evaluation object (ADC or DAC), and the setup
should be checked carefully . Following are example settings for three typical
evaluation situations. Note that when using S/PDIF I/O, the optical and coaxial
input corresponds to f
When the DAC section of PCM3010 is evaluated with S/PDIF input signal (the
PCM3010 operates as a slave of the DIR1703 PLL clock)
- Close all pins of JP107 with shorting plugs.
- Input an S/PDIF signal into the optical (U053) or coaxial (CN059)
connector.
- CN105 (L-ch) and CN106 (R-ch) are the analog signal outputs.
- Choose an S/PDIF input terminal (optical/coaxial) with the S/PDIF input
switch (SW051).
- Set the clock-mode switch (SW004) to PLL or Auto.
- The cutoff frequency of the LPF can be changed by JP101, JP102, JP103,
and JP104. All these jumpers are shorted at the time of shipment, which
sets the cutoff frequency to 20 kHz.
= 96 kHz.
S
When the ADC section of PCM3010 is evaluated with S/PDIF output signal (the
PCM3010 operates as a slave of the DIR1703 crystal clock)
- Short all pins of JP107 with shorting plugs.
- Connect an analog signal to CN101/CN102 using an LPF, or to CN103/
CN104 using only a coupling capacitor without an LPF.
- Select the analog input terminal by changing by the settings of JP105 and
JP106. (Setup at the time of shipment is for CN101 and CN102.)
- A Toslink (U052) and a pin jack (CN058) are the S/PDIF digital output
terminals. Select the digital output connector by setting the S/PDIF output
switch (SW051). Simultaneous use of optical and coaxial outputs is
impossible.
- Set the clock mode switch (SW004) to X’tal. The X’tal mode of DIR1703
is used as a master clock for the ADC and DIT.
- Set up the channel status data using SW006.
- Because system clock frequency is 256 f
= 96 kHz. T o operate the ADC section at a different fS, the crystal (X001)
f
S
, the ADC section operates at
S
connected to DIR1703 must be changed. The system clock setup can be
changed if required. The load capacitance used with the crystal is
dependent on the crystal properties. Therefore, when the crystal is
changed, the capacitance of C006 and C007 must be selected to match
the crystal specification.
1-4
When S/PDIF I/O is not used (the PCM3010 is evaluated alone)
- Remove all shorting plugs attached to JP107.
Setting Functions
- Data and a clock are supplied to the PCM3010 side of JP107.
- Set up FMT0 and FMT1 of SW101 according to the data format to be used.
- Set up DEMP0 and DEMP1 of SW101 for the desired de-emphasis of the
DAC section and PWDN
for the power-down setting.
1.4 Setting Functions
All functions of the devices (PCM3010, DIR1703, DIT4096) on the
DEM-DAI3010 are controlled by DIP switches or header pins on this PCB.
Therefore, the DEM-DAI3010 does not require a microcontroller or software
to transmit data to internal function-setting registers. For specific information
on any device, see the data sheet for that device.
1.4.1 Function Setting Switches and Header Pins
Table 1–3.Switches and Header Pins of the DEM-DAI3010
SW/JP No. Item Shape
SW001 S/PDIF input selection (optical/coax) Toggle switch
SW002 Reset of DIR1703 and DIT4096 Pushbutton switch
SW003 Format and system clock setting of DIR1703 4-pole DIP switch
SW004 Output clock selection of DIR1703 (X’tal/Auto/PLL) Toggle switch
SW005 Format and system clock setting of DIT4096 4-pole DIP switch
SW006 Channel status data setting of DIT4096 10-pole DIP switch
SW051 S/PDIF output selection (optical/coax) Toggle switch
SW101 Setting of PCM3010 (format, de-emphasis, power down) 5-pole DIP switch
JP001 Crystal frequency and system clock setting of DIR1703 2×5 header
JP107 Connection of S/PDIF I/O circuit and PCM3010 2×7 header
JP101 Cutoff frequency setting of DAC output filter (L-ch) 2×2 header
JP102 Cutoff frequency setting of DAC output filter (R-ch) 2×2 header
JP103 Cutoff frequency setting of DAC output filter (L-ch) 2×1 header
JP104 Cutoff frequency setting of DAC output filter (R-ch) 2×1 header
JP105 Selection of L-ch ADC input terminal (CN101/CN103) 2×2 header
JP106 Selection of R-ch ADC input terminal (CN102/CN104) 2×2 header
CN057 The way of power supply of PCM3010 VDD (3.3 V) 2×1 header
Note: The relation between the DIP switch setting (ON/OFF) and the setting of the IC input port is printed on the PCB. The DIP
switch H position does not always set the IC input port level HIGH.
Toggle switch settings are printed on the PCB.
Description
1-5
Setting Functions
1.4.2 Detailed Explanation of Function Setting Switches and Header Pins
SW001: Switch to select S/PDIF input connector (optical/coaxial). Selection of the
S/PDIF signal that is routed to the DIR1703 DIN port.
SW002: Reset switch for the DIR1703 and DIT4096. Pushing this switch resets the
DIR1703 and DIT4096 to the initial state. A reset circuit operates at the time of
power-supply connection, resetting the DIR1703 and DIT4096 automatically.
Therefore, it is not usually necessary to operate this switch.
SW003: Switch for setting the DIR1703 system clock and output data format
SCF1 SCF0 System Clock
L L 128 f
L H 256 fS (initial stting)
H L 384 f
H H 512 f
FMT1 FMT0 Output Data Format
L L 16-bit right-justified, MSB-first
L H 24-bit right-justified, MSB-first
H L 24-bit left-justified, MSB-first
H H 24-bit, I2S (initial setting)
S
S
S
SW004: Switch for setting the DIR1703 output clock source
Position Output Clock (SCK, BCK, LRCK)
X’tal Crystal clock
PLL PLL clock
Auto PLL (PLL locked) / crystal (PLL unlocked)
Note: When using the DIR1703 as a master clock for the ADC, this switch must be set to X’tal.
When inputting S/PDIF data demodulated by the DIR1703 into the DAC, set this switch to Auto or PLL.
SW005: Switch for setting the DIT4096 system clock and input data format
Note that the OFF state of this switch sets a HIGH level.
CLK1 CLK0 System Clock
L L Not used
L H 256 fS (initial setting)
H L 384 f
H H 512 f
S
S
1-6
Setting Functions
FMT1
L L 24-bit, left-justified, MSB-first
L H 24-bit, I2S (initial setting)
H L 24-bit, right-justified, MSB-first
H H 16-bit, right-justified, MSB-first
FMT0 Input Data Format
SW006: Switch for setting channel-status data of the DIT4096. Note that the OFF state
of this switch sets a HIGH level. Channel status data can set up if needed.
Moreover, it is also possible to connect a microcontroller to CN002 and to write
in channel-status data with the microcontroller. See the DIT4096 data sheet (TI
literature number SBOS225) for details about the contents of a setting.
SW051: Switch to select the S/PDIF output connector (optical/coaxial). An S/PDIF
output connector is chosen from optical (U052) and coaxial (CN058). The
optical and coaxial output terminals cannot be used simultaneously.
SW101: Switch for setting the functions of the PCM3010. All the functions of PCM3010
are set up with this switch. Functions that can be set are the audio serial data
I/O format, the DAC section de-emphasis, and power-down control.
FMT1 FMT0 DAC Input Data Format ADC Output Data Format
L L 24-bit, right-justified, MSB-first 24-bit, left-justified, MSB-first
L H 16-bit, right-justified, MSB-first 24-bit, left-justified, MSB-first
H L 24-bit, left-justified, MSB-first 24-bit, left-justified, MSB-first
H H 24-bit, I2S (initial setting) 24-bit, I2S (initial setting)
DEMP1 DEMP0 DAC De-Emphasis
L L De-emphasis ON, 44.1-kHz
L H De-emphasis OFF (initial setting)
H L De-emphasis ON, 48-kHz
H H De-emphasis ON, 32-kHz
PDOWN Power-Down Control
L Power-down mode
H Nomal operation (initial setting)
JP001: Setup of the crystal frequency and system clock for the DIR1703. When the
system clock and the frequency of the crystal for the DIR1703 are changed, a
shorting plug is inserted in only one position of JP001 according to the following
tables. In order to avoid the loss of a shorting plug which is not being used, the
plug is put in the header pin position labeled as OPEN. Because 24.576 MHz
is used for a quartz crystal and the system clock is set as the 256 f
output in
S
initial setting at the time of shipment, the shorting plug is attached in the CSBIT
position.
Description
1-7
Setting Functions
JP001 setting table: DIR1703 system clock and crystal frequency
fS in X’tal
Mode
32 kHz 4.096 MHz 8.192 MHz 12.288 MHz 16.384 MHz BFRAME
44.1 kHz 5.6448 MHz 11.2896 MHz 16.9344 MHz 22.5792 MHz EMFLG
48 kHz 6.144 MHz 12.288 MHz 18.432 MHz 24.576 MHz OPEN (no jumper)
88.2 kHz 11.2896 MHz 22.5792 MHz 33.8688 MHz 45.1584 MHz URBIT
96 kHz 12.288 MHz 24.576 MHz 36.864 MHz 49.152 MHz CSBIT
Sample of a of JP001 setting
JP101–JP104: Cutoff frequency setting of DAC output post-LPF
128 f
S
Target: system clock: 256 f
256 f
S
384 f
S
and fS = 48 kHz in the X’tal mode
S
512 f
S
BRSEL Jumper Position
In the preceding table, the frequency listed where the 256-fS column
intersects the 48-kHz row is 12.288 MHz.
The cutoff frequency of the LPF inserted in the DAC output is chosen by
these jumpers. The initial setting (all pins shorted) is 54 kHz at the time
of shipment. The cutoff frequency with all JP101–JP104 jumper pins open
is 108 kHz.
JP105–JP106: Selection of ADC input connectors (CN101 and CN102 or CN103 and
CN104)
There are two pairs of ADC input connectors. One pair is coupled to the
PCM3010 through capacitors (C121, C122). The other pair is connected
through a 103-kHz cutoff LPF and a –6 dB amplifier.
The input connectors are chosen by JP105 and JP106. When the jumpers
are on Direct-IN, then the left- and right-channel inputs on CN103 and
CN104, respectively, bypass the LPF.
When the jumpers are on –6 db/LPF, then the left- and right-channel
inputs on CN101 and CN102, respectively, go through the LPF to the
PCM3010.
ADC Full-Scale Input Connector No. Details
L-ch 2 V rms CN101 L-ch ADC input with LPF
R-ch 2 V rms CN102 R-ch ADC input with LPF
L-ch 1 V rms CN103 L-ch ADC input without LPF
R-ch 1 V rms CN104 R-ch ADC input without LPF
JP107: Connection of PCM3010 and S/PDIF I/O circuits
This is the header pin which connects the clock input and data I/O of the PCM3010
with an S/PDIF I/O circuit. All pin positions have shorting plugs installed at the time
of shipment.
For evaluating the PCM3010 with other DSPs, DIRs, and DIT s, JP107 jumpers are
removed. Connection to the alternative devices is made through the row of JP107
pins that is wired to the PCM3010.
1-8
CN057: VCC supply selection for the PCM3010
This jumper determines whether V
CC
regulator on this board (U051), or via an external power supply terminal (CN056).
In the initial setting, V
is supplied from the onboard regulator. When VCC for the
CC
PCM3010 is to be provided by an external power supply, the jumper is removed
from CN057 and 3.3 V is supplied to CN056. If 3.3 V is supplied externally, 5 V
must still be provided to CN054 in order to supply the analog section of the
PCM3010.
To avoid latch-up of the PCM3010, ensure that V
simultaneously at start-up.
Setting Functions
for the PCM3010 is supplied from a 3.3-V
and VDD are switched on
CC
Description
1-9
1-10
Chapter 2
Printed-Circuit Board and Schematic
This chapter presents the DEM-DAI3010 printed-circuit board and
schematics.
Topic Page
2.1 DEM-DAI3010 Printed-Circuit Board 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 DEM-DAI3010 Schematics 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Printed-Circuit Board and Schematic
2-1
DEM-DAI3010 Printed-Circuit Board
2.1 DEM-DAI3010 Printed-Circuit Board
Figure 2–1.DEM-DAI3010 Silkscreen
2-2
Figure 2–2.DEM-DAI3010—Top View
DEM-DAI3010 Printed-Circuit Board
Printed-Circuit Board and Schematic
2-3
DEM-DAI3010 Printed-Circuit Board
Figure 2–3.DEM-DAI3010—Bottom View
2-4
2.2 DEM-DAI3010 Schematics
Figure 2–4.DEM-DAI3010 Analog Section
DEM-DAI3010 Schematics
C130
10uF/16V
C129 0.1uF
C132
10uF/16V
R120
0
JP107
FFC–12BMEP1
GND
TX–DATA
SCLK
BCK
LRCK
RX–DATA
C128
10uF
/16V
R121
0
C127
0.1uF
C131
0.1uF
1
1
C105
1200pF
C106
1200pF
R113 1.2k
C117 330pF
4
U102
OPA2134PA 1/2
R114 1.2k
C118 330pF
4
R105 15k
JP101
2/2
R103
1k
JP102
2/2
R104
1k
2
3
2
3
U103
OPA2134PA
1/2
C107 120pF
2
3
R106 15k
C108 120pF
6
5
R111
3.3k
R112
3.3k
C109
120pF
C110
120pF
4
8
R109
C115
1800pF
R110
C116
1800pF
JP103
1
U101
OPA2134A
1/2
JP104
7
U101
OPA2134A
2/2
2.4k
2.4k
CN103
RCA pj
CN104
RCA pj
R107
100
AVCC–
R108
100
C113
10uF
/16V
C114
10uF
/16V
CN101
RCA pj
CN102
RCA pj
CN105
RCA
AV
CC
C111
10uF
/16V
C112
10uF
/16V
CN106
RCA
pj
+
pj
C119 100pF
OPA2134PA
OPA2134PA
C137
0.1uF
C135
0.1uF
R117 4.7k
7
U102
2/2
C120 100pF
R118 4.7k
7
U103
2/2
C138
10uF
/16V
C136
10uF/16V
C133
0.1uF
FMT0
FMT1
DEMP0
DEMP1
PDWN
8
8
C134
10uF /16V
6
5
6
5
V
DD
C121
10uF
/16V
C122
10uF
/16V
U104
PCM3010
1
VINL
2
V
R
IN
3
1
V
REF
4
V
2
REF
5
V
1
CC
6
AGND1
7
FMT0
8
FMT1
9
TEST
10
LRCK
11
BCK
12
DIN
SW101
DSS105
V
COM
V
OUT
V
OUT
V
AGND2
PCM3010
DEMP0
DEMP1
PDWN
SCKI
V
DGND
DOUT
R119 220
JP105
FFC–4BMEP1
JP106
FFC–4BMEP1
V
24
23
L
22
R
21
2
CC
20
19
18
17
16
15
DD
14
13
CC
5
4
3
2
1
R115
4.7k
R116
4.7k
R101
JP101
C103
1200pF
C102
10uF
/16V
JP102
C104
1200pF
8.2k
1/2
1/2
C101
10uF
/16V
AVCC+
C123
10uF/16V
C125
10uF/16V
AVCC–
AVCC+
C124
10uF/16V
C126
10uF/16V
AVCC–
JP101/102: FFC–4BMEP1
JP103/104: FFC–2BMEP1
R102
8.2k
Printed-Circuit Board and Schematic
2-5
DEM-DAI3010 Schematics
Figure 2–5.DEM-DAI3010 Regulator, Connector and Ext.-I/F
CN056 B2P–VH
21
U052
TOTX179P
12 45
CN05 8
RCA pj
6 4 2
5 3 1
TR001
DA–02
U053
TORX179P
23 45
CN057
FFC–2BMEP1
C056
10uF/16V
3
C057
0.1uF
R052 374
1
C059
0.1uF
V
DD
U051
REG1117–3.3
23
GND
C058
10uF
/16V
R051
90.9
C060
10uF
/16V
INOUT
1
CN055
banana jack
(Black)
V
CC
C051
0.1uF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
SW051
FT1D–2M
CN060 57LE–40360–7700(D3)
20
RA051
1
2
3
4
Optical
Coaxial
select
47k x 5
REC-out
DIT–out
SW053
DSS104
C061
0.1uF
C055
0.1uF
OPT/COAX–out
CN054
banana jack
(Red)
C052
10ouF
/16V
74LVC244
SW052
FT1D–2M
DIT/REC–out select
CN053
banana jack
(Blue)
C053
100uF
/16V
U054
[RESET]
[MDO]
[MDI]
[MC]
[ML]
CN052
banana jack
(Green)
C062 0.1uF
1
2
3
4
5
6
7
8
9
10
GND
CN051
banana jack
(Orange)
C054
100uF
/16V
20
Vcc
19
18
17
16
15
14
13
12
11
AV
CC
AVCC–
RESET
MDO
MDI
MC
ML
REC–out
DIT–out
OPT-in
COAX-in
+
CN059 RCA pj
2-6
R053
75
Figure 2–6.DEM-DAI3010 Digital Section (Digital Audio Interface)
DEM-DAI3010 Schematics
C019
10uF
/16V
REC–out
DIT–out
OPT–in
COAX in
CN003
XB–3–7–20
SW005
DSS108
[SCLK]
[BCK]
[LRCK]
[TX–DATA]
V
CC
FMT1
FMT0
CLK1
CLK0
MODE
MDAT
MONO
M/S
10
SW003
DSS104
R005
1M
Vcc
C009
0.1 uF
C007
18p F
14
13
12
11
10
9
8
4
3
2
1
RA001
47k x 5
C015
10 uF /16V
C014
0.1uF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
[ADFLG]
[BRATE0]
[BRATE1]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SW001
FT1D–2M
CSS
COPY/C
L
CLK1
CLK0
MCLK
V
DD
DGND
FMT0
FMT1
SCLK
SYNC
SDATA
M/S
U004 DIT4096
ADFLG
BRATE0
BRATE1
SCKO[SCLK]
V
DD
DGND
XTO
XTI
CKTRNS
LRCKO[LRCK]
BCKO[BCK]
DOUT[RX-DATA]
SCF0
SCF1
U002 DIR1703
MODE
DIT4096
EMPH
AUDIO
MONO
DGND
CKSEL
UNLOCK
AGND
DIR1703
BRSEL
BFRAME
EMFLG
URBIT
CSBIT
BLS
BLSM
MDAT
V
TX+
TX–
RST
FMT1
FMT0
V
FILT
RST
DIN
RA003
47k x 9
28
27
U
26
V
25
24
23
22
21
20
C016
0.1uF
19
DD
18
17
16
15
SW004
FT1E–2M
Clock mode select
28
27
26
25
24
CC
23
22
21
20
19
18
17
16
15
R006
1.2k
C011
10uF
C013
8200pF
C012
0.068uF
CN002
FFC
–9AMEP1
C017
10 uF /16V
X’tal
PLL
[BRSEL]
Auto
[CSBIT]
C010
[URBIT]
10uF
[EMFLG]
/16V
[BFRAME]
U003 REG1117–3.3
OUT
2
GND
1
C003
10uF/16V
XB–3–7–20
[TX–DATA ]
[SCLK ]
[BCK ]
[LRCK ]
[RX–DATA]
IN
CN004
3
C002
0.1uF
SW006
DSS109
9
8
7
6
5
4
3
2
1
CN001
FFC–10AMEP1
ADFLG
BRATE0
BRATE1
UNLOCK/PE
BFRAME
EMFLG
URBIT
CSBIT
CKTRNS
JP001
FFC10–
BMEP1
GND
V
CC
RESET
MDO
MDI
MC
ML
GND
TX–DATA
SCLK
BCK
LRCK
RX–DATA
CSS
COPY/C
U
V
L
AUDIO
EMPH
BLSM
BLS
C020
10uF
/16V
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
12
11
U005
74HCT244
47k
D001
1SS133
SW002
X001
24.576MHz
1
2
3
4
5
6
7
RA002
47k x 3
C008
10uF
/16V
C006
18p F
C0 04 0.1uF
GND
C018
0.1uF
1
2
3
4
5
6
7
8
9
GND
C005
10uF
/16V
R004
470
R001
R002
C001
0.1u F
47k
2.2k
Vcc
(PX–1 x2pcs.)
U001
74HCU04
R003
FP1F–2M
Printed-Circuit Board and Schematic
2-7
2-8
Loading...