TEXAS INSTRUMENTS DAC8562 Technical data

DAC756x DAC816x DAC856x

(12-Bit) (14-Bit) (16-Bit)

Data Buffer A

DAC Register A

Buffer Control Register Control

Control Logic

Power-

Down

Control

Logic

REFIN REFOUT

CLRLDAC

2.5-V

Reference

Data Buffer B

DAC Register B

V B

OUT

V A

OUT

GND

DAC

Input Control Logic

SYNC

SCLK

DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563

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SLAS719C –AUGUST 2010– REVISED JUNE 2011

DUAL 16-/14-/12-BIT, ULTRALOW-GLITCH, LOW-POWER, BUFFERED, VOLTAGE-OUTPUT

DAC WITH 2.5-V, 4-PPM/°C INTERNAL REFERENCE IN SMALL 3-MM × 3-MM QFN

Check for Samples: DAC8562, DAC8563, DAC8162, DAC8163, DAC7562, DAC7563

FEATURES

• Relative Accuracy: – DAC856x (16-Bit): 4 LSB INL – DAC816x (14-Bit): 1 LSB INL – DAC756x (12-Bit): 0.3 LSB INL

• Glitch Energy: 0.1 nV-s

• Bidirectional Reference: Input or 2.5-V Output – Output Disabled by Default – ±5-mV Initial Accuracy (Max) – 4-ppm/°C Temperature Drift (Typ) – 10-ppm/°C Temperature Drift (Max) – 20-mA Sink/Source Capability

• Power-On Reset to Zero Scale or Mid-Scale

• Low-Power: 4 mW (Typ, 5-V AVDD, Including

Internal Reference Current)

• Wide Power-Supply Range: 2.7 V to 5.5 V

• 50-MHz SPI With Schmitt-Triggered Inputs

• LDAC and CLR Functions

• Output Buffer With Rail-to-Rail Operation

• Packages: QFN-10 (3x3 mm), MSOP-10

• Temperature Range: –40°C to 125°C

APPLICATIONS

• Portable Instrumentation

• Bipolar Outputs (reference design)

• PLC Analog Output Module (reference design)

• Closed-Loop Servo Control

• Voltage Controlled Oscillator Tuning

• Data Acquisition Systems

• Programmable Gain and Offset Adjustment

DESCRIPTION

The DAC856x, DAC816x, and DAC756x are low-power, voltage-output, dual-channel, 16-, 14-, and 12-bit digital-to-analog converters (DACs), respectively. These devices include a 2.5-V, 4-ppm/°C internal reference, giving a full-scale output voltage range of 2.5 V or 5 V. The internal reference has an initial accuracy of ±5 mV and can source or sink up to 20 mA at the V

REFIN/VREFOUT

These devices are monotonic, providing excellent linearity and minimizing undesired code-to-code transient voltages (glitch). They use a versatile three-wire serial interface that operates at clock rates up to 50 MHz. The interface is compatible with standard SPI™, QSPI™, Microwire™, and digital signal processor (DSP) interfaces. The DACxx62 devices incorporate a power-on-reset circuit that ensures the DAC output powers up at zero scale until a valid code is written to the device, whereas the DACxx63s similarly power up at mid-scale. These devices contain a power-down feature that reduces current consumption to typically 10 nA at 5 V. The low power consumption, internal reference, and small footprint make these devices ideal for portable, battery-operated equipment.

The DACxx62 devices are drop-in and function-compatible with each other, as are the DACxx63s. The entire family is available in MSOP-10 and QFN-10 packages.

Table 1. RELATED DEVICES

16-BIT 14-BIT 12-BIT

Reset to zero DAC8562 DAC8162 DAC7562 Reset to mid-scale DAC8563 DAC8163 DAC7563

pin.

2SPI, QSPI are trademarks of Motorola, Inc. 3Microwire is a trademark of National Semiconductor.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563

SLAS719C –AUGUST 2010– REVISED JUNE 2011

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

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DEVICE INFORMATION

MAXIMUM MAXIMUM MAXIMUM

PRODUCT TEMPER-

DAC8562 Zero 8562

DAC8563 Mid-scale 8563

DAC8162 Zero 8162

DAC8163 Mid-scale 8163

DAC7562 Zero 7562

DAC7563 Mid-scale 7563

RELATIVE DIFFERENTIAL REFERENCE RESET PACKAGE- PACKAGE PACKAGE

ACCURACY NONLINEARITY DRIFT TO LEAD DESIGNATOR MARKING

(LSB) (LSB) (ppm/°C)

±12 ±1 10 –40°C to 125°C

±3 ±0.5 10 –40°C to 125°C

±0.75 ±0.25 10 –40°C to 125°C

(1)

SPECIFIED

ATURE RANGE

QFN-10 DSC

MSOP-10 DGS

QFN-10 DSC

MSOP-10 DGS

QFN-10 DSC

MSOP-10 DGS

QFN-10 DSC

MSOP-10 DGS

QFN-10 DSC

MSOP-10 DGS

QFN-10 DSC

MSOP-10 DGS

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI

Web site at www.ti.com.

DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563

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ABSOLUTE MAXIMUM RATINGS

(1)

Over operating free-air temperature range (unless otherwise noted).

AVDDto GND –0.3 to 6 V CLR, DIN, LDAC, SCLK and SYNC input voltage to GND –0.3 to AVDD+ 0.3 V V

to GND –0.3 to AVDD+ 0.3 V

OUT

REFIN/VREFOUT

to GND –0.3 to AVDD+ 0.3 V Operating temperature range –40 to 125 °C Junction temperature, maximum (T

) 150 °C

J max

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

THERMAL INFORMATION

THERMAL METRIC DSC DGS UNIT

θ θ θ ψ ψ θ

JA JCtop JB

JT JB

JCbot

Junction-to-ambient thermal resistance Junction-to-case (top) thermal resistance Junction-to-board thermal resistance Junction-to-top characterization parameter Junction-to-board characterization parameter Junction-to-case (bottom) thermal resistance

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific

JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(4) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(5) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(1)

(2)

(3)

(4)

(5)

(6)

SLAS719C –AUGUST 2010– REVISED JUNE 2011

VALUE UNIT

DAC856x, DAC816x, DAC756x

10 PINS 10 PINS

62.8 173.8 °C/W

44.3 48.5 °C/W

26.5 79.9 °C/W

0.4 1.7 °C/W

25.5 68.4 °C/W

46.2 N/A °C/W

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SLAS719C –AUGUST 2010– REVISED JUNE 2011

ELECTRICAL CHARACTERISTICS

At AVDD= 2.7 V to 5.5 V and TA= –40°C to 125°C (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

STATIC PERFORMANCE

Resolution 16 Bits

DAC856x Relative accuracy Using line passing through codes 512 and 65,024 ±4 ±12 LSB

Differential nonlinearity 16-bit monotonic ±0.2 ±1 LSB Resolution 14 Bits

DAC816x Relative accuracy Using line passing through codes 128 and 16,256 ±1 ±3 LSB

Differential nonlinearity 14-bit monotonic ±0.1 ±0.5 LSB Resolution 12 Bits

DAC756x Relative accuracy Using line passing through codes 32 and 4,064 ±0.3 ±0.75 LSB

Differential nonlinearity 12-bit monotonic ±0.05 ±0.25 LSB Offset error Extrapolated from two-point line Offset error drift ±2 µV/°C Full-scale error DAC register loaded with all 1s ±0.03 ±0.2 % FSR Zero-code error DAC register loaded with all 0s 1 4 mV Zero-code error drift ±2 µV/°C Gain error Extrapolated from two-point line

Gain temperature coefficient ±1

OUTPUT CHARACTERISTICS

Output voltage range 0 AV

Output voltage settling time

Slew rate Measured between 20% - 80% of a full-scale transition 0.75 V/µs

Capacitive load stability nF

Code-change glitch impulse 1-LSB change around major carry 0.1 nV-s Digital feedthrough SCLK toggling, SYNC high 0.1 nV-s Power-on glitch impulse RL= 2 kΩ, CL= 470 pF, AVDD= 5.5 V 40 mV

Channel-to-channel dc crosstalk µV

DC output impedance At mid-scale input 5 Ω Short-circuit current 40 mA Power-up time, including settling time Coming out of power-down mode 50 µs

AC PERFORMANCE

DAC output noise density TA= 25°C, at mid-scale input, f DAC output noise TA= 25°C, at mid-scale input, 0.1 Hz to 10 Hz 2.6 µV

LOGIC INPUTS

(2)

Input pin Leakage current –1 ±0.1 1 µA Logic input LOW voltage VINL 0 0.8 V

Logic input HIGH voltage VINH AV Pin capacitance 3 pF

(1) 16-bit: codes 512 and 65,024; 14-bit: codes 128 and 16,256; 12-bit: codes 32 and 4,064 (2) Specified by design or characterization (3) Transition time between 1/4 scale and 3/4 scale including settling to within ±0.024% FSR

(1)

, unloaded ±1 ±4 mV

(1)

, unloaded ±0.01 ±0.15 % FSR

(2)

(3)

DACs unloaded 7 RL= 1 MΩ 10

RL= ∞ 1 RL= 2 kΩ 3

Full-scale swing on adjacent channel, External reference

Full-scale swing on adjacent channel, Internal reference

DAC outputs at full-scale, DAC outputs shorted to GND

(2)

= 1 kHz 90 nV/√Hz

OUT

0.7 ×

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ppm

FSR/°C

µs

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ELECTRICAL CHARACTERISTICS (continued)

At AVDD= 2.7 V to 5.5 V and TA= –40°C to 125°C (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

REFERENCE

External reference current 15 µA V

reference input range 0 AV

REFIN

Reference input impedance kΩ

External V disabled), all channels active using gain = 1

Internal reference disabled, gain = 1 170 Internal reference disabled, gain = 2 85

REFERENCE OUTPUT

Output voltage TA= 25°C 2.495 2.5 2.505 V Initial accuracy TA= 25°C –5 ±0.1 5 mV Output voltage temperature drift

(4)

Output voltage noise f = 0.1 Hz to 10 Hz 12 µV

TA= 25°C, f = 1 kHz, CL= 0 µF 250 Output voltage noise density (high-frequency noise)

TA= 25°C, f = 1 MHz, CL= 0 µF 30 nV/√Hz

TA= 25°C, f = 1 MHz, CL= 4.7 µF 10 Load regulation, sourcing Load regulation, sinking Output current load capability

(5)

(6)

TA= 25°C 20 µV/mA

TA= 25°C 185 µV/mA

Line regulation TA= 25°C 50 µV/V Long-term stability/drift (aging)

Thermal hysteresis

(5)

POWER REQUIREMENTS

(5)

TA= 25°C, time = 0 to 1900 hours 100 ppm

First cycle 200

Additional cycles 50

(7)

Power supply voltage 2.7 5.5 V

Normal mode, internal reference off 0.25 0.5

AVDD= 3.6 V to 5.5 V

AVDD= 2.7 V to 3.6 V

Normal mode, internal reference on 0.8 1.3

Power-down modes

Normal mode, internal reference off 0.2 0.4

Normal mode, internal reference on 0.73 1.3

Power-down modes

Normal mode, internal reference off 0.9 2.75

AVDD= 3.6 V to 5.5 V

Power dissipation

AVDD= 2.7 V to 3.6 V

Normal mode, internal reference on 2.9 7.15

Power-down modes

Normal mode, internal reference off 0.54 1.44

Normal mode, internal reference on 1.97 4.68

Power-down modes

TEMPERATURE RANGE

Specified performance –40 125 °C

(4) Internal reference output voltage temperature drift is characterized from –40°C to 125°C. (5) Explained in more detail in the Application Information section of this data sheet. (6) Specified by design or characterization (7) Input code = mid-scale, no load, VINH = AVDD, and VINL = GND (8) Temperature range –40°C to 105°C (9) Temperature range –40°C to 125°C

= 2.5 V (when internal reference is

REF

(8) (9)

SLAS719C –AUGUST 2010– REVISED JUNE 2011

4 10 ppm/°C

±20 mA

ppm

0.01 1

0.01 3

0.008 1

0.008 3

0.04 5.5

0.04 16.5

µW

0.02 3.6

0.02 10.8

µW

µA

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V A

OUT

V B

OUT

GND

LDAC

CLR

SYNC

SCLK

V /V

REFIN REFOUT

V /V

REFIN REFOUT

V A

OUT

V B

OUT

GND

LDAC

CLR

DGS

(Top View)

DSC

(Top View)

MSOP Package QFN Package

Thermal Pad

(1)

DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563

SLAS719C –AUGUST 2010– REVISED JUNE 2011

PIN CONFIGURATIONS

(1) It is recommended to connect the thermal pad to the ground plane for better thermal dissipation.

Table 2. PIN DESCRIPTIONS

NAME NO.

9 Power-supply input, 2.7 V to 5.5 V

Asynchronous clear input. The CLR input is falling-edge sensitive. When CLR is activated, zero scale

CLR 5

(DACxx62) or mid-scale (DACxx63) is loaded to all input and DAC registers. This sets the DAC output voltages accordingly. The part exits clear code mode on the 24thfalling edge of the next write to the part. If CLR is activated during a write sequence, the write is aborted.

Serial data input. Data are clocked into the 24-bit input shift register on each falling edge of the serial clock

input. Schmitt-trigger logic input

GND 3 Ground reference point for all circuitry on the device

In synchronous mode, data are updated with the falling edge of the 24thSCLK cycle, which follows a falling edge of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to GND permanently or asserted and held low before sending commands to the device.

LDAC 4 In asynchronous mode, the LDAC pin is used as a negative edge-triggered timing signal for simultaneous

DAC updates. Multiple single-channel commands can be written in order to set different channel buffers to desired values and then make a falling edge on LDAC pin to simultaneously update the DAC output registers.

SCLK 7 Serial clock input. Data can be transferred at rates up to 50 MHz. Schmitt-trigger logic input

Level-triggered control input (active-low). This input is the frame synchronization signal for the input data. When SYNC goes low, it enables the input shift register, and data are sampled on subsequent falling clock

SYNC 6 edges. The DAC output updates following the 24thclock falling edge. If SYNC is taken high before the 23

clock edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC756x/DAC816x/DAC856x. Schmitt-trigger logic input

A 1 Analog output voltage from DAC-A

OUT

B 2 Analog output voltage from DAC-B

OUT

REFIN

/ V

REFOUT

10 Bidirectional voltage reference pin. If internal reference is used, 2.5-V output.

DESCRIPTION

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SCLK

SYNC

DIN

VOUT

DB23

DB0

LDAC

(1)

LDAC

(2)

CLR

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TIMING DIAGRAM

DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563

SLAS719C –AUGUST 2010– REVISED JUNE 2011

(1) Asynchronous LDAC update mode. For more information, see the LDAC Functionality section. (2) Synchronous LDAC update mode; LDAC remains low. For more information, see the LDAC Functionality section.

Figure 1. Serial Write Operation

TIMING REQUIREMENTS

At AVDD= 2.7 V to 5.5 V and over –40°C to 125°C (unless otherwise noted).

(3)

(1) All input signals are specified with tR= tF= 3 ns (10% to 90% of AVDD) and timed from a voltage level of (VINL + VINH)/2. (2) See the Serial Write Operation timing diagram (Figure 1). (3) Maximum SCLK frequency is 50 MHz at AVDD= 2.7 V to 5.5 V.

SCLK falling edge to SYNC falling edge (for successful write operation) 10 ns SCLK cycle time 20 ns SYNC rising edge to 23rdSCLK falling edge (for successful SYNC interrupt) 13 ns Minimum SYNC HIGH time 80 ns SYNC to SCLK falling edge setup time 13 ns SCLK LOW time 8 ns SCLK HIGH time 8 ns SCLK falling edge to SYNC rising edge 10 ns Data setup time 6 ns Data hold time 5 ns SCLK falling edge to LDAC falling edge for asynchronous LDAC update mode 5 ns LDAC pulse duration, LOW time 10 ns CLR pulse duration, LOW time 80 ns CLR falling edge to start of VOUT transition 100 ns

(1)(2)

PARAMETER UNIT

DAC756x/DAC816x/DAC856x

MIN TYP MAX

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TABLES OF GRAPHS

Table 3. Typical Characteristics: Internal Reference Performance

MEASUREMENT FIGURE NUMBER

Internal Reference Voltage vs Temperature Figure 2 Internal Reference Voltage Temperature Drift Histogram Figure 3 Internal Reference Voltage vs Load Current 5.5 V Figure 4 Internal Reference Voltage vs Time Figure 5 Internal Reference Noise Density vs Frequency Figure 6 Internal Reference Voltage vs Supply Voltage 2.7 V – 5.5 V Figure 7

Table 4. Typical Characteristics: DAC Static Performance

MEASUREMENT FIGURE NUMBER

FULL-SCALE, GAIN, OFFSET AND ZERO-CODE ERRORS

Full-Scale Error vs Temperature Figure 16 Gain Error vs Temperature Figure 17 Offset Error vs Temperature Figure 18 Zero-Code Error vs Temperature Figure 19 Full-Scale Error vs Temperature Figure 63 Gain Error vs Temperature Figure 64 Offset Error vs Temperature Figure 65 Zero-Code Error vs Temperature Figure 66

LOAD REGULATION

DAC Output Voltage vs Load Current

DIFFERENTIAL NONLINEARITY ERROR

T = –40°C Figure 9

Differential Linearity Error vs Digital Input Code T = 25°C Figure 11

T = 125°C Figure 13

Differential Linearity Error vs Temperature Figure 15

T = –40°C Figure 56

Differential Linearity Error vs Digital Input Code T = 25°C Figure 58

T = 125°C Figure 60

Differential Linearity Error vs Temperature Figure 62

INTEGRAL NONLINEARITY ERROR (RELATIVE ACCURACY)

T = –40°C Figure 8

Linearity Error vs Digital Input Code T = 25°C Figure 10

T = 125°C Figure 12

Linearity Error vs Temperature Figure 14

T = –40°C Figure 55

Linearity Error vs Digital Input Code T = 25°C Figure 57

T = 125°C Figure 59

Linearity Error vs Temperature Figure 61

POWER-SUPPLY

VOLTAGE

POWER-SUPPLY

VOLTAGE

5.5 V

2.7 V

5.5 V Figure 30

2.7 V Figure 74

5.5 V

2.7 V

5.5 V

2.7 V

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Table 4. Typical Characteristics: DAC Static Performance (continued)

MEASUREMENT FIGURE NUMBER

POWER-DOWN CURRENT

Power-Down Current vs Temperature 5.5 V Figure 28 Power-Down Current vs Power-Supply Voltage 2.7 V – 5.5 V Figure 29 Power-Down Current vs Temperature 2.7 V Figure 73

POWER-SUPPLY CURRENT

Power-Supply Current vs Temperature

Power-Supply Current vs Digital Input Code 5.5 V

Power-Supply Current Histogram

Power-Supply Current vs Power-Supply Voltage 2.7 V – 5.5 V

Power-Supply Current vs Temperature

Power-Supply Current vs Digital Input Code 3.6 V

Power-Supply Current Histogram

Power-Supply Current vs Temperature

Power-Supply Current vs Digital Input Code 2.7 V

Power-Supply Current Histogram

External V Internal V External V Internal V External V Internal V External V Internal V External V Internal V External V Internal V External V Internal V External V Internal V External V Internal V External V Internal V

REF

SLAS719C –AUGUST 2010– REVISED JUNE 2011

POWER-SUPPLY

VOLTAGE

Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72

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Table 5. Typical Characteristics: DAC Dynamic Performance

MEASUREMENT FIGURE NUMBER

CHANNEL-TO-CHANNEL CROSSTALK

Channel-to-Channel Crosstalk 5.5 V

CLOCK FEEDTHROUGH

Clock Feedthrough 500 kHz, Midscale

GLITCH ENERGY

Glitch Energy, 1-LSB Step

Glitch Energy, 4-LSB Step 5.5 V

Glitch Energy, 16-LSB Step

Glitch Energy, 1-LSB Step

Glitch Energy, 4-LSB Step 2.7 V

Glitch Energy, 16-LSB Step

NOISE

DAC Output Noise Density vs Frequency

DAC Output Noise 0.1 Hz to 10 Hz External V

POWER-ON GLITCH

Power-on Glitch

SETTLING TIME

Full-Scale Settling Time

Half-Scale Settling Time

Full-Scale Settling Time

Half-Scale Settling Time

5-V Rising Edge Figure 43 5-V Falling Edge Figure 44

Rising Edge, Code 7FFFh to 8000h Figure 37 Falling Edge, Code 8000h to 7FFFh Figure 38 Rising Edge, Code 7FFCh to 8000h Figure 39 Falling Edge, Code 8000h to 7FFCh Figure 40 Rising Edge, Code 7FF0h to 8000h Figure 41 Falling Edge, Code 8000h to 7FF0h Figure 42 Rising Edge, Code 7FFFh to 8000h Figure 79 Falling Edge, Code 8000h to 7FFFh Figure 80 Rising Edge, Code 7FFCh to 8000h Figure 81 Falling Edge, Code 8000h to 7FFCh Figure 82 Rising Edge, Code 7FF0h to 8000h Figure 83 Falling Edge, Code 8000h to 7FF0h Figure 84

External V Internal V

Reset to Zero Scale Figure 35 Reset to Midscale Figure 36 Reset to Zero Scale Figure 85 Reset to Midscale Figure 86

Rising Edge, Code 0h to FFFFh Figure 31 Falling Edge, Code FFFFh to 0h Figure 32 Rising Edge, Code 4000h to C000h Figure 33 Falling Edge, Code C000h to 4000h Figure 34 Rising Edge, Code 0h to FFFFh Figure 75 Falling Edge, Code FFFFh to 0h Figure 76 Rising Edge, Code 4000h to C000h Figure 77 Falling Edge, Code C000h to 4000h Figure 78

REF

POWER-SUPPLY

VOLTAGE

5.5 V Figure 48

2.7 V Figure 87

5.5 V Figure 46

5.5 V

2.7 V

5.5 V

2.7 V

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Figure 45

Figure 47

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2.495

2.496

2.497

2.498

2.499

2.500

2.501

2.502

2.503

2.504

2.505

−40 −25 −10 5 20 35 50 65 80 95 110 125 Temperature (°C)

REFOUT

(V)

60 units shown (30 MSOP, 30 QFN−10)

Temperature Drift (ppm/ °C)

Population (%)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

9.5

10.0

2.490

2.495

2.500

2.505

2.510

−20 −15 −10 −5 0 5 10 15 20

Load Current (mA)

REFOUT

(V)

0 250 500 750 1000 1250 1500

−400

−300

−200

−100

100

200

300

400

Elapsed Time (Hours)

Internal Reference Voltage Shift (ppm)

16 units shown (8 MSOP, 8 QFN−10) Average shown in dashed line

100

150

200

250

300

350

400

10 100 1k 10k 100k 1M

Frequency (Hz)

Voltage Noise (nV/rt−Hz)

No Load

4.7 µF Load

2.495

2.496

2.497

2.498

2.499

2.500

2.501

2.502

2.503

2.504

2.505

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 AV

(V)

REFOUT

(V)

−40°C +25°C +125°C

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SLAS719C –AUGUST 2010– REVISED JUNE 2011

TYPICAL CHARACTERISTICS: Internal Reference

At TA= 25°C, AVDD= 5.5 V, gain = 2 and V

INTERNAL REFERENCE VOLTAGE INTERNAL REFERENCE VOLTAGE

vs TEMPERATURE TEMPERATURE DRIFT HISTOGRAM

Figure 2. Figure 3.

, unloaded unless otherwise noted.

REFOUT

INTERNAL REFERENCE VOLTAGE INTERNAL REFERENCE VOLTAGE

vs LOAD CURRENT vs TIME

Figure 4. Figure 5.

INTERNAL REFERENCE NOISE DENSITY INTERNAL REFERENCE VOLTAGE

vs FREQUENCY vs SUPPLY VOLTAGE

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Figure 6. Figure 7.

−12

−9

−6

−3

0 8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

INL Error (LSB)

Typical channel shown

−40°C

−1.0

−0.8

−0.6

−0.4

−0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

DNL Error (LSB)

Typical channel shown

−40°C

−12

−9

−6

−3

0 8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

INL Error (LSB)

Typical channel shown 25°C

−1.0

−0.8

−0.6

−0.4

−0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

DNL Error (LSB)

Typical channel shown 25°C

−12

−9

−6

−3

0 8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

INL Error (LSB)

Typical channel shown 125°C

−1.0

−0.8

−0.6

−0.4

−0.2

0.0

0.2

0.4

0.6

0.8

1.0

0 8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

DNL Error (LSB)

Typical channel shown 125°C

DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563

SLAS719C –AUGUST 2010– REVISED JUNE 2011

TYPICAL CHARACTERISTICS: DAC at AVDD= 5.5 V

At TA= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (–40°C) vs DIGITAL INPUT CODE (–40°C)

Figure 8. Figure 9.

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LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (25°C) vs DIGITAL INPUT CODE (25°C)

Figure 10. Figure 11.

LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR

vs DIGITAL INPUT CODE (125°C) vs DIGITAL INPUT CODE (125°C)

Figure 12. Figure 13.

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−12

−9

−6

−3

−40 −25 −10 5 20 35 50 65 80 95 110 125 Temperature (°C)

INL Error (LSB)

INL Max INL Min

Typical channel shown

−1.0

−0.8

−0.6

−0.4

−0.2

0.0

0.2

0.4

0.6

0.8

1.0

−40 −25 −10 5 20 35 50 65 80 95 110 125 Temperature (°C)

DNL Error (LSB)

DNL Max DNL Min

Typical channel shown

−0.20

−0.15

−0.10

−0.05

0.00

0.05

0.10

0.15

0.20

−40 −25 −10 5 20 35 50 65 80 95 110 125 Temperature (°C)

Full−Scale Error (%FSR)

Ch A Ch B

−0.15

−0.10

−0.05

0.00

0.05

0.10

0.15

−40 −25 −10 5 20 35 50 65 80 95 110 125 Temperature (°C)

Gain Error (%FSR)

Ch A Ch B

−4

−3

−2

−1

−40 −25 −10 5 20 35 50 65 80 95 110 125 Temperature (°C)

Offset Error (mV)

Ch A Ch B

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

−40 −25 −10 5 20 35 50 65 80 95 110 125 Temperature (°C)

Zero−Code Error (mV)

Ch A Ch B

DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563

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TYPICAL CHARACTERISTICS: DAC at AVDD= 5.5 V (continued)

At TA= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

LINEARITY ERROR DIFFERENTIAL LINEARITY ERROR

vs TEMPERATURE vs TEMPERATURE

Figure 14. Figure 15.

SLAS719C –AUGUST 2010– REVISED JUNE 2011

FULL-SCALE ERROR GAIN ERROR

vs TEMPERATURE vs TEMPERATURE

Figure 16. Figure 17.

OFFSET ERROR ZERO-CODE ERROR

vs TEMPERATURE vs TEMPERATURE

Figure 18. Figure 19.

Product Folder Link(s): DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

−40 −25 −10 5 20 35 50 65 80 95 110 125 Temperature (°C)

Power−Supply Current (mA)

DACs at midscale code

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

−40 −25 −10 5 20 35 50 65 80 95 110 125 Temperature (°C)

Power−Supply Current (mA)

Internal reference enabled DACs at midscale code, Gain = 2

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0 8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Power−Supply Current (mA)

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

0 8192 16384 24576 32768 40960 49152 57344 65536

Digital Input Code

Power−Supply Current (mA)

Internal reference enabled, Gain = 2

Power Supply Current (mA)

Population (%)

0.15

0.17

0.19

0.21

0.23

0.25

0.27

0.29

0.31

0.33

0.35

0.37

0.39

0.41

0.43

0.45

Power Supply Current (mA)

Population (%)

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65

0.70

0.75

0.80

0.85

0.90

0.95

1.00

1.05

1.10

1.15

1.20

1.25

1.30

Internal reference enabled Gain = 2

DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563

SLAS719C –AUGUST 2010– REVISED JUNE 2011

TYPICAL CHARACTERISTICS: DAC at AVDD= 5.5 V (continued)

At TA= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

POWER-SUPPLY CURRENT POWER-SUPPLY CURRENT

vs TEMPERATURE vs TEMPERATURE

Figure 20. Figure 21.

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POWER-SUPPLY CURRENT POWER-SUPPLY CURRENT

vs DIGITAL INPUT CODE vs DIGITAL INPUT CODE

Figure 22. Figure 23.

POWER-SUPPLY CURRENT POWER-SUPPLY CURRENT

HISTOGRAM HISTOGRAM

Figure 24. Figure 25.

Product Folder Link(s): DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563

0.00

0.05

0.10

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 AV

(V)

Power−Supply Current (mA)

REFIN

= 2.5 V

DACs at midscale code, Gain = 1

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 AV

(V)

Power−Supply Current (mA)

Internal reference enabled DACs at midscale code, Gain = 1

0.0

0.5

1.0

1.5

2.0

2.5

3.0

−40 −25 −10 5 20 35 50 65 80 95 110 125 Temperature (°C)

Power−Down Current (µA)

0.000

0.005

0.010

0.015

0.020

0.025

0.030

0.035

0.040

2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 AV

(V)

Power−Down Current (µA)

IDD (µA) I

REFIN

(µA)

Both channels and internal reference in power−down mode; V

REFIN

= A

VDD

−1.0

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

−20 −15 −10 −5 0 5 10 15 20 I

(mA)

Output Voltage (V)

Full scale Mid scale Zero scale

Typical channel shown

DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563

www.ti.com

TYPICAL CHARACTERISTICS: DAC at AVDD= 5.5 V (continued)

At TA= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

POWER-SUPPLY CURRENT POWER-SUPPLY CURRENT

vs POWER-SUPPLY VOLTAGE vs POWER-SUPPLY VOLTAGE

Figure 26. Figure 27.

SLAS719C –AUGUST 2010– REVISED JUNE 2011

POWER-DOWN CURRENT POWER-DOWN CURRENT

vs TEMPERATURE vs POWER-SUPPLY VOLTAGE

Figure 28. Figure 29.

DAC OUTPUT VOLTAGE

vs LOAD CURRENT

Product Folder Link(s): DAC8562 DAC8563 DAC8162 DAC8163 DAC7562 DAC7563

Figure 30.

Time (5 s/div)μ

Trigger (5 V/div)LDAC

Large Signal V (2 V/div)

OUT

Small Signal Settling

(1.22 mV/div = 0.024% FSR)

From Code:

To Code:0hFFFFh

Time (5 s/div)μ

Trigger (5 V/div)LDAC

Large Signal V (2 V/div)

OUT

Small Signal Settling (1.22 mV/div = 0.024% FSR)

From Code: FFFF

To Code: 0hh

Time (5 s/div)μ

Trigger (5 V/div)LDAC

Large Signal V (2 V/div)

OUT

Small Signal Settling (1.22 mV/div = 0.024% FSR)

From Code:

To Code:

4000h

C000h

Time (5 s/div)μ

Trigger (5 V/div)LDAC

Large Signal V (2 V/div)

OUT

Small Signal Settling (1.22 mV/div = 0.024% FSR)

From Code: C000h

To Code: 4000h

Time (1 ms/div)

AV (2 V/div)

V A (50 mV/div)

OUT

V shorted to

REFIN

V B (50 mV/div)

OUT

Time (1 ms/div)

AV (2 V/div)

V A (1 V/div)

OUT

V shorted to

REFIN

V B (1 V/div)

OUT

DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563

SLAS719C –AUGUST 2010– REVISED JUNE 2011

TYPICAL CHARACTERISTICS: DAC at AVDD= 5.5 V (continued)

At TA= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

FULL-SCALE SETTLING TIME: FULL-SCALE SETTLING TIME:

RISING EDGE FALLING EDGE

Figure 31. Figure 32.

HALF-SCALE SETTLING TIME: HALF-SCALE SETTLING TIME:

RISING EDGE FALLING EDGE

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Figure 33. Figure 34.

POWER-ON GLITCH POWER-ON GLITCH

RESET TO ZERO SCALE RESET TO MIDSCALE

Figure 35. Figure 36.

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Time (5 s/div)μ

V (100 V/div)

OUT

From Code: 7FFFh

To Code: 8000h

Trigger (5 V/div)LDAC

FeedthroughLDAC

Glitch Impulse 0.1 nV-s»

Time (5 s/div)μ

V (100 V/div)

OUT

From Code:

To Code:

8000h

7FFFh

Trigger (5 V/div)LDAC

FeedthroughLDAC

Glitch Impulse 0.12 nV-s»

Time (5 s/div)μ

V (100 V/div)

OUT

From Code: 7FFCh

To Code: 8000h

Trigger (5 V/div)LDAC

FeedthroughLDAC

Glitch Impulse 0.1 nV-s»

Time (5 s/div)μ

V (100 V/div)

OUT

From Code:

To Code:

8000h

7FFCh

Trigger (5 V/div)LDAC

FeedthroughLDAC

Glitch Impulse 0.14 nV-s»

Time (5 s/div)μ

V (500 V/div)

OUT

From Code: 7FF0h

To Code: 8000h

Trigger (5 V/div)LDAC

FeedthroughLDAC

Glitch Impulse 0.1 nV-s»

Time (5 s/div)μ

V (500 V/div)

OUT

From Code:

To Code:

8000h

7FF0h

Trigger (5 V/div)LDAC

FeedthroughLDAC

Glitch Impulse 0.1 nV-s»

DAC8562, DAC8563 DAC8162, DAC8163 DAC7562, DAC7563

www.ti.com

TYPICAL CHARACTERISTICS: DAC at AVDD= 5.5 V (continued)

At TA= 25°C, 5-V external reference used, gain = 1 and DAC output not loaded, unless otherwise noted.

GLITCH ENERGY GLITCH ENERGY

RISING EDGE, 1-LSB STEP FALLING EDGE, 1-LSB STEP

Figure 37. Figure 38.

GLITCH ENERGY GLITCH ENERGY

RISING EDGE, 4-LSB STEP FALLING EDGE, 4-LSB STEP

SLAS719C –AUGUST 2010– REVISED JUNE 2011

Figure 39. Figure 40.

GLITCH ENERGY GLITCH ENERGY

RISING EDGE, 16-LSB STEP FALLING EDGE, 16-LSB STEP

Figure 41. Figure 42.

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