User's Guide
SBAU121 – January 2006
DAC8554EVM User's Guide
This user’s guide describes the characteristics, operation and use of the DAC8554
Evaluation Module (EVM). It covers all matters related to proper use and configuration
of this EVM along with the devices that it supports. The physical printed circuit board
(PCB) layout, schematic diagram and circuit descriptions are also included. For a more
detailed description of the DAC8554 , please refer to the product datasheet available
from the Texas Instruments web site at http://www.ti.com. Additional support
documents are listed in the section of this guide entitled Related Documentation from
Texas Instruments. Throughout this document, the acronym EVM and the phrases
evaluation module and demonstration board are synonymous with the DAC8554EVM.
Contents
1 Overview ............................................................................................. 2
2 PCB Design and Performance .................................................................... 4
3 EVM Operation .................................................................................... 14
4 Schematic .......................................................................................... 20
List of Figures
1 DAC8554EVM Functional Block Diagram ....................................................... 3
2 DAC8554EVM PCB—Top Silkscreen Image ................................................... 5
3 DAC8554EVM PCB—Layer 1 (Top Signal Layer) ............................................. 5
4 DAC8554EVM PCB—Layer 2 (Ground Plane) ................................................. 6
5 DAC8554EVM PCB—Layer 3 (Power Plane) .................................................. 6
6 DAC8554EVM PCB—Layer 4 (Bottom Signal Layer) ......................................... 7
7 DAC8554EVM PCB—Bottom Silkscreen Image ............................................... 7
8 DAC8554EVM—Drill Drawing..................................................................... 8
9 INL and DNL Characterization Graph of DAC A ............................................... 9
10 INL and DNL Characterization Graph of DAC B .............................................. 10
11 INL and DNL Characterization Graph of DAC C .............................................. 11
12 INL and DNL Characterization Graph of DAC D .............................................. 12
List of Tables
1 DAC8554EVM Parts List ......................................................................... 13
2 Factory Default Jumper Settings ................................................................ 14
3 DAC Output Channel Mapping .................................................................. 15
4 Unity Gain Output Jumper Settings ............................................................. 16
5 Output Gain of 2 Jumper Settings .............................................................. 16
6 Capacitive Load Drive Output Jumper Settings ............................................... 17
7 Jumper Settings and Functions ................................................................. 17
LabVIEW is a trademark of National Instruments.
All trademarks are the property of their respective owners.
SBAU121 – January 2006 DAC8554EVM User's Guide 1
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Overview
1 Overview
This section gives a general overview of the DAC8554EVM and describes some of the factors that must
be considered when using this demonstration board.
1.1 Features
The DAC8554EVM is a simple evaluation module designed for a quick and easy way to evaluate the
functionality and performance of the high-resolution, quad-channel, serial input DAC8554 digital-to-analog
converter (DAC). This EVM features a serial interface to communicate with any host microprocessor or TI
DSP-based system.
1.2 Power Requirements
This subsection describes the power requirements for this device.
1.2.1 Supply Voltage
The DC power supply requirement for the digital section (V
the J5-1 terminal or via the J3-10 terminal (when plugged in with another EVM board or interface card)
and is referenced to ground through the J5-2 and J3-5 terminals. The DC power supply requirements for
the analog section of this EVM are: V
through J1-3 and J1-1 respectively, or through terminals J3-1 and J3-2. The +5V
terminals J5-3 or J3-3, and the +3.3V
are referenced to analog ground through terminals J1-2 and J3-6.
The analog power supply for the device under test, U1, can be powered by either +5V
selecting the proper position of jumper JMP7. This configuration allows the DAC8554 analog section to
operate from either supply power while the I/O and digital section are powered by +5V, V
The V
reference chip, U3 and the reference buffer, U4. The negative rail of the output op amp, U2, can be
selected between V
provide output signal conditioning or to boost capacitive load drive, or for other desired output mode
requirements.
) of this EVM is typically +5V connected to
DD
and V
CC
connects through terminal J3-8. All of the analog power supplies
A
supply source is primarily used to provide the positive rail of the external output op amp, U2, the
CC
and AGND via jumper JMP10. The external op amp is installed as an option to
SS
range from +15.75V to –15.75V (maximum), connecting
SS
connects through
A
or +3.3V
A
DD
by
A
.
1.2.2 Reference Voltage
The +5V precision voltage reference is provided to supply the external voltage reference for the DAC
through the REF02 (U3) via jumper JMP8, by shorting pins 1 and 2. The reference voltage goes through
an adjustable 100k Ω potentiometer, R15, in series with 20k Ω , R16, to allow the user to adjust the
reference voltage to its desired settings. The voltage reference is then buffered through U4A as seen by
the device under test. The test points TP2, TP3 and TP4 are also provided, as well as J4-18 and J4-20, in
order to allow the user to connect another external reference source if the onboard reference circuit is not
desired. The external voltage reference should not exceed +5V DC.
The REF02 precision reference is powered by V
CAUTION
To avoid potential damage to the EVM board, be sure that the correct
cables are connected to their respective terminals as labeled on the EVM
board. Stresses above the maximum listed voltage ratings may cause
permanent damage to the device.
(+15V) through either terminal J1-3 or J3-1.
CC
CAUTION
When applying an external voltage reference through TP2 or J4-20, make
sure that it does not exceed +5V maximum. External voltage references in
excess of +5V can permanently damage the DAC8554 being tested (U1).
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1.3 EVM Basic Functions
JMP11
JMP12
JMP13
JMP14
External
Reference
Module
+5V
A
V
DD
+3.3V
A
(J2A)
(J2B)
DAC Module
(J4A)
(J4B)
8 CH
(J1)
(J5)
(J3A)
(J3B)
4 CH
JMP15
JMP16
JMP9
JMP10
DAC Out
V
SS
V H
REF
TP4
TP3
V
CC
GND
V
SS
GND
V
DD
+5V
A
+3.3V
A
A0
A1
EN
DIN
LDAC
SCLK
SYNC
JMP5
JMP6
JMP4A0JMP3
A1
JMP8
V H
REF
TP2
V
SS
V
CC
V L
REF
Output
Buffer
Module
Overview
The DAC8554EVM is designed to provide a demonstration platform for testing certain operational
characteristics of the DAC8554 digital-to-analog converter. Functional evaluation of the DAC8554 can be
accomplished with the use of any microprocessor, TI DSP or some sort of waveform generator.
Headers J2A (top side) and J2B (bottom side) are pass-through connectors provided to interface a host
processor or waveform generator with the DAC8554EVM using a custom-built cable. These connectors
enable the control signals and data to pass between the host and the device.
A mating adapter interface card (5-6k adapter interface) is also available to fit with TI’s TMS320C5000 and
TMS320C6000 DSP Starter Kits (DSKs). This card resolves most of the trouble involved with building a
custom cable. Additionally, there is also an MSP430-based platform (HPA449) that uses the MSP430F449
microprocessor, to which this EVM can connect and interface as well. For more details or information
regarding the 5-6k adapter interface card or the HPA449 platform, please contact your Texas Instruments
representative, visit the TI web site or email the Data Converter Applications Support Team at
dataconvapps@list.ti.com.
The DAC outputs can be monitored through the selected pins of the J4 header connector. All outputs can
be switched through their respective jumpers—JMP11, JMP12, JMP13 and JMP14—for the purpose of
stacking. Stacking allows a total of eight DAC channels to be used, provided the A0 and A1 address
signals are unique for each EVM board stacked.
In addition, the option of selecting one DAC output that can be fed to the noninverting side of the output
op amp, U2, is also possible by using a jumper across the selected pins of J4. The output op amp (U2)
must first be correctly configured for the desired waveform characteristic. For more information, refer to
Section 3 of this user’s guide.
A block diagram of the EVM is shown in Figure 1 .
Figure 1. DAC8554EVM Functional Block Diagram
SBAU121 – January 2006 DAC8554EVM User's Guide 3
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PCB Design and Performance
1.3.1 Related Documentation from Texas Instruments
The following documents provide information regarding Texas Instrument integrated circuits used in the
assembly of the DAC8554EVM. The latest revisions of these documents are available from the TI web site
at http://www.ti.com.
Data Sheet Literature Number
DAC8854 Datasheet SLAS431
REF02 Datasheet SBVS003
OPA627 Datasheet SBOS165
OPA2132 Datasheet SBOS054
2 PCB Design and Performance
This section discusses the layout design of the DAC8554EVM PCB, describing the physical and
mechanical characteristics of the EVM as well as a brief description of the demonstration board test
performance procedures performed. The list of components used in this evaluation module is also
included.
2.1 PCB Layout
The DAC8554EVM is designed to preserve the performance quality of the DAC8554, the device under
test (DUT), as specified in the data sheet. In order to take full advantage of the EVM capabilities, use care
during the schematic design phase to properly select the right components and to build the circuit
correctly. The circuit design should include adequate bypassing, identifying and managing the analog and
digital signals, and understanding the components' electrical and mechanical attributes.
The primary design concerns during the layout process are optimal component placement and proper
signal routing. Place the bypass capacitors as close as possible to the device pins, and properly separate
the analog and digital signals from each other. In the layout process, carefully consider the placement of
the power and ground planes. A solid plane is ideal, but because of its greater cost, a split plane can
sometimes be used satisfactorily. When considering a split plane design, analyze the component
placement and carefully split the board into its analog and digital sections starting from the DUT. The
ground plane plays an important role in controlling the noise and other effects that otherwise contribute to
the error of the DAC output. To ensure that the return currents are handled properly, route the appropriate
signals only in their respective sections, meaning that the analog traces should only lay directly above or
below the analog section and the digital traces in the digital section. Minimize trace length, but use the
largest possible trace width allowable within the design. These design practices are illustrated in Figure 2
through Figure 8 .
The DAC8554EVM board is constructed on a four-layer PCB using a copper-clad FR-4 laminate material.
The PCB has a dimension of 43,1800mm (1.7000in) by 82,5500mm (3.2500in), and the board thickness is
1,5748mm (0.062in). Figure 3 through Figure 7 show the individual artwork layers.
Note: Board layouts are not to scale. These are intended to show how the board is laid out; they
are not intended to be used for manufacturing DAC8554EVM PCBs.
DAC8554EVM User's Guide4 SBAU121 – January 2006
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Figure 2. DAC8554EVM PCB—Top Silkscreen Image
PCB Design and Performance
Figure 3. DAC8554EVM PCB—Layer 1 (Top Signal Layer)
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PCB Design and Performance
Figure 4. DAC8554EVM PCB—Layer 2 (Ground Plane)
Figure 5. DAC8554EVM PCB—Layer 3 (Power Plane)
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Figure 6. DAC8554EVM PCB—Layer 4 (Bottom Signal Layer)
PCB Design and Performance
Figure 7. DAC8554EVM PCB—Bottom Silkscreen Image
SBAU121 – January 2006 DAC8554EVM User's Guide 7
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400mil
47.5mil
2700mil
3250mil
1300mil
1700mil
1247.5mil 1247.5mil
Notes:
1. PWB to be fabricated to meet or exceed IPC-6012
Class 3 standards and workmanship shall conform
to IPC-A-600, Class 3 - current revisions.
2. Board material and construction to be UL-Approved
and marked on the finished board.
3. Laminate material: Copper-Clad FR-4.
4. Copper weight: 1 oz. finished, all layers.
5. Finished thickness: .062 ±.010.
6. Min plating thickness in through holes: .001in.
7. SMOBC / HASL.
8. LPI soldermask both sides using appropriate
layer artwork, color = green.
9. LPI silkscreen as required: color = white.
10. Vendor information to be incorporated on back side
whenever possible.
11. Minimum copper conductor width is: 7 mils.
Minimum conductor spacing is: 7 mils.
12. Number of finished layers: 4.
13. Board dimensions: 3.250 in x 1.7 in.
50 15mil 0.381 mm PTH
43 23.622mil 0.6mm PTH
42 39.37mil 1mm PTH
5 40mil 1.016mm PTH
6 47.244mil 1.2mm PTH
1 63mil 1.6002mm PTH
147 total
PCB Design and Performance
Figure 8. DAC8554EVM—Drill Drawing
2.2 EVM Performance
The EVM performance test is executed using a high-density DAC bench test board, an Agilent 3458A
digital multimeter and a PC running LabVIEW™ software. The EVM board is tested for linearity for all
codes between 485 and 64741. The DUT is then allowed to settle for 1ms before the meter is read. This
process is repeated for all codes to generate the measurements for INL and DNL.
Results of the DAC8554EVM tests are shown in Figure 9 through Figure 12 .
DAC8554EVM User's Guide8 SBAU121 – January 2006
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PCB Design and Performance
Figure 9. INL and DNL Characterization Graph of DAC A
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PCB Design and Performance
Figure 10. INL and DNL Characterization Graph of DAC B
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PCB Design and Performance
Figure 11. INL and DNL Characterization Graph of DAC C
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PCB Design and Performance
Figure 12. INL and DNL Characterization Graph of DAC D
12 DAC8554EVM User's Guide SBAU121 – January 2006
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2.3 Bill of Materials
PCB Design and Performance
The parts list, showing the components used in the assembly of the DAC8554EVM, is given in Table 1 .
Table 1. DAC8554EVM Parts List
ITEM BOARD Ref Des MFR PART NUMBER DESCRIPTION
Installed
Installed
Installed
Installed
Installed TP5, TP6
QTY PER MFR
1 4 R11–R14 Panasonic ERJ-3GEY0R00V Chip Resistor, 0 Ω , 1/10W, 0603
2 1 R24 Panasonic ERJ-8GEYJ101V Chip Resistor, 100 Ω , 1/4W, 1206
Not
3 7 Panasonic ERJ-3EKF1002V Chip Resistor, 10k Ω , 1/16W, 0603
4 1 R16 Panasonic ERJ-3EKF2002V Chip Resistor, 20k Ω , 1/16W, 0603
5 1 R10 Bourns 3214W-1-203E Series 5T Pot., 20k Ω , BOURNS_32X4W
6 1 R15 Bourns 3214W-1-104E Series 5T Pot., 100k Ω , BOURNS_32X4W
Not
7 1 C12 TDK C1608C0G1H102J Multilayer Ceramic Capacitor, 1nF, 0603 C0G
8 4 C4–C7 TDK C1608X7R1E104K Multilayer Ceramic Capacitor, 0.1 µ F, 0603 X7R
9 2 C10, C11 TDK C2012X7R1E105K Multilayer Ceramic Capacitor, 1 µ F, 0805 X7R
10 3 C1, C2, C3 TDK C3216X7R1C106M Multilayer Ceramic Capacitor, 10 µ F, 1206 X7R
Not
11 1 U1 Texas Instruments DAC8554IPW
12 1 U2 Texas Instruments OPA627AU 8-SOP(D) Precision Op Amp
13 1 U3 Texas Instruments REF02AU +5V, 8-SOP(D) Precision Voltage Reference
14 1 U4 Texas Instruments OPA2132UA 8-SOP(D) Dual Precision Op Amp
Not
15 2 J2A, J4A Samtec TSM-110-01-L-DV-P
16 1 J3A Samtec TSM-105-01-L-DV-P
17 2 J2B, J4B Samtec SSW-110-22-F-D-VS-K
18 1 J3B Samtec SSW-105-22-F-D-VS-K
19 6 JMP1–JMP6 Samtec TSW-102-07-G-S 2-position Jumper_ .1in spacing
20 10 JMP7–JMP16 Samtec TSW-103-07-G-S 3-position Jumper_ .1in spacing
21 1 TP4 Keystone Electronics 5011 Testpoint, Large-Loop
Not TP1, TP2, TP3,
22 16 N/A Samtec SNT-100-BK-G-H Shorting Block
2 R5, R6 Panasonic ERJ-3GEYJ302V Chip Resistor, 3k Ω , 1/10W, 0603
R1–R4, R7, R8,
R9
7 R17–R23 Panasonic Chip Resistor, 1/4W 1206
2 C8, C9 TDK Multilayer Ceramic Capacitor, 1206
16-bit, Quad Voltage Output, Serial Input DAC,
TSSOP-16
2 J1, J5 On-Shore Technology ED555/3DS 3-Pin Terminal Connector
SMT Header, 10x2x0.1, 20-pin, .025in
SMT Header, 5x2x0.1, 10-pin, .025in
SMT Socket, 10x2x0.1, 20-pin, .025in
SMT Socket, 5x2x0.1, 10-pin, .025in
5 Keystone Electronics 5000 Testpoint, Mini-Loop
2
2
2
2
SBAU121 – January 2006 DAC8554EVM User's Guide 13
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EVM Operation
3 EVM Operation
3.1 Default Settings
This section covers the operation of the EVM in detail, in order to provide guidance to the user in
evaluating the onboard DAC as well as how to interface the EVM to a specific host processor. Refer to the
DAC8554 datasheet for information about its serial interface and other related topics. The EVM board is
factory-tested and configured.
The EVM is set to its factory default configuration as described in Table 2 to operate in 5V mode.
Table 2. Factory Default Jumper Settings
Reference Jumper Position Function
JMP1 CLOSE ENABLE pin is tied to DGND
JMP2 CLOSE LDAC pin is tied to DGND. Software LDAC is used.
JMP3 CLOSE A1 pin is tied to DGND.
JMP4 CLOSE A0 pin is tied to DGND.
V
H is not routed to the inverting input of the op amp for voltage offset with
JMP5 OPEN
JMP6 OPEN Output op amp U2 is not configured for a gain of 2.
JMP7 1-2 Analog supply for the DAC8554 is +5V
JPM8 1-2 Onboard external buffered reference U3 is routed to V
JMP9 1-2 V
JMP10 1-2 Negative supply rail of U2 op amp is supplied with VSS.
JMP11 1-2 DAC output A (V
JMP12 1-2 DAC output B (V
JMP13 1-2 DAC output C (V
JMP14 1-2 DAC output D (V
JMP15 1-2 J4-1 is connected to the noninverting input of the output op amp U2.
JMP16 1-2 J4-5 is connected to the output of the op amp U2.
gain of 2 output.
REF
.
A
H.
REF
L is tied to AGND.
REF
A) is routed to J4-2.
OUT
B) is routed to J4-4.
OUT
C) is routed to J4-6.
OUT
D) is routed to J4-8.
OUT
3.2 Host Processor Interface
The host processor drives the DAC. Thus, proper DAC operation depends on a successful configuration
between the host processor and the EVM board. In addition, properly written code is also required to
operate the DAC.
As discussed earlier, a custom cable can be made specific to the host interface platform. The EVM allows
interface to the host processor through header connector J2 for the serial control signals and the serial
data input. The output can be monitored through header connector J4.
An interface adapter card is also available for specific TI DSP DSKs as well as an MSP430-based
microprocessor (see Section 1.3 of this manual). Using the interface card alleviates the tedious task of
building customized cables and allows easy configuration of a simple evaluation system.
The DAC8554 interfaces with any host processor capable of handling SPI protocols or the popular TI
DSPs. For more information regarding the DAC8554 data interface, please refer to the DAC8554
datasheet .
3.3 EVM Stacking
Stacking multiple EVMS is possible if there is a need to evaluate two DAC8554s, yielding a total of eight
output channels. A maximum of two EVMs can be stacked since the output terminal, J4, dictates the
number of DAC channels that can be connected without colliding. Table 3 shows how the DAC output
channels are mapped into the output terminal, J4, with respect to the jumper positions of JMP11, JMP12,
JMP13, and JMP14.
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In order to allow exclusive control of each EVM, different addresses must be selected for each DAC8554.
This differentiation is accomplished by using JMP3 and JMP4 on the EVM. When sending data to the
DAC8554, the address in the command byte must match the address of the device to be controlled.
LDAC, SYNC and ENABLE control signals are shared. The DAC8554 only responds when the correct
address is given.
The raw outputs of the DAC can be probed through the even numbered pins of J4, the output terminal,
which also provides mechanical stability when stacking or plugging into any interface card. In addition, it
provides easy access for monitoring up to eight DAC channels when stacking two EVMs together.
3.4 Output Op Amp
The DAC8554EVM includes an optional signal conditioning circuit for the DAC output through an external
operational amplifier, U2. The output op amp is set to unity gain configuration by default. Only one DAC
output channel can be monitored at any given time. JMP15 selects which pin of J4 is the input. Either J4-1
or J4-3 can be used as the op amp signal input. The default setting for JMP15 selects J4-1. A shorting
jumper can be placed between one of the DAC outputs and the op amp input. For example, a jumper
across J4-1 and J4-2 places the DAC A output as the input for the op amp if board jumpers are in the
default position. If JMP15 is in the alternate position, then a shorting block between J4-3 and J4-2 makes
the DAC B output the input to the op amp.
The output of U2 passes through JMP16. In the default position, the output connects to J4-5. When
JMP16 is in the alternate position, the output from U2 connects to J4-7. The output can be monitored
from, or passed to, another device from the J4 connector.
The jumper arrangement of JMP15 and JMP16 connecting to J4 allows U2 to be used in the stacked
board arrangement discussed above in Section 3.3 .
The following subsections describe the different configurations of the output amplifier, U2.
Table 3. DAC Output Channel Mapping
Reference Jumper Position Function
JMP11
JMP12
JMP13
JMP14
1-2 DAC output A (V
2-3 DAC output A (V
1-2 DAC output B (V
2-3 DAC output B (V
1-2 DAC output C (V
2-3 DAC output C (V
1-2 DAC output D (V
2-3 DAC output D (V
A) is routed to J4-2.
OUT
A) is routed to J4-10.
OUT
B) is routed to J4-4.
OUT
B) is routed to J4-12.
OUT
C) is routed to J4-6.
OUT
C) is routed to J4-14.
OUT
D) is routed to J4-8.
OUT
D) is routed to J4-16.
OUT
EVM Operation
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EVM Operation
3.4.1 Unity Gain Output
The buffered output configuration can be used to prevent loading of the DAC8554, though it may add
some slight distortion because of the feedback resistor and capacitor. The feedback circuit can be altered
by simply desoldering R8 and C12 and replacing them with components of desired value. If desired, R8
and C12 can be removed altogether by replacing R8 with a 0 Ω resistor.
Table 4 shows the jumper setting for the unity gain configuration of the DAC external output buffer in
unipolar or bipolar mode.
Reference Unipolar Bipolar Function
JMP5 Open Open
JMP10 2-3 1-2
JMP6 Open Open
3.4.2 Output Gain of 2
There are two types of configurations that will yield an output gain of 2, depending on the setup of jumpers
JMP5 and JMP6. These configurations allow the user to choose whether the DAC output will use V
as an offset. Table 5 shows the proper jumper settings of the EVM for the DAC8554 output gain of 2.
Table 4. Unity Gain Output Jumper Settings
Jumper Setting
Disconnect V
amp.
Supplies V
ties it to AGND.
Disconnect negative input of op amp from the gain
resistor, R9.
H from the inverting input of the op
REF
to the negative rail of the op amp or
SS
H
REF
Table 5. Output Gain of 2 Jumper Settings
Jumper Setting
Reference Unipolar Bipolar Function
Close Close connected to V
JMP5
Open Open
JMP10 2-3 1-2 U2 for bipolar mode, or ties it to AGND for unipolar
Close Close
JMP6
Open Open
Inverting input of the output op amp U2 is
with a gain of 2. JMP6 must be open.
V
H is disconnected from the inverting input of
REF
the output op amp U2. JMP6 must be closed.
Supplies power, VSS, to the negative rail of op amp
mode.
Configures op amp U2 for a gain of 2 output
without a voltage offset. JMP5 must be open.
Inverting input of op amp U2 is disconnected from
the gain resistor, R9. JMP5 must be closed.
H for use as its offset voltage
REF
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3.4.3 Capacitive Load Drive
It may be required to drive a wide range of capacitive loads. However, under certain conditions, all op
amps may become unstable, depending on the op amp configuration, gain, and load value. These factors
are just few of the issues that can affect op amp stability and should be considered during implementation.
In unity gain configuration, the OPA627 op amp (U2) performs very well with very large capacitive loads.
Increasing the gain enhances amplifier ability to drive even more capacitance, and adding a load resistor
even improves the capacitive load drive capability.
Table 6 shows the jumper setting configuration for a capacitive load drive.
Table 6. Capacitive Load Drive Output Jumper Settings
Jumper Setting
Reference Unipolar Bipolar Function
JMP5 Open Open
JMP10 2-3 1-2 U2 for bipolar mode, or ties it to AGND for unipolar
JMP6 Open Open
3.5 Optional Signal Conditioning Op-Amp (U4B)
One half of the OPA2132 dual package op amp (U4) is used for reference buffering (U4A), while the other
half is unused. This unused op amp (U4B) is left for whatever op amp circuit application the user desires
to implement. The 1206 footprint for the resistors and capacitors surrounding the U4B op amp are not
populated and are made available for easy configuration. Test points TP5 and TP6 are not installed, so it
is up to the user on how to connect the ( ± ) input signals to this op amp. No test point has been made
available for the output because of space restrictions, but a wire can be soldered to the output of the op
amp via an unused component pad that connects to it. The op amp circuit can be configured by populating
the corresponding components to those that match the circuit design while leaving all other unused
component footprints unpopulated.
EVM Operation
V
H is disconnected from the inverting input of
REF
the output op amp U2.
Supplies power, VSS, to the negative rail of op amp
mode.
Capacitive load drive output of DAC is routed to pin
2 of JMP6 and may be used as the output terminal.
3.6 Jumper Settings
Table 7 shows the function of each specific jumper setting of the EVM.
Table 7. Jumper Settings and Functions
Reference Jumper Setting
JMP1
JMP2
JMP3
(1)
Indicates the corresponding pins that are shorted or closed.
SBAU121 – January 2006 DAC8554EVM User's Guide 17
(1)
Function
EN pin is set high through pull-up resistor R1. EN can be driven by
GPIO2, J2-8.
EN pin is set low and DAC is enabled.
LDAC pin is set high through pull-up resistor R2. LDAC can be driven by
GPIO0, J2-2.
LDAC pin is set low and DAC update is accomplished via software.
A1 pin is set high through pull-up resistor R3. A1 can be driven by GPIO4,
J2-14.
A1 pin is set low.
www.ti.com
1 3
1 3
1 3
1 3
1 3
1 3
1 3
1 3
1 3
1 3
EVM Operation
Table 7. Jumper Settings and Functions (continued)
Reference Jumper Setting
JMP4
(1)
Function
A0 pin is set high through pull-up resistor R4. A0 can be driven by GPIO5,
J2-19.
A0 pin is set low.
Disconnects V
H to the inverting input of the op amp U2.
REF
JMP5
Connects V
H to the inverting input of the op amp U2.
REF
Disconnects the inverting input of the op amp U2 from the gain resistor,
R9.
JMP6
Connects the inverting input of the op amp U2 from the gain resistor, R9
for output gain of 2.
+5V analog supply is selected for AV
.
DD
JMP7
+3.3V analog supply is selected for AV
Routes the adjustable, buffered, onboard +5V reference to the V
input of the DAC8554.
.
DD
H
REF
JMP8
Routes the user-supplied reference from TP2 or J4-20 to the V
of the DAC8554.
V
L is tied to AGND.
REF
H input
REF
JMP9
Routes the user-supplied negative reference from TP3 or J4-18 to the
V
L input of the DAC8554. This voltage should be within the range of
REF
0V to V
H.
REF
Negative supply rail of the op amp U2 is powered by VSSfor bipolar
operation.
JMP10
Negative supply rail of the op amp U2 is tied to AGND for unipolar
operation.
Routes V
A to J4-2.
OUT
JMP11
Routes V
A to J4-10.
OUT
DAC8554EVM User's Guide18 SBAU121 – January 2006
www.ti.com
1 3
1 3
1 3
1 3
1 3
1 3
1 3
1 3
1 3
1 3
Table 7. Jumper Settings and Functions (continued)
Reference Jumper Setting
EVM Operation
(1)
Function
Routes V
JMP12
Routes V
Routes V
JMP13
Routes V
Routes V
JMP14
Routes V
Routes J4-1 to U2 noninverting input.
JMP15
Routes J4-3 to U2 noninverting input.
B to J4-4.
OUT
B to J4-12.
OUT
C to J4-6.
OUT
C to J4-14.
OUT
D to J4-8.
OUT
D to J4-16.
OUT
Routes U2 output to J4-5.
JMP16
Routes U2 output to J4-7.
SBAU121 – January 2006 DAC8554EVM User's Guide 19
www.ti.com
Schematic
4 Schematic
DAC8554EVM User's Guide20 SBAU121 – January 2006
REV ENGINEERING CHANGE NUMBER APPROVED
JMP7
VDD
D
R1
10KR210KR310KR410KR5NIR6NI
+5VA
C5
0.1uFC210uF
LDAC
ENABLE
A1
A0
SDI
JMP2
JMP1
1 2
C
B
A
1 2
VCC
C1
10uFC40.1uF
U3
2
3
VCC VSS+5VA -5VA VDD+3.3VD +1.8VD +3.3VA
JMP4
JMP3
1 2
1 2
VIN
TEMP
J3A (TOP) = SAM_TSM-105-01-L-DV-P
J3B (BOTTOM) = SAM_SSW-105-22-F-D-VS-K
GND
REF02AU
4
1
J3
1
+VA
3
+5VA
5
DGND
7
+1.8VD
9
+3.3VD
DAUGHTER-POWER
VOUT
TRIM
R10 20K
AGND
+5VD
-5VA
VD1
SCLK
SYNC
6
5
2
3
2
-VA
4
6
8
10
123
3
1
R16
20k
AVDD
R11 0
R12 0
TP1
REF OUT
R15
2
100K
+3.3VA
4
16
15
14
13
11
10
9
6
VCC
C6
0.1uF
84
3
2
R13
0
VCC = +15V Analog
VDD = +2.7V to +5.0V Digital
VSS = 0V to -15V Analog
U1
AVDD
LDAC
ENABLE
A1
A0
Din
SCLK
SYNC
GND
DAC8554IPW
1
U4A
OPA2132UA
IO_V/DVDD
VrefH
VrefL
VoutA
VoutB
VoutC
VoutD
JMP8
JMP9
1
2
3
3
2
1
J1
12
3
5
1
2
7
8
+REFin
-REFin
1
VSS
VDD
C7
0.1uFC310uF
VrefH
VrefL
OUT_A
OUT_B
OUT_C
OUT_D
VrefH
TP2
EXTERNAL
REFERENCE
TP3
NOTE: Voltage range of -REFin input should not exceed
0 - VrefH.
VrefL
TP4
AGND
J5
2
3
VCC VDD
1
VCC
C11
1uF
71
R14
U2_+IN
123
JMP15
OPA IN
J4
2
A0(+)
4
JMP11
1
2
3
OUT A
R19 NI
R20 NI
-REFin
+REFin
JMP12
1
2
3
OUT B
JMP13
1
2
3
OUT C
JMP14
1
2
3
OUT D
R18
TP5
+Vin
TP6
-Vin
2
3
+5VA
NI
R21
NI
A1(+)
6
A2(+)
8
A3(+)
10
A4
12
A5
14
A6
16
A7
18
REF-
20
REF+
OUTPUT HEADER
J4A (TOP) = SAM_TSM-110-01-L-DV-P
J4B (BOTTOM) = SAM_SSW-110-22-F-D-VS-K
C8
NI
R17
NI
5
6
U4B
OPA2227UA
R22
NI
C9
NI
A0(-)
A1(-)
A2(-)
A3(-)
AGND
AGND
AGND
VCOM
AGND
AGND
7
1
3
5
7
9
11
13
15
17
19
R23
NI
JMP5
1 2
R7
10K
VrefH
123
JMP16
OPA OUT
ENGINEER
DRAWN BY
DOCUMENT CONTROL NO.
SHEET OF FILE
3
0
U2_-IN
2
C10
1uF
JMP6
J2
1
SCLK
3
5
SYNC
7
9
SDI
11
13
15
17
A0
19
DAUGHTER-SERIAL
J2A (TOP) = SAM_TSM-110-01-L-DV-P
J2B (BOTTOM) = SAM_SSW-110-22-F-D-VS-K
R. BENJAMIN
R. BENJAMIN
1 1 C:\WORK\DAC8554EVM\SCH\DAC8554 EVM.SCH
6457377
CNTL
CLKX
CLKR
FSX
FSR
DX
DR
INT
TOUT
GPIO5
U2
OPA627AU
5
4
R8
10K
12
VSS
123
JMP10
C12
1nF
R9
10K
GPIO0
DGND
GPIO1
GPIO2
DGND
GPIO3
GPIO4
SCL
DGND
SDA
TITLE
SIZE
B
REVISION HISTORY
U2_OUT
6
LDAC
2
4
6
ENABLE
8
10
12
A1
14
16
18
20
R24
100
ti
DATA ACQUISITION PRODUCTS
HIGH-PERFORMANCE ANALOG DIVISION
SEMICONDUCTOR GROUP
6730 SOUTH TUCSON BLVD., TUCSON, AZ 85706 USA
DAC8554EVM
DATE REV
A6-Oct-2005
D
C
B
A
www.ti.com
Schematic
FCC Warnings
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can radiate radio frequency
energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules,
which are designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which case the user at his own expense will be required to
take whatever measures may be required to correct this interference.
EVM TERMS AND CONDITIONS
Texas Instruments (TI) provides the enclosed Evaluation Module and related material (EVM) to you, the user, (you or user)
SUBJECT TO the terms and conditions set forth below. By accepting and using the EVM, you are indicating that you have read,
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AND CONDITIONS, YOU MUST RETURN THE EVM AND NOT USE IT.
This EVM is provided to you by TI and is intended for your INTERNAL ENGINEERING DEVELOPMENT OR EVALUATION
PURPOSES ONLY. It is provided “AS IS” and “WITH ALL FAULTS.” It is not considered by TI to be fit for commercial use. As
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Should this EVM not meet the specifications indicated in the EVM User’s Guide, it may be returned within 30 days from the date of
delivery for a full refund of any amount paid by user for the EVM, which user agrees shall be user’s sole and exclusive remedy.
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claims. User shall indemnify and hold TI harmless against any damages, liabilities or costs resulting from any claim, suit or
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User assumes all responsibility and liability for proper and safe handling and use of the EVM and the evaluation of the EVM. TI
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TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
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User agrees to read the EVM User’s Guide and, specifically, the EVM warnings and Restrictions notice in the EVM User’s Guide
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It is user’s responsibility to ensure that persons handling the EVM and the product have electronics training and observe good
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By providing user with this EVM, product and services, TI is NOT granting user any license in any patent or other intellectual
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EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of –15.75V to +15.75V and the output voltage range of –15V to
+15V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are
questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the
EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load
specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than +60 ° C. The EVM is designed to
operate properly with certain components above +60 ° C as long as the input and output ranges are maintained. These components
include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of
devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near
these devices during operation, please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2006, Texas Instruments Incorporated
SBAU121 – January 2006 DAC8554EVM User's Guide 21
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