TEXAS INSTRUMENTS DAC7612 Technical data

®

DAC7612

DAC7612

Dual, 12-Bit Serial Input

DIGITAL-TO-ANALOG CONVERTER

FEATURES

● LOW POWER: 3.7mW

● FAST SETTLING: 7µs to 1 LSB

● 1mV LSB WITH 4.095V FULL-SCALE

RANGE

● COMPLETE WITH REFERENCE

● 12-BIT LINEARITY AND MONOTONICITY

OVER INDUSTRIAL TEMP RANGE

● 3-WIRE INTERFACE: Up to 20MHz Clock

● SMALL PACKAGE: 8-Lead SOIC

APPLICATIONS

● PROCESS CONTROL

● DATA ACQUISITION SYSTEMS

● CLOSED-LOOP SERVO-CONTROL

● PC PERIPHERALS

● PORTABLE INSTRUMENTATION

12-Bit DAC A

LOADDACS

DAC Register A

DESCRIPTION

The DAC7612 is a dual, 12-bit digital-to-analog con­verter (DAC) with guaranteed 12-bit monotonicity
performance over the industrial temperature range. It
requires a single +5V supply and contains an input
shift register, latch, 2.435V reference, a dual DAC, and
high speed rail-to-rail output amplifiers. For a full­scale step, each output will settle to 1 LSB within 7µs
while only consuming 3.7mW.

The synchronous serial interface is compatible with a
wide variety of DSPs and microcontrollers. Clock
(CLK), Serial Data In (SDI), Chip Select (CS) and
Load DACs (LOADDACS) comprise the serial inter­face.

The DAC7612 is available in an 8-lead SOIC package
and is fully specified over the industrial temperature
range of –40°C to +85°C.

V

DD

V

12

OUTA

SBAS106

CS

CLK

SDI

DAC7612

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: [phone]

Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: [phone] • Immediate Product Info: [phone]

© 1999 Burr-Brown Corporation PDS-1501A Printed in U.S.A. June, 1999

14-Bit Serial Shift Register

12

12

DAC Register B

12

12-Bit DAC B

GND

Ref

V

OUTB

SPECIFICATIONS

At TA = –40°C to +85°C, and VDD = +5V, unless otherwise noted.

DAC7612U DAC7612UB

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
RESOLUTION 12 ✻ Bits

ACCURACY

Relative Accuracy
Differential Nonlinearity Guaranteed Monotonic –1 ±1/2 +1 –1 ±1/4 +1 LSB
Zero-Scale Error Code 000
Zero Scale Match Code 000
Full-Scale Voltage Code FFF
Full-Scale Match Code FFF

ANALOG OUTPUT

Output Current Code 800
Load Regulation R
Capacitive Load No Oscillation 500 ✻ pF
Short-Circuit Current ±15 ✻ mA
Short-Circuit Duration GND or V

DIGITAL INPUT

Data Format Serial ✻
Data Coding Straight Binary ✻
Logic Family CMOS ✻
Logic Levels

V

IH

V

IL

I

IH

I

IL

DYNAMIC PERFORMANCE

Settling Time
DAC Glitch 2.5 ✻ nV-s
Digital Feedthrough 0.5 ✻ nV-s

POWER SUPPLY

V

DD

I

DD

Power Dissipation V
Power Supply Sensitivity ∆V

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻°C

(1)

H
H
H
H

≥ 402Ω, Code 800

LOAD

H

H

DD

–2 ±1/2 +2 –1 ±1/4 +1 LSB

–1 +1 +3 ✻✻✻ LSB

1/2 1/2 2 LSB

4.079 4.095 4.111 4.087 4.095 4.103 V
1/2 1/2 2 LSB

±5 ±7 ✻✻ mA

13 ✻✻ LSB

Indefinite ✻

0.7 • V

DD

0.3 • V

±10 ✻ µA

✻ V

DD

✻ V

±10 ✻ µA

(2)

(tS) To ±1 LSB of Final Value 7 ✻ µs

+4.75 +5.0 +5.25 ✻✻✻ V

VIH = 5V, VIL = 0V, No Load, at Code 000

= 5V, VIL = 0V, No Load 3.5 7.5 ✻✻ mW

IH

= ±5% 0.0025 0.002 ✻✻%/%

DD

H

0.75 1.5 ✻✻ mA

✻ Same specification as for DAC7612U.
NOTES: (1) This term is sometimes referred to as Linearity Error or Integral Nonlinearity (INL). (2) Specification does not apply to negative-going transitions where

the final output voltage will be within 3 LSBs of ground. In this region, settling time may be double the value indicated.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

®

DAC7612

2

PIN CONFIGURATION

PIN DESCRIPTIONS

Top View SO-8

1

SDI

2

CLK

LOADDACS

CS

DAC7612U

3
4

ABSOLUTE MAXIMUM RATINGS

VDD to GND .......................................................................... –0.3V to 6V

Digital Inputs to GND .............................................. –0.3V to V

to GND ...........................................................–0.3V to VDD + 0.3V

V

OUT

Power Dissipation ........................................................................ 325mW

Thermal Resistance,

Maximum Junction Temperature.................................................. +150°C

Operating Temperature Range ...................................... –40°C to +85°C

Storage Temperature Range ....................................... –65 °C to +150°C

Lead Temperature (soldering, 10s) .............................................. +300°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.

θ

........................................................... 150°C/W

JA

V

8

OUTA

V

7

DD

GND

6

V

5

OUTB

(1)

+ 0.3V

DD

PIN LABEL DESCRIPTION

1 SDI Serial Data Input. Data is clocked into the internal

2 CLK Synchronous Clock for the Serial Data Input.
3 LOADDACS Loads the internal DAC registers. All DAC registers

4 CS Chip Select. Active LOW.
5V
6 GND Ground
7V
8V

OUTB

OUTA

serial register on the rising edge of CLK.

are transparent latches and are transparent when
LOADDACS is LOW (regardless of the state of CS
or CLK).

DAC B Output Voltage

Positive Power Supply

DD

DAC A Output Voltage

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.

ESD damage can range from subtle performance degrada­tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.

PACKAGE/ORDERING INFORMATION

MINIMUM

RELATIVE DIFFERENTIAL SPECIFICATION PACKAGE

PRODUCT (LSB) (LSB) RANGE PACKAGE NUMBER

ACCURACY NONLINEARITY TEMPERATURE DRAWING ORDERING TRANSPORT

DAC7612U ±2 ±1 –40°C to +85°C SO-8 182 DAC7612U Rails

"" " " ""DAC7612U/2K5 Tape and Reel

DAC7612UB ±1 ±1 –40°C to +85°C SO-8 182 DAC7612UB Rails

"" " " ""DAC7612UB/2K5 Tape and Reel

NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “DAC7612U/2K5” will get a single
2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.

(1)

NUMBER

(2)

MEDIA

®

3

DAC7612

EQUIVALENT INPUT LOGIC

LOADDACS

SDI

CS

CLK

ESD protection

diodes to V

and GND

DD

DAC Switches

12

DAC B Register

12

Data

Serial Shift Register

12

DAC A Register

12

DAC Switches

®

DAC7612

4

TIMING DIAGRAMS

SDI

CLK

t

CL

t

CH

t

DH

t

DS

SDI

CLK

CS

LOADDACS

(MSB) (LSB)

A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A1

t

CSS

t

LD1

t

CSH

t

LD2

t

LDW

LOADDACS

t

FS

V

OUT

ZS

S

±1 LSB
Error Band

LOGIC TRUTH TABLE TIMING SPECIFICATIONS

A1 A0

LOADDACS

REGISTER REGISTER A REGISTER B

CLK

CS

X X X H H No Change No Change No Change

SERIAL SHIFT DAC DAC

XX
LXXH

↑

L H Shifts One Bit No Change No Change

(1)

L No Change Loads Serial Loads Serial

Data Word Data Word

H L X H L No Change Loads Serial No Change

Data Word

H H X H L No Change No Change Loads Serial

Data Word

↑ Positive Logic Transition; X = Don’t Care.

NOTE: (1) A HIGH value is suggested in order to avoid to “false clock” from
advancing the shift register and changing the DAC voltage.

DATA INPUT TABLE

B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13
A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

TA = –40°C to +85°C and VDD = +5V.

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t

t

t
t
t

t

CH

t

CL

LDW

t

DS

t

DH
LD1
LD2

CSS
CSH

Clock Width HIGH 30 ns

Clock Width LOW 30 ns
Load Pulse Width 20 ns

Data Setup 15 ns

Data Hold 15 ns

Load Setup 15 ns

Load Hold 10 ns

Select 30 ns

Deselect 20 ns

NOTE: All input control signals are specified with t
of +5V) and timed from a voltage level of 2.5V. These parameters are
guaranteed by design and are not subject to production testing.

= tF = 5ns (10% to 90%

R

5

DAC7612

®

TYPICAL PERFORMANCE CURVES

At TA = +25°, and VDD = 5V, unless otherwise specified.

5

OUTPUT SWING vs LOAD

4

3

RL tied to GND

Data = FFF

H

2

Output Voltage (V)

1

RL tied to V

Data = 000

DD

H

0

10 100 1k 10k 100k

Load Resistance (Ω)

BROADBAND NOISE

Noise Voltage (500µV/div)

Time (2ms/div)

Code = FFF

, BW = 1MHz

H

PULL-DOWN VOLTAGE vs OUTPUT SINK CURRENT

1k

100

10

(mV)

OUT

Delta V

+25°C

1

+85°C

–40°C

0.1
Data = 000

0.01

0.001 0.01 0.1 1 10 100
Current (mA)

SUPPLY CURRENT vs LOGIC INPUT VOLTAGE

4.0

3.5

3.0

2.5

2.0

1.5

Supply Current (mA)

1.0

0.5
0

012345

Logic Voltage (V)

H

70

POWER SUPPLY REJECTION vs FREQUENCY

60

50

Data = FFF
VDD = 5V
±200mV AC

40

30

PSR (dB)

20

10

0

10 100 1k 10k 100k 1M

Frequency (Hz)

®

DAC7612

5.0

MINIMUM SUPPLY VOLTAGE vs LOAD

H

4.8

4.6

Minimum (V)

4.4

DD

V

4.2

4.0

0.01 0.1 1 10
Output Load Current (mA)

6

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25°, and VDD = 5V, unless otherwise specified.

SHORT-CIRCUIT CURRENT vs OUTPUT VOLTAGE

20
15
10

5

Positive
Current

Limit

Data = 800

Output tied to I

SOURCE

0

–5

Output Current (mA)

–10
–15

Negative

Current

Limit

–20

01 423 56

Output Voltage (V)

MIDSCALE GLITCH PERFORMANCE

LOADDACS

2.0

SUPPLY CURRENT vs TEMPERATURE

V

= 3.5V

LOGIC

1.8
Data = FFF

1.6

No Load

H

1.4

1.2

1.0

0.8

0.6

Supply Current (mA)

0.4

At worst-case digital inputs.

0.2

H

VDD = 5.25V

VDD = 4.75V

VDD = 5.0V

0

–50 –30 –10 10 30 50 70 90 110 130

Temperature (°C)

MIDSCALE GLITCH PERFORMANCE

LOADDACS

(5mV/div)

OUT

V

(1V/div)

OUT

V

7FFH to 800

Time (500ns/div)

LARGE-SIGNAL SETTLING TIME

CL = 100pF
R

LOADDACS

Time (20µs/div)

H

= No Load

L

(5mV/div)

OUT

V

LOADDACS

(1mV/div)

OUT

V

Time (500ns/div)

RISE TIME DETAIL

Time (10µs/div)

800H to 7FF

CL = 100pF

R

= No Load

L

H

®

7

DAC7612

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25°, and VDD = 5V, unless otherwise specified.

FALL TIME DETAIL

CL = 100pF

R

(1mV/div)

OUT

V

LOADDACS

Time (10µs/div)

LONG-TERM DRIFT ACCELERATED BY BURN-IN

5
4
3
2
1

0
–1
–2
–3
–4

Output Voltage Change at FS (mV)

–5

0 168 336 504 672 840 1008

Hours of Operation at +150°C

Max

Avg

Min

= No Load

L

10.000

1.000

0.100

Noise (µV/√Hz)

0.010

35

30

25

20

15

Number of Units

10

OUTPUT VOLTAGE NOISE vs FREQUENCY

Data = FFF

10 100 1k 10k 100k

Frequency (Hz)

TOTAL UNADJUSTED ERROR HISTOGRAM

T.U.E = Σ (INL + ZSE + FSE)

Sample Size = 200 Units

T

= +25°C

A

5

0

–12

–10 –8 –6 –4 –2 0 2 84 6 10 12

H

4.111

4.103

4.095

Full-Scale Output (V)

4.087

4.079

FULL-SCALE VOLTAGE vs TEMPERATURE

Avg + 3σ

Avg

Avg – 3σ

–40 –15 10 35 60 85

Temperature (°C)

®

DAC7612

Zero-Scale Output (mV)

–1

8

3

ZERO-SCALE VOLTAGE vs TEMPERATURE

Avg + 3σ

2

Avg

1

Avg – 3σ

0

–40 –15 10 35 60 85

Temperature (°C)

TYPICAL PERFORMANCE CURVES (CONT)

At TA = +25°, and VDD = 5V, unless otherwise specified.

LINEARITY ERROR vs DIGITAL CODE

2.0

1.5

1.0

0.5
0

–0.5

Linearity Error (LSBs)

–1.0
–1.5
–2.0

0 512 1024 1536 2048 2560 3072 3584 4096

LINEARITY ERROR vs DIGITAL CODE

2.0

1.5

1.0

0.5
0

–0.5

Linearity Error (LSBs)

–1.0
–1.5
–2.0

0 512 1024 1536 2048 2560 3072 3584 4096

(DAC A at +85°C)

Code

(DAC A at +25°C)

Code

LINEARITY ERROR vs DIGITAL CODE

2.0

1.5

1.0

0.5
0

–0.5

Linearity Error (LSBs)

–1.0
–1.5
–2.0

0 512 1024 1536 2048 2560 3072 3584 4096

LINEARITY ERROR vs DIGITAL CODE

2.0

1.5

1.0

0.5
0

–0.5

Linearity Error (LSBs)

–1.0
–1.5
–2.0

0 512 1024 1536 2048 2560 3072 3584 4096

(DAC B at +85°C)

Code

(DAC B at +25°C)

Code

LINEARITY ERROR vs DIGITAL CODE

2.0

1.5

1.0

0.5
0

–0.5

Linearity Error (LSBs)

–1.0
–1.5
–2.0

0 512 1024 1536 2048 2560 3072 3584 4096

(DAC A at –40°C)

Code

LINEARITY ERROR vs DIGITAL CODE

2.0

1.5

1.0

0.5
0

–0.5

Linearity Error (LSBs)

–1.0
–1.5
–2.0

0 512 1024 1536 2048 2560 3072 3584 4096

9

(DAC B at –40°C)

Code

®

DAC7612

OPERATION

The DAC7612 is a dual, 12-bit digital-to-analog converter
(DAC) complete with a serial-to-parallel shift register, DAC
registers, laser-trimmed 12-bit DACs, on-board reference,
and rail-to-rail output amplifiers. Figure 1 shows the basic
operation of the DAC7612.

INTERFACE

Figure 1 shows the basic connection between a
microcontroller and the DAC7612. The interface consists of
a Serial Clock (CLK), Serial Data (SDI), and a Load DAC
signal (LOADDACS). In addition, a chip select (CS) input is
available to enable serial communication when there are
multiple serial devices. Loading either DAC A or DAC B is
done by shifting 14 serial bits in via the SDI input. The first
2 bits represent the address of the DAC to be updated and the

DAC7612 Full-Scale Range = 4.095V
Least Significant Bit = 1mV

DIGITAL INPUT CODE ANALOG OUTPUT
STRAIGHT OFFSETBINARY (V) DESCRIPTION

FFF

H

801

H

800

H

7FF

H

000

H

TABLE I. Digital Input Code and Corresponding Ideal

Analog Output.

+4.095 Full Scale
+2.049 Midscale + 1 LSB
+2.048 Midscale
+2.047 Midscale – 1 LSB

0 Zero Scale

next 12 bits are the code (MSB-first) sent to the DAC. The
data format is Straight Binary and is loaded MSB-first into
the shift registers after loading the address bits. Table I shows
the relationship between input code and output voltage.

The digital data into the DAC7612 is double-buffered. This
means that new data can be entered into the chosen DAC
without disturbing the old data and the analog output of the
converter. At some point after the data has been entered into
the serial shift register, this data can be transferred into the
DAC registers. This transfer is accomplished with a HIGH
to LOW transition of the LOADDACS pin. The LOADDACS
pin makes the DAC registers transparent. If new data is
shifted into the shift register while LOADDACS is LOW,
the DAC output voltages will change as each new bit is
entered. To prevent this, LOADDACS must be returned
HIGH prior to shifting in new serial data.

DIGITAL-TO-ANALOG CONVERTER

The internal DAC section is a 12-bit voltage output
device that swings between ground and the internal ref­erence voltage. The DAC is realized by a laser-trimmed
R-2R ladder network which is switched by N-channel
MOSFETs. Each DAC output is internally connected to a
rail-to-rail output operational amplifier.

OUTPUT AMPLIFIER

A precision, low-power amplifier buffers the output of each
DAC section and provides additional gain to achieve a 0V to

4.095V range. Each amplifier has low offset voltage, low

Serial Data

Serial Clock

Load DACs
Chip Select

FIGURE 1. Basic Operation of the DAC7612.

SDI

1

CLK

2

LOADDACS

3

CS

4

DAC7612U

V

GND

V

OUTA

V

OUTB

8
7

DD

6

5

0V to +4.095V

+

0.1µF

0V to +4.095V

10µF

®

DAC7612

10

noise, and a set gain of 1.682V/V (4.095/2.435). See Figure
2 for an equivalent circuit schematic of the analog portion of
the DAC7612.

The output amplifier has a 7µs typical settling time to ±1
LSB of the final value. Note that there are differences in the
settling time for negative-going signals versus positive­going signals.

The rail-to-rail output stage of the amplifier provides the full­scale range of 0V to 4.095V while operating on a supply voltage
as low as 4.75V. In addition to its ability to drive resistive loads,
the amplifier will remain stable while driving capacitive loads
of up to 500pF. See Figure 3 for an equivalent circuit schematic
of the amplifier’s output driver and the Typical Performance
Curves section for more information regarding settling time,
load driving capability, and output noise.

POWER SUPPLY

A BiCMOS process and careful design of the bipolar and
CMOS sections of the DAC7612 result in a very low power
device. Bipolar transistors are used where tight matching
and low noise are needed to achieve analog accuracy, and
CMOS transistors are used for logic, switching functions
and for other low power stages.

If power consumption is critical, it is important to keep the
logic levels on the digital inputs (SDI, CLK, CS,
LOADDACS) as close as possible to either VDD or ground.
This will keep the CMOS inputs (see “Supply Current vs
Logic Input Voltages” in the Typical Performance Curves)
from shunting current between VDD and ground.

The DAC7612 power supply should be bypassed as shown
in Figure 1. The bypass capacitors should be placed as close
to the device as possible, with the 0.1µF capacitor taking
priority in this regard. The “Power Supply Rejection vs
Frequency” graph in the Typical Performance Curves sec­tion shows the PSRR performance of the DAC7612. This
should be taken into account when using switching power
supplies or DC/DC converters.

In addition to offering guaranteed performance with VDD in
the 4.75V to 5.25V range, the DAC7612 will operate with
reduced performance down to 4.5V. Operation between

4.5V and 4.75V will result in longer settling time, reduced
performance, and current sourcing capability. Consult the
“VDD vs Load Current” graph in the Typical Performance
Curves section for more information.

Buffer

Bandgap

Reference

2.435V

FIGURE 2. Simplified Schematic of Analog Portion.

R-2R DAC

2R

2R

2R

2R

P-Channel

R

R

R

2R

Output Amplifier

R

2

R

1

Typical of DAC A or DAC B

V

DD

FIGURE 3. Simplified Driver Section of Output Amplifier.

N-Channel

11

V

OUT

GND

®

DAC7612

APPLICATIONS

POWER AND GROUNDING

The DAC7612 can be used in a wide variety of situations—
from low power, battery operated systems to large-scale
industrial process control systems. In addition, some appli­cations require better performance than others, or are par­ticularly sensitive to one or two specific parameters. This
diversity makes it difficult to define definite rules to follow
concerning the power supply, bypassing, and grounding.
The following discussion must be considered in relation to
the desired performance and needs of the particular system.

A precision analog component requires careful layout, ad­equate bypassing, and a clean, well-regulated power supply.
As the DAC7612 is a single-supply, +5V component, it will
often be used in conjunction with digital logic,
microcontrollers, microprocessors, and digital signal proces­sors. The more digital logic present in the design and the
higher the switching speed, the more difficult it will be to
achieve good performance.

Because the DAC7612 has a single ground pin, all return
currents, including digital and analog return currents, must
flow through this pin. The GND pin is also the ground

reference point for the internal bandgap reference. Ideally,
GND would be connected directly to an analog ground
plane. This plane would be separate from the ground con­nection for the digital components until they are connected
at the power entry point of the system (see Figure 4).

The power applied to VDD should be well regulated and low­noise. Switching power supplies and DC/DC converters will
often have high-frequency glitches or spikes riding on the
output voltage. In addition, digital components can create
similar high frequency spikes as their internal logic switches
states. This noise can easily couple into the DAC output
voltage through various paths between VDD and V

OUT

.

As with the GND connection, VDD should be connected to
a +5V power supply plane or trace that is separate from the
connection for digital logic until they are connected at the
power entry point. In addition, the 10µF and 0.1µF capaci­tors shown in Figure 4 are strongly recommended and
should be installed as close to VDD and ground as possible.
In some situations, additional bypassing may be required
such as a 100µF electrolytic capacitor or even a “Pi” filter
made up of inductors and capacitors—all designed to essen­tially lowpass filter the +5V supply, removing the high
frequency noise (see Figure 4).

+5V
Power
Supply

+5V

GND

100µF

Optional

Digital Circuits

+5V

GND

+

+

10µF

Analog

Components

Other

0.1µF

DAC7612

V

DD

GND

FIGURE 4. Suggested Power and Ground Connections for a DAC7612 Sharing a +5V Supply with a Digital System.

®

DAC7612

12

PACKAGE OPTION ADDENDUM

www.ti.com

8-Jan-2007

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

DAC7612U ACTIVE SOIC D 8 100 Green (RoHS &

no Sb/Br)

DAC7612U/2K5 ACTIVE SOIC D 8 2500 Green(RoHS &

no Sb/Br)

DAC7612U/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS &

no Sb/Br)

DAC7612UB ACTIVE SOIC D 8 100 Green (RoHS &

no Sb/Br)

DAC7612UB/2K5 ACTIVE SOIC D 8 2500 Green (RoHS &

no Sb/Br)

DAC7612UB/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS &

no Sb/Br)

DAC7612UBG4 ACTIVE SOIC D 8 100 Green (RoHS &

no Sb/Br)

DAC7612UG4 ACTIVE SOIC D 8 100 Green (RoHS &

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

CU NIPDAU Level-3-260C-168 HR

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

11-Mar-2008

*All dimensions are nominal

Device Package

DAC7612U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

DAC7612UB/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Type

Package
Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DAC7612U/2K5 SOIC D 8 2500 346.0 346.0 29.0

DAC7612UB/2K5 SOIC D 8 2500 346.0 346.0 29.0

Pack Materials-Page 2

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