The DAC7612 is a dual, 12-bit digital-to-analog converter (DAC) with guaranteed 12-bit monotonicity
performance over the industrial temperature range. It
requires a single +5V supply and contains an input
shift register, latch, 2.435V reference, a dual DAC, and
high speed rail-to-rail output amplifiers. For a fullscale step, each output will settle to 1 LSB within 7µs
while only consuming 3.7mW.
The synchronous serial interface is compatible with a
wide variety of DSPs and microcontrollers. Clock
(CLK), Serial Data In (SDI), Chip Select (CS) and
Load DACs (LOADDACS) comprise the serial interface.
The DAC7612 is available in an 8-lead SOIC package
and is fully specified over the industrial temperature
range of –40°C to +85°C.
V
DD
V
12
OUTA
SBAS106
CS
CLK
SDI
DAC7612
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Output CurrentCode 800
Load RegulationR
Capacitive LoadNo Oscillation500✻pF
Short-Circuit Current±15✻mA
Short-Circuit DurationGND or V
DIGITAL INPUT
Data FormatSerial✻
Data CodingStraight Binary✻
Logic FamilyCMOS✻
Logic Levels
V
IH
V
IL
I
IH
I
IL
DYNAMIC PERFORMANCE
Settling Time
DAC Glitch2.5✻nV-s
Digital Feedthrough0.5✻nV-s
POWER SUPPLY
V
DD
I
DD
Power DissipationV
Power Supply Sensitivity∆V
TEMPERATURE RANGE
Specified Performance–40+85✻✻°C
(1)
H
H
H
H
≥ 402Ω, Code 800
LOAD
H
H
DD
–2±1/2+2–1±1/4+1LSB
–1+1+3✻✻✻ LSB
1/21/22LSB
4.0794.0954.1114.0874.0954.103V
1/21/22LSB
±5±7✻✻mA
13✻✻ LSB
Indefinite✻
0.7 • V
DD
0.3 • V
±10✻µA
✻V
DD
✻V
±10✻µA
(2)
(tS)To ±1 LSB of Final Value7✻µs
+4.75+5.0+5.25✻✻✻ V
VIH = 5V, VIL = 0V, No Load, at Code 000
= 5V, VIL = 0V, No Load3.57.5✻✻ mW
IH
= ±5%0.00250.002✻✻%/%
DD
H
0.751.5✻✻ mA
✻ Same specification as for DAC7612U.
NOTES: (1) This term is sometimes referred to as Linearity Error or Integral Nonlinearity (INL). (2) Specification does not apply to negative-going transitions where
the final output voltage will be within 3 LSBs of ground. In this region, settling time may be double the value indicated.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
DAC7612
2
PIN CONFIGURATION
PIN DESCRIPTIONS
Top ViewSO-8
1
SDI
2
CLK
LOADDACS
CS
DAC7612U
3
4
ABSOLUTE MAXIMUM RATINGS
VDD to GND .......................................................................... –0.3V to 6V
Digital Inputs to GND .............................................. –0.3V to V
to GND ...........................................................–0.3V to VDD + 0.3V
V
OUT
Power Dissipation ........................................................................ 325mW
Thermal Resistance,
Maximum Junction Temperature.................................................. +150°C
Operating Temperature Range ...................................... –40°C to +85°C
Storage Temperature Range ....................................... –65 °C to +150°C
Lead Temperature (soldering, 10s) .............................................. +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
1SDISerial Data Input. Data is clocked into the internal
2CLKSynchronous Clock for the Serial Data Input.
3LOADDACS Loads the internal DAC registers. All DAC registers
4CSChip Select. Active LOW.
5V
6GNDGround
7V
8V
OUTB
OUTA
serial register on the rising edge of CLK.
are transparent latches and are transparent when
LOADDACS is LOW (regardless of the state of CS
or CLK).
DAC B Output Voltage
Positive Power Supply
DD
DAC A Output Voltage
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “DAC7612U/2K5” will get a single
2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
(1)
NUMBER
(2)
MEDIA
®
3
DAC7612
EQUIVALENT INPUT LOGIC
LOADDACS
SDI
CS
CLK
ESD protection
diodes to V
and GND
DD
DAC Switches
12
DAC B Register
12
Data
Serial Shift Register
12
DAC A Register
12
DAC Switches
®
DAC7612
4
TIMING DIAGRAMS
SDI
CLK
t
CL
t
CH
t
DH
t
DS
SDI
CLK
CS
LOADDACS
(MSB)(LSB)
A0D11D10D9D8D7D6D5D4D3D2D1D0
A1
t
CSS
t
LD1
t
CSH
t
LD2
t
LDW
LOADDACS
t
FS
V
OUT
ZS
S
±1 LSB
Error Band
LOGIC TRUTH TABLETIMING SPECIFICATIONS
A1A0
LOADDACS
REGISTERREGISTER A REGISTER B
CLK
CS
XXXHHNo ChangeNo ChangeNo Change
SERIAL SHIFTDACDAC
XX
LXXH
↑
LHShifts One BitNo ChangeNo Change
(1)
LNo ChangeLoads SerialLoads Serial
Data WordData Word
HLXHLNo ChangeLoads SerialNo Change
Data Word
HHXHLNo ChangeNo ChangeLoads Serial
Data Word
↑ Positive Logic Transition; X = Don’t Care.
NOTE: (1) A HIGH value is suggested in order to avoid to “false clock” from
advancing the shift register and changing the DAC voltage.
NOTE: All input control signals are specified with t
of +5V) and timed from a voltage level of 2.5V. These parameters are
guaranteed by design and are not subject to production testing.
= tF = 5ns (10% to 90%
R
5
DAC7612
®
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