• Function, pinout, and drive compatible with FCT and
F logic
• FCT-D speed at 3.6 ns max. (Com’l FCT244 only),
FCT-C speed at 4.1 ns max. (Com’l),
FCT-A speed at 4.8 ns max. (Com’l)
• Reduced V
FCT functions
(typically = 3.3V) versions of equivalent
OH
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• ESD > 2000V
• Matched rise and fall times
• Fully compatible with TTL input and output logic levels
• Extended commercial range of −40˚C to +85˚C
Logic Block Diagram
FCT240T
OE
A
OE
B
DA
OB
DA
OB
DA
OB
DA
OB
0
0
1
1
2
2
3
3
OA
0
DB
0
OA
1
DB
1
OA
2
DB
2
OA
3
DB
3
FCT240T–1
8-Bit Buffers/Line Drivers
• Sink current64 mA (Com’l), 48 mA (Mil)
Source current32 mA (Com’l), 12 mA (Mil)
Functional Description
The FCT240T and FCT244T are octal buffers and line drivers
designed to be employed as memory address drivers, clock
drivers, and bus-oriented transmitters/receivers. The devices
provide speed and drive capabilities equivalent to their fastest
bipolar logic counterparts while reducing power consumption. The
input and output v oltage levels allow direct interface with TTL,
NMOS, and CMOS devices without e xternal components.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care.
2. Unless otherwise noted, these limits are over the operating free-air temperature range.
3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V
4. T
5. Typical values are at V
6. This parameter is specified but not tested.
7. Not more than one outputshouldbeshorted at a time. Duration ofshort should notexceed one second. The use ofhigh-speedtest apparatus and/or sample
and hold techniques are preferable in order to minimizeinternal chip heatingandmoreaccurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I
Input HIGH Voltage2.0V
Input LOW Voltage0.8V
Hysteresis
[6]
All inputs0.2V
Input Clamp Diode VoltageVCC=Min., IIN=–18 mA–0.7–1.2V
Input HIGH CurrentVCC=Max., VIN=V
CC
Input HIGH CurrentVCC=Max., VIN=2.7V±1µA
Input LOW CurrentVCC=Max., VIN=0.5V±1µA
Off State HIGH-Level Output
Current
Off State LOW-Level
Output Current
Output Short Circuit Current
Power-Off DisableVCC=0V, V
is the “instant on” case temperature.
A
tests should be performed last.
OS
=5.0V, TA=+25˚C ambient.
CC
VCC= Max., V
VCC = Max., V
[7]
VCC=Max., V
= 2.7V10µA
OUT
= 0.5V–10µA
OUT
=0.0V–60–120–225mA
OUT
=4.5V±1µA
OUT
or ground.
CC
[5]
Max.Unit
5µA
2
CY54/74FCT240T
CY54/74FCT244T
]
Capacitance
ParameterDescriptionTyp.
C
IN
C
OUT
Power Supply Characteristics
ParameterDescriptionTest ConditionsTyp.
I
CC
∆I
CC
I
CCD
I
C
Notes:
8. Per TTL driven input (V
9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.
10. I
C
IC=ICC+∆ICCDHNT+I
I
CC
∆I
CC
D
H
N
T
I
CCD
f
0
f
1
N
1
All currents are in milliamps and all frequencies are in megahertz.
11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.
[6]
Input Capacitance510pF
Output Capacitance912pF
Quiescent Power Supply Current VCC=Max., VIN≤0.2V,
Quiescent Power Supply Current
(TTL inputs)
Dynamic Power Supply
[9]
Current
Total Power Supply Current
[10]
V
VCC=Max., VIN=3.4V,
f1=0, Outputs Open
VCC=Max., One Input Toggling,
50% Duty Cycle, Outputs Open,
V
VCC=Max., 50% Duty Cycle, Outputs Open,
–0.2V
IN≥VCC
≤0.2V or VIN≥VCC–0.2V
IN
One Bit Toggling at f
OE1=OE2=GND, VIN≤0.2V or VIN≥VCC–0.2V
VCC=Max., 50% Duty Cycle, Outputs Open,
One Bit Toggling at f
OE1=OE2=GND, VIN=3.4V or VIN=GND
VCC=Max., 50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f
OE1=OE2=GND, VIN≤0.2V or VIN≥VCC–0.2V
VCC=Max., 50% Duty Cycle, Outputs Open,
Eight Bits Toggling at f
OE1=OE2=GND, VIN=3.4V or VIN=GND
=3.4V); all other inputs at VCC or GND.
IN
=I
QUIESCENT
= Quiescent Current with CMOS input levels
= Power Supply Current for a TTL HIGH input (VIN=3.4V)
= Duty Cycle for TTL inputs HIGH
= Number of TTL inputs at D
= Dynamic Current caused by an input transition pair (HLH or LHL)
= Clock frequency for registered devices, otherwise zero
= Input signal frequency
= Number of inputs changing at f
+ I
INPUTS
CCD(f0
+ I
DYNAMIC
/2 + f1N1)
H
1
[8]
=10 MHz,
1
=10 MHz,
1
=2.5 MHz,
1
=2.5 MHz,
1
[5]
OE1=OE2=GND,
Max.Unit
[5]
Max.Unit
0.10.2mA
0.52.0mA
0.060.12mA/MHz
0.71.4mA
1.02.4mA
1.32.6
3.310.6
[11]
[11]
mA
mA
3
Switching Characteristics Over the Operating Range
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