Texas Instruments CDC2509PWR Datasheet

CDC2509

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS580A – OCTOBER 1996 – REVISED JANUARY 1998

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications

D

Distributes One Clock Input to One Bank of
Five and One Bank of Four Outputs

D

Separate Output Enable for Each Output
Bank

D

External Feedback (FBIN) Pin Is Used to
Synchronize the Outputs to the Clock Input

D

On-Chip Series Damping Resistors

D

No External RC Network Required

D

Operates at 3.3-V V

CC

D

Packaged in Plastic 24-Pin Thin Shrink
Small-Outline Package

description

The CDC2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to
precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It
is specifically designed for use with synchronous DRAMs. The CDC2509 operates at 3.3-V V

CC

and provides

integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output

signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. Each bank of outputs can
be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs
switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low
state.

Unlike many products containing PLLs, the CDC2509 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2509 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL can be bypassed for test purposes by strapping AV

CC

to ground.

The CDC2509 is characterized for operation from 0°C to 70°C.

FUNCTION TABLE

INPUTS

OUTPUTS

1G 2G CLK

1Y

(0:4)2Y(0:3)

FBOUT

X X L L L L
L LHLLH

L HHLHH
H LHHLH

H H H H H H

Copyright  1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

CLK
AV

CC

V

CC

2Y0
2Y1
GND
GND
2Y2
2Y3
V

CC

2G
FBIN

1
2
3
4
5
6
7
8
9
10
11
12

AGND

V

CC

1Y0
1Y1

1Y2
GND
GND

1Y3

1Y4

V

CC

1G

FBOUT

24
23
22
21
20
19
18
17
16
15
14
13

PW PACKAGE

(TOP VIEW)

CDC2509

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS580A – OCTOBER 1996 – REVISED JANUARY 1998

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

1Y2

1Y1

1Y0

PLL

FBIN

AV

CC

2G

CLK

1G

2Y2

2Y1

2Y0

2Y3

FBOUT

1Y3

1Y4

11

14

24

13

23

3

4

5

8

9

21

20

17

16

12

AVAILABLE OPTIONS

PACKAGE

T

A

SMALL OUTLINE

(PW)

0°C to 70°C CDC2509PWR

CDC2509

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS580A – OCTOBER 1996 – REVISED JANUARY 1998

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

TYPE

DESCRIPTION

CLK 24 I

Clock input. CLK provides the clock signal to be distributed by the CDC2509 clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.

FBIN 13 I

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.

1G 11 I

Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4) are
disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same
frequency as CLK.

2G 14 I

Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are
disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same
frequency as CLK.

FBOUT 12 O

Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
and integrated 25-Ω series-damping resistor.

1Y (0:4) 3, 4, 5, 8, 9 O

Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via
the 1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control input.
Each output has an integrated 25-Ω series-damping resistor.

2Y (0:3) 16, 17, 20, 21 O

Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via
the 2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control input.
Each output has an integrated 25-Ω series-damping resistor.

AV

CC

23 Power

Analog power supply . A VCC provides the power reference for the analog circuitry. In addition, A V

CC

can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed
and CLK is buffered directly to the device outputs.

AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry.

V

CC

2, 10, 15, 22 Power Power supply

GND 6, 7, 18, 19 Ground Ground