Texas Instruments CD74HCT93E, CD74HC93M96, CD74HC93M, CD74HC93E Datasheet

CD74HC93,

/
j

[ /Title
(CD74
HC93,
CD74
HCT93
)

Sub-

ect
(High
Speed
CMOS
Logic
4-Bit
Binary
Ripple
Counte
r)

Data sheet acquired from Harris Semiconductor
SCHS138

August 1997

Features

• Can Be Configured to Divide By 2, 8, and 16

• Asynchronous Master Reset

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

o

Pinout

CD74HC93, CD74HCT93

(PDIP, SOIC)

TOP VIEW

CP1
MR1
MR2

NC

V

CC

NC
NC

1
2
3
4
5
6
7

CPO

14
13

NC

12

Q

0

Q

11

3

GND

10

Q

9

1

Q

8

2

C to 125oC

CC

OH

CD74HCT93

High Speed CMOS Logic

4-Bit Binary Ripple Counter

Description

The Harris CD74HC93 and CD74HCT93 are high speed
silicon-gate CMOS devices and are pin-compatible with low
power Schottky TTL (LSTTL). These 4-bit binary ripple
counters consist of four master-slave flip-flops internally
connected to provide a divide-by-two-section and a divid- by­eight-section. Each section has a separate clock input (
and

CP1) to innate state changes of the counter on the HIGH
to LOW clock transition. Sate changes of the Qn outputs do
not occur simultaneously because of internal ripple delays.
Therefore, decoded output signals are subject to decoding
spikes and should not be used for clocks or strobes.

A gated AND asynchronous master reset (MR1 and MR2 is
provided which overrides both clocks and resets (clears) all
flip-flops.

Because the output from the divide by two section is not
internally connected to the succeeding stages, the device
may be operated in various counting modes.

In a 4-bit ripple counter the output Q0 must be connected
externally to input
to clock input
8, and 16 are performed at the Q0, Q1, Q2, and Q3 outputs
as shown in the function table. As a 3-bit ripple counter the
input count pulses are applied to input

Simultaneous frequency divisions of 2, 4, and 8 are available
at the Q
flop is available if the reset function coincides with the reset
of the 3-bit ripple-through counter.

1,Q2,Q3

CP1. The input count pulses are applied

CP0. Simultaneous frequency divisions of 2, 4,

CP1.

outputs. Independent use of the first flip-

Ordering Information

TEMP.RANGE

PART NUMBER

CD74HC93E -55 to 125 14 Ld PDIP E14.3
CD74HCT93E -55 to 125 14 Ld PDIP E14.3
CD74HC93M -55 to 125 14 Ld SOIC M14.15

(oC) PACKAGE

CP0

PKG.

NO.

CD74HCT93M -55 to 125 14 Ld SOIC M14.15

NOTES:

1. When ordering, use the entire partnumber. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

File Number 1849.1

CD74HC93, CD74HCT93

TRUTH TABLE

OUTPUTS

COUNT

0LLLL
1HLLL
2LHLL
3HHLL
4LLHL
5HLHL
6LHHL
7HHHL
8LLLH

9HLLH
10LHLH
11 H H L H
12 L L H H
13 H L H H
14LHHH
15HHHH

NOTE: H = High Voltage Level, L = Low Voltage Level

Q

0

Q

1

Q

2

Q

3

MODE SELECTION

RESET OUTPUTS OUTPUTS
MR1 MR2 Q

0

Q

1

Q

2

Q

HHLLLL

L H Count Count Count Count

HL

LL

NOTE: H = High Voltage Level, L = Low Voltage Level

3

2

CD74HC93, CD74HCT93

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD74HC93, CD74HCT93

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)

NOTE:

4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

∆I

CC

- - 4.5 to

- - 4.5 to

VIH or

V

VIH or

V

VCC to

GND

VCC or

GND

V

CC

-2.1

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

IL

IL

VCC (V)

5.5

5.5

-4 4.5 3.98 - - 3.84 - 3.7 - V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V

0 5.5 - - ±0.1 - ±1-±1 µA

0 5.5 - - 8 - 80 - 160 µA

- 4.5 to

5.5

25oC -40oC TO 85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

CP0, CP1 0.6

MR1, MR2 0.4

NOTE: Unit Load is ∆ICClimit specified in DC Electrical
Specifications table, e.g. 360µA max at 25oC.

Prerequisite For Switching Specifications

TEST CONDITIONS

PARAMETER SYMBOL

HC TYPES

Maximum Clock Frequency f

Clock Pulse Width
CP0, CP1

MAX

t

w

VCC (V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN MAX MIN MAX MIN MAX

2 6-5-4-MHz

4.5 30 - 24 - 20 - MHz
6 35 - 28 - 24 - MHz
2 80 - 100 - 120 - ns

4.5 16 - 20 - 24 - ns
6 14-17-20-ns

4

CD74HC93, CD74HCT93

Prerequisite For Switching Specifications (Continued)

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL

Reset Pulse Width t

TEST CONDITIONS

VCC (V)

W

2 80 - 100 - 120 - ns

4.5 16 - 20 - 24 - ns
6 14-17-20-ns

Reset Removal Time t

REM

2 50-65-75-ns

4.5 10 - 13 - 15 - ns
6 9 - 11 - 13 - ns

HCT TYPES

Maximum Clock Frequency f
Clock Pulse Width

MAX

t

W

4.5 30 - 24 - 20 - mHz

4.5 16 - 20 - 24 - ns

CP0, CP1
Reset Pulse Width t
Reset Removal Time t

W

REM

Switching Specifications Input t

, tf = 6ns

r

4.5 16 - 20 - 24 - ns

4.5 10 - 13 - 15 - ns

-55oC TO

PARAMETER SYMBOL

TEST

CONDITIONS

V

CC

25oC -40oC TO 85oC

(V)

125oC

HC TYPES

Propagation Delay Time t

PLH

, t

PHLCL

= 50pF 2 - - 125 - 155 - 190 ns

CP0 to Q0 CL= 50pF 4.5 - - 25 - 31 - 38 ns

CL= 15pF 5 - 10 ----ns
CL= 50pF 6 - - 21 - 26 - 32 ns

CP1 to Q1 t

PLH

, t

PHLCL

= 50pF 2 - 135 - 170 - 205 ns
CL= 50pF 4.5 - 27 - 34 - 41 ns
CL= 50pF 6 - 23 - 29 - 35 ns

CP1 to Q2 t

PLH

, t

PHLCL

= 50pF 2 - 185 - 230 - 280 ns
CL= 50pF 4.5 - 37 - 46 - 56 ns
CL= 50pF 6 - 31 - 39 - 48 ns

CP1 to Q3 t

PLH

, t

PHLCL

= 50pF 2 - 245 - 305 - 370 ns
CL= 50pF 4.5 - 49 - 61 - 74 ns
CL= 15pF 5 - 21 - ----ns
CL= 50pF 6 - - 42 - 52 - 63 ns

MR1, MR2 to Qn t

PLH

, t

PHLCL

= 50pF 2 - 155 - 195 - 235 ns
CL= 50pF 4.5 - 31 - 39 - 47 ns
CL= 15pF 5 - 13 - - - ns
CL= 50pF 6 - 26 - 33 - 40 ns

Output Transition Time t

TLH

, t

THLCL

= 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

Input Capacitance C
Power Dissipation Capacitance C

CL= 50pF - - - 10 - 10 - 10 pF

IN

PD

- - - 25 - - 10 - 19 pF

UNITSMIN MAX MIN MAX MIN MAX

UNITSMIN TYP MAX MIN MAX MIN MAX

5

CD74HC93, CD74HCT93

Switching Specifications Input t

, tf = 6ns (Continued)

r

-55oC TO

PARAMETER SYMBOL

TEST

CONDITIONS

V

CC

25oC -40oC TO 85oC

(V)

125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HCT TYPES

Propagation Delay Time t

PLH

, t

PHLCL

= 50pF 4.5 - - 34 - 43 - 51 ns
CP0 to Q0 CL= 15pF 5 - 14 - ----ns
CP1 to Q1 t

PLH

, t

PHLCL

= 50pF 4.5 - - 34 - 43 - 51 ns

CL= 15pF 5 - - - ----ns

CP1 to Q2 t

PLH

, t

PHLCL

= 50pF 4.5 - - 46 - 58 - 69 ns

CL= 15pF 5 - - - ----ns

CP1 to Q3 t

PLH

, t

PHLCL

= 50pF 4.5 - - 58 - 73 - 87 ns

CL= 15pF 5 - 24 - ----ns

MR1, MR2 to Qn t

PLH

, t

PHLCL

= 50pF 4.5 - - 33 - 41 - 50 ns

CL= 15pF 5 - 13 - ----ns
Output Transition Time t
Input Capacitance C
Power Dissipation Capacitance C

TLH

, t

THLCL

IN

PD

= 50pF 4.5 - - 15 - 19 - 22 ns

CL= 50pF - - - 10 - 10 - 10 pF

- --25-----pF

Test Circuits and Waveforms

90%

t

PLH

IC

t

TLH

tfC

L

50%

t

H(L)

t

SU(L)

t

THL

90%

50%

10%
t

PHL

C

L

50pF

V

CC

GND

V

CC

50%
GND

GND

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

OUTPUT

t

REM

V

CC

SET, RESET
OR PRESET

trC

L

90%

10%

t

H(H)

50%

FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVALTIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

OUTPUT

t

REM

3V
SET, RESET
OR PRESET

trC

L

2.7V

0.3V

t

H(H)

1.3V

1.3V

1.3V

90%

t

PLH

IC

1.3V

t

TLH

tfC

L

1.3V

t

H(L)

1.3V

t

SU(L)

t

THL

90%

1.3V
10%

t

PHL

C

L

50pF

3V

GND

3V

GND

GND

FIGURE 2. HCTSETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

6

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