Texas Instruments CD74ACT02M96, CD74ACT02M, CD74ACT02E, CD74AC02M96, CD74AC02M Datasheet

Data sheet acquired from Harris Semiconductor
SCHS224A

CD54/74AC02,

CD54/74ACT02

[ /Title
(CD74
AC02,
CD74
ACT02
)
/Sub­ject
(Quad
2-Input
NOR
Gate)
/Autho
r ()
/Key­words
(Har­ris
Semi­con­ductor,
Advan
ced
CMOS
,Harris
Semi­con­ductor,
Advan
ced
TTL)
/Cre­ator ()

September 1998 - Revised May 2000

Features

• Typical Propagation Delay

- 6ns at V

= 5V, TA = 25oC, CL = 50pF

CC

• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015

• SCR-Latchup-Resistant CMOS Process and Circuit
Design

• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

Pinout

CD54AC02, CD54ACT02

(CERDIP)

CD74AC02, CD74ACT02

(PDIP, SOIC)

TOP VIEW

1Y
1A
1B
2Y
2A
2B

GND

1
2
3
4
5
6
7

14

V

CC

4Y

13
12

4B

11

4A

10

3Y

9

3B

8

3A

Quad 2-Input NOR Gate

Description

The ‘AC02 and ‘ACT02arequad2-inputNORgatesthatutiliz e
Advanced CMOS Logic technology.

Ordering Information

PART

NUMBER

CD54AC02F3A -55 to 125 14 Ld CERDIP
CD74AC02E -55 to 125 14 Ld PDIP
CD74AC02M -55 to 125 14 Ld SOIC
CD54ACT02F3A -55 to 125 14 Ld CERDIP
CD74ACT02E -55 to 125 14 Ld PDIP
CD74ACT02M -55 to 125 14 Ld SOIC

NOTES:

1. When ordering,use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Waf eranddieforthis part number is availablewhich meets all elec­trical specifications. Please contact your local TI sales office or cus­tomer service for ordering information.

Functional Diagram

2

1A

3

1B

5

2A

6

2B

8

3A

9

3B

11

4A

12

4B

INPUTS OUTPUTS

ABY

LLH

HLL

LHL

HHL

TEMP.

RANGE (oC) PACKAGE

1

1Y

4

2Y

10

3Y

13

4Y

GND = 7
V

= 14

CC

TRUTH TABLE

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.

Copyright

© 2000, Texas Instruments Incorporated

1

CD54/74AC02, CD54/74ACT02

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, I

CC orIGND

(Note 3) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. For up to 4 outputs per device, add ±25mA for each additional output.

4. Unless otherwise specified, all voltages are referenced to ground.

5. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

CC

DC Electrical Specifications

PARAMETER SYMBOL

AC TYPES

High Level Input Voltage V

Low Level Input Voltage V

High Level Output Voltage V

IH

IL

OH

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

- - 1.5 1.2 - 1.2 - 1.2 - V
3 2.1 - 2.1 - 2.1 - V

5.5 3.85 - 3.85 - 3.85 - V

- - 1.5 - 0.3 - 0.3 - 0.3 V
3 - 0.9 - 0.9 - 0.9 V

5.5 - 1.65 - 1.65 - 1.65 V

VIH or V

-0.05 1.5 1.4 - 1.4 - 1.4 - V

IL

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

UNITSV

2

CD54/74AC02, CD54/74ACT02

DC Electrical Specifications (Continued)

-40oC TO
85oC

PARAMETER SYMBOL

Low Level Output Voltage V

OL

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

VIH or V

0.05 1.5 - 0.1 - 0.1 - 0.1 V

IL

V

CC

(V)

25

o

C

0.05 3 - 0.1 - 0.1 - 0.1 V

0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1 µA

GND

Quiescent Supply Current
SSI

I

CC

VCC or

GND

0 5.5 - 4 - 40 - 80 µA

ACT TYPES

High Level Input Voltage V

IH

- - 4.5 to

2-2-2-V

5.5

Low Level Input Voltage V

IL

- - 4.5 to

- 0.8 - 0.8 - 0.8 V

5.5

High Level Output Voltage V

OH

VIH or V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

IL

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

Low Level Output Voltage V

OL

VIH or V

0.05 4.5 - 0.1 - 0.1 - 0.1 V

IL

24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1 µA

GND

Quiescent Supply Current
SSI

AdditionalSupplyCurrentper
Input Pin TTL Inputs High

I

CC

VCC or

0 5.5 - 4 - 40 - 80 µA

GND

∆I

CC

V

CC

-2.1

- 4.5 to

5.5

- 2.4 - 2.8 - 3 mA

1 Unit Load

NOTES:

6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.

7. Test verifies a minimum 50Ω transmission-line-drive capability at 85

o

C, 75Ω at 125oC.

-55oC TO
125oC

UNITSV

ACT Input Load Table

INPUT UNIT LOAD

All 0.32

NOTE: Unit load is ∆ICClimit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.

3

CD54/74AC02, CD54/74ACT02

Switching Specifications Input t

, tf = 3ns, CL= 50pF (Worst Case)

r

PARAMETER SYMBOL VCC (V)

AC TYPES

Propagation Delay, Input to
Output

t

PLH

, t

PHL

1.5 - - 131 - - 144 ns

3.3

4.1 - 14.6 4 - 16.1 ns

(Note 9)

5

3 - 10.4 2.9 - 11.5 ns

(Note 10)
Input Capacitance C
Power Dissipation Capacitance C

I

PD

- - -10- -10pF

- - 55 - - 55 - pF

(Note 11)

ACT TYPES

Propagation Delay, Input to
Output

Input Capacitance C
Power Dissipation Capacitance C

t

PLH

, t

PD

I

PHL

5

3.1 - 11.1 3.1 - 12.2 ns

(Note 10)

- - -10- -10pF

- - 55 - - 55 - pF

(Note 11)

NOTES:

8. Limits tested at 100%.

9. 3.3V Min at 3.6V, Max at 3V.

10. 5V Min at 5.5V, Max at 4.5V.

11. CPD is used to determine the dynamic power consumption per gate.
AC: PD = V
ACT: PD = V

2

fi(CPD + CL)

CC

2

fi(CPD + CL) + VCC∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

CC

-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX

OUTPUT

R

(NOTE)

L

C

L

50pF

500Ω

DUT

OUTPUT

LOAD

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

AC ACT

Input Level V
Input Switching Voltage, V
Output Switching Voltage, V

S

S

0.5 V

0.5 V

CC

CC
CC

FIGURE 1. PROPAGATION DELAY TIMES

3V

1.5V

0.5 V

CC

t

PLH

t

f

tr = 3ns

LEVEL

V

I

V

O

INPUT

t

PHL

FIGURE 2. PROPAGATION DELAY TIMES

= 3ns

90%
V

S

10%

V

S

GND

4

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Copyright  2000, Texas Instruments Incorporated