TEXAS INSTRUMENTS CD4070B, CD4077B Technical data

CD4070B,

[ /Title
(CD40
70B,
CD407
7B)
/Sub­ject
(CMO
SQuad
Exclu­sive­OR
and
Exclu­sive­NOR
Gate)
/Autho
r ()
/Key­words
(Har­ris
Semi­con­ductor,
CD400
0,
metal
gate,
CMOS
, pdip,
cerdip,
mil,

Data sheet acquired from Harris Semiconductor
SCHS055E

January 1998 - Revised September 2003

Features

• High-Voltage Types (20V Rating)

• CD4070B - Quad Exclusive-OR Gate

• CD4077B - Quad Exclusive-NOR Gate

• Medium Speed Operation
, t

-t

PHL

• 100% Tested for Quiescent Current at 20V

• Standardized Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1µA at 18V Over Full

Package Temperature Range

- 100nA at 18V and 25

• Noise Margin (Over Full Package Temperature Range)

- 1V at V

• Meets All Requirements of JEDEC Standard No. 13B,

“Standard Specifications for Description of ‘B’ Series
CMOS Devices

= 65ns (Typ) at VDD = 10V, CL = 50pF

PLH

o

C

= 5V, 2V at VDD = 10V, 2.5V at VDD = 15V

DD

Applications

• Logical Comparators

• Adders/Subtractors

• Parity Generators and Checkers

Description

The Harris CD4070B contains four independent Exclusive­OR gates. The Harris CD4077B contains four independent
Exclusive-NOR gates.

The CD4070B and CD4077B provide the system designer
with a means for direct implementation of the Exclusive-OR
and Exclusive-NOR functions, respectively.

CD4077B

CMOS Quad Exclusive-OR

and Exclusive-NOR Gate

Ordering Information

TEMP. RANGE

PART NUMBER

CD4070BE -55 to 125 14 Ld PDIP
CD4070BF3A -55 to 125 14 Ld CERDIP
CD4070BM -55 to 125 14 Ld SOIC
CD4070BMT -55 to 125 14 Ld SOIC
CD4070BM96 -55 to 125 14 Ld SOIC
CD4070BNSR -55 to 125 14 Ld SOP
CD4070BPW -55 to 125 14 Ld TSSOP
CD4070BPWR -55 to 125 14 Ld TSSOP
CD4077BE -55 to 125 14 Ld PDIP
CD4077BF3A -55 to 125 14 Ld CERDIP
CD4077BM -55 to 125 14 Ld SOIC
CD4077BMT -55 to 125 14 Ld SOIC
CD4077BM96 -55 to 125 14 Ld SOIC
CD4077BNSR -55 to 125 14 Ld SOP
CD4077BPW -55 to 125 14 Ld TSSOP
CD4077BPWR -55 to 125 14 Ld TSSOP

NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.

(oC) PACKAGE

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2003, Texas Instruments Incorporated

1

Pinouts

CD4070B, CD4077B

CD4070B

(PDIP, CERDIP, SOIC, SOP, TSSOP)

TOP VIEW

A

1
2

B

⊕ B
⊕ D

V

SS

3
4
5

C

6

D

7

J = A

K = C

Functional Diagrams

CD4070B CD4077B

A
B

⊕ B

J = A

C

D

K =

⊕

C
D

⊕ H

M = G
L = E

⊕ F

E

= 14

F

12

G

13

H

V

= 7

SS

V

DD

CD4077B

(PDIP, CERDIP, SOIC, SOP, TSSOP)

TOP VIEW

V

14

DD

H

13
12

G
11
10

9
8

1
2

5
6

8
9

⊕ H

M = G

L = E ⊕ F

F

E

3

4

10

11

J

K

L

M

J = A

K = C

J=A
K = C

M = G
L=E

A
B

⊕ B
⊕ D

C
D

V

SS

⊕ B
⊕ D

⊕ H
⊕ F

1
2
3
4
5
6
7

1

A

2

B

5

C

6

D

8

E

9

F

12

G

13

H

14
13
12
11
10

9
8

V

DD

H
G

⊕ H

M = G
L = E ⊕ F
F
E

3

4

10

11

J

K

L

M

2

V

)

)

DD

B †

2(5,9,12)

A †

1(6,8,13)

† INPUTS PROTECTED

BY CMOS PROTECTION
NETWORK

p

n

V

SS

V

DD

p

n

V

SS

CD4070B, CD4077B

V

SS

DD

p

n

J

3(4,10,11

V

DD

V

DD

n

p

V

DD

p

p

p
n

V

SS

J

3(4,10,11

n

B †

2(5,9,12)

A †

1(6,8,13)

† INPUTS PROTECTED

BY CMOS PROTECTION
NETWORK

p

n

n

V

SS

V

DD

p

n

V

SS

p

n

p

n

V

DD

V

V

SS

FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B

(1 OF 4 IDENTICAL GATES)

CD4070B TRUTH TABLE (1 OF 4 GATES)

ABJ

000
101
011
110

NOTE:
1 = High Level
0 = Low Level
J = A ⊕ B

V

SS

FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B

(1 OF 4 IDENTICAL GATES)

CD4077B TRUTH TABLE (1 OF 4 GATES)

ABJ

001
100
010
111

NOTE:
1 = High Level
0 = Low Level
J = A ⊕ B

3

CD4070B, CD4077B

Absolute Maximum Ratings Thermal Information

DC Supply Voltage Range (VDD) . . . . . . . . . . . . . . . . . -0.5V to 20V

Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5V to VDD 0.5V

DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 10mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . 3V to 18V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specifications

Package Thermal Impedance, θJA(see Note 1):

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80oC/W

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86oC/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76oC/W

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 113oC/W

Maximum Junction Temperature (Hermetic Package or Die) . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

LIMITS AT INDICATED TEMPERATURES (oC)

PARAMETER

Quiescent Device Current
IDD Max

Output Low (Sink) Current
IOL Min

Output High (Source) Current
IOH Min

Output Voltage: Low Level,
VOL Max

CONDITIONS

V
(V)

0.4 0, 5 5 0.64 0.61 0.42 0.36 0.51 1 - mA

0.5 0, 10 10 1.6 1.5 1.1 0.9 1.3 2.6 - mA

1.5 0, 15 15 4.2 4 2.8 2.4 3.4 6.8 - mA

4.6 0, 5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mA

2.5 0, 5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - mA

9.5 0, 10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - mA

13.5 0, 15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 - mA

V

(V)

V

IN

DD

(V) MIN TYP MAX

O

- 0, 5 5 0.25 0.25 7.5 7.5 - 0.01 0.25 µA

- 0, 10 10 0.5 0.5 15 15 - 0.01 0.5 µA

- 0, 15 15 1 1 30 30 - 0.01 1 µA

- 0, 20 20 5 5 150 150 - 0.02 5 µA

- 0, 5 5 0.05 0.05 0.05 0.05 - 0 0.05 V

- 0, 10 10 0.05 0.05 0.05 0.05 - 0 0.05 V

- 0, 15 15 0.05 0.05 0.05 0.05 - 0 0.05 V

25

UNITS-55 -40 85 125

Output Voltage: High Level,
VOH Min

Input Low Voltage,
VIL Max

Input High Voltage,
VIH Min

Input Current, IIN Max - 0, 18 18 ±0.1 ±0.1 ±1 ±1-±10

- 0, 5 5 4.95 4.95 4.95 4.95 4.95 5 - V

- 0, 10 10 9.95 9.95 9.95 9.95 9.95 10 - V

- 0, 15 15 14.95 14.95 14.95 14.95 14.95 15 - V

0.5, 4.5 - 5 1.5 1.5 1.5 1.5 - - 1.5 V
1, 9-103333--3V

1.5, 13.5 - 15 4444--4V

0.5, 4.5 - 5 3.5 3.5 3.5 3.5 3.5 - - V
1, 9-1077777--V

1.5, 13.5 - 15 11 11 11 11 11 - - V

4

-5

±0.1 µA

CD4070B, CD4077B

AC Electrical Specifications T

= 25oC, Input tr, tf = 20ns, CL = 50pF, RL = 200kΩ

A

PARAMETER SYMBOL

Propagation Delay Time t

Transition Time t

Input Capacitance C

Typical Performance Curves

TA = 25oC

30

25

20

15

GATE TO SOURCE VOLTAGE (VGS) = 15V

10V

PHL

THL

TEST CONDITIONS LIMITS ON ALL TYPES

UNITSVDD (V) TYP MAX

, t

PLH

5 140 280 ns
10 65 130 ns
15 50 100 ns

, t

TLH

5 100 200 ns
10 50 100 ns
15 40 80 ns

IN

Any Input 5 7.5 pF

TA = 25oC

15

12.5

10

7.5

GATE TO SOURCE VOLTAGE (VGS) = 15V

10V

10

5

, OUTPUT LOW (SINK) CURRENT (mA)

OL

I

0

0 5 10 15

5V

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

VDS, DRAIN TO SOURCE VOLTAGE (V)

TA = 25oC

GATE TO SOURCE VOLTAGE (VGS) = -5V

-10V

-15V

5

2.5

, OUTPUT LOW (SINK) CURRENT (mA)

OL

I

0

0 5 10 15

FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

VDS, DRAIN TO SOURCE VOLTAGE (V)

0-5-10-15

0

-5

-10

-15

-20

-25

-30

, OUTPUT HIGH (SOURCE) CURRENT (mA)

OH

I

TA = 25oC

GATE TO SOURCE VOLTAGE (VGS) = -5V

5V

VDS, DRAIN TO SOURCE VOLTAGE (V)

-10V

-15V

0-5-10-15

0

-5

-10

-15

, OUTPUT HIGH (SINK) CURRENT (mA)

OH

I

FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

5

Typical Performance Curves (Continued)

TA = 25oC

200

SUPPLY VOLTAGE (VDD) = 5V

150

, TRANSITION TIME (ns)

100

TLH

, t

50

THL

t

0

0204060

CL, LOAD CAPACITANCE (pF)

10V

15V

80 100 110

FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF

LOAD CAPACITANCE

TA = 25oC
LOAD CAPACITANCE C

300

200

100

, PROPAGATION DELAY TIME (ns)

PLH

, t

0

PHL

t

0 5 10 15

VDD, SUPPLY VOLTAGE (V)

= 50pF

L

20

TA = 25oC

300

200

100

, PROPAGATION DELAY TIME (ns)

PLH

, t

0

PHL

t

0204060

SUPPLY VOLTAGE (VDD) = 5V

10V

15V

80 100

CL, LOAD CAPACITANCE (pF)

FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A

FUNCTION OF LOAD CAPACITANCE

5

10

TA = 25oC

4

, POWER DISSIPATION (µW)
P

10

3

10

2

10

10

D

1

-1

10

SUPPL

-1

10

TAGE (V

OL

Y V

110

fI, INPUT FREQUENCY (kHz)

5V

) = 15V

DD

10V

CL = 15pF

2

10

10V

CL = 50pF

3

10

4

10

FIGURE 9. TYPICAL PROPAGATIONDELAY TIME AS A

FUNCTION OF SUPPLY VOLTAGE

FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A

FUNCTION OF INPUT FREQUENCY

6