TEXAS INSTRUMENTS CD4070B, CD4077B Technical data

CD4070B,

[ /Title
(CD40
70B,
CD407
7B)
/Sub­ject
(CMO
SQuad
Exclu­sive­OR
and
Exclu­sive­NOR
Gate)
/Autho
r ()
/Key­words
(Har­ris
Semi­con­ductor,
CD400
0,
metal
gate,
CMOS
, pdip,
cerdip,
mil,

Data sheet acquired from Harris Semiconductor
SCHS055E

January 1998 - Revised September 2003

Features

• High-Voltage Types (20V Rating)

• CD4070B - Quad Exclusive-OR Gate

• CD4077B - Quad Exclusive-NOR Gate

• Medium Speed Operation
, t

-t

PHL

• 100% Tested for Quiescent Current at 20V

• Standardized Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1µA at 18V Over Full

Package Temperature Range

- 100nA at 18V and 25

• Noise Margin (Over Full Package Temperature Range)

- 1V at V

• Meets All Requirements of JEDEC Standard No. 13B,

“Standard Specifications for Description of ‘B’ Series
CMOS Devices

= 65ns (Typ) at VDD = 10V, CL = 50pF

PLH

o

C

= 5V, 2V at VDD = 10V, 2.5V at VDD = 15V

DD

Applications

• Logical Comparators

• Adders/Subtractors

• Parity Generators and Checkers

Description

The Harris CD4070B contains four independent Exclusive­OR gates. The Harris CD4077B contains four independent
Exclusive-NOR gates.

The CD4070B and CD4077B provide the system designer
with a means for direct implementation of the Exclusive-OR
and Exclusive-NOR functions, respectively.

CD4077B

CMOS Quad Exclusive-OR

and Exclusive-NOR Gate

Ordering Information

TEMP. RANGE

PART NUMBER

CD4070BE -55 to 125 14 Ld PDIP
CD4070BF3A -55 to 125 14 Ld CERDIP
CD4070BM -55 to 125 14 Ld SOIC
CD4070BMT -55 to 125 14 Ld SOIC
CD4070BM96 -55 to 125 14 Ld SOIC
CD4070BNSR -55 to 125 14 Ld SOP
CD4070BPW -55 to 125 14 Ld TSSOP
CD4070BPWR -55 to 125 14 Ld TSSOP
CD4077BE -55 to 125 14 Ld PDIP
CD4077BF3A -55 to 125 14 Ld CERDIP
CD4077BM -55 to 125 14 Ld SOIC
CD4077BMT -55 to 125 14 Ld SOIC
CD4077BM96 -55 to 125 14 Ld SOIC
CD4077BNSR -55 to 125 14 Ld SOP
CD4077BPW -55 to 125 14 Ld TSSOP
CD4077BPWR -55 to 125 14 Ld TSSOP

NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.

(oC) PACKAGE

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2003, Texas Instruments Incorporated

1

Pinouts

CD4070B, CD4077B

CD4070B

(PDIP, CERDIP, SOIC, SOP, TSSOP)

TOP VIEW

A

1
2

B

⊕ B
⊕ D

V

SS

3
4
5

C

6

D

7

J = A

K = C

Functional Diagrams

CD4070B CD4077B

A
B

⊕ B

J = A

C

D

K =

⊕

C
D

⊕ H

M = G
L = E

⊕ F

E

= 14

F

12

G

13

H

V

= 7

SS

V

DD

CD4077B

(PDIP, CERDIP, SOIC, SOP, TSSOP)

TOP VIEW

V

14

DD

H

13
12

G
11
10

9
8

1
2

5
6

8
9

⊕ H

M = G

L = E ⊕ F

F

E

3

4

10

11

J

K

L

M

J = A

K = C

J=A
K = C

M = G
L=E

A
B

⊕ B
⊕ D

C
D

V

SS

⊕ B
⊕ D

⊕ H
⊕ F

1
2
3
4
5
6
7

1

A

2

B

5

C

6

D

8

E

9

F

12

G

13

H

14
13
12
11
10

9
8

V

DD

H
G

⊕ H

M = G
L = E ⊕ F
F
E

3

4

10

11

J

K

L

M

2

V

)

)

DD

B †

2(5,9,12)

A †

1(6,8,13)

† INPUTS PROTECTED

BY CMOS PROTECTION
NETWORK

p

n

V

SS

V

DD

p

n

V

SS

CD4070B, CD4077B

V

SS

DD

p

n

J

3(4,10,11

V

DD

V

DD

n

p

V

DD

p

p

p
n

V

SS

J

3(4,10,11

n

B †

2(5,9,12)

A †

1(6,8,13)

† INPUTS PROTECTED

BY CMOS PROTECTION
NETWORK

p

n

n

V

SS

V

DD

p

n

V

SS

p

n

p

n

V

DD

V

V

SS

FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B

(1 OF 4 IDENTICAL GATES)

CD4070B TRUTH TABLE (1 OF 4 GATES)

ABJ

000
101
011
110

NOTE:
1 = High Level
0 = Low Level
J = A ⊕ B

V

SS

FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077B

(1 OF 4 IDENTICAL GATES)

CD4077B TRUTH TABLE (1 OF 4 GATES)

ABJ

001
100
010
111

NOTE:
1 = High Level
0 = Low Level
J = A ⊕ B

3

CD4070B, CD4077B

Absolute Maximum Ratings Thermal Information

DC Supply Voltage Range (VDD) . . . . . . . . . . . . . . . . . -0.5V to 20V

Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5V to VDD 0.5V

DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 10mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . . . . 3V to 18V

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specifications

Package Thermal Impedance, θJA(see Note 1):

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80oC/W

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86oC/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76oC/W

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 113oC/W

Maximum Junction Temperature (Hermetic Package or Die) . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

LIMITS AT INDICATED TEMPERATURES (oC)

PARAMETER

Quiescent Device Current
IDD Max

Output Low (Sink) Current
IOL Min

Output High (Source) Current
IOH Min

Output Voltage: Low Level,
VOL Max

CONDITIONS

V
(V)

0.4 0, 5 5 0.64 0.61 0.42 0.36 0.51 1 - mA

0.5 0, 10 10 1.6 1.5 1.1 0.9 1.3 2.6 - mA

1.5 0, 15 15 4.2 4 2.8 2.4 3.4 6.8 - mA

4.6 0, 5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mA

2.5 0, 5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - mA

9.5 0, 10 10 -1.6 -1.5 -1.1 -0.9 -1.3 -2.6 - mA

13.5 0, 15 15 -4.2 -4 -2.8 -2.4 -3.4 -6.8 - mA

V

(V)

V

IN

DD

(V) MIN TYP MAX

O

- 0, 5 5 0.25 0.25 7.5 7.5 - 0.01 0.25 µA

- 0, 10 10 0.5 0.5 15 15 - 0.01 0.5 µA

- 0, 15 15 1 1 30 30 - 0.01 1 µA

- 0, 20 20 5 5 150 150 - 0.02 5 µA

- 0, 5 5 0.05 0.05 0.05 0.05 - 0 0.05 V

- 0, 10 10 0.05 0.05 0.05 0.05 - 0 0.05 V

- 0, 15 15 0.05 0.05 0.05 0.05 - 0 0.05 V

25

UNITS-55 -40 85 125

Output Voltage: High Level,
VOH Min

Input Low Voltage,
VIL Max

Input High Voltage,
VIH Min

Input Current, IIN Max - 0, 18 18 ±0.1 ±0.1 ±1 ±1-±10

- 0, 5 5 4.95 4.95 4.95 4.95 4.95 5 - V

- 0, 10 10 9.95 9.95 9.95 9.95 9.95 10 - V

- 0, 15 15 14.95 14.95 14.95 14.95 14.95 15 - V

0.5, 4.5 - 5 1.5 1.5 1.5 1.5 - - 1.5 V
1, 9-103333--3V

1.5, 13.5 - 15 4444--4V

0.5, 4.5 - 5 3.5 3.5 3.5 3.5 3.5 - - V
1, 9-1077777--V

1.5, 13.5 - 15 11 11 11 11 11 - - V

4

-5

±0.1 µA

CD4070B, CD4077B

AC Electrical Specifications T

= 25oC, Input tr, tf = 20ns, CL = 50pF, RL = 200kΩ

A

PARAMETER SYMBOL

Propagation Delay Time t

Transition Time t

Input Capacitance C

Typical Performance Curves

TA = 25oC

30

25

20

15

GATE TO SOURCE VOLTAGE (VGS) = 15V

10V

PHL

THL

TEST CONDITIONS LIMITS ON ALL TYPES

UNITSVDD (V) TYP MAX

, t

PLH

5 140 280 ns
10 65 130 ns
15 50 100 ns

, t

TLH

5 100 200 ns
10 50 100 ns
15 40 80 ns

IN

Any Input 5 7.5 pF

TA = 25oC

15

12.5

10

7.5

GATE TO SOURCE VOLTAGE (VGS) = 15V

10V

10

5

, OUTPUT LOW (SINK) CURRENT (mA)

OL

I

0

0 5 10 15

5V

VDS, DRAIN TO SOURCE VOLTAGE (V)

FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

VDS, DRAIN TO SOURCE VOLTAGE (V)

TA = 25oC

GATE TO SOURCE VOLTAGE (VGS) = -5V

-10V

-15V

5

2.5

, OUTPUT LOW (SINK) CURRENT (mA)

OL

I

0

0 5 10 15

FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT

CHARACTERISTICS

VDS, DRAIN TO SOURCE VOLTAGE (V)

0-5-10-15

0

-5

-10

-15

-20

-25

-30

, OUTPUT HIGH (SOURCE) CURRENT (mA)

OH

I

TA = 25oC

GATE TO SOURCE VOLTAGE (VGS) = -5V

5V

VDS, DRAIN TO SOURCE VOLTAGE (V)

-10V

-15V

0-5-10-15

0

-5

-10

-15

, OUTPUT HIGH (SINK) CURRENT (mA)

OH

I

FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT

CHARACTERISTICS

5

Typical Performance Curves (Continued)

TA = 25oC

200

SUPPLY VOLTAGE (VDD) = 5V

150

, TRANSITION TIME (ns)

100

TLH

, t

50

THL

t

0

0204060

CL, LOAD CAPACITANCE (pF)

10V

15V

80 100 110

FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF

LOAD CAPACITANCE

TA = 25oC
LOAD CAPACITANCE C

300

200

100

, PROPAGATION DELAY TIME (ns)

PLH

, t

0

PHL

t

0 5 10 15

VDD, SUPPLY VOLTAGE (V)

= 50pF

L

20

TA = 25oC

300

200

100

, PROPAGATION DELAY TIME (ns)

PLH

, t

0

PHL

t

0204060

SUPPLY VOLTAGE (VDD) = 5V

10V

15V

80 100

CL, LOAD CAPACITANCE (pF)

FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A

FUNCTION OF LOAD CAPACITANCE

5

10

TA = 25oC

4

, POWER DISSIPATION (µW)
P

10

3

10

2

10

10

D

1

-1

10

SUPPL

-1

10

TAGE (V

OL

Y V

110

fI, INPUT FREQUENCY (kHz)

5V

) = 15V

DD

10V

CL = 15pF

2

10

10V

CL = 50pF

3

10

4

10

FIGURE 9. TYPICAL PROPAGATIONDELAY TIME AS A

FUNCTION OF SUPPLY VOLTAGE

FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A

FUNCTION OF INPUT FREQUENCY

6

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

CD4070BE ACTIVE PDIP N 14 25 Pb-Free

CD4070BEE4 ACTIVE PDIP N 14 25 Pb-Free

CD4070BF ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

CD4070BF3A ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

CD4070BM ACTIVE SOIC D 14 50 Green (RoHS &

CD4070BM96 ACTIVE SOIC D 14 2500 Green (RoHS &

CD4070BM96E4 ACTIVE SOIC D 14 2500 Green (RoHS &

CD4070BM96G4 ACTIVE SOIC D 14 2500 Green (RoHS &

CD4070BME4 ACTIVE SOIC D 14 50 Green (RoHS &

CD4070BMG4 ACTIVE SOIC D 14 50 Green (RoHS &

CD4070BMT ACTIVE SOIC D 14 250 Green (RoHS &

CD4070BMTE4 ACTIVE SOIC D 14 250 Green (RoHS &

CD4070BMTG4 ACTIVE SOIC D 14 250 Green (RoHS &

CD4070BNSR ACTIVE SO NS 14 2000 Green (RoHS &

CD4070BNSRE4 ACTIVE SO NS 14 2000 Green (RoHS &

CD4070BNSRG4 ACTIVE SO NS 14 2000 Green (RoHS &

CD4070BPW ACTIVE TSSOP PW 14 90 Green (RoHS &

CD4070BPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS &

CD4070BPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &

CD4070BPWR ACTIVE TSSOP PW 14 2000 Green (RoHS &

CD4070BPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS &

CD4070BPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &

CD4077BE ACTIVE PDIP N 14 25 Pb-Free

CD4077BEE4 ACTIVE PDIP N 14 25 Pb-Free

CD4077BF ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

CD4077BF3A ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

CD4077BM ACTIVE SOIC D 14 50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

no Sb/Br)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU N / A for Pkg Type

CU NIPDAU N / A for Pkg Type

9-Oct-2007

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

9-Oct-2007

(3)

no Sb/Br)

CD4077BM96 ACTIVE SOIC D 14 2500 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4077BM96E4 ACTIVE SOIC D 14 2500 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4077BM96G4 ACTIVE SOIC D 14 2500 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4077BME4 ACTIVE SOIC D 14 50 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4077BMG4 ACTIVE SOIC D 14 50 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4077BMT ACTIVE SOIC D 14 250 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4077BMTE4 ACTIVE SOIC D 14 250 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4077BMTG4 ACTIVE SOIC D 14 250 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4077BNSR ACTIVE SO NS 14 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4077BNSRE4 ACTIVE SO NS 14 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4077BNSRG4 ACTIVE SO NS 14 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4077BPW ACTIVE TSSOP PW 14 90 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4077BPWE4 ACTIVE TSSOP PW 14 90 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4077BPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4077BPWR ACTIVE TSSOP PW 14 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4077BPWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4077BPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

JM38510/17203BCA ACTIVE CDIP J 14 1 TBD A42 SNPB N / A for Pkg Type

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

9-Oct-2007

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

TAPE AND REEL INFORMATION

11-Mar-2008

*All dimensions are nominal

Device Package

Type

CD4070BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

CD4070BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

CD4070BPWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1

CD4077BM96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

CD4077BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

CD4077BPWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1

Package
Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Mar-2008

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD4070BM96 SOIC D 14 2500 346.0 346.0 33.0

CD4070BNSR SO NS 14 2000 346.0 346.0 33.0

CD4070BPWR TSSOP PW 14 2000 346.0 346.0 29.0

CD4077BM96 SOIC D 14 2500 346.0 346.0 33.0

CD4077BNSR SO NS 14 2000 346.0 346.0 33.0

CD4077BPWR TSSOP PW 14 2000 346.0 346.0 29.0

Pack Materials-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

14

0,30
0,19

8

4,50
4,30

PINS **

7

Seating Plane

0,15

0,05

8

1

A

DIM

14

0,10

6,60
6,20

M

0,10

0,15 NOM

0°–8°

2016

Gage Plane

24

0,25

0,75
0,50

28

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

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