Texas Instruments BQ4842YMA-85 Datasheet

bq4842Y

RTC Module With 128Kx8 NVSRAM

Features

➤ Integrated SRAM, real-time

clock, CPU supervisor, crystal,
power-fail control circuit, and
battery

➤ Real-Time Clock counts hun-

dredths of seconds through years
in BCD format

➤ RAM-like clockaccess
➤ Compatible with industry-

standard 128K x 8 SRAMs

➤ Unlimited write cycles
➤ 10-year minimum data retention

and clock operation in the ab­sence of power

➤ Automatic power-fail chip dese-

lect and write-protection

➤ Watchdog timer, power-on reset,

alarm/periodic interrupt, power­fail and battery-low warning

➤ Software clock calibration for

greater than±1 minute per
month accuracy

General Description

The bq4842Y RTC Module is a non­volatile 1,048,576-bit SRAM organ­ized as 131,072 words by 8 bits with
an integral accessible real-time
clock and CPU supervisor. The CPU
supervisor provides a programmable
watchdog timer and a microproces­sor reset. Other features include
alarm, power-fail, and periodic inter­rupts,andabattery-lowwarning.

The device combines an internal
lithium battery, quartz crystal, clock
and power-fail chip, and a full
CMOS SRAM in a plastic 32-pin
DIP module. The RTC Module di­rectly replaces industry-standard
SRAMs and also fits into many
EPROM and EEPROM sockets
without any requirement for special
write timing or limitations on the
number of write cycles.

Registers for the real-time clock,
alarm and other special functions
are located in registers 1FFF0h–
1FFFFh of the memory array.

The clock and alarm registers are
dual-port read/write SRAM loca­tions that are updated once per sec­ond by a clock control circuit from
the internal clock counters. The
dual-port registers allow clock up­dates to occur without interrupting
normal access to the rest of the
SRAM array.

The bq4842Y also contains a power­fail-detect circuit. The circuit dese­lects the device whenever V

CC

falls
below tolerance, providing a high de­gree of data security. The battery is
electrically isolated when shipped
from the factory to provide maxi­mum battery capacity. The battery
remains disconnected until the first
application of VCC.

Pin Connections

RST

1

A

2

16

A

3

14

4

A

12

5

A

7

A

6

6

A

7

5

8

A

4

A

9

3

A

10

2

11

A

1

12

A

0

13

DQ

0

DQ

14

1

15

DQ

2

V

16

SS

32-Pin DIP Module

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32
31

30
29
28
27
26
25
24
23
22

21
20
19
18
17

PN484201.eps

V
A

INT
WE
A
A
A
A
OE
A
CE
DQ
DQ
DQ
DQ
DQ

CC
15

13
8
9
11

10

Pin Names

A0–A

CE Chip enable

RST Microprocessor reset

WE Write enable

OE Output enable

DQ0–DQ7Data in/data out

7
6
5
4
3

INT Programmable interrupt

V

CC

V

SS

1

16

Address input

+5 volts

Ground

bq4842Y

Functional Description

Figure 1 is a block diagram of the bq4842Y. The follow­ing sections describe the bq4842Y functional operation,
including memory and clock interface, data-retention

modes, power-on reset timing, watchdog timer activa­tion,andinterruptgeneration.

Truth Table

V

CC

(max.) V

<V

CC

(min.) V

>V

CC

(min.) > V

<V

PFD

≤ V

SO

Figure 1. Block Diagram

CE OE WE Mode DQ Power

X X Deselect High Z Standby
XVILWrite D

V

IL

V

IH

V

IH

V

IH

Read D
Read High Z Active

IN

OUT

SO

IH

V

IL

IL

V

IL

X X X Deselect High Z CMOS standby
X X X Deselect High Z Battery-backup mode

2

Active
Active

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bq4842Y

Address Map

The bq4842Y provides 16 bytes of clock and control
status registers and 131,056 bytes of storage RAM.

Figure 2 illustrates the address map for the bq4842Y.
Table 1 is a map of the bq4842Y registers, and Table 2
describes the register bits.

Memory Interface

Read Mode

The bq4842Y is in read mode whenever OE (output enable)
is low and CE (chip enable) is low. The device architecture
allows ripple-through access of data from eight of 1,048,576
locations in the static storage array. Thus, the unique ad­dress specified by the 17 address inputs defines which one
of the 131,072 bytes of data is to be accessed. Valid data is
available at the data I/O pins within tAA(address access
time) after the last address input signal is stable, providing
that the CE and OE (output enable) access times are also
satisfied. If the CE and OE access times are not met, valid
data is available after the latter of chip enable access time
(t

) or output enable access time (tOE).

ACE

and OE control the state of the eight three-state data

CE
I/O signals. If the outputs are activated before tAA, the data
lines are driven to an indeterminate state until tAA. If the

16 Bytes

131,056

Bytes

Clock and

Control Status

Registers

Storage

RAM

1FFFF
1FFF0

1FFEF

0000

address inputs are changed while CE
output data remains valid for tOH(output data hold time),
but goes indeterminate until the next address access.

and OE remain low,

Write Mode

The bq4842Y is in write mode whenever WE and CE are
active. The start of a write is referenced from the latter­occurring falling edge of WE
by the earlier rising edge of WE or CE. The addresses
must be held valid throughout the cycle. CE or WE must
return high for a minimum of t
WE prior to the initiation of another read or write cycle.

Data-in must be valid t
main valid for t
high during write cycles to avoid bus contention; although,
if the output bus has been activated by a low on CE and
OE,alowonWEdisablestheoutputstWZafter WE falls.

DH1

or t

or CE. A write is terminated

from CE or t

WR2

prior to the end of write and re-

DW

afterward. OE should be kept

DH2

WR1

from

Data-Retention Mode

With valid VCC applied, the bq4842Y operates as a
conventional static RAM. Should the supply voltage
decay, the RAM automatically power-fail deselects,
write-protecting itself t
All outputs become high impedance, and all inputs are
treated as “don’t care.”

after VCCfalls below V

WPT

0
1
2
3
4
5
6
7
8

9
10
11
12
13

14
15

Year

Month

Date

Days

Hours

Minutes

Seconds

Control

Watchdog

Interrupts

Alarm Date

Alarm Hours

Alarm Minutes

Alarm Seconds

Tenths/

Hundredths

Flags

PFD

1FFFF
1FFFE
1FFFD
1FFFC
1FFFB
1FFFA
1FFF9
1FFF8
1FFF7
1FFF6
1FFF5
1FFF4
1FFF3
1FFF2

1FFF1
1FFF0

.

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FG484201.eps

Figure 2. Address Map

3

bq4842Y

If power-fail detection occurs during a valid access, the
memory cycle continues to completion. If the memory cycle
fails to terminate within time t
place. When VCCdrops below VSO, the control circuit
switches power to the internal energy source, which pre­serves data.

The internal coin cell maintains data in the bq4842Y after
the initial application of V
at least 10 years when VCCis less than VSO. As system
power returns and Vcc rises above VSO, the battery is dis­connected, and the power supply is switched to external
VCC. Write-protection continues for t
V

to allow for processor stabilization. After t

PFD

mal RAM operation can resume.

CC

, write-protection takes

WPT

for an accumulated period of

after VCCreaches

CER

CER

, nor-

Clock Interface

Reading the Clock

The interface to the clock and control registers of the
bq4842Y is the same as that for the general-purpose stor­age memory. Once every second, the user-accessible
clock/calendar locations are updated simultaneously from
the internal real time counters. To prevent reading data
in transition, updates to the bq4842Y clock registers

should be halted. Updating is halted by setting the read
bit D6 of the control register to 1. As long as the read bit
is 1, updates to user-accessible clock locations are inhib­ited. Once the frozen clock information is retrieved by
reading the appropriate clock memory locations, the read
bit should be reset to 0 in order to allow updates to occur
from the internal counters. Because the internal coun­ters are not halted by setting the read bit, reading the
clock locations has no effect on clock accuracy. Once the
read bit is reset to 0, within one second the internal regis­ters update the user-accessible registers with the correct
time. A halt command issued during a clock update al­lows the update to occur before freezing the data.

Setting the Clock

Bit D7 of the control register is the write bit. Like the
read bit, the write bit when set to a 1 halts updates to
the clock/calendar memory locations. Once frozen, the
locations can be written with the desired information in
24-hour BCD format. Resetting the write bit to 0 causes
the written values to be transferred to the internal clock
counters and allows updates to the user-accessible regis­ters to resume within one second. Use the write bit, D7,
only when updating the time registers (1FFF–1FFF9).

Table 1. bq4842 Clock and Control Register Map

Address D7 D6 D5 D4 D3 D2 D1 D0 Range (h) Register

1FFFF 10 Years Year 00–99 Year
1FFFF X X X 10 Month Month 01–12 Month
1FFFD X X 10 Date Date 01–31 Date
1FFFC X FTE X X X Day 01–07 Days
1FFFB X X 10 Hours Hours 00–23 Hours
1FFFA X 10 Minutes Minutes 00–59 Minutes
1FFF9 OSC 10 Seconds Seconds 00–59 Seconds
1FFF8 W R S Calibration 00–31 Control
1FFF7 WDS BM4 BM3 BM2 BM1 BM0 WD1 WD0 Watchdog
1FFF6 AIE PWRIE ABE PIE RS3 RS2 RS1 RS0 Interrupts
1FFF5 ALM3 X 10-date alarm Alarm date 01–31 Alarm date
1FFF4 ALM2 X 10-hour alarm Alarm hours 00–23 Alarm hours
1FFF3 ALM1 Alarm 10 minutes Alarm minutes 00–59 Alarm minutes
1FFF2 ALM0 Alarm 10 seconds Alarm seconds 00–59 Alarm seconds
1FFF1 0.1 seconds 0.01 seconds 00–99 0.1/0.01 seconds
1FFF0 WDF AF PWRF BLF PF X X X Flags

Notes: X = Unused bits; can be written and read.

Clock/Calendar data in 24-hour BCD format.
BLF = 1 for low battery.
OSC = 1 stops the clock oscillator.
Interrupt enables are cleared on power-up.

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bq4842Y

Table 2. Clock and Control Register Bits

Bits Description

ABE

AF Alarm interrupt flag
AIE Alarm interrupt enable
ALM0–ALM3 Alarm repeat rate
BLF Battery-low flag
BM0–BM4 Watchdogmultiplier
FTE Frequency test mode enable
OSC Oscillatorstop
PF Periodic interrupt flag
PIE Periodic interrupt enable
PWRF Power-fail interrupt flag
PWRIE Power-fail interrupt enable
R Read clock enable
RS0–RS3 Periodic interrupt rate
S Calibration sign
W Write clock enable
WD0–WD1 Watchdog resolution
WDF Watchdog flag
WDS Watchdogsteering

Alarm interrupt enable in
battery-backup mode

Stopping and Starting the Clock Oscillator

The OSC bit in the seconds register turns the clock on or
off. If the bq4842Y is to spend a significant period of
time in storage, the clock oscillator can be turned off to
preserve battery capacity. OSC set to 1 stops the clock
oscillator. When OSC is reset to 0, the clock oscillator is
turned on and clock updates to user-accessible memory
locations occur within one second.

The OSC bit is set to 1 when shipped from the Bench­marq factory.

adjust the calibration based on the typical operating
temperature of individual applications.

The software calibration bits are located in the control reg­ister . Bits D0–D4 control the magnitude of correction, and
bit D5 the direction (positive or negative) of correction.
Assuming that the oscillator is running at exactly 32,786
Hz, each calibration step of D0–D4 adjusts the clock rate
by +4.068 ppm (+10.7 seconds per month) or -2.034 ppm
(-5.35 seconds per month) depending on the value of the
sign bit D5. When the sign bit is 1, positive adjustment
occurs; a 0 activates negative adjustment. The total range
of clockcalibrationis+5.5or-2.75minutespermonth.

Two methods can be used to ascertain how much cali­bration a given bq4842Y may require in a system. The
first involves simply setting the clock, letting it run for a
month, and then comparing the time to an accurate
known reference like WWV radio broadcasts. Based on
the variation to the standard, the end user can adjust
the clock to match the system’s environment even after
the product is packaged in a non-serviceable enclosure.
The only requirement is a utility that allows the end
user to access the calibration bits in the control register.

The second approach uses a bq4842Y test mode. When the
frequency test mode enable bit FTE in the days register is
set to a 1, and the oscillator is running at exactly 32,768 Hz,
the LSB of the seconds register toggles at 512 Hz. Any de­viation from 512 Hz indicates the degree and direction of os­cillator frequency shift at the test temperature. For example,
a reading of 512.01024 Hz indicates a (1E6*0.01024)/512 or
+20 ppm oscillator frequency error, requiring ten steps of
negative calibration (10*-2.034 or -20.34) or 001010 to be
loaded into the calibration byte for correction. To read the
test frequency , the bq4842Y must be selected and held in an
extended read of the seconds register, location 1FFF9, with-

Calibrating the Clock

The bq4842Y real-time clock is driven by a quartz con­trolled oscillator with a nominal frequency of 32,768 Hz.
The quartz crystal is contained within the bq4842Y
package along with the battery. The clock accuracy of
the bq4842Y module is tested to be within 20ppm or
about 1 minute per month at 25°C. The oscillation rates
of crystals change with temperature as Figure 3 shows.
To compensate for the frequency shift, the bq4842Y of­fers onboard software clock calibration. The user can

Sept. 1996C

Figure 3. Frequency Error

5

bq4842Y

out having the read bit set. The frequency appears on
DQ0. The FTE bit must be set using the write bit con­trol. The FTE bit must be reset to 0 for normal clock op­eration to resume.

Power-On Reset

The bq4842Y provides a power-on reset, which pulls the
RST pin low on power-down and remains low on power­up for t

after VCCpasses V

CER

PFD.

Watchdog Timer

The watchdog circuit monitors the microprocessor’s ac­tivity. If the processor does not reset the watchdog timer
within the programmed time-out period, the circuit as­serts the INT or RST pin. The watchdog timer is acti­vated by writing the desired time-out period into the
eight-bit watchdog register described in Table 3 (device
address 1FFF7). The five bits (BM4–BM0) store a bi­nary multiplier, and the two lower-order bits
(WD1–WD0) select the resolution, where 00 =

1

01 =

second,10=1second,and11=4seconds.

4

The time-out period is the multiplication of the five-bit multi­plier with the two-bit resolution. For example, writing 00011
in BM4–BM0 and 10 in WD1–WD0 results in a total time­out setting of3x1or3seconds. A multiplier of zero disables
the watchdog circuit. Bit 7 of the watchdog register (WDS) is
the watchdog steering bit. When WDS is set toa1anda
time-out occurs, the watchdog asserts a reset pulse for t
on the RST pin. During the reset pulse, the watchdog regis­ter is cleared to all zeros disabling the watchdog. When
WDS is set to a 0, the watchdog asserts the INT pin on a
time-out. The INT pin remains low until the watchdog is re­set by the microprocessor or a power failure occurs. Addition­ally, when the watchdog times out, the watchdog flag bit
(WDF) in the flags register ,location 1FFF0,is set.

To reset the watchdog timer, the microprocessor must write
to the watchdog register. After being reset by a write, the
watchdog time-out period starts over. As a precaution, the
watchdog circuit is disabled on a power failure. The user
must,therefore, set the watchdogat boot-up for activation.

1

16

second,

CER

Interrupts

The bq4842Y allows four individually selected interrupt
events to generate an interrupt request on the INT pin.
These four interrupt events are:

The watchdog timer interrupt, programmable to

■

occur according to the time-out period and conditions
described in the watchdog timer section.

The periodic interrupt, programmable to occur once

■

every 122µs to 500ms.
The alarm interrupt, programmable to occur once per

■

second to once per month.
The power-fail interrupt, which can be enabled to be

■

asserted when the bq4842Y detects a power failure.

The periodic, alarm, and power-fail interrupts are en­abled by an individual interrupt-enable bit in register
1FFF6, the interrupts register. When an event occurs,
its event flag bit in the flags register, location 1FFF0, is
set. If the corresponding event enable bit is also set,
then an interrupt request is generated. Reading the
flags register clears all flag bits and makes INT
pedance. To reset the flag register, the bq4842Y ad­dresses must be held stable at location 1FFF0 for at
least 50ns to avoid inadvertent resets.

PeriodicInterrupt

Bits RS3–RS0 in the interrupts register program the rate
for the periodic interrupt. The user can interpret the inter­rupt in two ways: either by polling the flags register for PF
assertion or by setting PIE so that INT goes active when
the bq4842Y sets the periodic flag. Reading the flags regis­ter resets the PF bit and returns INT to the high­impedance state. Table 4 shows the periodic rates.

Alarm Interrupt

Registers 1FFF5–1FFF2 program the real-time clock
alarm. During each update cycle, the bq4842Y com­pares the date, hours, minutes, and seconds in the clock
registers with the corresponding alarm registers. If a
match between all the corresponding bytes is found, the
alarm flag AF in the flags register is set. If the alarm
interrupt is enabled with AIE, an interrupt request is
generated on INT. The alarm condition is cleared by a
read to the flags register. ALM3–ALM0 puts the alarm

high im-

Table 3. Watchdog Register Bits

MSB Bits LSB

76543210

WDS BM4 BM3 BM2 BM1 BM0 WD1 WD0

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