Texas Instruments BQ4832YMA-85 Datasheet

bq4832Y

RTC Module With 32Kx8 NVSRAM

Features

➤ Integrated SRAM, real-time

clock, CPU supervisor, crystal, power-fail circuit,andbattery

➤ Real-Time Clock counts hun-

dredths of seconds through years in BCD format

➤ RAM-like clock access ➤ Compatible with industry-

standard 32K x 8 SRAMs

➤ Unlimited write cycles ➤ 10-year minimum data retention

and clock operation in the absence of power

➤ Automatic power-fail chip dese-

lect and write-protection

➤ Watchdogtimer,power-on reset,

alarm/periodic interrupt, powerfail and battery-low warning

➤ Software clock calibration for

greater than±1 minute per month accuracy

Pin Connections

RST

32-Pin DIP Module

32 31

30 29 28 27 26 25 24 23 22

21 20 19 18 17

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General Description

The bq4832Y RTC Module is a nonvolatile 262,144-bit SRAM organized as 32,768 words by 8 bits with an integral real-time clock and CPU supervisor. The CPU supervisor provides a programmable watchdog timer and a microprocessor reset. Other features include alarm, power-fail, and periodic interrupts, and abattery-low warning.

The device combines an internal lithium battery,quartz crystal, clock and power-fail chip, and a full CMOS SRAM in a plastic 32-pin DIP module. The RTC Module directly replaces industry-standard SRAMs and also fits into many EPROM and EEPROM sockets without any requirement for special write timing or limitations on the number of write cycles.

Pin Names

A0–A

V NC

INT WE A A A A OE A CE DQ DQ DQ DQ DQ

13 8 9 11

7 6 5 4 3

CE Chip enable

RST Microprocessor reset

WE Write enable

OE Output enable

DQ0–DQ7Data in/data out

INT Programmable interrupt

Registers for the real-time clock, alarm and other special functions are located in registers 7FF0h– 7FFFh of the memory array.

The clock and alarm registers are dual-port read/write SRAM locations that are updated once per second by a clock control circuit from the internal clock counters. The dual-port registers allow clock updates to occur without interrupting normal access to the rest of the SRAM array.

The bq4832Y also contains a powerfail-detect circuit. The circuit deselects the device whenever V below tolerance, providing a high degree of data security. The battery is electrically isolated when shipped from the factory to provide maximum battery capacity. The battery remains disconnected until the first application of VCC.

Address input

+5 volts

Ground

falls

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bq4832Y

Functional Description

Figure 1 is a block diagram of the bq4832Y. The following sections describe the bq4832Y functional operation,

including memory and clock interface, data-retention modes, power-on reset timing, watchdog timer activation,and interrupt generation.

Truth Table

(max.) V

(min.) V

(min.) > V

PFD

≤ V

Figure 1. Block Diagram

CE OE WE Mode DQ Power

X X Deselect High Z Standby XVILWrite D

Read D Read High Z Active

OUT

X X X Deselect High Z CMOS standby X X X Deselect High Z Battery-backup mode

Active Active

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bq4832Y

Address Map

The bq4832Y provides 16 bytes of clock and control status registers and 32,752 bytes of storage RAM.

Figure 2 illustrates the address map for the bq4832Y. Table 1 is a map of the bq4832Y registers, and Table 2 describes the register bits.

Memory Interface

Read Mode

The bq4832Y is in read mode whenever OE (output enable) is low and CE (chip enable) is low. The device architecture allows ripple-through access of data from eight of 262,144 locations in the static storage array. Thus, the unique address specified by the 15 address inputs defines which one of the 32,768 bytes of data is to be accessed. Valid data is available at the data I/O pins within tAA(address access time) after the last address input signal is stable, providing that the CE and OE (output enable) access times are also satisfied. If the CE and OE access times are not met, valid data is available after the latter of chip enable access time (t put enable access time (tOE).

16 Bytes

Clock and

Control Status

Registers

32,752

Bytes

Storage

RAM

ACE

7FFF 7FF0

7FEF

0000

) or out-

and OE control the state of the eight three-state data I/O signals. If the outputs are activated before tAA, the data lines are driven to an indeterminate state until tAA. If the address inputs are changed while CE and OE remain low , output data remains valid for tOH(output data hold time), but goes indeterminate until the next address access.

Write Mode

The bq4832Y is in write mode whenever WE and CE are active. The start of a write is referenced from the latter-occurring falling edge of WE or CE. A write is terminated by the earlier rising edge of WE or CE. The addresses must be held valid throughout the cycle. CE or WE must return high for a minimum of t or t or write cycle.

Data-in must be valid t remain valid for t kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on CE and OE, a low on WE disables the outputs tWZafter WE falls.

from WE prior to the initiation of another read

WR1

prior to the end of write and

DH1

or t

afterward. OE should be

DH2

0 1 2 3 4 5 6 7 8

9 10 11 12 13

14 15

Year

Month

Date

Days

Hours

Minutes

Seconds

Control

Watchdog

Interrupts

Alarm Date

Alarm Hours

Alarm Minutes

Alarm Seconds

Tenths/

Hundredths

Flags

WR2

from CE

7FFF 7FFE 7FFD 7FFC 7FFB 7FFA 7FF9 7FF8 7FF7 7FF6 7FF5 7FF4 7FF3 7FF2

7FF1 7FF0

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Figure 2. Address Map

bq4832Y

Data-Retention Mode

With valid VCCapplied, the bq4832Y operates as a conventional static RAM. Should the supply voltage decay, the RAM automatically power-fail deselects, write-protecting itself t All outputs become high impedance, and all inputs are treated as “don’t care.”

If power-fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within time t protection takes place. When VCCdrops below VSO, the control circuit switches power to the internal energy source,which preserves data.

The internal coin cell maintains data in the bq4832Y after the initial application of V riod of at least 10 years when VCCis less than VSO.As system power returns and Vcc rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write-protection continues for t VCCreaches V After t

,normal RAM operation can resume.

CER

to allow for processor stabilization.

PFD

after VCCfalls below V

WPT

for an accumulated pe-

WPT

, write-

after

CER

Clock Interface

Reading the Clock

The interface to the clock and control registers of the

PFD

bq4832Y is the same as that for the general-purpose storage memory. Once every second, the user-accessible clock/calendar locations are updated simultaneously from the internal real time counters. To prevent reading data in transition, updates to the bq4832Y clock registers should be halted. Updating is halted by setting the read bit D6 of the control register to 1. As long as the read bit is 1, updates to user-accessible clock locations are inhibited. Once the frozen clock information is retrieved by reading the appropriate clock memory locations, the read bit should be reset to 0 in order to allow updates to occur from the internal counters. Because the internal counters are not halted by setting the read bit, reading the clock locations has no effect on clock accuracy. Once the read bit is reset to 0, within one second the internal registers update the user-accessible registers with the correct time. A halt command issued during a clock update allows the update to occur before freezing the data.

Table 1.bq4832Y Clock and Control Register Map

Address D7 D6 D5 D4 D3 D2 D1 D0 Range (h) Register

7FFF 10 Years Year 00–99 Year 7FFE X X X 10 Month Month 01–12 Month 7FFD X X 10 Date Date 01–31 Date 7FFC X FTE X X X Day 01–07 Days 7FFB X X 10 Hours Hours 00–23 Hours 7FFA X 10 Minutes Minutes 00–59 Minutes 7FF9 OSC 10 Seconds Seconds 00–59 Seconds 7FF8 W R S Calibration 00–31 Control 7FF7 WDS BM4 BM3 BM2 BM1 BM0 WD1 WD0 Watchdog 7FF6 AIE PWRIE ABE PIE RS3 RS2 RS1 RS0 Interrupts 7FF5 ALM3 X 10-date alarm Alarm date 01–31 Alarm date 7FF4 ALM2 X 10-hour alarm Alarm hours 00–23 Alarm hours 7FF3 ALM1 Alarm 10 minutes Alarm minutes 00–59 Alarm minutes 7FF2 ALM0 Alarm 10 seconds Alarm seconds 00–59 Alarm seconds 7FF1 0.1 seconds 0.01 seconds 00–99 0.1/0.01 seconds 7FF0 WDF AF PWRF BLF PF X X X Flags

Notes: X = Unused bits; can be written and read.

Clock/Calendar data in 24-hour BCD format. BLF = 1 for low battery. OSC = 1 stops the clock oscillator. Interrupt enables are cleared on power-up.

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Table 2.Clock and Control Register Bits

Bits Description

ABE AF Alarm interrupt flag

AIE Alarm interrupt enable ALM0–ALM3 Alarm repeat rate BLF Battery-low flag BM0–BM4 Watchdog multiplier FTE Frequency test mode enable OSC Oscillatorstop PF Periodic interrupt flag PIE Periodic interrupt enable PWRF Power-fail interrupt flag PWRIE Power-fail interrupt enable R Read clock enable RS0–RS3 Periodic interrupt rate S Calibration sign W Write clock enable WD0–WD1 Watchdog resolution WDF Watchdog flag WDS Watchdogsteering

Alarm interrupt enable in battery-backup mode

Setting the Clock

Bit D7 of the control register is the write bit. Like the read bit, the write bit when set to a 1 halts updates to the clock/calendar memory locations. Once frozen, the locations can be written with the desired information in 24-hour BCD format. Resetting the write bit to 0 causes the written values to be transferred to the internal clock counters and allows updates to the user-accessible registers to resume within one second. Use the write bit, D7, only when updating the time registers (7FFF-7FF9).

Calibrating the Clock

The bq4832Y real-time clock is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The quartz crystal is contained within the bq4832Y package along with the battery. The clock accuracy of the bq4832Y module is tested to be within 20ppm or about 1 minute per month at 25°C. The oscillation rates of crystals change with temperature as Figure 3 shows. To compensate for the frequency shift, the bq4832Y offers onboard software clock calibration. The user can adjust the calibration based on the typical operating temperature of individual applications.

The software calibration bits are located in the control register. Bits D0–D4 control the magnitude of correction, and bit D5 the direction (positive or negative) of correction. Assuming that the oscillator is running at exactly 32,786 Hz, each calibration step of D0–D4 adjusts the clock rate by +4.068 ppm (+10.7 seconds per month) or -2.034 ppm (-5.35 seconds per month) depending on the value of the sign bit D5. When the sign bit is 1, positive adjustment occurs; a 0 activates negative adjustment. The total range of clock calibration is +5.5 or

-2.75 minutes per month. Two methods can be used to ascertain how much cali-

bration a given bq4832Y may require in a system. The first involves simply setting the clock, letting it run for a month, and then comparing the time to an accurate known reference like WWV radio broadcasts. Based on the variation to the standard, the end user can adjust the clock to match the system’s environment even after the product is packaged in a non-serviceable enclosure. The only requirement is a utility that allows the end user to access the calibration bits in the control register.

Stopping and Starting the Clock Oscillator

The OSC bit in the seconds register turns the clock on or off. If the bq4832Y is to spend a significant period of time in storage, the clock oscillator can be turned off to preserve battery capacity. OSC set to 1 stops the clock oscillator. When OSC is reset to 0, the clock oscillator is turned on and clock updates to user-accessible memory locations occur within one second.

The OSC bit is set to 1 when shipped from the Benchmarq factory.

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Figure 3. Frequency Error

bq4832Y

The second approach uses a bq4832Y test mode. When the frequency test mode enable bit FTE in the days register is set to a 1,and the oscillator is running at exactly 32,768 Hz, the LSBof the seconds register toggles at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz indicates a (1E6*0.01024)/512 or +20 ppm oscillator frequency error, requiring ten steps of negative calibration (10*-2.034 or -20.34) or 001010 to be loaded into the calibration byte for correction. To read the test frequency, the bq4832Y must be selected and held in an extended read of the seconds register, location 7FF9, without having the read bit set. The frequency appears on DQ0. The FTE bit must be set using the write bit control. The FTE bit must be reset to 0 for normal clock operation to resume.

Power-On Reset

The bq4832Y provides a power-on reset, which pulls the RST pin low on power-down and remains low on powerup for t

after VCCpasses V

CER

PFD.

Watchdog Timer

The watchdog circuit monitors the microprocessor’s activity. If the processor does not reset the watchdog timer within the programmed time-out period, the circuit asserts the INT or RST pin. The watchdog timer is activated by writing the desired time-out period into the eight-bit watchdog register described in Table 3 (device address 7FF7). The five bits (BM4–BM0) store a binary multiplier, and the two lower-order bits (WD1–WD0) select the resolution, where 00 = 10 = 1 second, and 11 = 4 seconds.

The time-out period is the multiplication of the five-bit multiplier with the two-bit resolution. For example, writing 00011 in BM4–BM0 and 10 in WD1–WD0 results in a total time-out setting of3x1or3seconds. A multiplier of zero disables the watchdog circuit. Bit 7 of the watchdog register (WDS) is the watchdog steering bit. When WDS is set to a 1 and a time-out occurs, the watchdog asserts a reset pulse for t During the reset pulse, the watchdog register is cleared to all zeros disabling the watchdog. When WDS is set to a 0, the watchdog asserts the INT pin on a time-out. The INT pin remains low until the watchdog is reset by the microprocessor or a power failure occurs. Addition-

second, 01 =

CER

second,

on the RST pin.

ally, when the watchdog times out, the watchdog flag bit (WDF) in the flags register, location 7FF0,is set.

To reset the watchdog timer, the microprocessor must write to the watchdog register. After being reset by a write, the watchdog time-out period starts over. As a precaution, the watchdog circuit is disabled on a power failure. The user must, therefore, set the watchdog at boot-up for activation.

Interrupts

The bq4832Y allows four individually selected interrupt events to generate an interrupt request on the INT pin. These four interrupt events are:

The watchdog timer interrupt, programmable to

occur according to the time-out period and conditions described in the watchdog timer section.

The periodic interrupt, programmable to occur once

every 122µs to 500ms. The alarm interrupt, programmable to occur once per

second to once per month.

The power-fail interrupt, which can be enabled to be asserted when the bq4832Y detects a power failure.

The periodic, alarm, and power-fail interrupts are enabled by an individual interrupt-enable bit in register 7FF6, the interrupts register. When an event occurs, its event flag bit in the flags register, location 7FF0, is set. If the corresponding event enable bit is also set, then an interrupt request is generated. Reading the flags register clears all flag bits and makes INT To reset the flag register, the bq4832Y addresses must be held stable at location 7FF0 for at least 50ns to avoid inadvertent resets.

PeriodicInterrupt

Bits RS3–RS0 in the interrupts register program the rate for the periodic interrupt. The user can interpret the interrupt in two ways: either by polling the flags register for PF assertion or by setting PIE so that INT goes active when the bq4832Y sets the periodic flag. Reading the flags register resets the PF bit and returns INT to the high-impedance state. Table 4 shows the periodic rates.

high impedance.

Table 3.Watchdog Register Bits

MSB Bits LSB

76543210

WDS BM4 BM3 BM2 BM1 BM0 WD1 WD0

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