Texas Instruments BQ4822YMA-70 Datasheet

bq4822Y

RTC Module With 8Kx8 NVSRAM

Features

➤ Integrated SRAM, real-time

clock, CPU supervisor, crystal, power-fail circuit,andbattery

➤ Real-Time Clock counts hun-

dredths of seconds through years in BCD format

➤ RAM-like clock access ➤ Compatible with industry-

standard 8K x 8 SRAMs

➤ Unlimited write cycles ➤ 10-year minimum data retention

and clock operation in the absence of power

➤ Automatic power-fail chip dese-

lect and write-protection

➤ Watchdogtimer, power-on reset,

alarm/periodic interrupt, powerfail and battery-low warning

➤ Automatic leap year adjustment ➤ Software clock calibration for

greater than ±1 minute per month accuracy

General Description

The bq4822Y RTC Module is a nonvolatile 65,536-bit SRAM organized as 8192 words by 8 bits with an integral real-time clock and CPU supervisor. The CPU supervisor provides a programmable watchdog timer and a microprocessor reset. Other features include an alarm, power-fail and periodic interrupt, and a battery low warning.

The device combines an internal lithium battery,quartz crystal, clock and power-fail chip, and a full CMOS SRAM in a plastic 28-pin DIP module. The RTC Module directly replaces industry-standard SRAMs and also fits into many EPROM and EEPROM sockets without any requirement for special write timing or limitations on the number of write cycles.

Registers for the real-time clock, alarm and other special functions are located in registers 1FF0h–1FFFh of the memory array.

The clock and alarm registers are dual-port read/write SRAM locations that are updated once per second by a clock control circuit from the internal clock counters. The dual-port registers allow clock updates to occur without interrupting normal access to the rest of the SRAM array.

The bq4822Y also contains a powerfail-detect circuit. The circuit deselects the device whenever V

falls below tolerance, providing a high degree of data security. The battery is electrically isolated when shipped from the factory to provide maximum battery capacity. The battery remains disconnected until the first application of VCC.

Pin Connections

RST

28-Pin DIP Module

May 1997

Pin Names

A0–A

INT A

18 17 16 15

DQ DQ DQ

PN482201.eps

6 5 4 3

CE Chip enable

RST Microprocessor reset

WE Write enable

OE Output enable

DQ0–DQ7Data in/data out

INT Programmable interrupt

Address input

+5 volts

Ground

bq4822Y

Functional Description

Figure 1 is a block diagram of the bq4822Y. The following sections describe the bq4822Y functional operation,

Time-

Base

Oscillator

Control/Status

Registers

Clock/Calendar, Alarm

and Control Bytes

Storage Registers

(16 Bytes)

Storage Registers

(8,176 Bytes)

CE OE

DQ0–DQ

AD0–AD

Internal

Battery

Internal

Quartz Crystal

Bus

I/F

Power-

Fail

Control

Write Protect

including memory and clock interface, data-retention modes, power-on reset timing, watchdog timer activation,and interrupt generation.

÷ 8 ÷ 64 ÷ 64

16 1 MUX

Reset and

Interupt

Generator

Control/Calendar

Update

BD482201.eps

RST

INT

Truth Table

(max.) V

(min.) V

(min.) > V

PFD

≤ V

Figure 1. Block Diagram

CE OE WE Mode DQ Power

X X Deselect High Z Standby XVILWrite D

Read D Read High Z Active

OUT

X X X Deselect High Z CMOS standby X X X Deselect High Z Battery-backup mode

Active Active

May 1997

Address Map

The bq4822Y provides 16 bytes of clock and control status registers and 8,176 bytes of storage RAM.

Figure 2 illustrates the address map for the bq4822Y. Table 1 is a map of the bq4822Y registers, and Table 2 describes the register bits.

Memory Interface

Read Mode

The bq4822Y is in read mode whenever OE (output enable) is low and CE (chip enable) is low. The device architecture allows ripple-through access of data from eight of 65,536 locations in the static storage array. Thus, the unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data is available at the data I/O pins within tAA(address access time) after the last address input signal is stable, providing that the CE and OE (output enable) access times are also satisfied. If the CE and OE access times are not met, valid data is available after the latter of chip enable access time (t put enable access time (tOE).

ACE

) or out-

bq4822Y

and OE control the state of the eight three--state data I/O signals. If the outputs are activated before tAA, the data lines are driven to an indeterminate state until tAA. If the address inputs are changed while CE and OE remain low , output data remains valid for tOH(output data hold time), but goes indeterminate until the next address access.

Write Mode

The bq4822Y is in write mode whenever WE and CE are active. The start of a write is referenced from the latter--occurring falling edge of WE or CE. A write is terminated by the earlier rising edge of WE or CE. The addresses must be held valid throughout the cycle. CE or WE must return high for a minimum of t CE or t read or write cycle.

Data-in must be valid t remain valid for t kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on CE and OE, a low on WE disables the outputs tWZafter WE falls.

from WE prior to the initiation of another

WR1

prior to the end of write and

DH1

or t

afterward. OE should be

DH2

WR2

from

16 Bytes

8,176 Bytes

May 1997

Clock and

Control Status

Registers

Storage

RAM

1FFF 1FF0

1FEF

0000

Figure 2. Address Map

0 1 2 3 4 5 6 7 8 9

Alarm Date

Alarm Hours

Alarm Minutes

Alarm Seconds

13 14

Hundredths

Year

Month

Date

Days

Hours

Minutes

Seconds

Control

Watchdog

Interrupts

Tenths/

Flags

FG482201.eps

1FFF 1FFE 1FFD 1FFC 1FFB 1FFA 1FF9 1FF8 1FF7 1FF6 1FF5 1FF4 1FF3 1FF2

1FF1 1FF0

bq4822Y

Data-Retention Mode

With valid VCCapplied, the bq4822Y operates as a conventional static RAM. Should the supply voltage decay, the RAM automatically power-fail deselects, write-protecting itself t All outputs become high impedance, and all inputs are treated as “don't care.”

If power-fail detection occurs during a valid access, the memory cycle continues to completion. If the memory cycle fails to terminate within time t protection takes place. When VCCdrops below VSO, the control circuit switches power to the internal energy source,whichpreserves data.

The internal coin cell maintains data in the bq4822Y after the initial application of V riod of at least 10 years when VCCis less than VSO.As system power returns and Vcc rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Write-protection continues for t VCCreaches V After t

,normal RAM operation can resume.

CER

to allow for processor stabilization.

PFD

after VCCfalls below V

WPT

for an accumulated pe-

WPT

, write-

after

CER

Clock Interface

Reading the Clock

The interface to the clock and control registers of the

PFD

bq4822Y is the same as that for the general-purpose storage memory. Once every second, the user-accessible clock/calendar locations are updated simultaneously from the internal real time counters. To prevent reading data in transition, updates to the bq4822Y clock registers should be halted. Updating is halted by setting the read bit D6 of the control register to 1. As long as the read bit is 1, updates to user-accessible clock locations are inhibited. Once the frozen clock information is retrieved by reading the appropriate clock memory locations, the read bit should be reset to 0 in order to allow updates to occur from the internal counters. Because the internal counters are not halted by setting the read bit, reading the clock locations has no effect on clock accuracy. Once the read bit is reset to 0, within one second the internal registers update the user-accessible registers with the correct time. A halt command issued during a clock update allows the update to occur before freezing the data.

Table 1.bq4822Y Clock and Control Register Map

Address D7 D6 D5 D4 D3 D2 D1 D0 Range (h) Register

1FFF 10 Years Year 00–99 Year 1FFE X X X 10 Month Month 01–12 Month 1FFD X X 10 Date Date 01–31 Date 1FFC X FTE X X X Day 01–07 Days 1FFB X X 10 Hours Hours 00–23 Hours 1FFA X 10 Minutes Minutes 00–59 Minutes 1FF9 OSC 10 Seconds Seconds 00–59 Seconds 1FF8 W R S Calibration 00–31 Control 1FF7 WDS BM4 BM3 BM2 BM1 BM0 WD1 WD0 Watchdog 1FF6 AIE PWRIE ABE PIE RS3 RS2 RS1 RS0 Interrupts 1FF5 ALM3 X 10-date alarm Alarm date 01–31 Alarm date 1FF4 ALM2 X 10-hour alarm Alarm hours 00–23 Alarm hours 1FF3 ALM1 Alarm 10 minutes Alarm minutes 00–59 Alarm minutes 1FF2 ALM0 Alarm 10 seconds Alarm seconds 00–59 Alarmseconds 1FF1 0.1 seconds 0.01 seconds 00–99 0.1/0.01 seconds 1FF0 WDF AF PWRF BLF PF X X X Flags

Notes: X = Unused bits; can be written and read.

Clock/Calendar data in 24-hour BCD format. BLF = 1 for low battery. OSC = 1 stops the clock oscillator. Interrupt enables are cleared on power-up.

May 1997

bq4822Y

Table 2.Clock and Control Register Bits

Bits Description

ABE AF Alarm interrupt flag

AIE Alarm interrupt enable ALM0–ALM3 Alarm repeat rate BLF Battery-low flag BM0–BM4 Watchdog multiplier FTE Frequency test mode enable OSC Oscillatorstop PF Periodic interrupt flag PIE Periodic interrupt enable PWRF Power-fail interrupt flag PWRIE Power-fail interrupt enable R Read clock enable RS0–RS3 Periodic interrupt rate S Calibration sign W Write clock enable WD0–WD1 Watchdog resolution WDF Watchdog flag WDS Watchdogsteering

Alarm interrupt enable in battery-backup mode

Setting the Clock

Bit D7 of the control register is the write bit. Like the read bit, the write bit when set to a 1 halts updates to the clock/calendar memory locations. Once frozen, the locations can be written with the desired information in 24-hour BCD format. Resetting the write bit to 0 causes the written values to be transferred to the internal clock counters and allows updates to the user-accessible registers to resume within one second.

Stopping and Starting the Clock Oscillator

The OSC bit in the seconds register turns the clock on or off. If the bq4822Y is to spend a significant period of time in storage, the clock oscillator can be turned off to preserve battery capacity. OSC set to 1 stops the clock oscillator. When OSC is reset to 0, the clock oscillator is turned on and clock updates to user-accessible memory locations occur within one second.

The OSC bit is set to 1 when shipped from the Benchmarq factory.

Calibrating the Clock

The bq4822Y real-time clock is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The quartz crystal is contained within the bq4822Y package along with the battery. The clock accuracy of the bq4822Y module is tested to be within 20ppm or about 1 minute per month at 25°C. The oscillation rates of crystals change with temperature as Figure 3 shows. To compensate for the frequency shift, the bq4822Y offers onboard software clock calibration. The user can adjust the calibration based on the typical operating temperature of individual applications.

The software calibration bits are located in the control register. Bits D0–D4 control the magnitude of correction, and bit D5 the direction (positive or negative) of correction. Assuming that the oscillator is running at exactly 32,786 Hz, each calibration step of D0–D4 adjusts the clock rate by +4.068 ppm (+10.7 seconds per month) or -2.034 ppm (-5.35 seconds per month) depending on the value of the sign bit D5. When the sign bit is 1, positive adjustment occurs; a 0 activates negative adjustment. The total range of clock calibration is +5.5 or

-2.75 minutes per month. Two methods can be used to ascertain how much cali-

bration a given bq4822Y may require in a system. The first involves simply setting the clock, letting it run for a month, and then comparing the time to an accurate known reference like WWV radio broadcasts. Based on the variation to the standard, the end user can adjust the clock to match the system's environment even after the product is packaged in a non-serviceable enclosure. The only requirement is a utility that allows the end user to access the calibration bits in the control register.

-20

-40

-60

-80

Frequency Error

-100

-120

-30 -20-10 0 10 20 30 40 50 60

GR482201

Temperature ( C)

Figure 3. Frequency Error

May 1997

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