Texas Instruments bq24741, bq24742 Schematics

SW

LPMOD

18

17

16

15

21

bq24741

QFN-28

TOP VIEW

24 23 22

8 9 10 11 12

1

2

3

5

6

CE

ACN

ACP

ACDET

LPREF

ACSET

13 14

20

19

27 26 2528

IADAPT

ISET

BAT

CSP

CELLS

7

bq24741/2

QFN-28

TOP VIEW

8 9 10 11 12

1

2

3

4

5

6

27

CSN

7

PVCC

BTST

HIDRV

REGN

LODR

PGND

TRICKL

AGND

VREF

VDAC

VADJ

EXTPWR

FSET

DPMDET

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bq24741, bq24742

SLUS875B –MARCH 2009–REVISED OCTOBER 2009

Li-Ion or Li-Polymer Battery Charger with Low Iqand Accurate Trickle Charge

Check for Samples :bq24741 bq24742

1

FEATURES

• NMOS-NMOS Synchronous Buck Converter

• Resistor-Programmable Switching Frequency
between 300 kHz and 800 kHz

• 9 V-24 V Input Voltage Operation Range

• Support Two to Four Cells

• Analog Inputs with Ratiometric Programming
via Resistors or DAC/GPIO

– Charge Voltage (4-4.512 V/cell)
– Charge Current (up to 10 A)
– Adapter Current Limit for DPM

• High-Accuracy Voltage and Current Regulation
– ±0.5% Charge Voltage Accuracy
– ±3% Charge Current Accuracy
– ±3% Adapter Current Accuracy
– ±2% Input Current Sense Amp Accuracy

• 150 mA Trickle-charge Current with ±33%
Accuracy Down to Zero Battery Voltage

• Safety Protection
– Input Overvoltage Protection
– Battery Overvoltage Protection
– Charger Overcurrent Protection
– Thermal Shutdown Protection
– FET/Inductor/Battery Short Protection

• Status and Monitoring Outputs
– Adapter Present Indicator
– Programmable Input Power Detect with

Adjustable Threshold

– Dynamic Power Management (DPM) with

Status Indicator

– Current Drawn from Input Source

• Charge Enable Pin

• Internal Soft-Start and Loop Compensation

• 25 ns Minimum Driver Dead-Time and 99.5%
Maximum Effective Duty Cycle

• 28-pin, 5x5-mm2QFN package

• Energy Star Low Quiescent Current I
– < 10 μA Off-State Battery Discharge Current
– < 1.5 mA Off-State Input Quiescent Current

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

q

APPLICATIONS

• Notebook and Ultra-Mobile PC

• Portable Data Capture Terminals

• Portable Printers

• Medical Diagnostics Equipment

• Battery Bay Chargers

• Battery Back-up Systems

DESCRIPTION

The bq24741/2 is a high-efficiency, synchronous
battery charger with integrated compensation,
offering low component count for space-constrained
Li-ion or Li-polymer battery charging applications.
Ratiometric charge current and voltage programming
allows high regulation accuracies, and can be either
hardwired with resistors or programmed by the
system power-management microcontroller using a
DAC or GPIOs.

The bq24741/2 charges two, three, or four series Li+
cells, supporting up to 10 A of charge current, and is
available in a 28-pin, 5x5-mm2thin QFN package.

Text for space
Text for space

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2009, Texas Instruments Incorporated

VREF

R

AC

0.010 Ω

Q1 (ACFET)

SI4435

Q3(BATFET)

SI4435

Controlledby

HOST

N

PP

ACN

ACP

ACDET

EXTPWR

ISET

ACSET

VREF

GPIO

CELLS

CE

VDAC

VADJ

ADC IADAPT

HOST

PVCC

HIDRV

N

SW

BTST

REGN

LODRV

PGND

CSP

CSN

P

PACK+

PACK-

SYSTEM

ADAPTER+

ADAPTER-

EXTPWR

AGND

bq24741/2

432 kΩ
1%

66.5 kΩ
1%

R1

R2

R3

C4

C2

C3

C5

C8

Q4_A
FDS8978

Q4_B
FDS8978

C9

L1

D1 BAT54

C10

BAT

TRICKLE

FSET

R6

97.6

kΩ

DPMDET

R4

LPMOD

VREF

LPREF

R7

73.2 kΩ
1%

R8

26.7 kΩ
1%

Q2 (ACFET)

SI4435

Controlledby

HOST

C6

C15

0.1 µF

R5

C1

2 Ω

R11

2.2 µF

0.1 µF

0.1 µF

1 µF

10 kΩ 10k Ω

100 pF

C14

0.1 µF

C13

0.1 µF

0.1 µF

1 µF

C11
10 µF

10µH

R

SR

0.020 Ω

0.1 µF

10 µF

C7

10 µF

C12
10 µF

PowerPad

D2

BAT54

C13

100 nF

120 kΩ

R14

ISET_PWM

VREF

102 kΩ

1%

R12

64.9 kΩ
1%

R13

VREF

60.4 kΩ
1%

R9

40.2 kΩ
1%

R10

(D=0.72,V =VDAC)

peak

10k Ω

10kΩ

R15

R16

10 Ω

bq24741, bq24742

SLUS875B –MARCH 2009–REVISED OCTOBER 2009

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION (CONTINUED)

The bq24741/2 features resistor-programmable PWM switching frequency and accurate 150mA trickle charge
(with 20 mΩ sensing resistor), which can be enabled via the TRICKLE pin. The bq24741/2 also features Dynamic
Power Management (DPM) and input power limiting. These features reduce battery charge current when the
input power limit is reached to avoid overloading the AC adapter when supplying the load and the battery charger
simultaneously. A high-accuracy current sense amplifier enables accurate measurement of input current from the
AC adapter, allowing monitoring the overall system power. If the adapter current is above the programmed
low-power threshold, a signal is sent to host so that the system optimizes its power performance according to
what is available from the adapter.

Text for space
Text for space

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Text for space

FS= 400 kHz, 90 W Adapter, V

Figure 1. Typical System Schematic, Voltage, and Current Programmed by Resistor

Text for space
Text for space
Text for space
Text for space

2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated

ADAPTER

= 19 V, V

Product Folder Link(s) :bq24741 bq24742

= 3-cell Li-Ion (4.2V/cell), I

BAT

charge

= 3.6 A, I

adapter_limit

= 4.0 A

VREF

R

AC

0.010 Ω

Q1 (ACFET)

SI4435

Q3 (BATFET)

SI4435

Controlledby

HOST

N

PP

ACN

ACP

ACDET

EXTPWR

ISET

ACSET

VREF

GPIO

CELLS

CE

VDAC

VADJ

DAC

ADC IADAPT

HOST

PVCC

HIDRV

N

SW

BTST

REGN

LODRV

PGND

CSP

CSN

P

PACK+

PACK-

SYSTEM

ADAPTER+

ADAPTER-

EXTPWR

AGND

bq24741/2

432 kΩ
1%

66.5 kΩ
1%

R1

R2

R3

C4

C2

C3

C5

C8

Q4_A
FDS8978

Q4_B
FDS8978

C9

L1

D1 BAT54

C10

BAT

TRICKLE

FSET

R6

56.2 kΩ

DPMDET

R4

LPMOD

VREF

LPREF

R7

73.2 kΩ
1%

R8

26.7 kΩ
1%

Q2 (ACFET)

SI4435

Controlledby

HOST

C6

C15

0.1 µF

R5

C1

2 Ω

R11

2.2 µF

0.1 µF

0.1 µF

1 µF

10 kΩ 10k Ω

10 kΩ

100 pF

C14

0.1 µF

C13

0.1 µF

0.1 µF

1 µF

C11
10 µF

4.7 µH

R

SR

0.020 Ω

0.1 µF

10 µF

C7

10 µF

C12
10 µF

PowerPad

D2

BAT54

C13

100 nF

120 kΩ

R14

ISET_PWM

(D=0.72,V =VDAC)

peak

10 kΩ

R15

R16

10 Ω

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Text for space

bq24741, bq24742

SLUS875B –MARCH 2009–REVISED OCTOBER 2009

Text for space

(1) Pull-up rail could be either VREF or other system rail.
(2) SRSET/ACSET could come from either DAC or resistor dividers.
FS= 650 kHz, 90 W Adapter, V

Figure 2. Typical System Schematic, Voltage and Current Programmed by DAC

Part number Package Ordering Number Quantity

bq24741 28-PIN 5 x 5 mm2QFN

bq24742 28-PIN 5 x 5 mm2QFN

PACKAGE THERMAL DATA

PACKAGE θ

QFN – RHD

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

(2) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is

connected to the ground plane by a 2x3 via matrix.

Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 3

(1) (2)

JA

39°C/W 2.36 W 0.028 W/°C

ADAPTER

= 19 V, V

= 3-cell Li-Ion (4.2V/cell), I

BAT

charge

= 3.6 A, I

adapter_limit

= 4.0 A

ORDERING INFORMATION

TA= 25°C POWER RATING DERATING FACTOR ABOVE TA= 25°C

Product Folder Link(s) :bq24741 bq24742

(Tape and Reel)

bq24741RHDR 3000
bq24741RHDT 250
bq24742RHDR 3000
bq24742RHDT 250

bq24741, bq24742

SLUS875B –MARCH 2009–REVISED OCTOBER 2009

Table 1. Pin Functions – 28-Pin QFN

PIN

NAME NO.

CE 1

ACN 2 differential-mode filtering. An optional 0.1 μF ceramic capacitor is placed from ACN pin to AGND for common-mode

ACP 3

LPMOD 4 pull-up voltage rail. The output is HI when IADAPT pin voltage is lower than LPREF pin voltage. The output is LOW

ACDET 5 current sense amplifier is active when ACDET pin voltage is greater than 0.6V and PVCC > VUVLO. ACOV is input

ACSET 6

LPREF 7 the LOPWR comparator. The LPREF pin voltage is compared to the IADAPT pin voltage and the logic output is given

TRICKLE 8 with 20 mΩ sense resistor. A LOW level on this pin enables the ISET pin to program the charge current. It has an

AGND 9

VREF 10 could be used for ratio-metric programming of voltage and current regulation and for programming the LPREF

VDAC 11 ACSET pin voltages, respectively. Place resistor dividers from VDAC to VADJ, ISET, and ACSET pins to AGND for

VADJ 12 regulation set-point. Program by connecting a resistor divider from VDAC to VADJ, to AGND; or, by connecting the

EXTPWR 13 threshold OR input current is greater than 1.25 A with 10 mΩ sense resistor. Connect a 10 kΩ pull-up resistor from

FSET 14 PWM switching frequency (Fs) program pin. Program the switching frequency by placing a resistor to AGND on this pin.
IADAPT 15

ISET 16 regulation set-point. Program by connecting a resistor divider from VDAC to ISET, to AGND; or, by connecting the

BAT 17 pin to accurately sense the battery pack voltage. Place a 0.1 μF capacitor from BAT to AGND close to the IC to filter

CSN 18 differential-mode filtering. An optional 0.1 μF ceramic capacitor is placed from CSN pin to AGND for common-mode

CSP 19
CELLS 20 2, 3 or 4 cells selection logic input. Logic Lo programs 3–cell. Logic HI programs 4-cell. Floating programs 2–cell.

Charge-enable active-HIGH logic input. HI enables charge. LO disables charge. It has an internal 1 MΩ pull-down
resistor. A 10 KΩ external resistor is required to connect the CE pin to the external pull-up rail other than VREF.

Adapter current sense resistor, negative input. A 0.1 μF ceramic capacitor is placed from ACN to ACP to provide
filtering.

Adapter current sense resistor, positive input. A 0.1 μF ceramic capacitor is placed from ACN to ACP to provide
differential-mode filtering. A 0.1 μF ceramic capacitor is placed from ACP pin to AGND for common-mode filtering.

Low-power-mode-detect active-LOW open-drain logic output. Place a 10kohm pull-up resistor from LPMOD pin to the
when IADAPT pin voltage is higher than LPREF pin voltage. Internal 6% hysteresis.

Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from adapter
input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET pin voltage is greater than 2.4 V. IADAPT

over-voltage protection; it disables charge when ACDET > 3.1 V. ACOV does not latch, and normal operation resumes
when ACDET < 3.1 V.

Adapter current set input. The voltage ratio of ACSET voltage versus VDAC voltage programs the input current
regulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VDAC to
ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin and connect the DAC supply to the
VDAC pin.

Low power voltage set input. Connect a resistor divider from VREF to LPREF, and AGND to program the reference for
on the LPMOD open-drain pin. Connect LPREF to ACSET through a resistor divider to track the adapter power.

Trickle current enable logic input. When CE is HIGH, a HIGH level on this pin enables accurate 150 mA trickle charge
internal 1MΩ pull-down resistor.

Analog ground. Ground connection for low-current sensitive analog and digital signals. On PCB layout, connect to the
analog ground plane, and only connect to PGND through the PowerPad underneath the IC.

3.3 V regulated voltage output. Place a 1 μF ceramic capacitor from VREF to AGND pin close to the IC. This voltage
threshold. VREF is also the voltage source for the internal circuit.

Charge voltage set reference input. Connect the VREF or external DAC voltage source to VDAC pin. Battery voltage,
charge current, and input current are programmed as a ratio of the VDAC pin voltage versus the voltage on VADJ, and

programming. A DAC could be used by connecting the DAC supply to VDAC and connecting the output to VADJ, ISET,
or ACSET.

Charge voltage set input. The voltage ratio of VADJ voltage versus VDAC voltage programs the battery voltage
output of an external DAC to VADJ pin and connect the DAC supply to VDAC pin.

Valid adapter active-low detect logic open-drain output. Pulled LO when Input voltage is above ACDET programmed
EXTPWR pin to pull-up supply rail.

Adapter current sense amplifier output. IADAPT voltage is 20 times the differential voltage across ACP-ACN. Place a
100pF (max) or less ceramic decoupling capacitor from IADAPT to AGND.

Charge current set input. The voltage ratio of ISET voltage versus VDAC voltage programs the charge current
output of an external DAC to ISET pin and connect the DAC supply to VDAC pin.

Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal to the BAT
high frequency noise.

Charge current sense resistor, negative input. A 0.1 μF ceramic capacitor is placed from CSN to CSP to provide
filtering.

Charge current sense resistor, positive input. A 0.1 μF ceramic capacitor is placed from CSN to CSP to provide
differential-mode filtering. A 0.1 μF ceramic capacitor is placed from CSP pin to AGND for common-mode filtering.

DESCRIPTION

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Table 1. Pin Functions – 28-Pin QFN (continued)

PIN

NAME NO.

DPMDET 21 current is being limited by reducing the charge current. Connect 10-kohm pull-up resistor from DPMDET pin to VREF or

PGND 22 low-side power MOSFET, to ground connection of in put and output capacitors of the charger. Only connect to AGND

LODRV 23 PWM low side driver output. Connect to the gate of the low–side power MOSFET with a short and wide trace.

REGN 24 IC. Use for low side driver and high-side driver bootstrap voltage by connecting a small signal Schottky diode from

SW 25 drain, high-side power MOSFET source, and output inductor). Connect the 0.1 μF bootstrap capacitor from SW to

HIDRV 26 PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.

BTST 27

PVCC 28

PowerPad to the board, and have vias on the PowerPad plane connecting to AGND and PGND planes. It also serves as a thermal

Dynamic power management (DPM) input current loop active, open-drain output status. Logic low (LO) indicates input
a different pull-up supply rail.

Power ground. Ground connection for high-current power converter node. On PCB layout, connect directly to source of
through the PowerPad underneath the IC.

PWM low side driver positive supply output. Connect a 1 μF ceramic capacitor from REGN to PGND pin, close to the
REGN to BTST. REGN is disabled when CE is LOW.

PWM high side driver negative supply. Connect to the Phase switching node (junction of the low-side power MOSFET
BTST.

PWM high side driver positive supply. Connect a 0.1 μF bootstrap ceramic capacitor from BTST to SW. Connect a
bootstrap Schottky diode from REGN to BTST. A optional 2.0Ω - 5.1Ω bootstrap resistor can be inserted between the
BTST pin and the common point of the bootstrap capacitor and bootstrap diode, thus dampening the SW node voltage
ring and spike.

IC power positive supply. Connect to the adapter input through a schottky diode. Place a 0.1 uF ceramic capacitor from
PVCC to PGND pin close to the IC.

Exposed pad beneath the IC. AGND and PGND star-connected only at the PowerPad plane. Always solder PowerPad
pad to dissipate the heat.

DESCRIPTION

SLUS875B –MARCH 2009–REVISED OCTOBER 2009

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

PVCC, ACP, ACN, CSP, CSN, BAT –0.3 to 30
SW –1 to 30
REGN, LODRV, VADJ, ACSET, ISET, ACDET, FSET, IADAPT, LPMOD, –0.3 to 7

Voltage range

Maximum difference voltage ACP–ACN, CSP–CSN -0.5 to 0.5
Junction temperature range –40 to 155 °C
Storage temperature range –55 to 155 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging

Section of the data book for thermal limitations and considerations of packages.

LPREF, CE, CELLS, EXTPWR, DPMDET, TRICKLE
VDAC, VREF –0.3 to 3.6
BTST, HIDRV with respect to AGND and PGND –0.3 to 36
AGND, PGND –1 to 1

(1) (2)

VALUE UNIT

V

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Product Folder Link(s) :bq24741 bq24742

bq24741, bq24742

SLUS875B –MARCH 2009–REVISED OCTOBER 2009

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

SW –0.8 24 V
PVCC, ACP, ACN, CSP, CSN, BAT 0 24 V
REGN, LODRV 0 6.5 V
VREF 3.3 V

Voltage range

Maximum difference voltage: ACP–ACN, CSP–CSN –0.3 0.3 V
Junction temperature range –40 125 °C
Storage temperature range –55 150 °C

VDAC 3.6 V
VADJ, ACSET, ISET, ACDET, FSET, IADAPT, LPMOD, LPREF, CE, CELLS, 0 5.5 V

EXTPWR, DPMDET, TRICKLE
BTST, HIDRV with respect to AGND and PGND 0 30 V
AGND, PGND –0.3 0.3 V

ELECTRICAL CHARACTERISTICS

9.0 V ≤ V
otherwise noted)

OPERATING CONDITIONS

V

PVCC_OP

CHARGE VOLTAGE REGULATION

V

BAT_REG_RNG

V

VDAC_OP

V

VADJ_OP

CHARGE CURRENT REGULATION (ENABLE CE & DISABLE TRICKLE)

V

IREG_CHG

V

ISET_OP

TRICKLE CHARGE CURRENT REGULATION (ENABLE CE & TRICKLE)

(1) Verified by design
(2) Deglitch time and delay are proportional to the period of oscillator, unless specified.
(3) When CE=HIGH, the internal oscillator frequency is equal to external setting Fs; when CE=LOW, the internal oscillator frequency is fixed

internal setting 700 kHz.

≤ 24 V, 0°C < TJ< +125°C, Fs=600 kHz, typical values are at TA= 25°C, with respect to AGND (unless

PVCC

(1) (2) (3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PVCC input voltage operating range 9 24 V

BAT voltage regulation range 4-4.512 V per cell, times 2,3,4 cells 8 18.048 V
VDAC reference voltage range 2.6 3.6 V
VADJ voltage range 0 VDAC V

8 V, 8.4 V, 9.024 V –0.5 0.5

Charge voltage regulation accuracy 12 V, 12.6 V, 13.536 V –0.5 0.5 %

16 V, 16.8 V, 18.048 V –0.5 0.5

Charge current regulation differential V
voltage range

SRSET voltage range 0 VDAC V

V
V

Charge current regulation accuracy V

V
V

Off-set Voltage of Amplifier mV

Charge Current Regulation Accuracy V
Off-set Voltage of Amplifier –1.0 1.0 mV

V
V

= V

IREG_CHG

IREG_CHG
IREG_CHG
IREG_CHG
IREG_CHG
IREG_CHG

≥ 4 V –1.0 1.0

BAT

< 4 V –1.5 1.5

BAT

IREG_CHG

– V

CSP

CSN

= 40 mV –3% 3%
= 20 mV –5% 5%
= 5 mV –25% 25%
= 3 mV (V
= 3 mV (V

= 3 mV –33% 33%

≥ 4 V) –33% 33%

BAT

< 4 V) –50% 50%

BAT

0 100 mV

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ELECTRICAL CHARACTERISTICS (continued)

9.0 V ≤ V
otherwise noted)

INPUT CURRENT REGULATION

V

IREG_DPM

V

ACSET_OP

VREF REGULATOR

V

VREF_REG

I

VREF_LIM

REGN REGULATOR

V

REGN_REG

I

REGN_LIM

ADAPTER CURRENT SENSE AMPLIFIER

V

ACP/N_OP

V

IADAPT

I

IADAPT

A

IADAPT

I

IADAPT_LIM

C

IADAPT_MAX

ACDET COMPARATOR (INPUT UNDER_VOLTAGE, ACVGOOD)

V

ACDET_CHG

V

ACDET_CHG_HYS

T

ACDET_EXTPWR

AC CURRENT DETECT COMPARATOR (INPUT UNDER_CURRENT, ACIGOOD)

V

ACIDET

V

ACIDE_HYS

(4) Verified by design

≤ 24 V, 0°C < TJ< +125°C, Fs=600 kHz, typical values are at TA= 25°C, with respect to AGND (unless

PVCC

(1) (2) (3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Adapter current regulation differential V
voltage range

IREG_DPM

= V

ACSET voltage range 0 VDAC V

Input current regulation accuracy

V
V
V
V

= 40 mV –3% 3%

IREG_DPM

= 20 mV –5% 5%

IREG_DPM

= 5 mV –25% 25%

IREG_DPM

= 1.5 mV –33% 33%

IREG_DPM

Off-set Voltage of Amplifier -500 500 μV

VREF regulator voltage V
VREF short current limit V

REGN regulator voltage V
REGN short current limit V

> 0.6 V, 0-30 mA 3.267 3.3 3.333 V

ACDET

= 0 V, V

VREF

> 0.6 V, 0-75 mA, PVCC > 10 V 5.6 5.9 6.2 V

ACDET

= 0 V, V

REGN

Input common mode range Voltage on ACP/ACN 0 24
IADAPT output voltage range 0 2
IADAPT output current 0 1 mA
Current sense amplifier voltage gain A

Adapter current sense accuracy

Output short current limit V

= V

IADAPT

V
V
V
V

= 40 mV –2% 2%

IREG_DPM

= 20 mV –4% 4%

IREG_DPM

= 5 mV –25% 25%

IREG_DPM

= 1.5 mV –33% 33%

IREG_DPM

= 0 V 1 mA

IADAPT

Maximum output load capacitance For stability with 0 mA to 1 mA load 100 pF

ACDET adapter-detect rising threshold Min voltage to enable charging, V
ACDET falling hysteresis V
ACDET rising deglitch to turn on EXTPWR V

(4)

FET
ACDET rising deglitch to enable charge
ACDET falling deglitch to turn off EXTPWR V

(4)

FET
ACDET falling deglitch to disable charge
Power-up delay from V

EXTPWR FET turn-on

>2.4V to First time power up, Fs= 300 kHz – 800 kHz 2 ms

ACDET

(4)

(4)

(4)

Adapter current detect falling threshold V

falling, PVCC>8V 40 mV

ACDET

rising, PVCC>8V 1.2 ms

ACDET

V

rising, PVCC>8V, CE=HIGH 333 ms

ACDET

falling, PVCC>8V 80 μs

ACDET

V

falling, PVCC>8V 80 μs

ACDET

= 20 X IACx RAC, falling edge 200 250 300 mV

ACI

Adapter current detect hysteresis Rising edge 50 mV

Adapter current detect deglitch

IADAPT rising 10 μs
IADAPT falling 10 μs

bq24741, bq24742

SLUS875B –MARCH 2009–REVISED OCTOBER 2009

– V

ACP

ACN

> 0.6 V 35 80 mA

ACDET

> 0.6 V 90 145 mA

ACDET

/ V

IADAPT

IREG_DPM

rising 2.376 2.40 2.424 V

ACDET

0 100 mV

V

20 V/V

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ELECTRICAL CHARACTERISTICS (continued)

9.0 V ≤ V
otherwise noted)

PVCC / BAT COMPARATOR

V

PVCC_BAT_OP

V

PVCC-BAT_FALL

V

PVCC-BAT__HYS

BAT OVERVOLTAGE COMPARATOR

V

OV_RISE

V

OV_FALL

BATSHORT COMPARATOR

V

BATSHORT_RISE

V

BATSHORT_FALL

CHARGE OVERCURRENT COMPARATOR

V

OC_peak

MOSFET SHORT PROTECTION COMPARATOR

V

HS

V

HS

V

LS

CHARGE UNDERCURRENT PROTECTION COMPARATOR (UCP)

V

UCP

INPUT OVERVOLTAGE COMPARATOR (ACOV)

V

ACOV

V

ACOV_HYS

INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO)

V

UVLO

V

UVLO_HYS

INPUT LOW POWER MODE COMPARATOR (LPMOD)

V

ACLP_HYS

V

ACLP_OFFSET

THERMAL SHUTDOWN COMPARATOR

T

SHUT

T

SHUT_HYS

PWM HIGH SIDE DRIVER (HIDRV)

R

DS_HI_ON

R

DS_HI_OFF

V

BTST_REFRESH

I

BTST_LEAK

(5) Verified by design

≤ 24 V, 0°C < TJ< +125°C, Fs=600 kHz, typical values are at TA= 25°C, with respect to AGND (unless

PVCC

(1) (2) (3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Differential Voltage from PVCC to BAT -20 24 V
PVCC to BAT falling threshold V

PVCC

PVCC to BAT hysteresis 200 225 250 mV
PVCC to BAT rising deglitch V
PVCC to BAT falling deglitch V

Overvoltage rising threshold
Overvoltage falling threshold

(5)

(5)

PVCC
PVCC

As percentage of V
As percentage of V

Battery rising voltage for BATSHORT exit 2 V/Cell
Battery falling voltage for BATSHORT 1.7 V/Cell

entry

Peak charge over-current threshold V

(CSP- CSN)

V

(CSP- CSN)

High-side Threshold (bq24741) Measured on ACP-SW 120 250 455 mV
High-side Threshold (bq24742) Measured on ACP-SW 475 750 1065 mV
Low-side Threshold Measured on SW-AGND 90 160 320 mV

Charge under-current threshold, falling V
edge operation

Charge under-current threshold, rising V
edge operation

(CSP- CSN)

(CSP-CSN)

Charge under-current rising deglitch 10 μs
Charge under-current falling deglitch 320 μs

AC over-voltage rising threshold on Measure on ACDET pin 3.007 3.1 3.193 V
ACDET

AC over-voltage deglitch (rising edge) 650 μs
AC over-voltage deglitch (falling edge) 650 μs

AC under-voltage rising threshold Measured on PVCC pin 7 8 9 V
AC under-voltage hysteresis 260 mV

AC low power mode comparator internal 5% 7%
hysteresis

AC low power mode comparator offset 1 mV
voltage

Thermal shutdown rising temperature Temperature Increasing 155 °C
Thermal shutdown hysteresis, falling 20 °C

High side driver turn-on resistance V
High side driver turn-off resistance V
Bootstrap refresh comparator threshold V

voltage requested

BTST
BTST
BTST

BTST leakage current High side is on; charge enabled 200 μA

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– V

to disable charge 850 900 950 mV

BAT

– V
– V

> V

BAT

< V

BAT

, when V
, when V

PVCC-BAT_RISE
PVCC-BAT_FALL

BAT_REG
BAT_REG

/ VDAC < 0.8 90 110 130 mV

ISET

/ V

ISET

≥ 0.8 100 125 150 mV

DAC

4.5 ms
10 μs

104%
102%

from synchronous to non-synchronous 25 30 35 mV

from non-synchronous to synchronous 35 40 45 mV

– VSW= 5.5 V, tested at 100 mA 6 Ω
– VSW= 5.5 V, tested at 100 mA 1.4 Ω
– VSWwhen low side refresh pulse is

4 V

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ELECTRICAL CHARACTERISTICS (continued)

9.0 V ≤ V
otherwise noted)

PWM LOW SIDE DRIVER (LODRV)

R

DS_LO_ON

R

DS_LO_OFF

PWM DRIVERS TIMING

PWM OSCILLATOR

F

S

QUIESCENT CURRENT

I

OFF_STATE

I

BAT_ON

I

BATQ_CD

I

AC

INTERNAL SOFT START (8 steps to regulation current)

LOGIC INPUT PIN CHARACTERISTICS (CE, TRICKLE)

V

IN_LO

V

IN_HI

R

PULLDOWN

T

CE_ENCHARGE

LOGIC INPUT PIN CHARACTERISTICS (CELLS)

V

IN_LO

V

IN_FLOAT

V

IN_HI

I

BIAS_FLOAT

OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS ( EXTPWR, DPMDET, LPMOD)

V

OUT_LO

(6) Verified by design

≤ 24 V, 0°C < TJ< +125°C, Fs=600 kHz, typical values are at TA= 25°C, with respect to AGND (unless

PVCC

(1) (2) (3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Low side driver turn-on resistance REGN = 6 V, tested at 100 mA 6 Ω
Low side driver turn-off resistance REGN = 6 V, tested at 100 mA 1.2 Ω

Driver Dead Time between HIDRV and
LODRV

Programmable PWM switching frequency R
range

=130 kΩ - 45 kΩ 300 800 kHz

FSET

PWM switching frequency accuracy -20% 20%
RAMP amplitude 1.33 V
DC offset of RAMP 300 mV

Total off-state quiescent current into pins: V
CSP, CSN, BAT, BTST, SW, PVCC, ACP, V
ACN

Total off-state battery current from ACP, V
ACN V

Battery on-state quiescent current V

= 16.8 V, V

BAT

> 8 V, TJ= 0 to 125°C 7 11 μA

PVCC

= 16.8 V, V

BAT

> 8 V, TJ= 0 to 125°C

PVCC

= 16.8 , 0.6 V < V

BAT

V

> 8V

PVCC

ACDET

ACDET

Total quiescent current into CSP, CSN, Adapter present, V
BAT, PVCC, BTST, SW

Adapter quiescent current V

= 20 V, charge disabled 1 1.5 mA

PVCC

Soft start steps 8 step
Soft start time of each step (512 PWM 853 μs

cycles)

Input low threshold voltage 0.8
Input high threshold voltage 2.1
PIN pull down resistance inside IC V = 0 to V
Delay from CE=HIGH to charge enable

(6)

Fs=300 kHz - 800 kHz 2 ms

REGN

Input low threshold voltage, 3 cells CELLS voltage falling edge 0.5
Input float threshold voltage, 2 cells CELLS voltage rising for MIN,

CELLS voltage falling for MAX
Input high threshold voltage, 4 cells CELLS voltage rising 2.5
Input bias float current for 2 cell selection VCE = 0 to VREGN –1 1 μA

Output low saturation voltage Sink Current = 5 mA 0.5 V
Leakage current Pull up to 3.3 v 1 μA
DPMDET delay, both edge 5 ms

< 0.6 V,

< 0.6 V,

< 2.4 V,

ACDET

> 2.4 V, charge disabled

ACDET

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SLUS875B –MARCH 2009–REVISED OCTOBER 2009

25 ns

1 μA

1 mA

100 200 μA

V

1 MΩ

0.8 1.8 V

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TYPICAL CHARACTERISTICS

Table 2. Table of Graphs

Y X Figure

VREF Load and Line Regulation vs Load Current Figure 3
REGN Load and Line Regulation vs Load Current Figure 4
BAT Voltage vs VADJ/VDAC Ratio Figure 5
BAT Voltage Regulation Accuracy vs Setpoint Figure 6
Charge Current vs ISET/VDAC Ratio Figure 7
Charge Current Regulation Accuracy vs V(CSP-CSN) Setpoint Figure 8
Input Current vs ACSET/VDAC Radio Figure 9
DPM Accuracy vs V(ACP-ACN) Setpoint Figure 10
BAT Voltage Regulation Accuracy vs Charge Current Figure 11
V_IADAPT Accuracy vs V(ACP-ACN) Voltage Figure 12
Trickle Charge Current vs BAT Voltage Figure 13
DPM and Charge Current vs System Current Figure 14
REF, REGN, and EXTPWR Startup (CE=HIGH) Figure 15
Transient System Load (DPM) Response Transition Figure 16
Transient Response of IADAPT and LPMOD Figure 17
Battery Overcurrent Protection (OCP) Figure 18
Battery to Ground Short Transition Figure 19
Battery to Ground Short Protection Figure 20
Charge Enable and Current Soft-Start Figure 21
Charge Disable Figure 22
Trickle Disable and Current Soft-Start Figure 23
Synchronous to Non-synchronous Transition Figure 24
Non-synchronous to Synchronous Transition Figure 25
Continuous Conduction Mode Switching Waveforms Figure 26
Near 100% Duty Cycle Bootstrap Recharge Pulse Figure 27
Efficiency vs Battery Charge Current Figure 28
Switch Frequency vs Setting Resistor Figure 29

(1) Test results based on Figure 2 application schematic. VIN= 20 V, V

unless otherwise specified.

(1)

Fs=400 kHz, Ta = 25 °C

= 3-cell Li-Ion, I

BAT

CHG

= 3 A, I

ADAPTER_LIMIT

= 4 A, TA= 25°C,

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-0.20

-0.10

0

0.10

0.20

0.30

0.40

0.50

0 10 20 30 40 50

VREF-LoadCurrent-mA

RegulationError-%

PVCC=10V

PVCC=20V

-3

-2.50

-2

-1.50

-1

-0.50

0

0 10 20 30 40 50 60 70 80

REGN-LoadCurrent-mA

RegulationError-%

PVCC=10V

PVCC=20V

VoltageRegulation-V

0 0.1 0.2

0.3

0.4 0.5 0.6 0.7 0.8 0.9

1

VADJ/VDACRatio

12

12.2

12.6

12.4

12.8

13

13.2

13.4

13.6

3-Cell

RegulationError(%)

VBAT_regSetpoint(V)

12 12.2 12.4

12.6 12.8

13 13.2 13.4 13.6

-0.02

-0.01

0

0.01

0.02

0.03

0.04

0.05

0.06

0

0.5

1

1.5

2

3

3.5

4

4.5

5

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

ACSET/VDACRatio

InputCurrentRegulation- A

2.5

3-Cell

RegulationError-%

ICHG_regSetpoint(mV)

0 10 20

30

40 50 60 70 80 90 100

0

5

10

15

20

25

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SLUS875B –MARCH 2009–REVISED OCTOBER 2009

VREF LOAD AND LINE REGULATION REGN LOAD AND LINE REGULATION

vs vs

Load Current LOAD CURRENT

Figure 3. Figure 4.

BAT VOLTAGE BAT VOLTAGE REGULATION ACCURACY

vs vs

VADJ/VDAC RATIO SETPOINT

Figure 5. Figure 6.

CHARGE CURRENT CHARGE CURRENT REGULATION ACCURACY

vs vs

ISET/VDAC V(CSP-CSN) SETPOINT

Figure 7. Figure 8.

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