Texas Instruments bq24740 Schematics

LPREF

bq24740

28LDQFN

TOP VIEW

DPMDET

SRN

BAT

CELLS

SRP

SRSET

IADAPT

LPMD

ACSET

CHGEN

ACN

ACP

ACDET

PVCC

BTST

HIDRV

REGNPHLODRV

PGND

IADSLP

AGND

VREF

V

ADJ

VDAC

EXTPWR

ISYNSET

1

2

3

4

5

6

7

8 9 10 11 12 13 14

15

16

17

18

19

20

21

22232425262728

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............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009

Host-Controlled Multi-Chemistry Battery Charger With Low Input Power Detect

1

FEATURES APPLICATIONS

2

• NMOS-NMOS Synchronous Buck Converter

with 300 kHz Frequency and >95% Efficiency

• 30-ns Minimum Driver Dead-time and 99.5%

Maximum Effective Duty Cycle

• High-Accuracy Voltage and Current Regulation

– ± 0.5% Charge Voltage Accuracy
– ± 3% Charge Current Accuracy
– ± 3% Adapter Current Accuracy
– ± 2% Input Current Sense Amp Accuracy

• Integration

– Internal Loop Compensation
– Internal Soft Start

• Safety

– Input Overvoltage Protection (OVP)
– Dynamic Power Management (DPM) with

Status Indicator

• Supports Two, Three, or Four Li+ Cells

• 5 – 24 V AC/DC-Adapter Operating Range

• Analog Inputs with Ratiometric Programming

via Resistors or DAC/GPIO Host Control
– Charge Voltage (4-4.512 V/Cell)
– Charge Current (up to 10 A, with 10-m Ω

Sense Resistor)

– Adapter Current Limit (DPM)

• Status and Monitoring Outputs

– AC/DC Adapter Present with Programmable

Voltage Threshold

– Low Input-Power Detect with Adjustable

Threshold and Hysteresis
– DPM Loop Active
– Current Drawn from Input Source

• Battery Discharge Current Sense with No

Adapter, or Selectable Low-Iq mode

• Supports Any Battery Chemistry: Li+, NiCd,

NiMH, Lead Acid, etc.

• Charge Enable

• 10- µ A Off-State Current

• 28-pin, 5x5-mm QFN package

1

2 PowerPad is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

bq24740

• Notebook and Ultra-Mobile Computers

• Portable Data-Capture Terminals

• Portable Printers

• Medical Diagnostics Equipment

• Battery Bay Chargers

• Battery Back-up Systems

DESCRIPTION

The bq24740 is a high-efficiency, synchronous
battery charger with integrated compensation,
offering low component count for space-constrained
multi-chemistry battery charging applications.
Ratiometric charge current and voltage programming
allows high regulation accuracies, and can be either
hardwired with resistors or programmed by the
system power-management microcontroller using a
DAC or GPIOs.

The bq24740 charges two, three, or four series Li+
cells, supporting up to 10 A of charge current, and is
available in a 28-pin, 5x5-mm thin QFN package.

Copyright © 2006 – 2009, Texas Instruments Incorporated

VREF

RAC

0.010 Ω

.( 1) Pull -uprailcouldbeeitherVREForothersystemrail

( 2) SRSET /ACSET couldcomefromeitherDACorresistordividers .

Q1 (ACFET )

SI4435

Q3(BATFET )

SI4435

Controlledby

HOST

N

PP

ACN

ACP

ACDET

EXTPWR

SRSET

ACSET

VREF

DAC

CELLS

CHGEN

VDAC

VADJ

DAC

ADC

IADAPT

HOST

PVCC

HIDRV

N

PH

BTST

REGN

LODRV

PGND

SRP

SRN

P

PACK+

PACK-

SYSTEM

ADAPTER+

ADAPTER-

EXTPWR

AGND

bq24740

432 k Ω
1%

66.5 k Ω
1%

R1

R2

R3

C4

C2

C3

C5

C8

Q4
FDS6680 A

Q5
FDS6680 A

C9

L1

D1 BAT 54

C10

BAT

IADSLP

ISYNSET

R6
24 k Ω

DPMDET

R4

LPMD

VREF

LPREF

R7
200 k Ω

R8

24.9 k Ω

R9

1.8 MΩ

Q2 (ACFET )

SI4435

Controlledby

HOST

C6

C15

0.1 µF

R5

C1

2 Ω

R10

2.2 µF

0.1 µF

0.1 µF

1 µF

10k Ω 10 k Ω

10k Ω

100 pF

C14

0.1 µF

C13

0.1 µF

0.1 µF

1 µF

C11
10 µF

8.2 µH

RSR

0.010 Ω

0.1 µF

10 µ F

C7

10 µF

C12
10 µF

PowerPad

D2

BAT54

bq24740

SLUS736C – DECEMBER 2006 – REVISED MARCH 2009 ...............................................................................................................................................

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)

The bq24740 features Dynamic Power Management (DPM) and input power limiting. These features reduce
battery charge current when the input power limit is reached to avoid overloading the ac adapter when supplying
the load and the battery charger simultaneously. A current-sense amplifier enables precise measurement of input
current from the ac adapter to monitor the overall system power. If the adapter current is above the programmed
low-power threshold, a signal is sent to host so that the system optimizes its power performance according to
what is available from the adapter.

TYPICAL APPLICATION

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2 Submit Documentation Feedback Copyright © 2006 – 2009, Texas Instruments Incorporated

VIN= 20 V, V

Figure 1. Typical System Schematic, Voltage and Current Programmed by DAC

BAT

= 3-cell Li-Ion, I

CHARGE

ADAPTER_LIMIT

= 3 A, I

Product Folder Link(s) :bq24740

= 4 A

VREF

100 kΩ

R 11

66.5 kΩ

R 12

100 kΩ

R13

43 k Ω

R14

VREF

R AC

0 .010 Ω

( 1 ) Pull -uprailcouldbeeitherVREForothersystemrail.
( 2 ) SRSET / ACSET couldcomefromeitherDACorresistordividers.

Q 1 ( ACFET )

SI 4435

Q 3( BATFET)

SI 4435

Controlledby

HOST

N

PP

ACN

ACP

ACDET

EXTPWR

SRSET

ACSET

VREF

GPIO

CELLS

CHGEN

VDAC

VADJ

ADC

IADAPT

HOST

PVCC

HIDRV

N

PH

BTST

REGN

LODRV

PGND

SRP

SRN

P

PACK+

PACK-

SYSTEMADAPTER+

ADAPTER-

EXTPWR

AGND

432 k Ω
1 %

66 .5 k Ω
1 %

R1

R2

R 3

C 4

C 2

C 3

C 5

C 8

Q 4

FDS 6680 A

Q 5

FDS 6680 A

C 9

L 1

D 1 BAT 54

C10

BAT

IADSLP

ISYNSET

R 6
24 k Ω

DPMDET

R4

LPMD

VREF

LPREF

R 7

200 k Ω

R 8

24.9 k Ω

R 9

1 .8 M Ω

Q 2 (ACFET)

SI4435

Controlledby

HOST

C 6

C 15

0.1 µF

R 5

C 1

2 Ω

R10

2. 2 µF

0. 1 µF

0. 1 µF

1 µF

10 k Ω 10

kΩ

10

k Ω

100 pF

C 14

0 .1 µF

C 13

0 .1 µF

0. 1 µF

1 µ F

C 11

10 µF

8. 2 µH

R

SR

0 .010 Ω

0. 1µ F

10 µ F

C7

10 µ F

C 12
10 µF

PowerPad

VREF

REGN

D2

BAT54

bq24740

bq24740

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............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009

A. VIN= 20 V, V

Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 3

BAT

= 3-cell Li-Ion, I

CHARGE

Figure 2. Typical System Schematic, Voltage and Current Programmed by Resistor

= 3 A, I

ADAPTER_LIMIT

Product Folder Link(s) :bq24740

= 4 A

VREF

RAC

0.010 Ω

( 1) Pull- uprailcouldbeeitherVREForothersystemrail .

( 2) SRSET /ACSET couldcomefromeitherDACorresistordividers .

Q1 (ACFET )

SI4435

Q3 (BATFET)

SI4435

Controlledby

HOST

N

PP

ACN

ACP

ACDET

EXTPWR

SRSET

ACSET

VREF

DAC

CELLS

CHGEN

VDAC

VADJ

DAC

ADC

IADAPT

HOST

PVCC

HIDRV

N

PH

BTST

REGN

LODRV

PGND

SRP

SRN

P

PACK+

PACK-

SYSTEMADAPTER+

ADAPTER-

/EXTPWR

AGND

bq 24740

432 k Ω
1%

66.5 kΩ
1%

R1

R2

R3

C4

C2

C3

C5

C8

Q4
FDS 6680 A

Q 5
FDS6680A

C9

L1

D1 BAT 54

C10

BAT

IADSLP

ISYNSET

R6
24 kΩ

DPMDET

R4

LPMD

VREF

LPREF

R7
200 k Ω

R8

24.9 kΩ

R9

1.8 MΩ

Q 2 (ACFET )

SI 4435

Controlledby

HOST

C6

C15

0. 1 µF

R5

C1

2 Ω

R10

2.2 µF

0.1 µF

0.1 µF

1 µF

10

k Ω10kΩ

10

kΩ

100 pF

C14

0. 1 µF

C13

0. 1 µF

0.1 µF

1 µ F

C11

10 µF

8.2 µH

R

SR

0.010 Ω

0.1 µF

10 µF

C7
10 µF

C12
10 µF

PowerPad

D2

BAT54C

bq24740

SLUS736C – DECEMBER 2006 – REVISED MARCH 2009 ...............................................................................................................................................

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PACKAGE THERMAL DATA

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Part number Package Quantity

PACKAGE θ

QFN – RHD

Web site at www.ti.com .

(2) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is

connected to the ground plane by a 2x3 via matrix.

4 Submit Documentation Feedback Copyright © 2006 – 2009, Texas Instruments Incorporated

VIN= 20 V, V

bq24740 28-PIN 5 x 5 mm QFN

(1) (2)

= 3-cell Li-Ion, I

BAT

Figure 3. Typical System Schematic: Sensing Battery Discharge Current,

When Adapter Removed. (Set IADSLP at logic high)

CHARGE

JA

39 ° C/W 2.36 W 0.028 W/ ° C

= 3 A, I

ORDERING INFORMATION

Product Folder Link(s) :bq24740

ADAPTER_LIMIT

TA= 70 ° C POWER RATING DERATING FACTOR ABOVE TA= 25 ° C

= 4 A

Ordering Number

(Tape and Reel)

bq24740RHDR 3000

bq24740RHDT 250

bq24740

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NAME NO.

CHGEN 1 Charge enable active-low logic input. LO enables charge. HI disables charge.
ACN 2

ACP 3

LPMD 4

ACDET 5 The I

ACSET 6

LPREF 7

IADSLP 8

AGND 9

VREF 10 could be used for ratiometric programming of voltage and current regulation. VREF is the source for the internal

VDAC 11 SRSET, and ACSET pin voltages, respectively. Place resistor dividers from VDAC to VADJ, SRSET, and ACSET

VADJ 12

EXTPWR 13 threshold, OR input current is greater than 1.25 A with 10-m Ω sense resistor. Connect a 10-k Ω pullup resistor from

ISYNSET 14 threshold to force non-synchronous converter operation at low output current, and to prevent negative inductor

IADAPT 15

SRSET 16 regulation set-point. Program by connecting a resistor divider from VDAC to SRSET to AGND; or by connecting the

BAT 17 BAT pin to accurately sense the battery pack voltage. Place a 0.1- µ F capacitor from BAT to AGND close to the IC to

SRN 18 differential-mode filtering. An optional 0.1- µ F ceramic capacitor is placed from SRN pin to AGND for common-mode

SRP 19

............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009

Table 1. TERMINAL FUNCTIONS – 28-PIN QFN

TERMINAL

DESCRIPTION

Adapter current sense resistor, negative input. A 0.1- µ F ceramic capacitor is placed from ACN pin to AGND for
common-mode filtering. A 0.1- µ F ceramic capacitor is placed from ACN to ACP to provide differential-mode filtering.

Adapter current sense resistor, positive input. A 0.1- µ F ceramic capacitor is placed from ACN to ACP to provide
differential-mode filtering. A 0.1- µ F ceramic capacitor is placed from ACP pin to AGND for common-mode filtering.

Low power mode detect active-high open-drain logic output. Place a 10-k Ω pullup resistor from LPMD pin to the
pullup-voltage rail. Place a positive-feedback resistor from LPMD pin to LPREF pin for programming hysteresis (see
the design example for calculation). The output is HI when I
output is LO when IADAPT pin voltage is higher than LPREF pin voltage.

Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from
adapter input to ACDET pin to AGND pin. Adapter voltage is detected if ACDET-pin voltage is greater than 2.4 V.

overvoltage protection; it disables charge when ACDET > 3.1 V. ACOV does not latch, and normal operation
resumes when ACDET < 3.1 V.

Adapter current set input. The voltage ratio of ACSET voltage versus VDAC voltage programs the input current
regulation set-point during Dynamic Power Management (DPM). Program by connecting a resistor divider from VDAC
to ACSET to AGND; or by connecting the output of an external DAC to the ACSET pin and connect the DAC supply
to the VDAC pin.

Low power voltage set input. Connect a resistor divider from VREF to LPREF and AGND to program the reference
for the LOPWR comparator. The LPREF-pin voltage is compared to the IADAPT-pin voltage and the logic output is
given on the LPMD open-drain pin. Connecting a positive-feedback resistor from LPREF pin to LPMD pin programs
the hysteresis.

Enable IADAPT to enter sleep mode; active-low logic input. Allows low Iqsleep mode when adapter not detected.
Logic low turns off the Input Current Sense Amplifier (IADAPT) when adapter is not detected and ACDET pin is < 0.6
V - allows lower battery discharge current. Logic high keeps IADAPT current-sense amplifier on when adapter is not
detected and ACDET pin is < 0.6 V - this allows measuring battery discharge current.

Analog ground. Ground connection for low-current sensitive analog and digital signals. On PCB layout, connect to the
analog ground plane, and only connect to PGND through the PowerPad underneath the IC.

3.3-V regulated voltage output. Place a 1- µ F ceramic capacitor from VREF to AGND pin close to the IC. This voltage
circuit.

Charge voltage set reference input. Connect the VREF or external DAC voltage source to the VDAC pin. Battery
voltage, charge current, and input current are programmed as a ratio of the VDAC pin voltage versus the VADJ,

pins to AGND for programming. A DAC could be used by connecting the DAC supply to VDAC and connecting the
output to VADJ, SRSET, or ACSET.

Charge voltage set input. The voltage ratio of VADJ voltage versus VDAC voltage programs the battery voltage
regulation set-point. Program by connecting a resistor divider from VDAC to VADJ, to AGND; or, by connecting the
output of an external DAC to VADJ, and connect the DAC supply to VDAC. VADJ connected to REGN programs the
default of 4.2 V per cell.

Valid adapter active-low detect logic open-drain output. Pulled low when input voltage is above ACDET programmed
EXTPWR pin to pullup supply rail.

Synchronous mode current set input. Place a resistor from ISYNSET to AGND to program the charge undercurrent
current. Threshold should be set at greater than half of the maximum inductor ripple current (50% duty cycle).

Adapter current sense amplifier output. IADAPT voltage is 20 times the differential voltage across ACP-ACN. Place a
100-pF or less ceramic decoupling capacitor from IADAPT to AGND.

Charge current set input. The voltage ratio of SRSET voltage versus VDAC voltage programs the charge current
output of an external DAC to SRSET pin and connect the DAC supply to VDAC pin.

Battery voltage remote sense. Directly connect a kelvin sense trace from the battery pack positive terminal to the
filter high-frequency noise.

Charge current sense resistor, negative input. A 0.1- µ F ceramic capacitor is placed from SRN to SRP to provide
filtering.

Charge current sense resistor, positive input. A 0.1- µ F ceramic capacitor is placed from SRN to SRP to provide
differential-mode filtering. A 0.1- µ F ceramic capacitor is placed from SRP pin to AGND for common-mode filtering.

current sense amplifier is active when the ACDET pin voltage is greater than 0.6 V. ACOV is input

ADAPT

pin voltage is lower than LPREF pin voltage. The

ADAPT

Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Link(s) :bq24740

bq24740

SLUS736C – DECEMBER 2006 – REVISED MARCH 2009 ...............................................................................................................................................

Table 1. TERMINAL FUNCTIONS – 28-PIN QFN (continued)

TERMINAL

NAME NO.

CELLS 20 2, 3 or 4 cells selection logic input. Logic low programs 3 cell. Logic high programs 4 cell. Floating programs 2 cell.

DPMDET 21 current is being limited by reducing the charge current. Connect 10-k Ω pullup resistor from DPMDET to VREF or a

PGND 22 of low-side power MOSFET, to ground connection of in put and output capacitors of the charger. Only connect to

LODRV 23 PWM low side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
REGN 24

PH 25 MOSFET drain, high-side power MOSFET source, and output inductor). Connect the 0.1- µ F bootstrap capacitor from

HIDRV 26 PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
BTST 27
PVCC 28 IC power positive supply. Place a 0.1- µ F ceramic capacitor from PVCC to PGND pin close to the IC.

PowerPad™ PowerPad to the board, and have vias on the PowerPad plane connecting to AGND and PGND planes. It also serves

DESCRIPTION

Dynamic power management (DPM) input current loop active, open-drain output status. Logic low indicates input
different pullup-supply rail.

Power ground. Ground connection for high-current power converter node. On PCB layout, connect directly to source
AGND through the PowerPad underneath the IC.

PWM low side driver positive 6-V supply output. Connect a 1- µ F ceramic capacitor from REGN to PGND, close to the
IC. Use for high-side driver bootstrap voltage by connecting a small-signal Schottky diode from REGN to BTST.

PWM high side driver negative supply. Connect to the phase switching node (junction of the low-side power
from PH to BTST.

PWM high side driver positive supply. Connect a 0.1- µ F bootstrap ceramic capacitor from BTST to PH. Connect a
small bootstrap Schottky diode from REGN to BTST.

Exposed pad beneath the IC. AGND and PGND star-connected only at the PowerPad plane. Always solder
as a thermal pad to dissipate the heat.

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

PVCC, ACP, ACN, SRP, SRN, BAT – 0.3 to 30
PH – 1 to 30
REGN, LODRV, VADJ, ACSET, SRSET, ACDET, ISYNSET, LPMD, LPREF,

Voltage range

Maximum difference voltage ACP – ACN, SRP – SRN, AGND – PGND – 0.5 to 0.5
Junction temperature range – 40 to 155
Storage temperature range – 55 to 155

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging

Section of the data book for thermal limitations and considerations of packages.

CHGEN, CELLS, EXTPWR, DPMDET
VDAC – 0.3 to 5.5
VREF – 0.3 to 3.6
BTST, HIDRV with respect to AGND and PGND, IADAPT – 0.3 to 36

(1) (2)

VALUE UNIT

– 0.3 to 7

V

° C

6 Submit Documentation Feedback Copyright © 2006 – 2009, Texas Instruments Incorporated

Product Folder Link(s) :bq24740

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............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

PH – 1 24
PVCC, ACP, ACN, SRP, SRN, BAT 0 24
REGN, LODRV 0 6.5
VREF 0 3.3

Voltage range

Maximum difference voltage: ACP – ACN, SRP – SRN – 0.3 0.3
Junction temperature range – 40 125
Storage temperature range – 55 150

VDAC, IADAPT 0 3.6
ACSET, SRSET, ACDET, ISYNSET, LPMD, LPREF, CHGEN, CELLS, EXTPWR, 0 5.5

DPMDET
VADJ 0 6.5
BTST, HIDRV with respect to AGND and PGND 0 30
AGND, PGND – 0.3 0.3

ELECTRICAL CHARACTERISTICS

7 V ≤ V

OPERATING CONDITIONS

V

PVCC_OP

CHARGE VOLTAGE REGULATION

V

BAT_REG_RNG

V

VDAC_OP

V

ADJ_OP

CHARGE CURRENT REGULATION

V

IREG_CHG

V

SRSET_OP

≤ 24 V, 0 ° C < TJ< 125 ° C, typical values are at TA= 25 ° C, with respect to AGND (unless otherwise noted)

PVCC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PVCC Input voltage operating range 5 24 V

BAT voltage regulation range 4V-4.512V per cell, times 2,3,4 cell 8 18 V
VDAC reference voltage range 2.6 3.6 V
VADJ voltage range 0 REGN V

8 V, 8.4 V, 9.024 V – 0.5% 0.5%

Charge voltage regulation accuracy 12 V, 12.6 V, 13.536 V – 0.5% 0.5%

16 V, 16.8 V, 18.048 V – 0.5% 0.5%

Charge voltage regulation set to default to

4.2 V per cell

Charge current regulation differential
voltage range

VADJ connected to REGN, 8.4 V,

12.6 V, 16.8 V

V

IREG_CHG

= V

– V

SRP

SRN

SRSET voltage range 0 VDAC V

V

IREG_CHG

V

Charge current regulation accuracy %

IREG_CHG

V

IREG_CHG

V

IREG_CHG

= 40 – 100 mV – 3 3
= 20 mV – 5 5
= 5 mV – 25 25
= 1.5 mV (V

≥ 4 V) – 33 33

BAT

– 0.5% 0.5%

0 100 mV

bq24740

V

° C

Copyright © 2006 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Link(s) :bq24740

bq24740

SLUS736C – DECEMBER 2006 – REVISED MARCH 2009 ...............................................................................................................................................

ELECTRICAL CHARACTERISTICS (continued)

7 V ≤ V

INPUT CURRENT REGULATION

V

IREG_DPM

V

ACSET_OP

VREF REGULATOR

V

VREF_REG

I

VREF_LIM

REGN REGULATOR

V

REGN_REG

I

REGN_LIM

ADAPTER CURRENT SENSE AMPLIFIER

V

ACP/N_OP

V

IADAPT

I

IADAPT

A

IADAPT

I

IADAPT_LIM

C

IADAPT_MAX

ACDET COMPARATOR

V

PVCC-BAT_OP

V

ACDET_CHG

V

ACDET_CHG_HYS

V

ACDET_BIAS

V

ACDET_BIAS_HYS

INPUT OVERVOLTAGE COMPARATOR (ACOV)

V

ACOV

V

ACOV_HYS

(1) Specified by design.

≤ 24 V, 0 ° C < TJ< 125 ° C, typical values are at TA= 25 ° C, with respect to AGND (unless otherwise noted)

PVCC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Adapter current regulation differential
voltage range

ACSET voltage range 0 VDAC V

Input current regulation accuracy

VREF regulator voltage V
VREF current limit V

REGN regulator voltage 5.6 5.9 6.2 V
REGN current limit V

Input common mode range Voltage on ACP/SRN 0 24 V
IADAPT output voltage range 0 2 V
IADAPT output current 0 1 mA
Current sense amplifier voltage gain A

Adapter current sense accuracy

Output current limit V
Maximum output load capacitance For stability with 0 mA to 1 mA load 100 pF

Differential Voltage from PVCC to BAT – 20 24 V
ACDET adapter-detect rising threshold 2.376 2.40 2.424 V
ACDET falling hysteresis V

ACDET rising deglitch
ACDET falling deglitch VACDET falling 7 9 11 ms

ACDET enable-bias rising threshold 0.56 0.62 0.68 V
Adapter present falling hysteresis V

ACDET rising deglitch
ACDET falling deglitch V

AC Over-voltage rising threshold on
ACDET (See ACDET in Terminal 3.007 3.1 3.193 V

Functions )

AC Overvoltage rising deglitch 1.3
AC Overvoltage falling deglitch 1.3

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V

IREG_DPM

V

IREG_DPM

V

IREG_DPM

V

IREG_DPM

V

IREG_DPM

ACDET
VREF

V

ACDET

V

REGN

IADAPT

V

IREG_DPM

V

IREG_DPM

V

IREG_DPM

V

IREG_DPM
IADAPT

= V

– V

ACP

ACN

0 100 mV

= 40 – 100 mV – 3% 3%
= 20 mV – 5% 5%
= 5 mV – 25% 25%
= 1.5 mV – 33% 33%

> 0.6 V, 0-30 mA 3.267 3.3 3.333 V

= 0 V, V

> 0.6 V 35 75 mA

ACDET

> 0.6 V, 0-75 mA, PVCC > 10

= 0 V, V

= V

IADAPT

> 0.6 V 90 135 mA

ACDET

/ V

IREG_DPM

20 V/V
= 40 – 100 mV – 2% 2%
= 20 mV – 3% 3%
= 5 mV – 25% 25%
= 1.5 mV – 30% 30%

= 0 V 1 mA

Min voltage to enable charging,
V

rising

ACDET

falling 40 mV

(1)

(1)

ACDET

VACDET rising 518 700 908 ms

Min voltage to enable all bias, V
rising

falling 20 mV

ACDET

V

rising 10

ACDET

falling 10

ACDET

ACDET

µ s

ms

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ELECTRICAL CHARACTERISTICS (continued)

7 V ≤ V

AC CURRENT DETECT COMPARATOR (INPUT UNDERCURRENT)

V

ACIDET

V

ACIDET_HYS

PVCC / BAT COMPARATOR

V

PVCC-BAT_FALL

V

PVCC-BAT__HYS

INPUT UNDERVOLTAGE LOCK-OUT COMPARATOR (UVLO)

UVLO AC Undervoltage rising threshold Measure on PVCC 3.5 4 4.5 V
UVLO_HYS AC Undervoltage hysteresis, falling 260 mV

BAT OVERVOLTAGE COMPARATOR

V

OV_RISE

V

OV_FALL

CHARGE OVERCURRENT COMPARATOR

V

OC

INPUT CURRENT LOW-POWER MODE COMPARATOR

V

ACLP_HYS

V

ACLP_OFFSET

THERMAL SHUTDOWN COMPARATOR

T

SHUT

T

SHUT_HYS

PWM HIGH SIDE DRIVER (HIDRV)

R

DS(on)_HI

R

DS(off)_HI

V

BTST_REFRESH

PWM LOW SIDE DRIVER (LODRV)

R

DS(on)_HI

R

DS(off)_LO

PWM DRIVERS TIMING

PWM OSCILLATOR

F

SW

V

RAMP_HEIGHT

(2) Specified by design.

............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009

≤ 24 V, 0 ° C < TJ< 125 ° C, typical values are at TA= 25 ° C, with respect to AGND (unless otherwise noted)

PVCC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Adapter current detect rising threshold V

ACI

= IAC× R

× 20, falling edge 200 250 300 mV

AC

Adapter current detect hysteresis Rising edge 50 mV

PVCC to BAT falling threshold V

– V

PVCC

to disable charger 140 185 240 mV

BAT

PVCC to BAT hysteresis 50 mV
PVCC to BAT Rising Deglitch V
PVCC to BAT Falling Deglitch V

Overvoltage rising threshold
Overvoltage falling threshold

(2)

(2)

Charge overcurrent falling threshold As percentage of I

– V

PVCC
PVCC

> V

BAT

– V

< V

BAT

As percentage of V

PVCC-BAT_RISE
PVCC-BAT_FALL

7 9 11 ms

10 µ s

104%

BAT_REG

REG_CHG

102%

145%

Minimum Current Limit (SRP-SRN) 50 mV

AC low power hysteresis 2.8
AC low power rising threshold 1

Thermal shutdown rising temperature Temperature Increasing 155
Thermal shutdown hysteresis, falling 20

High side driver turn-on resistance V
High side driver turn-off resistance V
Bootstrap refresh comparator threshold V

voltage pulse is requested

– V

BTST
BTST
BTST

= 5.5 V, tested at 100 mA 3 6

PH

– V

= 5.5 V, tested at 100 mA 0.7 1.4

PH

– V

when low side refresh

PH

4 V

Low side driver turn-on resistance REGN = 6 V, tested at 100 mA 3 6
Low side driver turn-off resistance REGN = 6 V, tested at 100 mA 0.6 1.2

Driver Dead Time — Dead time when
switching between LODRV and HIDRV. No 30 ns
load at LODRV and HIDRV

PWM switching frequency 240 360 kHz
PWM ramp height As percentage of PVCC 6.6 %PVCC

mV

° C

Ω

Ω

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SLUS736C – DECEMBER 2006 – REVISED MARCH 2009 ...............................................................................................................................................

ELECTRICAL CHARACTERISTICS (continued)

7 V ≤ V

QUIESCENT CURRENT

I

OFF_STATE

I

BATQ_CD

I

AC

INTERNAL SOFT START (8 steps to regulation current)

CHARGER SECTION POWER-UP SEQUENCING

ISYNSET AMPLIFIER AND COMPARATOR (SYNCHRONOUS TO NON-SYNCHRONOUS TRANSITION)

V

ISYNSET

LOGIC IO PIN CHARACTERISTICS ( CHGEN, IADSLP )

V

IN_LO

V

IN_HI

I

BIAS

LOGIC INPUT PIN CHARACTERISTICS (CELLS)

V

IN_LO

V

IN_MID

V

IN_HI

I

BIAS_FLOAT

OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS ( EXTPWR)

V

OUT_LO

OPEN-DRAIN LOGIC OUTPUT PIN CHARACTERISTICS ( DPMDET, LPMD)
V

OUT_LO

≤ 24 V, 0 ° C < TJ< 125 ° C, typical values are at TA= 25 ° C, with respect to AGND (unless otherwise noted)

PVCC

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

= 16.8 V, V

Total off-state quiescent current into pins
SRP, SRN, BAT, BTST, PH, PVCC, ACP,
ACN

V
V

V

BAT
PVCC

BAT
PVCC

= 16.8 V, V

> 5 V, TJ= 85 ° C

> 5 V, TJ= 125 ° C

Total quiescent current into pins SRP, Adapter present, VACDET > 2.4V,
SRN, BAT, BTST, PH charge disabled

Adapter quiescent current V

= 20 V, charge disabled 2.8 4 mA

PVCC

Soft start steps 8 step
Soft start step time 1.7 ms

Delay from when adapter is detected

Charge-enable delay after power-up to when the charger is allowed to turn 518 700 908 ms

on

I

Accuracy V

SYN

(SRP-SRN)

= 5 mV – 20% 20%

ISYNSET pin voltage 1 V
ISYNSET rising deglitch 20 µ s
ISYNSET falling deglitch 640 µ s

Input low threshold voltage 0.8 V
Input high threshold voltage 2.1
Input bias current V

= 0 to V

CHGEN

Input low threshold voltage, 3 cells CELLS voltage falling edge 0.5
Input mid threshold voltage, 2 cells 0.8 1.8 V

CELLS voltage rising for MIN,

CELLS voltage falling for MAX
Input high threshold voltage, 4 cells CELLS voltage rising 2.5
Input bias float current for 2-cell selection V = 0 to V – 1 1 µ A

Output low saturation voltage Sink Current = 4 mA 0.5 V
Delay, EXTPWR falling 518 700 908 ms
Delay, EXTPWR rising 7 9 11 ms

Output low saturation voltage Sink Current = 5 mA 0.5 V
Delay, rising/falling 10 ms

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< 0.6 V,

ACDET

< 0.6 V,

ACDET

7 10

7 11 µ A

100 200

REGN

1 µ A

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-0.20

-0.10

0

0.10

0.20

0.30

0.40

0.50

0 10 20 30 40 50

VREF-LoadCurrent-mA

RegulationError-%

PVCC=10V

PVCC=20V

-3

-2.50

-2

-1.50

-1

-0.50

0

0 10 20 30 40 50 60 70 80

REGN-LoadCurrent-mA

RegulationError-%

PVCC=10V

PVCC=20V

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............................................................................................................................................... SLUS736C – DECEMBER 2006 – REVISED MARCH 2009

TYPICAL CHARACTERISTICS

Table of Graphs

Y X Figure

VREF Load and Line Regulation vs Load Current Figure 4
REGN Load and Line Regulation vs Load Current Figure 5
BAT Voltage vs VADJ/VDAC Ratio Figure 6
Charge Current vs SRSET/VDAC Ratio Figure 7
Input Current vs ACSET/VDAC Ratio Figure 8
BAT Voltage Regulation Accuracy vs Charge Current Figure 9
BAT Voltage Regulation Accuracy Figure 10
Charge Current Regulation Accuracy Figure 11
Input Current Regulation (DPM) Accuracy Figure 12
V
Input Regulation Current (DPM), and Charge Current vs System Current Figure 14
Transient System Load (DPM) Response Figure 15
Charge Current Regulation vs BAT Voltage Figure 16
Efficiency vs Battery Charge Current Figure 17
Battery Removal (from Constant Current Mode) Figure 18
REF and REGN Startup Figure 19
Charger on Adapter Removal Figure 20
Charge Enable / Disable and Current Soft-Start Figure 21
Nonsynchronous to Synchronous Transition Figure 22
Synchronous to Nonsynchronous Transition Figure 23
Near 100% Duty Cycle Bootstrap Recharge Pulse Figure 24
Battery Shorted Charger Response, Over Current Protection (OCP) and Charge Current Regulation Figure 25
Continuous Conduction Mode (CCM) Switching Waveforms Figure 26
Discontinuous Conduction Mode (DCM) Switching Waveforms Figure 27
DPMDET Response With Transient System Load Figure 28

Input Current Sense Amplifier Accuracy Figure 13

IADAPT

bq24740

VREF LOAD AND LINE REGULATION REGN LOAD AND LINE REGULATION

LOAD CURRENT LOAD CURRENT

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Figure 4. Figure 5.

vs vs

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