TEXAS INSTRUMENTS bq24630 Technical data

24 23 22 21 20 19

7 8 9 10 11 12

ACN

ACP

ACDRV

STAT1

SRN

SRP

ISET 2

ACSET

GND

REGN

VCC

BATDRV

BTST

HIDRVPHLODRV

TTC

STAT2

VREF

ISET1

VFB

OAT

(bq24630)

QFN-24

bq24630

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SLUS894 –JANUARY 2010

Stand-Alone Synchronous Switch-Mode Lithium Phosphate Battery Charger with System

Power Selector and Low I

Check for Samples: bq24630

FEATURES

• 300 kHz NMOS-NMOS Synchronous Buck • Energy Star Low Quiescent Current I Converter

• Stand-alone Charger Specifically for Lithium Phosphate

• 5V–28V VCC Input Operating Range, Support APPLICATIONS 1-7 Battery Cells

• High-Accuracy Voltage and Current Regulation – ±0.5% Charge Voltage Accuracy – ±3% Charge Current Accuracy – ±3% Adapter Current Accuracy

• Integration – Automatic System Power Selection from

Adapter or Battery – Internal Loop Compensation – Internal Soft Start – Dynamic Power Management (DPM)

• Safety Protection – Input Over-Voltage Protection – Battery Thermistor Sense Suspend Charge

at Hot/Cold and Automatically I

CHARGE

/8 at

Hot/Cold or Warm/Cool – Battery Detection – Reverse Protection Input FET – Programmable Safety Timer – Charge Over-Current Protection – Battery Short Protection – Battery Over-Voltage Protection – Thermal Shutdown

• Status Outputs – Adapter Present – Charger Operation Status

• Charge Enable Pin

• 6V Gate Drive for Synchronous Buck Converter

• 30ns Driver Dead-time and 99.95% Max Effective Duty Cycle

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

• 24-Pin 4×4-mm2QFN Package

– < 15 mA Off-State Battery Discharge current – < 1.5 mA Off-State Input Quiescent Current

• Power Tool and Portable Equipment

• Personal Digital Assistants

• Handheld Terminals

• Industrial and Medical Equipment

• Netbook, Mobile Internet Device and Ultra-Mobile PC

DESCRIPTION

The bq24630 is highly integrated switch-mode battery charge controller designed specifically for Lithium Phosphate battery. It offers a constant-frequency synchronous PWM controller with high accuracy current and voltage regulation, charge preconditioning, termination, adapter current regulation, and charge status monitoring.

The bq24630 charges the battery in three phases: preconditioning, constant current, and constant voltage. Charge is terminated when the current reaches a minimum user-selectable level. A programmable charge timer provides a safety backup. The bq24630 automatically restarts the charge cycle if the battery voltage falls below an internal threshold, and enters a low-quiescent current sleep mode when the input voltage falls below the battery voltage.

PACKAGE AND PINOUT

RAC

0.010 W

Q1 (ACFET)

ACN

ACP

ISET2

ACSET

VREF

VFB

VCC

HIDRV

BTST

REGN

LODRV

GND

SRP

SRN

PACK+

PACK-

SYSTEM

ADAPTER+

ADAPTER-

0.1 µF

C3 C7

BAT54

C10

0.1

µF

TTC

CTTC

VREF

STAT2

Pack

Thermistor

Sense

BATDRV

ACDRV

bq24630

Q2 (ACFET)

Q3 (BATFET)

VREF

ISET1

STAT1

VBAT

2.2kW

R10

6.8kW

100

ADAPTER +

Cff 22 pF

0.1 µF

1 µF

10 µF

1 µF

RSR

0.010

C11

0.1

µF

C12

10 µF*

C13

10 µF*

500kW

R1210kW

R1110

R1310kW

100 kW

32.4 kW

100 kW

10kW

100 kW

22.1 kW

R14

100 kW

C14

0.1 mF

R15

100

C15

0.1

µF

PwrPad

0.11 Fμ

R16 100

0.1 Fμ

103AT

SI7617DN

SIS412DN

SI7617DN

10 μF

R17 10Ω

R20

2Ω

C16

2.2μF

R18 1kΩ

R19 1kΩ

8.2µH*

bq24630

SLUS894 –JANUARY 2010

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION (CONTINUED)

The bq24630 controls external switches to prevent battery discharge back to the input, connect the adapter to the system, and to connect the battery to the system using 6-V gate drives for better system efficiency. The bq24630 features Dynamic Power Management (DPM). These features reduce battery charge current when the input power limit is reached to avoid overloading the AC adapter when supplying the load and the battery charger simultaneously. A highly-accurate current-sense amplifier enables precise measurement of input current from the AC adapter to monitor the overall system power.

NOTE: VIN=19V, BAT=3-cell LiFePO4, I

adapter_limit

=4A, I

Figure 1. Typical System Schematic

charge

=3A, I

pre-charge

=0.125A, I

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=0.3A, 2.5hr safety timer

term

bq24630

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SLUS894 –JANUARY 2010

ORDERING INFORMATION

PART NUMBER IC MARING PACKAGE QUANTITY

bq24630 OAT 24-Pin 4×4 mm2QFN

PACKAGE THERMAL DATA

PACKAGE q

QFN – RGE

(2)

4°C/W 43°C/W 2.3W 0.023 W/°C

(1) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is

connected to the ground plane by a 2×2 via matrix. qJAhas 5% improvement by 3x3 via matrix.

(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1) (2) (3)

over operating free-air temperature range (unless otherwise noted)

Voltage range VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1, –0.3 to 33 V

Maximum difference voltage ACP–ACN, SRP–SRN –0.5 to 0.5 V Junction temperature range, T Storage temperature range, T

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging

Section of the data book for thermal limitations and considerations of packages.

(3) Must have a series resistor between battery pack to VFB if Battery Pack voltage is expected to be greater than 16V. Usually the resistor

divider top resistor will take care of this.

STAT2, PG PH –2 to 36 V VFB –0.3 to 16 V REGN, LODRV, ACSET, TS, TTC –0.3 to 7 V BTST, HIDRV with respect to GND –0.3 to 39 V VREF, ISET1, ISET2 –0.3 to 3.6 V

stg

ODERING NUMBER

(Tape and Reel)

bq24630RGER 3000 bq24630RGET 250

(1)

TA= 25°C DERATING FACTOR

POWER RATING ABOVE TA= 25°C

VALUE UNIT

–40 to 155 °C –55 to 155 °C

RECOMMENDED OPERATING CONDITIONS

VALUE UNIT

Voltage range VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1, STAT2, PG –0.3 to 28 V

PH –2 to 30 V VFB –0.3 to 14 V REGN, LODRV, ACSET, TS, TTC –0.3 to 6.5 V BTST, HIDRV with respect to GND –0.3 to 34 V ISET1, ISET2 –0.3 to 3.3 V VREF 3.3 V

Maximum difference voltage ACP–ACN, SRP–SRN –0.2 to 0.2 V

Junction temperature range 0 to 125 °C

Storage temperature range –55 to 155 °C

stg

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SLUS894 –JANUARY 2010

ELECTRICAL CHARACTERISTICS

5.0V ≤ V(VCC) ≤28V, 0°C<TJ<+125°C,typical values are at TA=25°C, with respect to GND unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OPERATING CONDITIONS

VCC_OP

QUIESCENT CURRENTS

BAT

CURRENT REGULATION – FAST CHARGE

ISET1

IREG_CHG

(ISET1)

ISET1

CURRENT REGULATION – PRECHARGE

CHARGE TERMINATION

ISET2

TERM

QUAL

ISET2

INPUT CURRENT REGULATION

ACSET

IREG_DPM

(ACSET)

ACSET

INPUT UNDER-VOLTAGE LOCK-OUT COMPARATOR (UVLO)

UVLO

UVLO_HYS

VCC Input voltage operating range 5.0 28.0 V

Total battery discharge current (sum of currents into VCC, BTST, PH, ACP, ACN, V SRP, SRN, VFB), VFB ≤2.1 V

Battery discharge current (sum of currents V into BTST, PH, SRP, SRN, VFB), VFB ≤

2.1 V

Adapter supply current (current into V VCC,ACP,ACN pin)

< V

> V > V > V

> V > V

SRN

SRN SRN SRN

, V

, V , V , V

, V , V

VCC

VCC VCC>VVCCLOW VCC>VVCCLOW

VCC

VCC VCC

VCC

Qg_total = 20 nC, V

> V

(SLEEP) 15

UVLO

> V

CE = LOW 5

UVLO

> V > V

CE = HIGH, Charge done 5 µA

VCCLOW

CE = LOW 1 1.5

UVLO

, CE = HIGH, charge done 2 5 , CE = HIGH, Charging,

=20V

VCC

Feedback regulation voltage 1.8 V

Charge voltage regulation accuracy

TJ= 0°C to 125°C –0.5% 0.5% TJ= –40°C to 125°C –0.7% 0.7%

Input leakage current into VFB pin VFB = 1.8 V 100 nA

ISET1 voltage range 2 V SRP–SRN current sense voltage range V Charger current set factor amps of charge

current per volt on ISET1 pin)

Charge current regulation accuracy

Leakage current in to ISET1 Pin V

Precharge current R

R V

V V V

= V

IREG_CHG

= 10 mΩ 5 A/V

SENSE

IREG_CHG IREG_CHG IREG_CHG IREG_CHG

= 2 V 100 nA

ISET1

= 10 mΩ, VFB < V

SENSE

– V

SRP

SRN

= 40 mV –3% 3% = 20 mV –4% 4% = 5 mV –25% 25% = 1.5 mV (V

> 3.1 V) –40% 40%

SRN

LOWV

50 125 200 mA

ISET2 voltage range 2 V Termination current range R Termination current set factor (amps of

termination current per volt on ISET2 pin)

Termination current accuracy V

= 10 mΩ 2 A

SENSE

1 A/V

= 20 mV –4% 4%

ITERM

= 5 mV –25% 25%

ITERM

= <1.5 mV –45% 45%

ITERM

Deglitch time for termination (both edge) 100 ms Termination qualification time V

BAT

> V

RECH

and I

CHARGE

< I

TERM

250 ms Termination qualification time Discharge current once termination is detected 2 mA Leakage current into ISET2 pin V

= 2 V 100 nA

ISET2

ACSET voltage range 0 2 V ACP-ACN current sense voltage range V Input current set factor (amps of input

current per volt on ACSET pin)

Input current regulation accuracy V

Leakage current into ACSET pin V

R V

= V

IREG_DPM

= 10 mΩ 5 A/V

SENSE

IREG_DPM IREG_DPM IREG_DPM

= 2 V 100 nA

ACSET

– V

ACP

ACN

= 40 mV –3% 3% = 20 mV –4% 4% = 5 mV –25% 25%

0 100 mV

AC under-voltage rising threshold Measure on VCC 3.65 3.85 4 V AC under-voltage hysteresis, falling 350 mV

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100 mV

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SLUS894 –JANUARY 2010

ELECTRICAL CHARACTERISTICS (continued)

5.0V ≤ V(VCC) ≤28V, 0°C<TJ<+125°C,typical values are at TA=25°C, with respect to GND unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VCC LOWV COMPARATOR

Falling threshold, disable charge Measure on VCC 4.1 V Rising threshold, resume charge 4.35 4.5 V

SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)

SLEEP _FALL

SLEEP_HYS

ACN / SRN COMPARATOR

ACN-SRN_FALL

ACN-SRN_HYS

BAT LOWV COMPARATOR

LOWV

LOWV_HYS

RECHARGE COMPARATOR

RECHG

BAT OVER-VOLTAGE COMPARATOR

OV_RISE

OV_FALL

INPUT OVER-VOLTAGE COMPARATOR (ACOV)

ACOV

ACOV_HYS

THERMAL SHUTDOWN COMPARATOR

SHUT

SHUT_HYS

THERMISTOR COMPARATOR

LTF

LTF_HYS

COOL

COOL_HYS

WARM

WARM_HYS

HTF

TCO

SLEEP falling threshold V

VCC

– V

to enter SLEEP 40 100 150 mV

SRN

SLEEP hysteresis 500 mV SLEEP rising delay VCC falling below SRN, Delay to turn off ACFET 1 ms SLEEP falling delay VCC rising above SRN, Delay to turn on ACFET 30 ms SLEEP rising shutdown deglitch VCC falling below SRN, Delay to enter SLEEP mode 100 ms SLEEP falling powerup deglitch VCC rising above SRN, Delay to exit out of SLEEP mode 30 ms

ACN to SRN falling threshold V

ACN–VSRN

to turn on BATFET 100 200 310 mV ACN to SRN rising hysteresis 100 mV ACN to SRN rising deglitch V ACN to SRN falling deglitch V

Precharge to fastcharge transition (LOWV threshold)

– V

ACN ACN

– V

SRN SRN

> V

ACN-SRN_RISE

< V

ACN-SRN_FALL

2 ms

50 ms

Measured on VFB pin, rising 0.333 0.35 0.367 V

LOWV hysteresis 100 mV LOWV rising deglitch VFB falling below VLOWV 25 ms LOWV falling deglitch VFB rising above VLOWV 25 ms

Recharge threshold (with respect to VREG)

Recharge rising deglitch VFB decreasing below V Recharge falling deglitch VFB increasing above V

Over-voltage rising threshold As percentage of V Over-voltage falling threshold As percentage of V

Measured on VFB pin, rising 110 125 140 mV

RECHG

FB FB

10 ms 10 ms

108% 105%

AC over-voltage rising threshold on VCC 31.04 32 32.96 V AC over-voltage falling hysteresis 1 V AC over-voltage deglitch (both edge) Delay to changing the STAT pins 1 ms AC over-voltage rising deglitch Delay to disable charge 1 ms AC over-voltage falling deglitch Delay to resume charge 20 ms

Thermal shutdown rising temperature Temperature increasing 145 °C Thermal shutdown hysteresis 15 °C Thermal shutdown rising deglitch Temperature increasing 100 ms Thermal shutdown falling deglitch Temperature decreasing 10 ms

Cold temperature rising threshold Charger suspended below this temperature 72.5% 73.5% 74.5% Cold temperature hysteresis 0.2% 0.4% 0.6%

Cool Temperature rising threshold 70.2% 70.7% 71.2%

Charger enabled, cuts back to I temperature

CHARGE

/8 below this

Cool temperature hysteresis 0.2% 0.6% 1.0% Warm temperature rising threshold Charger cuts back to I

/8 above this temperature 47.5% 48% 48.5%

CHARGE

Warm temperature hysteresis 1.0% 1.2% 1.4% Hot temperature rising threshold 36.2% 37% 37.8%

Cut-off temperature rising threshold 33.7% 34.4% 35.1%

Charger suspended above this temperature before initiating charge

Charger suspended above this temperature during initiating charge

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bq24630

SLUS894 –JANUARY 2010

ELECTRICAL CHARACTERISTICS (continued)

5.0V ≤ V(VCC) ≤28V, 0°C<TJ<+125°C,typical values are at TA=25°C, with respect to GND unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Deglitch time for Temperature Out of Range Detection

Deglitch time for Temperature in Valid Range Detection

Deglitch time for current reduction to I

/8 due to warm or cool temperature

CHARGE

Deglitch time to charge at I I

/8 when resuming from warm or VTS< V

CHARGE

cool temperatures

CHARGE

from

Charge current due to warm or cool V temperatures VTS< V

CHARGE OVER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)

Charge over-current falling threshold

Charge over-current threshold floor 50 mV

Charge over-current threshold ceiling 180 mV

CHARGE UNDER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)

ISYNSET

Charge under-current falling threshold Switch from SYNCH to NON-SYNCH, V

BATTERY SHORTED COMPARATOR (BATSHORT)

BATSHT

BATSHT_HYS

BATSHT_DEG

BAT Short falling threshold, forced non-synchronous mode

BAT short rising hysteresis 200 mV Deglitch on both edge 1 ms

LOW CHARGE CURRENT COMPARATOR

LC_HYS

LC_DEG

Average low charge current falling Measure on V threshold mode

Low charge current rising hysteresis 1.25 mV Deglitch on both edge 1 ms

VREF REGULATOR

VREF_REG

VREF_LIM

VREF regulator voltage V VREF current limit V

REGN REGULATOR

REGN_REG

REGN_LIM

REGN regulator voltage V REGN current limit V

TTC INPUT

PRECHG

CHARGE

TTC

Precharge safety timer range Fast charge saftey timer range, with +/-

10% accuracy

(1)

Fast charge timer accuracy Timer multiplier 1.4 min/nF

(1)

TTC low threshold 0.4 V TTC comparator high threshold 1.5 V

TTC comparator low threshold 1 V TTC source/sink current 45 50 55 mA

BATTERY SWITCH (BATFET) DRIVER

DS_BAT_OFF

DS_BAT_ON

BATDRV_REG

BATFET turn-off resistance V BATFET turn-on resistance V

BATFET drive voltage 4.2 7 V

VTS> V

VTS< V

VTS> V

Current rising, in non-synchronous mode, mesure on V

Current rising, as percentage of V synchronous mode, V

< VTS< V

COOL

(SRP-SRN)

, or VTS< V

LTF

– V

LTF

, or VTS< V

COOL

- V

COOL

TCO

, V

SRP

LTF_HYS

COOL_HYS

, or V

LTF

< 2 V

, or VTS< V

TCO

or VTS>V

WARM

, or VTS> V

WARM

> 2.2V

SRP

HTF

, or VTS> V

TCO

WARM

< VTS< V

(IREG_CHG)

HTF

- V

WARM_HYS

, or V

, in

HTF

WARM

< I

400 ms

20 ms

25 ms

CHARGE

45.5 mV

160%

Minimum OCP threshold in synchronous mode, measure on V

(SRP-SRN)

, V

SRP

> 2.2V

Maximum OCP threshold in synchronous mode, measure on V

SRP

VCC VREF

VCC REGN

, V

(SRP-SRN)

SRP

> 2.2V

> 2.2V 1 5 9 mV

SRP

falling 2 V

, forced into non-synchronous

(SRP-SRN)

> V

, ( 0 – 35mA load) 3.267 3.3 3.333 V

UVLO

= 0 V, V

VCC

> V

UVLO

1.25 mV

35 mA

> 10 V, CE = HIGH (0 – 40mA load) 5.7 6.0 6.3 V

= 0 V, V

VCC

> V

UVLO

40 mA

Precharge time before fault occurs 1440 1800 2160 sec Tchg = C

0.047 mF ≤ C

TTC

termination

ACN ACN

BATDRV_REG

BATFET is on

× K

TTC

≤ 0.47 mF –10% 10%

TTC

1 10 Hr

below this threshold disables the safety timer and

> 5V 150 Ω > 5V 20 kΩ

= V

ACN

– V

BATDRV

when V

ACN

> 5V and

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SLUS894 –JANUARY 2010

ELECTRICAL CHARACTERISTICS (continued)

5.0V ≤ V(VCC) ≤28V, 0°C<TJ<+125°C,typical values are at TA=25°C, with respect to GND unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AC SWITCH (ACFET) DRIVER

DS_AC_OFF

DS_AC_ON

ACDRV_REG

AC / BAT MOSFET DRIVERS TIMING

BATTERY DETECTION

WAKE

DISCHARGE

FAULT

WAKE

DISCH

PWM HIGH SIDE DRIVER (HIDRV)

DS_HI_ON

DS_HI_OFF

BTST_REFRESH

PWM LOW SIDE DRIVER (LODRV)

DS_LO_ON

DS_LO_OFF

PWM DRIVERS TIMING

PWM OSCILLATOR

RAMP_HEIGHT

INTERNAL SOFT START (8 steps to regulation current ICHG)

CHARGER SECTION POWER-UP SEQUENCING

LOGIC IO PIN CHARACTERISTICS

IN_LO

IN_HI

BIAS_CE

OUT_LO

OUT_HI

(2) Verified by design

ACFET turn-off resistance V ACFET turn-on resistance V

ACFET drive voltage 4.2 7 V

> 5V 30 Ώ

VCC

> 5V 20 kΏ

VCC

ACDRV_REG

ACFET is on

= V

VCC

– V

ACDRV

when V

VCC

> 5 V and

Driver dead time Dead time when switching between AC and BAT 10 ms

Wake timer Max time charge is enabled 500 ms Wake Current R

= 10 mΩ 50 125 200 mA

SENSE

Discharge timer Max time discharge current is applied 1 sec Discharge current 8 mA Fault current after a timeout fault 2 mA Wake threshold ( with-respect-to V

) Voltage on VFB to detect battery absent during Wake 125 mV

REG

Discharge threshold Voltage on VFB to detect battery absent during Discharge 0.35 V

High Side driver (HSD) turn-on resistance V High Side driver turn-off resistance V Bootstrap refresh comparator threshold

voltage

– VPH= 5.5 V 3.3 6 Ω

BTST

– VPH= 5.5 V 1 1.3 Ω

BTST

– VPHwhen low side refresh pulse is requested 4.0 4.2 V

BTST

Low side driver (LSD) turn-on resistance 4.1 7 Ω Low side driver turn-off resistance 1 1.4 Ω

Driver dead time ns

Dead time when switching between LSD and HSD, no 30 load at LSD and HSD

PWM ramp height As percentage of VCC 7 % PWM switching frequency

(2)

255 300 345 kHz

Soft start steps 8 step Soft start step time 1.6 ms

Charge-enable delay after power-up 1.5 s

Delay from when adapter is detected to when the charger is allowed to turn on

CE input low threshold voltage 0.8 V CE input high threshold voltage 2.1 V CE input bias current V = 3.3 V (CE has internal 1MΩ pulldown resistor) 6 mA STAT1, STAT2, PG output low saturation

voltage

Sink current = 5 mA 0.5 V

Leakage current V = 32 V 1.2 µA

Product Folder Link(s): bq24630

VCC

/PG

VREF

REGN

t − Time=4ms/div

5V/div

2V/div

10V/div

2V/div

t − Time=200ms/div

LODRV

IBAT

5V/div

10V/div

2 A/div

LDRV

10V/div

5V/div

2V/div

2 A/div

t − Time=4 s/divμ

t − Time=4ms/div

LODRV

IBAT

5V/div

10V/div

2 A/div

bq24630

SLUS894 –JANUARY 2010

TYPICAL CHARACTERISTICS

Table 1. Table of Graphs

Figure

REF REGN and PG Power Up (CE=1) Figure 2 Charge Enable Figure 3 Current Soft-Start (CE=1) Figure 4 Charge Disable Figure 5 Continuous Conduction Mode Switching Waveforms Figure 6 Cycle-by-Cycle Synchronous to Nonsynchronous Figure 7 100% Duty and Refresh Pulse Figure 8 Transient System Load (DPM) Figure 9 Battery Insertion Figure 10 Battery to Ground Short Protection Figure 11 Battery to ground Short Transition Figure 12 Efficiency vs Output Current Figure 13 Input ACOV Transition Figure 14 Input ACOV Resume Normal Transition Figure 15

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Figure 2. REF REGN and PG Power Up (CE=1) Figure 3. Charge Enable

Figure 4. Current Soft-Start (CE=1) Figure 5. Charge Disable

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5V/div

2 A/div

LODRV

t Time=200ns/div–

20V/div

5V/div

2 A/div

LODRV

HIDRV

t − Time=200ns/div

t − Time=400ns/div

LODRV

0.5 A/div

10V/div

5V/div

t − Time=200 s/divμ

IIN

ISYS

IBAT

2 A/div

20V/div

10V/div

2 A/div

VBAT

LDRV

5V/div

t Time=4ms/div–

10V/div

2 A/div

VBAT

t Time=200ms/div–

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SLUS894 –JANUARY 2010

Figure 6. Continuous Conduction Mode Switching Waveform Figure 7. Cycle-by-Cycle Synchronous to Nonsynchronous

Figure 8. 100% Duty and Refresh Pulse Figure 9. Transient System Load (DPM)

Figure 10. Battery Insertion Figure 11. Battery to GND Short Protection

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20V/div

10V/div

2 A/div

5V/div

VBAT

LDRV

t Time=8 s/div– μ

0 1 2 3

IBAT-OutputCurrent- A

Efficiency-%

12Vin,1cell

24Vin,5cell

12Vin,2cell

24Vin,6cell

20V/div

2V/div

20V/div

/PG

/BATDRV

VCC

/ACDRV

t Time=10ms/div–

20V/div

2V/div

20V/div

/PG

/BATDRV

VCC

/ACDRV

t Time=20ms/div–

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SLUS894 –JANUARY 2010

Figure 12. Battery to GND Short Transition Figure 13. Efficiency vs Output Current

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Figure 14. Input ACOV Transition Figure 15. Input ACOV Resume Normal Transition

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SLUS894 –JANUARY 2010

Pin Functions – 24-Pin QFN

NO. NAME

1 ACN Adapter current sense resistor, negative input. A 0.1-mF ceramic capacitor is placed from ACN to ACP to provide differential-mode

filtering. An optional 0.1-mF ceramic capacitor is placed from ACN pin to GND for common-mode filtering.

2 ACP Adapter current sense resistor, positive input. A 0.1-mF ceramic capacitor is placed from ACN to ACP to provide differential-mode

filtering. A 0.1-mF ceramic capacitor is placed from ACP pin to GND for common-mode filtering.

3 ACDRV AC adapter to system MOSFET driver output. Connect through a 1-kΩ resistor to the gate of the ACFET P-channel power MOSFET

and the reverse conduction blocking P-channel power MOSFET. The internal gate drive is asymmetrical, allowing a quick turn-off and slow turn-on, in addition to the internal break-before-make logic with respect to BATDRV. If needed, an optional capacitor from gate to

source of the ACFET is used to slow down the ON and OFF times. 4 CE Charge-enable active-HIGH logic input. HI enables charge. LO disables charge. It has an internal 1MΩ pull-down resistor. 5 STAT1 Open-drain charge status pin to indicate various charger operation. 6 TS Temperature qualification voltage input for battery pack negative temperature coefficient thermistor. Program the hot and cold

temperature window with a resistor divider from VREF to TS to GND. 7 TTC SafetyTimer and termination control. Connect a capacitor from this node to GND to set the timer. When this input is LOW, the timer

and termination are disabled. When this input is HIGH, the timer is disabled but termination is allowed. 8 PG Open-drain power-good status output. Active LOW when IC has a valid VCC (not in UVLO or ACOV or SLEEP mode). Active HIGH

when IC has an invalid VCC. PGcan be used to drive a LED or communicate with a host processor. 9 STAT2 Open-drain charge status pin to indicate various charger operation.

10 VREF 3.3V regulated voltage output. Place a 1-mF ceramic capacitor from VREF to GND pin close to the IC. This voltage could be used for

programming of voltage and current regulation and for programming the TS threshold.

11 ISET1 Fast Charge current set input. The voltage of ISET1 pin programs the fast charge current regulation set-point. 12 VFB Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider from the battery terminals to this node to

adjust the output battery regulation voltage.

13 SRN Charge current sense resistor, negative input. A 0.1-mF ceramic capacitor is placed from SRN to SRP to provide differential-mode

filtering. An optional 0.1-mF ceramic capacitor is placed from SRN pin to GND for common-mode filtering.

14 SRP Charge current sense resistor, positive input. A 0.1-mF ceramic capacitor is placed from SRN to SRP to provide differential-mode

filtering. A 0.1-mF ceramic capacitor is placed from SRP pin to GND for common-mode filtering.

15 ISET2 Termination current set input. The voltage of ISET2 pin programs termination current trigger point. 16 ACSET Adapter current set input. The voltage of ACSET pin programs the input current regulation set-point during Dynamic Power

Management (DPM)

17 GND Low-current sensitive analog/digital ground. On PCB layout, connect with PowerPad underneath the IC. 18 REGN PWM low side driver positive 6V supply output. Connect a 1-mF ceramic capacitor from REGN to GND pin, close to the IC. Use for

low side driver and high-side driver bootstrap voltage by connecting a small signal Schottky diode from REGN to BTST.

19 LODRV PWM low side driver output. Connect to the gate of the low-side power MOSFET with a short trace. 20 PH PWM high side driver negative supply. Connect to the Phase switching node (junction of the low-side power MOSFET drain, high-side

power MOSFET source, and output inductor). Connect the 0.1-mF bootstrap capacitor from PH to BTST.

21 HIDRV PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace. 22 BTST PWM high side driver positive supply. Connect to the Phase switching node (junction of the low-side power MOSFET drain, high-side

power MOSFET source, and output inductor). Connect the 0.1-mF bootstrap capacitor from SW to BTST.

23 BATDRV Battery to system MOSFET driver output. Gate drive for the battery to system load BAT PMOS power FET to isolate the system from

the battery to prevent current flow from the system to the battery, while allowing a low impedance path from battery to system.

Connect this pin through a 1-kΩ resistor to the gate of the input BAT P-channel MOSFET. Connect the source of the FET to the

system load voltage node. Connect the drain of the FET to the battery pack positive terminal. The internal gate drive is asymmetrical

to allow a quick turn-off and slow turn-on, in addition to the internal break-before-make logic with respect to ACDRV. If needed, an

optional capacitor from gate to source of the BATFET is used to slow down the ON and OFF times.

24 VCC IC power positive supply. Connect through a 10-Ω to the common-source (diode-OR) point: source of high-side P-channel MOSFET

and source of reverse-blocking power P-channel MOSFET. Place a 1-mF ceramic capacitor from VCC to GND pin close to the IC.

PowerPAD Exposed pad beneath the IC. Always solder PowerPAD to the board, and have vias on the PowerPAD plane star-connecting to GND

and ground plane for high-current power converter. It also serves as a thermal pad to dissipate the heat.

FUNCTION DESCRIPTION

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