TEXAS INSTRUMENTS bq24630 Technical data

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24 23 22 21 20 19

7 8 9 10 11 12

ACN

ACP

ACDRV

STAT1

SRN

SRP

ISET 2

ACSET

GND

REGN

VCC

BATDRV

BTST

HIDRVPHLODRV

TTC

STAT2

VREF

ISET1

VFB

OAT

(bq24630)

QFN-24

bq24630

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SLUS894 –JANUARY 2010

Stand-Alone Synchronous Switch-Mode Lithium Phosphate Battery Charger with System

Power Selector and Low I

Check for Samples: bq24630

FEATURES

• 300 kHz NMOS-NMOS Synchronous Buck • Energy Star Low Quiescent Current I Converter

• Stand-alone Charger Specifically for Lithium Phosphate

• 5V–28V VCC Input Operating Range, Support APPLICATIONS 1-7 Battery Cells

• High-Accuracy Voltage and Current Regulation – ±0.5% Charge Voltage Accuracy – ±3% Charge Current Accuracy – ±3% Adapter Current Accuracy

• Integration – Automatic System Power Selection from

Adapter or Battery – Internal Loop Compensation – Internal Soft Start – Dynamic Power Management (DPM)

• Safety Protection – Input Over-Voltage Protection – Battery Thermistor Sense Suspend Charge

at Hot/Cold and Automatically I

CHARGE

/8 at

Hot/Cold or Warm/Cool – Battery Detection – Reverse Protection Input FET – Programmable Safety Timer – Charge Over-Current Protection – Battery Short Protection – Battery Over-Voltage Protection – Thermal Shutdown

• Status Outputs – Adapter Present – Charger Operation Status

• Charge Enable Pin

• 6V Gate Drive for Synchronous Buck Converter

• 30ns Driver Dead-time and 99.95% Max Effective Duty Cycle

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

• 24-Pin 4×4-mm2QFN Package

– < 15 mA Off-State Battery Discharge current – < 1.5 mA Off-State Input Quiescent Current

• Power Tool and Portable Equipment

• Personal Digital Assistants

• Handheld Terminals

• Industrial and Medical Equipment

• Netbook, Mobile Internet Device and Ultra-Mobile PC

DESCRIPTION

The bq24630 is highly integrated switch-mode battery charge controller designed specifically for Lithium Phosphate battery. It offers a constant-frequency synchronous PWM controller with high accuracy current and voltage regulation, charge preconditioning, termination, adapter current regulation, and charge status monitoring.

The bq24630 charges the battery in three phases: preconditioning, constant current, and constant voltage. Charge is terminated when the current reaches a minimum user-selectable level. A programmable charge timer provides a safety backup. The bq24630 automatically restarts the charge cycle if the battery voltage falls below an internal threshold, and enters a low-quiescent current sleep mode when the input voltage falls below the battery voltage.

PACKAGE AND PINOUT

RAC

0.010 W

Q1 (ACFET)

ACN

ACP

ISET2

ACSET

VREF

VFB

VCC

HIDRV

BTST

REGN

LODRV

GND

SRP

SRN

PACK+

PACK-

SYSTEM

ADAPTER+

ADAPTER-

0.1 µF

C3 C7

BAT54

C10

0.1

µF

TTC

CTTC

VREF

STAT2

Pack

Thermistor

Sense

BATDRV

ACDRV

bq24630

Q2 (ACFET)

Q3 (BATFET)

VREF

ISET1

STAT1

VBAT

2.2kW

R10

6.8kW

100

ADAPTER +

Cff 22 pF

0.1 µF

1 µF

10 µF

1 µF

RSR

0.010

C11

0.1

µF

C12

10 µF*

C13

10 µF*

500kW

R1210kW

R1110

R1310kW

100 kW

32.4 kW

100 kW

10kW

100 kW

22.1 kW

R14

100 kW

C14

0.1 mF

R15

100

C15

0.1

µF

PwrPad

0.11 Fμ

R16 100

0.1 Fμ

103AT

SI7617DN

SIS412DN

SI7617DN

10 μF

R17 10Ω

R20

2Ω

C16

2.2μF

R18 1kΩ

R19 1kΩ

8.2µH*

bq24630

SLUS894 –JANUARY 2010

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION (CONTINUED)

The bq24630 controls external switches to prevent battery discharge back to the input, connect the adapter to the system, and to connect the battery to the system using 6-V gate drives for better system efficiency. The bq24630 features Dynamic Power Management (DPM). These features reduce battery charge current when the input power limit is reached to avoid overloading the AC adapter when supplying the load and the battery charger simultaneously. A highly-accurate current-sense amplifier enables precise measurement of input current from the AC adapter to monitor the overall system power.

NOTE: VIN=19V, BAT=3-cell LiFePO4, I

adapter_limit

=4A, I

Figure 1. Typical System Schematic

charge

=3A, I

pre-charge

=0.125A, I

Product Folder Link(s): bq24630

=0.3A, 2.5hr safety timer

term

bq24630

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SLUS894 –JANUARY 2010

ORDERING INFORMATION

PART NUMBER IC MARING PACKAGE QUANTITY

bq24630 OAT 24-Pin 4×4 mm2QFN

PACKAGE THERMAL DATA

PACKAGE q

QFN – RGE

(2)

4°C/W 43°C/W 2.3W 0.023 W/°C

(1) This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is

connected to the ground plane by a 2×2 via matrix. qJAhas 5% improvement by 3x3 via matrix.

(2) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1) (2) (3)

over operating free-air temperature range (unless otherwise noted)

Voltage range VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1, –0.3 to 33 V

Maximum difference voltage ACP–ACN, SRP–SRN –0.5 to 0.5 V Junction temperature range, T Storage temperature range, T

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging

Section of the data book for thermal limitations and considerations of packages.

(3) Must have a series resistor between battery pack to VFB if Battery Pack voltage is expected to be greater than 16V. Usually the resistor

divider top resistor will take care of this.

STAT2, PG PH –2 to 36 V VFB –0.3 to 16 V REGN, LODRV, ACSET, TS, TTC –0.3 to 7 V BTST, HIDRV with respect to GND –0.3 to 39 V VREF, ISET1, ISET2 –0.3 to 3.6 V

stg

ODERING NUMBER

(Tape and Reel)

bq24630RGER 3000 bq24630RGET 250

(1)

TA= 25°C DERATING FACTOR

POWER RATING ABOVE TA= 25°C

VALUE UNIT

–40 to 155 °C –55 to 155 °C

RECOMMENDED OPERATING CONDITIONS

VALUE UNIT

Voltage range VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1, STAT2, PG –0.3 to 28 V

PH –2 to 30 V VFB –0.3 to 14 V REGN, LODRV, ACSET, TS, TTC –0.3 to 6.5 V BTST, HIDRV with respect to GND –0.3 to 34 V ISET1, ISET2 –0.3 to 3.3 V VREF 3.3 V

Maximum difference voltage ACP–ACN, SRP–SRN –0.2 to 0.2 V

Junction temperature range 0 to 125 °C

Storage temperature range –55 to 155 °C

stg

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bq24630

SLUS894 –JANUARY 2010

ELECTRICAL CHARACTERISTICS

5.0V ≤ V(VCC) ≤28V, 0°C<TJ<+125°C,typical values are at TA=25°C, with respect to GND unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OPERATING CONDITIONS

VCC_OP

QUIESCENT CURRENTS

BAT

CURRENT REGULATION – FAST CHARGE

ISET1

IREG_CHG

(ISET1)

ISET1

CURRENT REGULATION – PRECHARGE

CHARGE TERMINATION

ISET2

TERM

QUAL

ISET2

INPUT CURRENT REGULATION

ACSET

IREG_DPM

(ACSET)

ACSET

INPUT UNDER-VOLTAGE LOCK-OUT COMPARATOR (UVLO)

UVLO

UVLO_HYS

VCC Input voltage operating range 5.0 28.0 V

Total battery discharge current (sum of currents into VCC, BTST, PH, ACP, ACN, V SRP, SRN, VFB), VFB ≤2.1 V

Battery discharge current (sum of currents V into BTST, PH, SRP, SRN, VFB), VFB ≤

2.1 V

Adapter supply current (current into V VCC,ACP,ACN pin)

< V

> V > V > V

> V > V

SRN

SRN SRN SRN

, V

, V , V , V

, V , V

VCC

VCC VCC>VVCCLOW VCC>VVCCLOW

VCC

VCC VCC

VCC

Qg_total = 20 nC, V

> V

(SLEEP) 15

UVLO

> V

CE = LOW 5

UVLO

> V > V

CE = HIGH, Charge done 5 µA

VCCLOW

CE = LOW 1 1.5

UVLO

, CE = HIGH, charge done 2 5 , CE = HIGH, Charging,

=20V

VCC

Feedback regulation voltage 1.8 V

Charge voltage regulation accuracy

TJ= 0°C to 125°C –0.5% 0.5% TJ= –40°C to 125°C –0.7% 0.7%

Input leakage current into VFB pin VFB = 1.8 V 100 nA

ISET1 voltage range 2 V SRP–SRN current sense voltage range V Charger current set factor amps of charge

current per volt on ISET1 pin)

Charge current regulation accuracy

Leakage current in to ISET1 Pin V

Precharge current R

R V

V V V

= V

IREG_CHG

= 10 mΩ 5 A/V

SENSE

IREG_CHG IREG_CHG IREG_CHG IREG_CHG

= 2 V 100 nA

ISET1

= 10 mΩ, VFB < V

SENSE

– V

SRP

SRN

= 40 mV –3% 3% = 20 mV –4% 4% = 5 mV –25% 25% = 1.5 mV (V

> 3.1 V) –40% 40%

SRN

LOWV

50 125 200 mA

ISET2 voltage range 2 V Termination current range R Termination current set factor (amps of

termination current per volt on ISET2 pin)

Termination current accuracy V

= 10 mΩ 2 A

SENSE

1 A/V

= 20 mV –4% 4%

ITERM

= 5 mV –25% 25%

ITERM

= <1.5 mV –45% 45%

ITERM

Deglitch time for termination (both edge) 100 ms Termination qualification time V

BAT

> V

RECH

and I

CHARGE

< I

TERM

250 ms Termination qualification time Discharge current once termination is detected 2 mA Leakage current into ISET2 pin V

= 2 V 100 nA

ISET2

ACSET voltage range 0 2 V ACP-ACN current sense voltage range V Input current set factor (amps of input

current per volt on ACSET pin)

Input current regulation accuracy V

Leakage current into ACSET pin V

R V

= V

IREG_DPM

= 10 mΩ 5 A/V

SENSE

IREG_DPM IREG_DPM IREG_DPM

= 2 V 100 nA

ACSET

– V

ACP

ACN

= 40 mV –3% 3% = 20 mV –4% 4% = 5 mV –25% 25%

0 100 mV

AC under-voltage rising threshold Measure on VCC 3.65 3.85 4 V AC under-voltage hysteresis, falling 350 mV

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100 mV

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SLUS894 –JANUARY 2010

ELECTRICAL CHARACTERISTICS (continued)

5.0V ≤ V(VCC) ≤28V, 0°C<TJ<+125°C,typical values are at TA=25°C, with respect to GND unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VCC LOWV COMPARATOR

Falling threshold, disable charge Measure on VCC 4.1 V Rising threshold, resume charge 4.35 4.5 V

SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)

SLEEP _FALL

SLEEP_HYS

ACN / SRN COMPARATOR

ACN-SRN_FALL

ACN-SRN_HYS

BAT LOWV COMPARATOR

LOWV

LOWV_HYS

RECHARGE COMPARATOR

RECHG

BAT OVER-VOLTAGE COMPARATOR

OV_RISE

OV_FALL

INPUT OVER-VOLTAGE COMPARATOR (ACOV)

ACOV

ACOV_HYS

THERMAL SHUTDOWN COMPARATOR

SHUT

SHUT_HYS

THERMISTOR COMPARATOR

LTF

LTF_HYS

COOL

COOL_HYS

WARM

WARM_HYS

HTF

TCO

SLEEP falling threshold V

VCC

– V

to enter SLEEP 40 100 150 mV

SRN

SLEEP hysteresis 500 mV SLEEP rising delay VCC falling below SRN, Delay to turn off ACFET 1 ms SLEEP falling delay VCC rising above SRN, Delay to turn on ACFET 30 ms SLEEP rising shutdown deglitch VCC falling below SRN, Delay to enter SLEEP mode 100 ms SLEEP falling powerup deglitch VCC rising above SRN, Delay to exit out of SLEEP mode 30 ms

ACN to SRN falling threshold V

ACN–VSRN

to turn on BATFET 100 200 310 mV ACN to SRN rising hysteresis 100 mV ACN to SRN rising deglitch V ACN to SRN falling deglitch V

Precharge to fastcharge transition (LOWV threshold)

– V

ACN ACN

– V

SRN SRN

> V

ACN-SRN_RISE

< V

ACN-SRN_FALL

2 ms

50 ms

Measured on VFB pin, rising 0.333 0.35 0.367 V

LOWV hysteresis 100 mV LOWV rising deglitch VFB falling below VLOWV 25 ms LOWV falling deglitch VFB rising above VLOWV 25 ms

Recharge threshold (with respect to VREG)

Recharge rising deglitch VFB decreasing below V Recharge falling deglitch VFB increasing above V

Over-voltage rising threshold As percentage of V Over-voltage falling threshold As percentage of V

Measured on VFB pin, rising 110 125 140 mV

RECHG

FB FB

10 ms 10 ms

108% 105%

AC over-voltage rising threshold on VCC 31.04 32 32.96 V AC over-voltage falling hysteresis 1 V AC over-voltage deglitch (both edge) Delay to changing the STAT pins 1 ms AC over-voltage rising deglitch Delay to disable charge 1 ms AC over-voltage falling deglitch Delay to resume charge 20 ms

Thermal shutdown rising temperature Temperature increasing 145 °C Thermal shutdown hysteresis 15 °C Thermal shutdown rising deglitch Temperature increasing 100 ms Thermal shutdown falling deglitch Temperature decreasing 10 ms

Cold temperature rising threshold Charger suspended below this temperature 72.5% 73.5% 74.5% Cold temperature hysteresis 0.2% 0.4% 0.6%

Cool Temperature rising threshold 70.2% 70.7% 71.2%

Charger enabled, cuts back to I temperature

CHARGE

/8 below this

Cool temperature hysteresis 0.2% 0.6% 1.0% Warm temperature rising threshold Charger cuts back to I

/8 above this temperature 47.5% 48% 48.5%

CHARGE

Warm temperature hysteresis 1.0% 1.2% 1.4% Hot temperature rising threshold 36.2% 37% 37.8%

Cut-off temperature rising threshold 33.7% 34.4% 35.1%

Charger suspended above this temperature before initiating charge

Charger suspended above this temperature during initiating charge

Product Folder Link(s): bq24630

bq24630

SLUS894 –JANUARY 2010

ELECTRICAL CHARACTERISTICS (continued)

5.0V ≤ V(VCC) ≤28V, 0°C<TJ<+125°C,typical values are at TA=25°C, with respect to GND unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Deglitch time for Temperature Out of Range Detection

Deglitch time for Temperature in Valid Range Detection

Deglitch time for current reduction to I

/8 due to warm or cool temperature

CHARGE

Deglitch time to charge at I I

/8 when resuming from warm or VTS< V

CHARGE

cool temperatures

CHARGE

from

Charge current due to warm or cool V temperatures VTS< V

CHARGE OVER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)

Charge over-current falling threshold

Charge over-current threshold floor 50 mV

Charge over-current threshold ceiling 180 mV

CHARGE UNDER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)

ISYNSET

Charge under-current falling threshold Switch from SYNCH to NON-SYNCH, V

BATTERY SHORTED COMPARATOR (BATSHORT)

BATSHT

BATSHT_HYS

BATSHT_DEG

BAT Short falling threshold, forced non-synchronous mode

BAT short rising hysteresis 200 mV Deglitch on both edge 1 ms

LOW CHARGE CURRENT COMPARATOR

LC_HYS

LC_DEG

Average low charge current falling Measure on V threshold mode

Low charge current rising hysteresis 1.25 mV Deglitch on both edge 1 ms

VREF REGULATOR

VREF_REG

VREF_LIM

VREF regulator voltage V VREF current limit V

REGN REGULATOR

REGN_REG

REGN_LIM

REGN regulator voltage V REGN current limit V

TTC INPUT

PRECHG

CHARGE

TTC

Precharge safety timer range Fast charge saftey timer range, with +/-

10% accuracy

(1)

Fast charge timer accuracy Timer multiplier 1.4 min/nF

(1)

TTC low threshold 0.4 V TTC comparator high threshold 1.5 V

TTC comparator low threshold 1 V TTC source/sink current 45 50 55 mA

BATTERY SWITCH (BATFET) DRIVER

DS_BAT_OFF

DS_BAT_ON

BATDRV_REG

BATFET turn-off resistance V BATFET turn-on resistance V

BATFET drive voltage 4.2 7 V

VTS> V

VTS< V

VTS> V

Current rising, in non-synchronous mode, mesure on V

Current rising, as percentage of V synchronous mode, V

< VTS< V

COOL

(SRP-SRN)

, or VTS< V

LTF

– V

LTF

, or VTS< V

COOL

- V

COOL

TCO

, V

SRP

LTF_HYS

COOL_HYS

, or V

LTF

< 2 V

, or VTS< V

TCO

or VTS>V

WARM

, or VTS> V

WARM

> 2.2V

SRP

HTF

, or VTS> V

TCO

WARM

< VTS< V

(IREG_CHG)

HTF

- V

WARM_HYS

, or V

, in

HTF

WARM

< I

400 ms

20 ms

25 ms

CHARGE

45.5 mV

160%

Minimum OCP threshold in synchronous mode, measure on V

(SRP-SRN)

, V

SRP

> 2.2V

Maximum OCP threshold in synchronous mode, measure on V

SRP

VCC VREF

VCC REGN

, V

(SRP-SRN)

SRP

> 2.2V

> 2.2V 1 5 9 mV

SRP

falling 2 V

, forced into non-synchronous

(SRP-SRN)

> V

, ( 0 – 35mA load) 3.267 3.3 3.333 V

UVLO

= 0 V, V

VCC

> V

UVLO

1.25 mV

35 mA

> 10 V, CE = HIGH (0 – 40mA load) 5.7 6.0 6.3 V

= 0 V, V

VCC

> V

UVLO

40 mA

Precharge time before fault occurs 1440 1800 2160 sec Tchg = C

0.047 mF ≤ C

TTC

termination

ACN ACN

BATDRV_REG

BATFET is on

× K

TTC

≤ 0.47 mF –10% 10%

TTC

1 10 Hr

below this threshold disables the safety timer and

> 5V 150 Ω > 5V 20 kΩ

= V

ACN

– V

BATDRV

when V

ACN

> 5V and

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SLUS894 –JANUARY 2010

ELECTRICAL CHARACTERISTICS (continued)

5.0V ≤ V(VCC) ≤28V, 0°C<TJ<+125°C,typical values are at TA=25°C, with respect to GND unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AC SWITCH (ACFET) DRIVER

DS_AC_OFF

DS_AC_ON

ACDRV_REG

AC / BAT MOSFET DRIVERS TIMING

BATTERY DETECTION

WAKE

DISCHARGE

FAULT

WAKE

DISCH

PWM HIGH SIDE DRIVER (HIDRV)

DS_HI_ON

DS_HI_OFF

BTST_REFRESH

PWM LOW SIDE DRIVER (LODRV)

DS_LO_ON

DS_LO_OFF

PWM DRIVERS TIMING

PWM OSCILLATOR

RAMP_HEIGHT

INTERNAL SOFT START (8 steps to regulation current ICHG)

CHARGER SECTION POWER-UP SEQUENCING

LOGIC IO PIN CHARACTERISTICS

IN_LO

IN_HI

BIAS_CE

OUT_LO

OUT_HI

(2) Verified by design

ACFET turn-off resistance V ACFET turn-on resistance V

ACFET drive voltage 4.2 7 V

> 5V 30 Ώ

VCC

> 5V 20 kΏ

VCC

ACDRV_REG

ACFET is on

= V

VCC

– V

ACDRV

when V

VCC

> 5 V and

Driver dead time Dead time when switching between AC and BAT 10 ms

Wake timer Max time charge is enabled 500 ms Wake Current R

= 10 mΩ 50 125 200 mA

SENSE

Discharge timer Max time discharge current is applied 1 sec Discharge current 8 mA Fault current after a timeout fault 2 mA Wake threshold ( with-respect-to V

) Voltage on VFB to detect battery absent during Wake 125 mV

REG

Discharge threshold Voltage on VFB to detect battery absent during Discharge 0.35 V

High Side driver (HSD) turn-on resistance V High Side driver turn-off resistance V Bootstrap refresh comparator threshold

voltage

– VPH= 5.5 V 3.3 6 Ω

BTST

– VPH= 5.5 V 1 1.3 Ω

BTST

– VPHwhen low side refresh pulse is requested 4.0 4.2 V

BTST

Low side driver (LSD) turn-on resistance 4.1 7 Ω Low side driver turn-off resistance 1 1.4 Ω

Driver dead time ns

Dead time when switching between LSD and HSD, no 30 load at LSD and HSD

PWM ramp height As percentage of VCC 7 % PWM switching frequency

(2)

255 300 345 kHz

Soft start steps 8 step Soft start step time 1.6 ms

Charge-enable delay after power-up 1.5 s

Delay from when adapter is detected to when the charger is allowed to turn on

CE input low threshold voltage 0.8 V CE input high threshold voltage 2.1 V CE input bias current V = 3.3 V (CE has internal 1MΩ pulldown resistor) 6 mA STAT1, STAT2, PG output low saturation

voltage

Sink current = 5 mA 0.5 V

Leakage current V = 32 V 1.2 µA

Product Folder Link(s): bq24630

VCC

/PG

VREF

REGN

t − Time=4ms/div

5V/div

2V/div

10V/div

2V/div

t − Time=200ms/div

LODRV

IBAT

5V/div

10V/div

2 A/div

LDRV

10V/div

5V/div

2V/div

2 A/div

t − Time=4 s/divμ

t − Time=4ms/div

LODRV

IBAT

5V/div

10V/div

2 A/div

bq24630

SLUS894 –JANUARY 2010

TYPICAL CHARACTERISTICS

Table 1. Table of Graphs

Figure

REF REGN and PG Power Up (CE=1) Figure 2 Charge Enable Figure 3 Current Soft-Start (CE=1) Figure 4 Charge Disable Figure 5 Continuous Conduction Mode Switching Waveforms Figure 6 Cycle-by-Cycle Synchronous to Nonsynchronous Figure 7 100% Duty and Refresh Pulse Figure 8 Transient System Load (DPM) Figure 9 Battery Insertion Figure 10 Battery to Ground Short Protection Figure 11 Battery to ground Short Transition Figure 12 Efficiency vs Output Current Figure 13 Input ACOV Transition Figure 14 Input ACOV Resume Normal Transition Figure 15

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Figure 2. REF REGN and PG Power Up (CE=1) Figure 3. Charge Enable

Figure 4. Current Soft-Start (CE=1) Figure 5. Charge Disable

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5V/div

2 A/div

LODRV

t Time=200ns/div–

20V/div

5V/div

2 A/div

LODRV

HIDRV

t − Time=200ns/div

t − Time=400ns/div

LODRV

0.5 A/div

10V/div

5V/div

t − Time=200 s/divμ

IIN

ISYS

IBAT

2 A/div

20V/div

10V/div

2 A/div

VBAT

LDRV

5V/div

t Time=4ms/div–

10V/div

2 A/div

VBAT

t Time=200ms/div–

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SLUS894 –JANUARY 2010

Figure 6. Continuous Conduction Mode Switching Waveform Figure 7. Cycle-by-Cycle Synchronous to Nonsynchronous

Figure 8. 100% Duty and Refresh Pulse Figure 9. Transient System Load (DPM)

Figure 10. Battery Insertion Figure 11. Battery to GND Short Protection

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20V/div

10V/div

2 A/div

5V/div

VBAT

LDRV

t Time=8 s/div– μ

0 1 2 3

IBAT-OutputCurrent- A

Efficiency-%

12Vin,1cell

24Vin,5cell

12Vin,2cell

24Vin,6cell

20V/div

2V/div

20V/div

/PG

/BATDRV

VCC

/ACDRV

t Time=10ms/div–

20V/div

2V/div

20V/div

/PG

/BATDRV

VCC

/ACDRV

t Time=20ms/div–

bq24630

SLUS894 –JANUARY 2010

Figure 12. Battery to GND Short Transition Figure 13. Efficiency vs Output Current

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Figure 14. Input ACOV Transition Figure 15. Input ACOV Resume Normal Transition

Product Folder Link(s): bq24630

bq24630

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SLUS894 –JANUARY 2010

Pin Functions – 24-Pin QFN

NO. NAME

1 ACN Adapter current sense resistor, negative input. A 0.1-mF ceramic capacitor is placed from ACN to ACP to provide differential-mode

filtering. An optional 0.1-mF ceramic capacitor is placed from ACN pin to GND for common-mode filtering.

2 ACP Adapter current sense resistor, positive input. A 0.1-mF ceramic capacitor is placed from ACN to ACP to provide differential-mode

filtering. A 0.1-mF ceramic capacitor is placed from ACP pin to GND for common-mode filtering.

3 ACDRV AC adapter to system MOSFET driver output. Connect through a 1-kΩ resistor to the gate of the ACFET P-channel power MOSFET

and the reverse conduction blocking P-channel power MOSFET. The internal gate drive is asymmetrical, allowing a quick turn-off and slow turn-on, in addition to the internal break-before-make logic with respect to BATDRV. If needed, an optional capacitor from gate to

source of the ACFET is used to slow down the ON and OFF times. 4 CE Charge-enable active-HIGH logic input. HI enables charge. LO disables charge. It has an internal 1MΩ pull-down resistor. 5 STAT1 Open-drain charge status pin to indicate various charger operation. 6 TS Temperature qualification voltage input for battery pack negative temperature coefficient thermistor. Program the hot and cold

temperature window with a resistor divider from VREF to TS to GND. 7 TTC SafetyTimer and termination control. Connect a capacitor from this node to GND to set the timer. When this input is LOW, the timer

and termination are disabled. When this input is HIGH, the timer is disabled but termination is allowed. 8 PG Open-drain power-good status output. Active LOW when IC has a valid VCC (not in UVLO or ACOV or SLEEP mode). Active HIGH

when IC has an invalid VCC. PGcan be used to drive a LED or communicate with a host processor. 9 STAT2 Open-drain charge status pin to indicate various charger operation.

10 VREF 3.3V regulated voltage output. Place a 1-mF ceramic capacitor from VREF to GND pin close to the IC. This voltage could be used for

programming of voltage and current regulation and for programming the TS threshold.

11 ISET1 Fast Charge current set input. The voltage of ISET1 pin programs the fast charge current regulation set-point. 12 VFB Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider from the battery terminals to this node to

adjust the output battery regulation voltage.

13 SRN Charge current sense resistor, negative input. A 0.1-mF ceramic capacitor is placed from SRN to SRP to provide differential-mode

filtering. An optional 0.1-mF ceramic capacitor is placed from SRN pin to GND for common-mode filtering.

14 SRP Charge current sense resistor, positive input. A 0.1-mF ceramic capacitor is placed from SRN to SRP to provide differential-mode

filtering. A 0.1-mF ceramic capacitor is placed from SRP pin to GND for common-mode filtering.

15 ISET2 Termination current set input. The voltage of ISET2 pin programs termination current trigger point. 16 ACSET Adapter current set input. The voltage of ACSET pin programs the input current regulation set-point during Dynamic Power

Management (DPM)

17 GND Low-current sensitive analog/digital ground. On PCB layout, connect with PowerPad underneath the IC. 18 REGN PWM low side driver positive 6V supply output. Connect a 1-mF ceramic capacitor from REGN to GND pin, close to the IC. Use for

low side driver and high-side driver bootstrap voltage by connecting a small signal Schottky diode from REGN to BTST.

19 LODRV PWM low side driver output. Connect to the gate of the low-side power MOSFET with a short trace. 20 PH PWM high side driver negative supply. Connect to the Phase switching node (junction of the low-side power MOSFET drain, high-side

power MOSFET source, and output inductor). Connect the 0.1-mF bootstrap capacitor from PH to BTST.

21 HIDRV PWM high side driver output. Connect to the gate of the high-side power MOSFET with a short trace. 22 BTST PWM high side driver positive supply. Connect to the Phase switching node (junction of the low-side power MOSFET drain, high-side

power MOSFET source, and output inductor). Connect the 0.1-mF bootstrap capacitor from SW to BTST.

23 BATDRV Battery to system MOSFET driver output. Gate drive for the battery to system load BAT PMOS power FET to isolate the system from

the battery to prevent current flow from the system to the battery, while allowing a low impedance path from battery to system.

Connect this pin through a 1-kΩ resistor to the gate of the input BAT P-channel MOSFET. Connect the source of the FET to the

system load voltage node. Connect the drain of the FET to the battery pack positive terminal. The internal gate drive is asymmetrical

to allow a quick turn-off and slow turn-on, in addition to the internal break-before-make logic with respect to ACDRV. If needed, an

optional capacitor from gate to source of the BATFET is used to slow down the ON and OFF times.

24 VCC IC power positive supply. Connect through a 10-Ω to the common-source (diode-OR) point: source of high-side P-channel MOSFET

and source of reverse-blocking power P-channel MOSFET. Place a 1-mF ceramic capacitor from VCC to GND pin close to the IC.

PowerPAD Exposed pad beneath the IC. Always solder PowerPAD to the board, and have vias on the PowerPAD plane star-connecting to GND

and ground plane for high-current power converter. It also serves as a thermal pad to dissipate the heat.

FUNCTION DESCRIPTION

Product Folder Link(s): bq24630

VCC

ACDRV

BATDRV

BTST

HIDRV

REGN

LODRV

GND

bq24630

ACP

ACN

VFB

SRP

6 VLDO

V(ACP-ACN)

V(SRP-SRN)

COMP

ERROR

AMPLIFIER

1.8V

IBAT_ REG

SRN

VCC

VCC- 6 V

REG

STATE

MACHINE

LOGIC

BATTERY

DETECTION

LOGIC

VCC

4.2V

BTST

REFRESH

SYSTEM

POWER

SELECTOR

LOGIC

145°C

IC Tj

TSHUT

SRN+100 mV

VCC

SLEEP

LEVEL

SHIFTER

ACN

V(SRP-SRN)

CHG_OCP

160% XIBAT_REG

SYNCH

SRP- SRN

ISET1

ISET2

ACSET

IBAT_ REG

ISET1

5mV

20X

BAT

BAT_OVP

108% XVBAT_REG

LTF

HTF

VREF

TCO

SUSPEND

VCC

ACOV

VREF

STAT1

20X

STAT2

3.3V LDO

VCC

VFB

LOWV

RCHRG

0.35V

1.675V

VFB

RCHRG

TERM

ISET2

TERM

TERMINATECHARGE

bq24630

UVLO

VCC

SLEEP

UVLO

VCC- 6 V

ACN- 6 V

VCC- 6 V

REG

ACN

ACN-6 V

ACOV

PWM

CONTROL

LOGIC

PWM

CHARGE

20 mA

DISCHARGE

CHARGE

8 mA

BAT_OVP

DISABLE

TMR/TERM

0.4V

TTC

VOLTAGE

REFERENCE

VREF

ACN- SRN

SRN+200 mV

ACN

Safety Timer

30 minute Precharge

timer

TTC

FAULT

2 mA

FAULT

1 M

TTC

WARM

COOL

WARM

20 mA

1.25mV

100XV(SRP -SRN)

bq24630

SLUS894 –JANUARY 2010

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BLOCK DIAGRAM

Figure 16. Functional Block Diagram of bq24630

Product Folder Link(s): bq24630

VCC > SRN

IndicateSLEEP

SLEEP MODE

Yes

EnableVREFLDO&

ChipBias

Turnon

BATDRVFET

30 msdelay

TurnoffBATFET

Turnon ACFET

Battery

present?

Yes

Initiatebattery

detectalgorithm

Indicatebattery

absent

Conditionsmet

forcharge

IndicateNOT CHARGING,

Suspendtimers

Yes

VFB < VLOWV

Yes

Start 30 minute

prechargetimer

IndicateCharge-

In-Progress

Regulate

prechargecurrent

VFB < VLOWV

Precharge

timerexpired?

Yes

IndicateFAULT

FAULT

EnableI

FAULT

VFB > VRECH

StartFastcharge

timer

IndicateCharge-

In-Progress

Regulate

fastchargecurrent

Fastcharge

TimerExpired?

No Yes

VFB > VRECH

ICHG < ITERM

Yes

IndicateChargeIn

Progress

Turnoffcharge,

EnableI

DISCHG

for1

second

VFB < VRECH No

IndicateDONE

ChargeComplete

Yes

IndicateBATTERY

ABSENT

BatteryRemoved

Yes

POR

See EnablingandDisabling

Charg eSection

Conditionsmet

forcharge?

Yes

Conditionsmet

forcharge?

Yes

IndicateNOT

CHARGING,

Suspendtimers

bq24630

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OPERATIONAL FLOWCHART

SLUS894 –JANUARY 2010

Product Folder Link(s): bq24630

Precharge

Time

FastchargeSafety Time

Precharge

Current

Regulation

Phase

FastchargeCurrent

RegulationPhase

FastchargeVoltage

RegulationPhase

Termination

Charge

Voltage

Charge

Current

RegulationCurrent

RegulationVoltage

RECH

LOWV

I &I

PRECH TERM

BAT

V = 1.8 V 1

é ù

´ +

ê ú ë û

ISET1

CHARGE

I =

20 R´

bq24630

SLUS894 –JANUARY 2010

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DETAILED DESCRIPTION

BATTERY VOLTAGE REGULATION

The bq24630 uses a high accuracy voltage bandgap and regulator for the high accuracy charging voltage. The charge voltage is programmed via a resistor divider from the battery to ground, with the midpoint tied to the VFB pin. The voltage at the VFB pin is regulated to 1.8V, giving Equation 1 for the regulation voltage:

where R2 is connected from VFB to the battery and R1 is connected from VFB to GND

BATTERY CURRENT REGULATION

The ISET1 input sets the maximum fast charging current. Battery charge current is sensed by resistor R connected between SRP and SRN. The full-scale differential voltage between SRP and SRN is 100mV. Thus, for a 10mΩ sense resistor, the maximum charging current is 10A. Equation 2 is for charge current

V across RSRwith default value of 10mΩ. However, resistors of other values can also be used. A larger sense resistor will give a larger sense voltage, a higher regulation accuracy; but, at the expense of higher conduction loss.

Figure 17. Typical Charging Profile

, the input voltage range of ISET1 is between 0 and 2V. The SRP and SRN pins are used to sense voltage

ISET1

(1)

(2)

Product Folder Link(s): bq24630

ACSET

DPM

I =

20 R´

ISET2

TERM

I =

100 R´

CHARGE TTC TTC

t = C K´

bq24630

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SLUS894 –JANUARY 2010

PRECHARGE

On power-up, if the battery voltage is below the V to the battery

(1)

. The precharge feature is intended to revive deeply discharged cells. If the V reached within 30 minutes of initiating precharge, the charger turns off and a FAULT is indicated on the status pins.

threshold, the bq24630 applies 125mA precharge current

LOWV

threshold is not

LOWV

INPUT ADAPTER CURRENT REGULATION

The total input from an AC adapter or other DC sources is a function of the system supply current and the battery charging current. System current normally fluctuates as portions of the systems are powered up or down. Without Dynamic Power Management (DPM), the source must be able to supply the maximum system current and the maximum charger input current simultaneously. By using DPM, the input current regulator reduces the charging current when the input current exceeds the input current limit set by ACSET. The current capability of the AC adaptor can be lowered, reducing system cost.

Similar to setting battery regulation current, adaptor current is sensed by resistor RACconnected between ACP and ACN. Its maximum value is set by ACSET using Equation 3:

(3)

, the input voltage range of ACSET is between 0 and 2V. The ACP and ACN pins are used to sense

ACSET

voltage across RACwith default value of 10mΩ. However, resistors of other values can also be used. A larger the sense resistor will give a larger sense voltage, and a higher regulation accuracy; but, at the expense of higher conduction loss.

CHARGE TERMINATION, RECHARGE, AND SAFETY TIMER

The bq24630 monitors the charging current during the voltage regulation phase. When V is detected while the voltage on the VFB pin is higher than the V than the I

, the input voltage of ISET2 is between 0 and 2V. The minimum termination current is clamped to be

ISET2

threshold, as calculated in Equation 4:

TERM

threshold AND the charge current is less

RECH

around 125mA with default 10mΩ sensing resistor. To avoid early termination during WARM/COOL condition, set I

TERM

≤ I

CHARGE

/10. As a safety backup, the bq24630 also provides a programmable charge timer. The charge

time is programmed by the capacitor connected between the TTC pin and GND, and is given by Equation 5

where C to GND, and K

(range from 0.047µF to 0.47µF to give 1-10hr safety timer) is the capacitor connected from TTC pin

TTC

is the constant multiplier (1.4min/nF).

TTC

A new charge cycle is initiated and safety timer is reset when one of the following conditions occur:

• The battery voltage falls below the recharge threshold.

• A power-on-reset (POR) event occurs.

• CE is toggled. The TTC pin may be taken LOW to disable termination and to disable the safety timer. If TTC is pulled to VREF,

the bq24630 will continue to allow termination but disable the safety timer. TTC taken low will reset the safety timer. When ACOV, VCCLOWV and SLEEP mode resume normal, the safety timer will be reset.

is valid, termination

TTC

(4)

(5)

(1) assuming a 10mΩ sense resistor. 1.25mV will be regulated across SRP-SRN, regardless of the value of the sense resistor.

Product Folder Link(s): bq24630

bq24630

SLUS894 –JANUARY 2010

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POWER UP

The bq24630 uses a SLEEP comparator to determine the source of power on the VCC pin, since VCC can be supplied either from the battery or the adapter. If the VCC voltage is greater than the SRN voltage, bq24630 will enable the ACFET and disable BATFET. If all other conditions are met for charging, bq24630 will then attempt to charge the battery (See Enabling and Disabling Charging). If the SRN voltage is greater than VCC, indicating that the battery is the power source, bq24630 enables the BATFET, and enters a low quiescent current (<15mA) SLEEP mode to minimize current drain from the battery.

If VCC is below the UVLO threshold, the device is disabled, ACFET turns off and BATFET turns on.

ENABLE AND DISABLE CHARGING

The following conditions have to be valid before charge is enabled:

• CE is HIGH

• The device is not in Under-Voltage-Lockout (UVLO) and not in VCCLOWV mode

• The device is not in SLEEP mode

• The VCC voltage is lower than the AC over-voltage threshold (VCC < V

• 30 ms delay is complete after initial power-up

• The REGN LDO and VREF LDO voltages are at the correct levels

• Thermal Shut (TSHUT) is not valid

• TS fault is not detected One of the following conditions will stop on-going charging

• CE is LOW

• Adapter is removed, causing the device to enter UVLO, VCCLOWV, or SLEEP mode

• Adapter is over voltage

• The REGN or VREF LDOs are overloaded

• TSHUT IC temperature threshold is reached (145°C on rising-edge with 15°C hysteresis)

• TS voltage goes out of range indicating the battery temperature is too hot or too cold

• TTC saftey timer times out

ACOV

)

SYSTEM POWER SELECTOR

The bq24630 automatically switches adapter or battery power to the system load. The battery is connected to the system by default during power up or during SLEEP mode. The battery is disconnected from the system and then the adapter is connected to the system 30ms after exiting SLEEP. An automatic break-before-make logic prevents shoot-through currents when the selectors switch.

The ACDRV is used to drive a pair of back-to-back p-channel power MOSFETs between adapter and ACP with sources connected together and to VCC. The FET connected to adapter prevents reverse discharge from the battery to the adapter when turned off. The p-channel FET with the drain connected to the adapter input provides reverse battery discharge protection when off; and also minimizes system power dissipation, with its low-R compared to a Schottky diode. The other p-channel FET connected to ACP separates battery from adapter, and provides a limited dI/dt when connecting the adapter to the system by controlling the FET turn-on time. The BATDRV controls a p-channel power MOSFET placed between BAT and system.

When adapter is not detected, the ACDRV is pulled to VCC to keep ACFET off, disconnecting the adapter from system. BATDRV stays at ACN-6V to connect battery to system.

Approximately 30ms after the device comes out of SLEEP mode, the system begins to switch from battery to adapter. The break-before-make logic keeps both ACFET and BATFET off for 10µs before ACFET turns on. This prevents shoot-through current or any large discharging current from going into the battery. The /BATDRV is pulled up to ACN and the ACDRV pin is set to VCC-6V by an internal regulator to turn on p-channel ACFET, connecting the adapter to the system.

When the adapter is removed, the system waits until VCC drops back to within 200mV above SRN to switch from adapter back to battery. The break-before-make logic still keeps 10ms dead time. The ACDRV is pulled up to VCC and the BATDRV pin is set to ACN-6V by an internal regulator to turn on p-channel BATFET, connecting the battery to the system.

DSON

Product Folder Link(s): bq24630

o o

f =

2 L Cp

bq24630

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SLUS894 –JANUARY 2010

Asymmetrical gate drive for the ACDRV and BATDRVdrivers provides fast turn-off and slow turn-on of the ACFET and BATFET to help the break-before-make logic and to allow a soft-start at turn-on of either FET. The soft-start time can be further increased, by putting a capacitor from gate to source of the p-channel power MOSFETs.

AUTOMATIC INTERNAL SOFT-START CHARGER CURRENT

The charger automatically soft-starts the charger regulation current every time the charger goes into fast-charge to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists of stepping-up the charge regulation current into 8 evenly divided steps up to the programmed charge current. Each step lasts around 1.6ms, for a typical rise time of 12.8ms. No external components are needed for this function.

CONVERTER OPERATION

The synchronous buck PWM converter uses a fixed frequency voltage mode with feed-forward control scheme. A type III compensation network allows using ceramic capacitors at the output of the converter. The compensation input stage is connected internally between the feedback output (FBO) and the error amplifier input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output (EAO). The LC output filter is selected to give a resonant frequency of 10 kHz – 15 kHz for bq24630, where resonant frequency, fo, is given by Equation 6:

(6)

An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the converter. The ramp height is 7% of the input adapter voltage making it always directly proportional to the input adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and simplifies the loop compensation. The ramp is offset by 300mV in order to allow zero percent duty-cycle when the EAO signal is below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order to get a 100% duty-cycle PWM request. Internal gate drive logic allows achieving 99.95% duty-cycle while ensuring the N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below

4.2V for more than 3 cycles, then the high-side n-channel power MOSFET is turned off and the low-side n-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low again due to leakage current discharging the BTST capacitor below the 4.2 V, and the reset pulse is reissued.

The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible noise region. Also see Application Information for how to select inductor, capacitor and MOSFET.

Synchronous and Non-Synchronous Operation

The charger operates in synchronous mode when the SRP-SRN voltage is above 5mV (0.5A inductor current for a 10mΩ sense resistor). During synchronous mode, the internal gate drive logic ensures there is break-before-make complimentary switching to prevent shoot-through currents. During the 30ns dead time where both FETs are off, the body-diode of the low-side power MOSFET conducts the inductor current. Having the low-side FET turn-on keeps the power dissipation low, and allows safely charging at high currents. During synchronous mode the inductor current is always flowing and converter operates in continuous conduction mode (CCM), creating a fixed two-pole system.

The charger operates in non-synchronous mode when the SRP-SRN voltage is below 5mV (0.5A inductor current for a 10mΩ sense resistor). The charger is forced into non-synchronous mode when battery voltage is lower than 2V or when the average SRP-SRN voltage is lower than 1.25mV.

During non-synchronous operation, the body-diode of lower-side MOSFET can conduct the positive inductor current after the high-side n-channel power MOSFET turns off. When the load current decreases and the inductor current drops to zero, the body diode will be naturally turned off and the inductor current will become discontinuous. This mode is called Discontinuous Conduction Mode (DCM). During DCM, the low-side n-channel power MOSFET will turn-on for around 80ns when the bootstrap capacitor voltage drops below 4.2V, then the low-side power MOSFET will turn-off and stay off until the beginning of the next cycle, where the high-side power MOSFET is turned on again. The 80ns low-side MOSFET on-time is required to ensure the bootstrap capacitor is

Product Folder Link(s): bq24630

bq24630

SLUS894 –JANUARY 2010

always recharged and able to keep the high-side power MOSFET on during the next cycle. This is important for battery chargers, where unlike regular dc-dc converters, there is a battery load that maintains a voltage and can both source and sink current. The 80ns low-side pulse pulls the PH node (connection between high and low-side MOSFET) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value. After the 80ns, the low-side MOSFET is kept off to prevent negative inductor current from occurring.

At very low currents during non-synchronous operation, there may be a small amount of negative inductor current during the 80ns recharge pulse. The charge should be low enough to be absorbed by the input capacitance. Whenever the converter goes into zero percent duty-cycle, the high-side MOSFET does not turn on, and the low-side MOSFET does not turn on (only 80ns recharge pulse) either, and there is almost no discharge from the battery.

During the DCM mode the loop response automatically changes and has a single pole system at which the pole is proportional to the load current, because the converter does not sink current, and only the load provides a current sink. This means at very low currents the loop response is slower, as there is less sinking current available to discharge the output voltage.

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Cycle-by-Cycle Charge Under Current Protection

If the SRP-SRN voltage decreases below 5mV (The charger is also forced into non-synchronous mode when the average SRP-SRN voltage is lower than 1.25mV), the low side FET will be turned off for the remainder of the switching cycle to prevent negative inductor current. During DCM, the low-side FET will only turn on for at around 80ns when the bootstrap capacitor voltage drops below 4.2V to provide refresh charge for the bootstrap capacitor. This is important to prevent negative inductor current from causing a boost effect in which the input voltage increases as power is transferred from the battery to the input capacitors and lead to an over-voltage stress on the VCC node and potentially cause damage to the system.

INPUT OVER VOLTAGE PROTECTION (ACOV)

ACOV provides protection to prevent system damage due to high input voltage. Once the adapter voltage reaches the ACOV threshold, charge is disabled and the battery is switched to system instead of adapter.

INPUT UNDER VOLTAGE LOCK OUT (UVLO)

The system must have a minimum VCC voltage to allow proper operation. This VCC voltage could come from either input adapter or battery, since a conduction path exists from the battery to VCC through the high side NMOS body diode. When VCC is below the UVLO threshold, all circuits on the IC are disabled, and the gate drive bias to ACFET and BATFET are disabled.

BATTERY OVER-VOLTAGE PROTECTION

The converter will not allow the high-side FET to turn-on until the BAT voltage goes below 105% of the regulation voltage. This allows one-cycle response to an over-voltage condition – such as occurs when the load is removed or the battery is disconnected. An 8mA current sink from SRP to GND is on only during charge and allows discharging the stored output inductor energy that is transferred to the output capacitors. BATOVP will also suspend the safety timer.

CYCLE-BY-CYCLE CHARGE OVER-CURRENT PROTECTION

The charger has a secondary cycle-to-cycle over-current protection. It monitors the charge current, and prevents the current from exceeding 160% of the programmed charge current. The high-side gate drive turns off when the over-current is detected, and automatically resumes when the current falls below the over-current threshold.

THERMAL SHUTDOWN PROTECTION

The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off and self-protects whenever the junction temperature exceeds the TSHUT threshold of 145°C. The charger stays off until the junction temperature falls below 130°C. Then the charger will soft-start again if all other enable charge conditions are valid. Thermal shutdown will also suspend the safety timer.

Product Folder Link(s): bq24630

CHARGESUSPENDED CHARGESUSPENDED

TEMPERATURERANGE TO

INITIATECHARGE

TEMPERATURERANGE

DURING A CHARGECYCLE

HTF

GND

TCO

GND

VREF

CHARGESUSPENDED CHARGESUSPENDED

LTF

CHARGEatI /8

CHARGE

CHARGEat I /8

CHARGE

WARM

CHARGEat I /8

CHARGE

CHARGEat I /8

CHARGE

COOL

CHARGEat I

CHARGE

CHARGEat I

CHARGE

COOL

WARM

LTF_HYS

COOL_HYS

WARM_HYS

bq24630

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SLUS894 –JANUARY 2010

TEMPERATURE QUALIFICATION

The controller continuously monitors battery temperature by measuring the voltage between the TS pin and GND. A negative temperature coefficient thermistor (NTC) and an external voltage divider typically develop this voltage. The controller compares this voltage against its internal thresholds to determine if charging is allowed. To initiate a charge cycle, the battery temperature must be within the V(LTF) to V(HTF) thresholds. If battery temperature is outside of this range, the controller suspends charge and the safety timer and waits until the battery temperature is within the V(LTF) to V(HTF) range. During the charge cycle the battery temperature must be within the V(LTF) to V(TCO) thresholds. If battery temperature is outside of this range, the controller suspends charge and safety timer and waits until the battery temperature is within the V(LTF) to V(HTF) range. If the battery temperature is between the V(LTF) and the V(COOL) thresholds or between the V(HTF) and V(WARM) thresholds, charge is automatically reduced to I condition, set I

TERM

≤ I

CHARGE

/10. The controller suspends charge by turning off the PWM charge FETs. Figure 18

and Figure 19 summarizes the operation.

/8. To avoid early termination during COOL/WARM

CHARGE

Figure 18. TS, Thermistor Sense Thresholds

Product Folder Link(s): bq24630

Temperature

Programmed

ChargeCurrent

1/8xProgrammed

ChargeCurrent

Charge

Current

Charge

Suspended

CHARGEG

Charge

Chargeat I

CHG

I /8

CHARGE

Charge

Suspended

LTF

COOL

WARM

HTF

TCO

(I )

CHARGE

(I /8)

CHARGE

VREF COOL WA RM

COOL W AR M

VREF VREF

WA RM COOL

WA RM COO L

1 1

V RTH RTH

V V

RT2 =

V V

RTH 1 RTH 1

V V

æ ö

´ ´ ´ -

ç ÷ è ø

æ ö

´ - - ´ -

ç ÷

ç ÷ è ø

è ø

VREF

COOL

RT1 =

1 1

RT2 RTH

VREF

RT2

RT1

RTH

103 AT

bq24630

SLUS894 –JANUARY 2010

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Assuming a 103AT NTC thermistor on the battery pack as shown in the Typical System Schematic, the value RT1 and RT2 can be determined by using Equation 7 and Equation 8:

Figure 19. Typical Charge Current vs Temperature Profile

(7)

(8)

Figure 20. TS Resistor Network

Product Folder Link(s): bq24630

o o

f =

2 L Cp

bq24630

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For example, 103AT NTC thermistor is used to monitor the battery pack temperature. Select T

SLUS894 –JANUARY 2010

= 0ºC, T

COOL

WARM

= 60ºC. From the calculation and select standard 5% resistor value. We can get RT1= 2.2kΩ, RT2= 6.8kΩ, and T

is -17ºC (target -20ºC); T

COLD

is 77ºC (target 75ºC), and T

HOT

CUT-OFF

is 86ºC (target 80ºC). A small RC filter is

suggested to protect TS pin from system-level ESD.

Timer Fault Recovery

The bq24630 provides a recovery method to deal with timer fault conditions. The following summarizes this method:

Condition 1: The battery voltage is above the recharge threshold and a timeout fault occurs. Recovery Method: The timer fault will clear when the battery voltage falls below the recharge threshold, and

battery detection will begin. Taking CE low or a POR condition will also clear the fault.

Condition 2: The battery voltage is below the RECHARGE threshold and a timeout fault occurs. Recovery Method: Under this scenario, the bq24630 applies the IFAULT current to the battery. This small

current is used to detect a battery removal condition and remains on as long as the battery voltage stays below the recharge threshold. If the battery voltage goes above the recharge threshold, the bq24630 disables the fault current and executes the recovery method described in Condition 1. Taking CE low or a POR condition will also clear the fault.

PG Output

The open drain PG(power good) output indicates whether the VCC voltage is valid or not. The open drain FET turns on whenever bq24630 has a valid VCC input ( not in UVLO or ACOV or SLEEP mode). The PG pin can be used to drive an LED or communicate to the host processor.

CE (Charge Enable)

The CE digital input is used to disable or enable the charge process. A high-level signal on this pin enables charge, provided all the other conditions for charge are met (see Enabling and Disabling Charge). A high to low transition on this pin also resets all timers and fault conditions. There is an internal 1 MΩ pulldown resistor on the CE pin, so if CE is floated the charge will not turn on.

INDUCTOR, CAPACITOR, AND SENSE RESISTOR SELECTION GUIDELINES

The bq24630 provides internal loop compensation. With this scheme, best stability occurs when the LC resonant frequency, fo, is approximately 10kHz – 15kHz per Equation 9:

(9)

Table 2 provides a summary of typical LC components for various charge currents

Table 2. Typical Inductor, Capacitor, and Sense Resistor Values as a Function of Charge Current

CHARGE CURRENT 2A 4A 6A 8A 10A

Output Inductor Lo 8.2 mH 8.2 mH 5.6 mH 4.7 mH 4.7 mH Output Capacitor Co 20 mF 20 mF 30 mF 40 mF 40 mF Sense Resistor 10 mΩ 10 mΩ 10 mΩ 10 mΩ 10 mΩ

CHARGE STATUS OUTPUTS

The open-drain STAT1 and STAT2 outputs indicate various charger operations as shown in Table 3. These status pins can be used to drive LEDs or communicate with the host processor. Note that OFF indicates that the open-drain transistor is turned off.

Product Folder Link(s): bq24630

PORorRECHARGE

Enable 125mA Charge,

Start 0.5stimer

VFB > V

RECH

BatteryPresent,

BeginCharge

0.5stimer expired

Yes

Disable 125mA

Charge

Apply 8 mA discharge current, start 1stimer

VFB < V

LOWV

BatteryPresent,

BeginCharge

1stimer

expired

Yes

Disable 8 mA

dischargecurrent

Thebatterydetectionroutinerunson powerup, orifVFBfallsbelowVRECH duetoremovingabatteryor dischargingabattery

Battery Absent

bq24630

SLUS894 –JANUARY 2010

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Table 3. STAT Pin Definition for bq24630

CHARGE STATE STAT1 STAT2

Charge in progress ON OFF Charge complete OFF ON Charge suspend, timer fault, over-voltage, sleep mode, battery absent OFF OFF

BATTERY DETECTION

For applications with removable battery packs, bq24630 provides a battery absent detection scheme to reliably detect insertion or removal of battery packs.

Figure 21. Battery Detection Flowchart

Product Folder Link(s): bq24630

Battery

Inserted

BatterynotDetected

BatteryDetected

LOWV_DEGtRECH_DEG

WAKE

REG

RECH

LOWV

(V )

WAKE

(V )

DISH

é ù

ê ú ë û

DISCH DI SCH

MAX

I t

C =

1.42 5 1+ R

é ù

ê ú ë û

MAX

8mA 1sec

C = = 930 F

500k

1.425 1+

100k

bq24630

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SLUS894 –JANUARY 2010

Once the device has powered up, an 8mA discharge current will be applied to the SRN terminal. If the battery voltage falls below the LOWV threshold within 1 second, the discharge source is turned off, and the charger is turned on at low charge current (125mA). If the battery voltage gets up above the recharge threshold within 500ms, there is no battery present and the cycle restarts. If either the 500ms or 1 second timer time out before the respective thresholds are hit, a battery is detected and a charge cycle is initiated.

Figure 22. Battery Detect Timing Diagram

Care must be taken that the total output capacitance at the battery node is not so large that the discharge current source cannot pull the voltage below the LOWV threshold during the 1 second discharge time. The maximum output capacitance can be calculated as seen in Equation 10:

(10)

Where C

is the maximum output capacitance, I

MAX

is the discharge current, t

DISCH

is the discharge time, and

DISCH

R2and R1are the voltage feedback resistors from the battery to the VFB pin. The 1.425 factor is the difference between the RECHARGE and the LOWV thresholds at the VFB pin.

EXAMPLE

For a 3-cell LiFePO4charger, with R2 = 500k, R1 = 100k (giving 10.8V for voltage regulation), I t

= 1 second,

DISCH

= 8mA,

(11)

Based on these calculations, no more than 930 mF should be allowed on the battery node for proper operation of the battery detection circuit.

Product Folder Link(s): bq24630

bq24630

SLUS894 –JANUARY 2010

Component List for Typical System Circuit of Figure 1

PART DESIGNATOR QTY DESCRIPTION

Q1, Q2, Q3 3 P-channel MOSFET, –30 V,–35 A, PowerPAK 1212-8, Vishay-Siliconix, Si7617DN Q4, Q5 2 N-channel MOSFET, 30 V, 12 A, PowerPAK 1212-8, Vishay-Siliconix, Sis412DN D1 1 Diode, Dual Schottky, 30 V, 200 mA, SOT23, Fairchild, BAT54C D2, D3, D4 3 LED Diode, Green, 2.1V, 20mA, LTST-C190GKT RAC, R

L1 1 Inductor, 6.8 µH, 5.5A, Vishay-Dale IHLP2525CZ C2, C10 2 Capacitor, Ceramic, 0.1 µF, 50V, 10%, X7R C7 1 Capacitor, Ceramic, 1 µF, 50V, 10%, X7R C8, C9, C12, C13 4 Capacitor, Ceramic, 10 µF, 35 V, 20%, X7R C4, C5 2 Capacitor, Ceramic, 1 µF, 25 V, 10%, X7R C1, C3, C6, C11 4 Capacitor, Ceramic, 0.1 µF, 16 V, 10%, X7R C14, C15 (Optional) 2 Capacitor, Ceramic, 0.1 µF, 50 V, 10%, X7R C16 1 Capacitor, Ceramic, 2.2 µF, 35V, 10%, X7R C

TTC

R1, R3, R5, R7 4 Resistor, Chip, 100 kΩ, 1/16W, 0.5% R2 1 Resistor, Chip, 500 kΩ, 1/16W, 0.5% R4 1 Resistor, Chip, 32.4 kΩ, 1/16W, 0.5% R6 1 Resistor, Chip, 10 kΩ, 1/16W, 0.5% R8 1 Resistor, Chip, 22.1 kΩ, 1/16W, 0.5% R9 1 Resistor, Chip, 2.2 kΩ, 1/16W, 5% R10 1 Resistor, Chip, 6.8 kΩ, 1/16W, 5% R11, R12, R13 3 Resistor, Chip, 10 kΩ, 1/16W, 5% R14, R15 (optional) 2 Resistor, Chip, 100 kΩ, 1/16W, 5% R16 1 Resistor, Chip, 100 Ω, 1/16W, 5% R17 1 Resistor, Chip, 10 Ω, 1/4W, 5% R18, R19 2 Resistor, Chip, 1 kΩ, 1/16W, 5% R20 1 Resistor, Chip, 2 Ω, 1W, 5%

2 Sense Resistor, 10 mΩ, 2010, Vishay-Dale, WSL2010R0100F

1 Capacitor, Ceramic, 22 pF, 25V, 10%, X7R 1 Capacitor, Ceramic, 0.11 µF, 25V, 5%, X7R

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Product Folder Link(s): bq24630

SAT CHG RIPPLE

I I + (1/2) I³

RIPPLE

V D (1 D)

I =

f L

´ ´ -

CIN CHG

I = I D (1 D)´ ´ -

RIPPLE

COUT RIPPLE

I = 0.29 I

2 3

» ´

OUT OUT

V V

V 1

8LCf

æ ö

D = -

ç ÷ è ø

bq24630

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SLUS894 –JANUARY 2010

APPLICATION INFORMATION

Inductor Selection

The bq24630 has 300kHz switching frequency to allow the use of small inductor and capacitor values. Inductor saturation current should be higher than the charging current (I

CHARGE

The inductor ripple current depends on input voltage (VIN), duty cycle (D=V

) plus half the ripple current (I

OUT/VIN

), switching frequency (fs) and

RIPPLE

(12)

inductance (L):

(13)

The maximum inductor ripple current happens with D = 0.5. For example, the battery charging voltage range is from 2.8V to 14.4V for 4-cell battery pack. For 20V adapter voltage, 10V battery voltage gives the maximum inductor ripple current.

Usually inductor ripple is designed in the range of (20–40%) maximum charging current as a trade-off between inductor size and efficiency for a practical design.

The bq24630 has cycle-by-cycle charge under current protection (UCP) by monitoring charging current sensing resistor to prevent negative inductor current. The Typical UCP threshold is 5mV falling edge corresponding to

0.5A falling edge for a 10mΩ charging current sensing resistor.

Input Capacitor

Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current I and can be estimated by the following equation:

occurs where the duty cycle is closest to 50%

CIN

(14)

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage rating of the capacitor must be higher than normal input voltage level. 25V rating or higher capacitor is preferred for 20V input voltage. 20µF capacitance is suggested for typical of 3-4A charging current.

Output Capacitor

Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The output capacitor RMS current I

COUT

is given:

(15)

The output capacitor voltage ripple can be calculated as follows:

(16)

At certain input/output voltage and switching frequenccy, the voltage ripple can be reduced by increasing the output filter LC.

The bq24630 has internal loop compensator. To get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed between 10 kHz and 15 kHz. The preferred ceramic capacitor is 25V, X7R or X5R for 4-cell application.

Power MOSFETs Selection

Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are internally integrated into the IC with 6V of gate drive voltage. 30V or higher voltage rating MOSFETs are preferred for 20V input voltage and 40V MOSFETs are prefered for 20-28V input voltage.

Product Folder Link(s): bq24630

top DS(on) G D bottom D S(on ) G

FOM = R Q FOM = R Q´ ´

( )

top CHG DS(on) IN CHG on off S

P = D I R + V I t + t f

´ ´ ´ ´ ´ ´

SW SW

on off

Q Q

t = , t =

I I

SW GD GS

Q = Q + Q2´

REG N plt plt

on off

V V V

I = , I =

R R

bottom C HG D S(on)

P = (1 D) I R- ´ ´

ICLoss_driver IN g_total s

P V Q f= × ×

VREF IN VREF VREF

ICLOSS ICLOSS _ driver VREF Quiescent

P (V V ) I

P P P P

= - ×

= + +

bq24630

SLUS894 –JANUARY 2010

www.ti.com

Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction loss and switching loss. For top side MOSFET, FOM is defined as the product of a MOSFET's on-resistance, R MOSFET's on-resistance, R

The lower the FOM value, the lower the total power loss. Usually lower R

, and the gate-to-drain charge, QGD. For bottom side MOSFET, FOM is defined as the product of the

DS(ON)

, and the total gate charge, QG.

DS(ON)

has higher cost with the same

DS(ON)

(17)

package size. The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle

(D=V

OUT/VIN

frequency (F), turn on time (ton) and turn off time (t

The first item represents the conduction loss. Usually MOSFET R

), charging current (I

CHARGE

), MOSFET's on-resistance R

toff

DS(ON)

), input voltage (VIN), switching

DS(ON)

(18)

increases by 50% with 100ºC junction temperature rise. The second term represents the switching loss. The MOSFET turn-on and turn off times are given by:

(19)

where Qswis the switching charge, Ionis the turn-on gate driving current and Ioff is the turn-off gate driving current. If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge (QGD) and gate-to-source charge (QGS):

(20)

Gate driving current total can be estimated by REGN voltage (V turn-on gate resistance (Ron) and turn-off gate resistance R

) of the gate driver:

off

), MOSFET plateau voltage (V

REGN

), total

plt

(21)

The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in synchronous continuous conduction mode:

(22)

As a result all the freewheeling current goes through the body-diode of the bottom-side MOSFET. The maximum charging current in non-synchronous mode can be up to 0.9A (0.5A typ) for a 10mΩ charging current sensing resistor considering IC tolerance. Choose the bottom-side MOSFET with either an internal Schottky or body diode capable of carrying the maximum non-synchronous mode charging current.

MOSFET gate driver power loss contributes to the domainant losses on controller IC, when the buck converter is switching. Choosing the MOSFET with a small Q

Where Q

is the total gate charge for both upper and lower MOSFET at 6V V

g_total

will reduce the IC power loss to avoid thermal shut down.

g_total

REGN.

(23)

The VREF load current is another component on VCC input current (Do not overload VREF) where total IC loss can be described by following equations:

Product Folder Link(s): bq24630

(24)

2 W

2.2 mF

0.1-1 mF

4.7 -30W

Adapter connector

VCCpin

(2010)

(1206)

bq24630

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SLUS894 –JANUARY 2010

Input Filter Design

During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a second order system. The voltage spike at VCC pin maybe beyond IC maximum voltage rating and damage IC. The input filter must be carefully designed and tested to prevent over voltage event on VCC pin. ACP/ACN pin needs to be placed after the input ACFETs in order to avoid the over voltage stress and high dv/dt during hot-plug-in.

There are several methods to damping or limit the over voltage spike during adapter hot plug-in. An electrolytic capacitor with high ESR as an input capacitor can damp the over voltage spike well below the IC maximum pin voltage rating. A high current capability TVS Zener diode can also limit the over voltage level to an IC safe level. However these two solutions may not have low cost or small size.

A cost effective and small size solution is shown in Figure 23. The R1 and C1 are composed of a damping RC network to damp the hot plug-in oscillation. As a result the over voltage spike is limited to a safe level. D1 is used for reverse voltage protection for VCC pin ( it can be the body diode of input ACFET). C2 is VCC pin decoupling capacitor and it should be place to VCC pin as close as possible. The R2 and C2 form a damping RC network to further protect the IC from high dv/dt and high voltage spike. C2 value should be less than C1 value so R1 can dominant the equivalent ESR value to get enough damping effetc for hot plug-in. R1 and R2 package must be sized enough to handle static current and inrush current power loss according to resistor manufacturer’s datasheet. The filter components value always need to be verified with real application and minor adjustments may need to fit in the real application circuit.

Figure 23. Input Filter

PCB Layout

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop (see Figure 24) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB according to this specific order is essential.

1. Place input capacitor as close as possible to switching MOSFET’s supply and ground connections and use shortest copper trace connection. These parts should be placed on the same layer of PCB instead of on different layers and using vias to make this connection.

2. The IC should be placed close to the switching MOSFET’s gate terminals and keep the gate drive signal traces short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of switching MOSFETs.

3. Place inductor input terminal to switching MOSFET’s output terminal as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane.

4. The charging current sensing resistor should be placed right next to the inductor output. Route the sense leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop area) and do not route the sense leads through a high-current path (see Figure 25 for Kelvin connection for best current accuracy). Place decoupling capacitor on these traces next to the IC.

5. Place output capacitor next to the sensing resistor output and ground.

6. Output capacitor ground connections need to be tied to the same copper that connects to the input capacitor ground before connecting to system ground.

7. Route analog ground separately from power ground and use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC use analog ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling. Connect analog ground to GND. Connect analog ground and power ground together using PowerPAD as the single ground connection point. Or using a 0Ω resistor to

Product Folder Link(s): bq24630

High

Frequency

Current

Path

PGND

BAT

CurrentDirection

ToSRP -SRNpinor ACP - ACNpin

SNS

CurrentSensingDirection

bq24630

SLUS894 –JANUARY 2010

www.ti.com

tie analog ground to power ground (PowerPAD should tie to analog ground in this case). A star-connection under PowerPAD is highly recommended.

8. It is critical that the exposed PowerPAD on the backside of the IC package be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers.

9. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.

10. All via size and number should be enough for a given current path.

Figure 24. High Frequency Current Path

Figure 25. Sensing Resistor PCB Layout

Refer to the EVM design (SLUU396) for the recommended component placement with trace and via locations. For the QFN information, refer to SCBA017 and SLUA271.

Product Folder Link(s): bq24630

PACKAGE OPTION ADDENDUM

www.ti.com 1-Feb-2010

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

BQ24630RGER ACTIVE VQFN RGE 24 3000 Green (RoHS &

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-2-260C-1 YEAR

(3)

no Sb/Br)

BQ24630RGET ACTIVE VQFN RGE 24 250 Green (RoHS &

CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Jul-2010

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

BQ24630RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 BQ24630RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 20-Jul-2010

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

BQ24630RGER VQFN RGE 24 3000 346.0 346.0 29.0 BQ24630RGET VQFN RGE 24 250 190.5 212.7 31.8

Pack Materials-Page 2

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TEXAS INSTRUMENTS bq24630 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

• 5V–28V VCC Input Operating Range, Support APPLICATIONS 1-7 Battery Cells

DESCRIPTION

DESCRIPTION (CONTINUED)

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

TYPICAL CHARACTERISTICS

BLOCK DIAGRAM

OPERATIONAL FLOWCHART

DETAILED DESCRIPTION

BATTERY VOLTAGE REGULATION

BATTERY CURRENT REGULATION

PRECHARGE

INPUT ADAPTER CURRENT REGULATION

CHARGE TERMINATION, RECHARGE, AND SAFETY TIMER

POWER UP

ENABLE AND DISABLE CHARGING

SYSTEM POWER SELECTOR

AUTOMATIC INTERNAL SOFT-START CHARGER CURRENT

CONVERTER OPERATION

Synchronous and Non-Synchronous Operation

Cycle-by-Cycle Charge Under Current Protection

INPUT OVER VOLTAGE PROTECTION (ACOV)

INPUT UNDER VOLTAGE LOCK OUT (UVLO)

BATTERY OVER-VOLTAGE PROTECTION

CYCLE-BY-CYCLE CHARGE OVER-CURRENT PROTECTION

THERMAL SHUTDOWN PROTECTION

TEMPERATURE QUALIFICATION

Timer Fault Recovery

PG Output

CE (Charge Enable)

INDUCTOR, CAPACITOR, AND SENSE RESISTOR SELECTION GUIDELINES

CHARGE STATUS OUTPUTS

BATTERY DETECTION

Component List for Typical System Circuit of Figure 1

APPLICATION INFORMATION

Inductor Selection

Input Capacitor

Output Capacitor

Power MOSFETs Selection

Input Filter Design

PCB Layout