Texas Instruments bq24133 Schematics

bq24133

www.ti.com

SLUSAF7B –DECEMBER 2010– REVISED MAY 2011

1.6-MHz Synchronous Switch-Mode Li-Ion and Li-Polymer Stand-Alone Battery Charger
with Integrated MOSFETs and Power Path Selector

Check for Samples: bq24133

1

FEATURES

• 1.6MHz Synchronous Switch-Mode Charger • Tablet PC
with 2.5A Integrated N-MOSFETs

• Up to 92% Efficiency

• 30V Input Rating with Adjustable Over-Voltage

Protection

– 4.5V to 17V Input Operating Voltage

• Battery Charge Voltage
– 1, 2, or 3-Cell with 4.2V/Cell

• High Integration
– Automatic Power Path Selector Between

Adapter and Battery

– Dynamic Power Management
– Integrated 20-V Switching MOSFETs
– Integrated Bootstrap Diode
– Internal Loop Compensation
– Internal Digital Soft Start

• Safety
– Thermal Regulation Loop Throttles Back

Current to Limit Tj= 120°C
– Thermal Shutdown
– Battery Thermistor Sense Hot/Cold Charge

Suspend & Battery Detect
– Input Over-Voltage Protection with

Programmable Threshold

– Cycle-by-Cycle Current Limit

• Accuracy
– ±0.5% Charge Voltage Regulation
– ±5% Charge Current Regulation
– ±6% Input Current Regulation voltage falls below the battery voltage.

• Less than 15μA Battery Current with Adapter

Removed

• Less than 1.5mA Input Current with Adapter
Present and Charge Disabled

• Small QFN Package
– 3.5mm × 5.5mm QFN-24 Pin

APPLICATIONS

• Netbook and Ultra-Mobile Computers

• Portable Data Capture Terminals

• Portable Printers

• Medical Diagnostics Equipment

• Battery Bay Chargers

• Battery Back-Up Systems

DESCRIPTION

The bq24133 is highly integrated stand-alone Li-ion
and Li-polymer switch-mode battery charger with two
integrated N-channel power MOSFETs. It offers a
constant-frequency synchronous PWM controller with
high accuracy regulation of input current, charge
current, and voltage. It closely monitors the battery
pack temperature to allow charge only in a preset
temperature window. It also provides battery
detection, pre-conditioning, charge termination, and
charge status monitoring. The thermal regulation loop
reduces charge current to maintain the junction
temperature of 120°C during operation.

The bq24133 charges a one, two, or three cell Li-Ion
battery in three phases: precondictioning, constant
current, and constant voltage.

Charge is terminated when the current reaches 10%
of the fast charge rate. A programmable charge timer
offers a safety back up. The bq24133 automatically
restarts the charge cycle if the battery voltage falls
below an internal threshold, and enters a
low-quiescent current sleep mode when the input

The bq24133 features Dynamic Power Management
(DPM) to reduce the charge current when the input
power limit is reached to avoid over-loading the
adapter. A highly-accurate current-sense amplifier
enables precise measurement of input current from
adapter to monitor overall system power.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2010–2011, Texas Instruments Incorporated

PVCC
PVCC

AVCC

ACN
ACP

CMSRC

ACDRV

STAT

TS

TTC

PGND
PGND
BTST
REGN
BATDRV
OVPSET
ACSET
SRP
SRN
CELL

1

SW

SW

VREF

ISET

24

AGND

2

3

4

5

6

7

8

9

10

11

23

22

21

20

19

18

17

16

15

14

12 13

bq24133

SLUSAF7B –DECEMBER 2010– REVISED MAY 2011

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)

The bq24133 provides power path selector gate driver ACDRV/CMSRC on input NMOS pair ACFET (Q1) and
RBFET (Q2), and BATDRV on a battery PMOS device (Q3). When the qualified adapter is present, the system is
directly connected to the adapter. Otherwise, the system is connected to the battery. In addition, the power path
prevents battery from boosting back to the input.

The bq24170/172 charges the battery from a DC source as high as 17V, including a car battery. The input
over-voltage limit is adjustable through the OVPSET pin. The AVCC, ACP, and ACN pins have a 30V rating.
When a high voltage DC source is inserted, Q1/Q2 remain off to avoid high voltage damage to the system.

For 1 cell applications, if the battery is not removable, the system can be directly connected to the battery to
simplify the power path design and lower the cost. With this configuration, the battery can automatically
supplement the system load if the adapter is overloaded.

The bq24133 is available in a 24-pin, 3.5mmx5.5 mm thin QFN package.

RGY PACKAGE

(TOP VIEW)

PIN FUNCTIONS

PIN

NO. NAME

1,24 SW P Switching node, charge current output inductor connection. Connect the 0.047-µF bootstrap capacitor

2,3 PVCC P Charger input voltage. Connect at least 10-µF ceramic capacitor from PVCC to PGND and place it as

4 AVCC P IC power positive supply. Place a 1-µF ceramic capacitor from AVCC to AGND and place it as close as

5 ACN I Adapter current sense resistor negative input. A 0.1-µF ceramic capacitor is placed from ACN to ACP to

6 ACP P/I Adapter current sense resistor positive input. A 0.1-µF ceramic capacitor is placed from ACN to ACP to

7 CMSRC O Connect to common source of N-channel ACFET and reverse blocking MOSFET (RBFET). Place 4-kΩ

2 Copyright © 2010–2011, Texas Instruments Incorporated

TYPE DESCRIPTION

from SW to BTST.

close as possible to IC.

possible to IC. Place a 10-Ω resistor from input side to AVCC pin to filter the noise. For 5V input, a 5-Ω
resistor is recommended.

provide differential-mode filtering. An optional 0.1-µF ceramic capacitor is placed from ACN pin to AGND
for common-mode filtering.

provide differential-mode filtering. A 0.1-µF ceramic capacitor is placed from ACP pin to AGND for
common-mode filtering.

resistor from CMSRC pin to the common source of ACFET and RBFET to control the turn-on speed. The
resistance between ACDRV and CMSRC should be 500-kΩ or bigger.

ISET

CHG

SR

V

I =

20 R´

ACSET

DPM

AC

V

I =

20 R´

bq24133

www.ti.com

SLUSAF7B –DECEMBER 2010– REVISED MAY 2011

PIN FUNCTIONS (continued)

PIN

NO. NAME

8 ACDRV O AC adapter to system switch driver output. Connect to 4-kΩ resistor then to the gate of the ACFET

9 STAT O Open-drain charge status pin with 10-kΩ pull up to power rail. The STAT pin can be used to drive LED or

10 TS I Temperature qualification voltage input. Connect a negative temperature coefficient thermistor. Program

11 TTC I Safety Timer and termination control. Connect a capacitor from this node to AGND to set the fast charge

12 VREF P 3.3V reference voltage output. Place a 1-μF ceramic capacitor from VREF to AGND pin close to the IC.

13 ISET I Fast charge current set point. Use a voltage divider from VREF to ISET to AGND to set the fast charge

TYPE DESCRIPTION

N-channel power MOSFET and the reverse conduction blocking N-channel power MOSFET. Connect
both FETs as common-source. The internal gate drive is asymmetrical, allowing a quick turn-off and
slower turn-on in addition to the internal break-before-make logic with respect to the BATDRV.

communicate with the host processor. It indicates various charger operations: LOW when charge in
progress. HIGH when charge is complete or in SLEEP mode. Blinking at 0.5Hz when fault occurs,
including charge suspend, input over-voltage, timer fault and battery absent.

the hot and cold temperature window with a resistor divider from VREF to TS to AGND. The temperature
qualification window can be set to 5-40°C or wider. The 103AT thermistor is recommended.

safety timer(5.6min/nF). Pre-charge timer is internally fixed to 30 minutes. Pull the TTC to LOW to disable
the charge termination and safety timer. Pull the TTC to HIGH to disable the safety timer but allow the
charge termination.

This voltage could be used for programming ISET and ACSET and TS pins. It may also serve as the
pull-up rail of STAT pin and CELL pin.

current:

The pre-charge and termination current is internally as one tenth of the charge current. The charger is
disabled when ISET pin voltage is below 40mV and enabled when ISET pin voltage is above 120mV.

14 CELL I Cell selection pin. Set CELL pin LOW for 1-cell, Float for 2-cell (0.8V-1.8V), and HIGH for 3-cell with a

15 SRN I Charge current sense resistor negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to

16 SRP I/P Charge current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to

17 ACSET I Input current set point. Use a voltage divider from VREF to ACSET to AGND to set this value:

18 OVPSET I Valid input voltage set point. Use a voltage divider from input to OVPSET to AGND to set this voltage.

19 BATDRV O Battery discharge MOSFET gate driver output. Connect to 1kohm resistor to the gate of the BATFET

20 REGN P PWM low side driver positive 6V supply output. Connect a 1-μF ceramic capacitor from REGN to PGND

21 BTST P PWM high side driver positive supply. Connect the 0.047-µF bootstrap capacitor from SW to BTST.

22,23 PGND P Power ground. Ground connection for high-current power converter node. On PCB layout, connect

Thermal AGND P Exposed pad beneath the IC. Always solder Thermal Pad to the board, and have vias on the Thermal

Pad Pad plane star-connecting to AGND and ground plane for high-current power converter. It dissipates the

fixed 4.2V per cell.

provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRN pin to AGND for
common-mode filtering.

provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRP pin to AGND for
common-mode filtering.

The voltage above internal 1.6V reference indicates input over-voltage, and the voltage below internal

0.5V reference indicates input under-voltage. In either condition, charge terminates, and input NMOS pair
ACFET/RBFET turn off. LED driven by STAT pin keeps blinking, reporting fault condition.

P-channel power MOSFET. Connect the source of the BATFET to the system load voltage node. Connect
the drain of the BATFET to the battery pack positive node. The internal gate drive is asymmetrical to
allow a quick turn-off and slower turn-on, in addition to the internal break-before-make logic with respect
to ACDRV.

pin, close to the IC. Generate high-side driver bootstrap voltage by integrated diode from REGN to BTST.

directly to ground connection of input and output capacitors of the charger. Only connect to AGND
through the Thermal Pad underneath the IC.

heat from the IC.

Copyright © 2010–2011, Texas Instruments Incorporated 3

L: 3.3?H

12V Adapter

C9, C10

10?

VBAT

SW

BTST

REGN

PGND

C5

0.047?

ACP

C

IN

2.2?

ISET

VREF

CMSRC

TTC

SRN

OVPSET

TS

SRP

THERMAL

PAD

C3: 0.1?

STAT

PVCC

ACN

VREF

CELL

R

IN

2

BATDRV

C7

0.1?

C11: 0.1µ

C12: 0.1µ

C4: 10µ

C2: 1µ

C1
1µ

C6
1?

VREF

R11

4.02k

R12

4.02k

ACDRV

Q1

Q2

Q3

R14
1k

C8

0.1?

R

T

103AT

R2
232k

R3

32.4k

R1
10

R6
1000k

R7
100k

R8

5.23k

R9

30.1k

R10

1.5k

AVCC

ACSET

R4
100k

R5

k

VREF

D1

D3

D2

VBAT

VREF

bq24133

Float

L: 3.3?H

C9, C10

10?

VBAT

SW

BTST

REGN

PGND

C5

0.047?

ACP

C

IN

2.2?

ISET

VREF

CMSRC

TTC

SRN

OVPSET

TS

SRP

THERMAL

PAD

C3: 0.1?

STAT

PVCC

ACN

VREF

CELL

R

IN

2

R : 20m

AC

BATDRVBATDRV

C7

0.1?

C11: 0.1µ

C12: 0.1µ

C4: 10µ

C2: 1µ

C1
1µ

C6
1?

VREF

R11

4.02k

R12

4.02k

ACDRV

R :10m

SR

Q1

Q2

Q3

R14
1k

C8

0.1?

R

T

103AT

R2
232k

R3

32.4k

R1
10

R6
1000k

R7
100k

R8

5.23k

R9

30.1k

R10

1.5k

AVCC

ACSET

R4
100k

R5

32.4k

VREF

D1

D3

D2

VBAT

VREF

Float

10?10?

System

bq24133

SLUSAF7B –DECEMBER 2010– REVISED MAY 2011

TYPICAL APPLICATIONS

www.ti.com

Figure 1. Typical Application Schematic (12V input, 2 cell battery 8.4V, 2A charge current, 0.2A

pre-charge/termination current, 2A DPM current, 18V input OVP, 0 – 45°C TS)

4 Copyright © 2010–2011, Texas Instruments Incorporated

3.3?H

Adapter
Or USB

10?

SW

BTST

REGN

PGND

0.047?

ACP

ISET

VREF

CMSRC

TTC

SRN

OVPSET

TS

SRP

THERMAL

PAD

STAT

PVCC

ACN

VREF

CELL

BATDRV

0.1?

0.1µ

0.1µ

4.7µ

1µ

C1
1µ

1?

VREF

ACDRV

Q4

0.1?

R

T

103AT

AVCC

ACSET

VREF

D3

ILIM_500mA

RevFET

Selectable input
current limit

R2
100k

R3

32.4k

R6
845k

R7
100k

R8

6.81k

R9
133k

R10

1.5k

R4
100k

R5A

32.4k

R5B

8.06k

VREF

bq24133

3.3?H

Adapter
Or USB

10?

VBAT

SW

BTST

REGN

PGND

0.047?

ACP

ISET

VREF

CMSRC

TTC

SRN

OVPSET

TS

SRP

THERMAL

PAD

STAT

PVCC

ACN

VREF

CELL

BATDRVBATDRV

0.1?

0.1µ

0.1µ

4.7µ

1µ

C1
1µ

1?

VREF

ACDRV

R : 10m

SR

Q4

0.1?

R

T

103AT

R11
5

AVCC

ACSET

VREF

D3

ILIM_500mA

System

RevFET

Selectable input
current limit

R2
100k

R3

32.4k

R6
845k

R7
100k

R8

6.81k

R9
133k

R10

1.5k

R4
100k

R5A

32.4k

R5B

8.06k

VREF

10?10?

R : 20m

AC

D1D

Optional

bq24133

www.ti.com

SLUSAF7B –DECEMBER 2010– REVISED MAY 2011

5 – 40°C TS, system connected before sense resistor)

ORDERING INFORMATION

(1)

bq24133RGYR 3000
bq24133RGYT 250

Figure 2. Typical Application Schematic wth Single Cell Unremovable Battery (USB or adapter with input

OVP 15V, up to 2A charge current, 0.2A pre-charge current, 2A adapter current or 500mA USB current,

PART NUMBER PART MARKING PACKAGE ORDERING NUMBER QUANTITY

bq24133 bq24133 24-Pin 3.5mm×5.5mm QFN

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

Copyright © 2010–2011, Texas Instruments Incorporated 5

bq24133

SLUSAF7B –DECEMBER 2010– REVISED MAY 2011

www.ti.com

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

AVCC, ACP, ACN, ACDRV, CMSRC, STAT –0.3 to 30
PVCC –0.3 to 20
BTST –0.3 to 26

Voltage range (with respect to AGND) V

Maximum difference voltage SRP–SRN, ACP-ACN –0.5 to 0.5 V
Junction temperature range, T
Storage temperature range, T

J

stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging

Section of the data book for thermal limitations and considerations of packages.

BATDRV, SRP, SRN –0.3 to 20
SW –2 to 20
OVPSET, REGN, TS, TTC, CELL –0.3 to 7
VREF, ISET, ACSET –0.3 to 3.6
PGND –0.3 to 0.3

(1)(2)

VALUE UNIT

–40 to 155 °C
–55 to 155 °C

THERMAL INFORMATION

bq24133

THERMAL METRIC

θ

JA

ψ

JT

ψ

JB

Junction-to-ambient thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(4) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(1)

RGY UNITS

24 PINS

(2)

(3)

(4)

35.7

0.4 °C/W

31.2

RECOMMENDED OPERATING CONDITIONS

MIN MAX UNIT

Input voltage V
Output voltage V
Output current (RSR10mΩ) I

Maximum difference voltage

Operation free-air temperature range, T

IN
OUT

OUT

ACP - ACN –200 200 mV
SRP–SRN –200 200 mV

A

6 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated

Product Folder Link(s): bq24133

4.5 17 V

13.5 V

0.6 2.5 A

–40 85 °C

bq24133

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SLUSAF7B –DECEMBER 2010– REVISED MAY 2011

ELECTRICAL CHARACTERISTICS

4.5V ≤ V(PVCC, AVCC) ≤ 17V, –40°C < TJ+ 125°C, typical values are at TA= 25°C, with respect to AGND (unless otherwise

noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

OPERATING CONDITIONS

V

AVCC_OP

QUIESCENT CURRENTS

I

BAT

I

AC

CHARGE VOLTAGE REGULATION

V

BAT_REG

CURRENT REGULATION – FAST CHARGE

V

ISET

K

ISET

V

ISET_CD

V

ISET_CE

I

ISET

INPUT CURRENT REGULATION

K

DPM

I

ACSET

CURRENT REGULATION – PRE-CHARGE

K

IPRECHG

(1) Specified by design
(2) The minimum current is 120 mA on 10mΩ sense resistor.

AVCC input voltage operating range during
charging

V

> V

, V

, V

, V

, V

> V

SRN

AVCC

AVCC

=12.6V, Charge 25 µA

BAT

AVCC

=12.6V, Charge done

BAT

> V

AVCC

SRN

> V

AVCC

SRN

> V

AVCC

SRN

AVCC

UVLO

, ISET < 40mV, V

SRN

Battery discharge current (sum of currents
into AVCC, PVCC, ACP, ACN)

to 85°C
BTST, SW, SRP, SRN, V

V
disabled

BTST, SW, SRP, SRN, V
V

, ISET > 120mV, V

SRN

V

> V

AVCC

V

Adapter supply current (sum of current into V
AVCC,ACP, ACN) Charge enabled, no switching

V
Charge enabled, switching

UVLO

=12.6V, Charge disabled

BAT

> V

AVCC

UVLO

> V

AVCC

UVLO

(SLEEP), TJ= 0°C

> V

, V

UVLO

AVCC

> V

, V

UVLO

AVCC

, ISET < 40mV,

, ISET > 120mV,

, ISET > 120mV,

4.5 17 V

>

>

15

25

1.2 1.5

2.5 5 mA

(1)

15

CELL to AGND, 1 cell, measured on SRN 4.2 V

SRN regulation voltage CELL floating, 2 cells, measured on SRN 8.4 V

CELL to VREF, 3 cells, measured on SRN 12.6 V

Charge voltage regulation accuracy

ISET Voltage Range R
Charge Current Set Factor (Amps of Charge

Current per Volt on ISET pin)

Charge Current Regulation Accuracy V

TJ= 0°C to 85°C –0.5% 0.5%
TJ= –40°C to 125°C -0.7% 0.7%

= 10mΩ 0.12 0.5 V

SENSE

R

= 10mΩ 5 A/V

SENSE

V

= 40 mV -5% 5%

SRP-SRN

= 20 mV -8% 8%

SRP-SRN

V

= 5 mV -25% 25%

SRP-SRN

Charge Disable Threshold ISET falling 40 50 mV
Charge Enable Threshold ISET rising 100 120 mV
Leakage Current into ISET VISET = 2V 100 nA

Input DPM Current Set Factor (Amps of
Input Current per Volt on ACSET)

Input DPM Current Regulation Accuracy

Leakage Current into ACSET pin V

Precharge current set factor Percentage of fast charge current 10%

Precharge current regulation accuracy

R

= 20mΩ 2.5 A/V

SENSE

V

= 80 mV -6% 6%

ACP-ACN

V

= 40 mV -10% 10%

ACP-ACN

V

= 20 mV –15% 15%

ACP-ACN

V

= 5 mV –20% 20%

ACP-ACN

= 2V 100 nA

ACSET

(2)

V

= 4 mV –25% 25%

SRP-SRN

V

= 2 mV –40% 40%

SRP-SRN

Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback 7

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bq24133

SLUSAF7B –DECEMBER 2010– REVISED MAY 2011

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ELECTRICAL CHARACTERISTICS (continued)

4.5V ≤ V(PVCC, AVCC) ≤ 17V, –40°C < TJ+ 125°C, typical values are at TA= 25°C, with respect to AGND (unless otherwise

noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

CHARGE TERMINATION

K

TERM

Termination current set factor Percentage of fast charge current 10%

Termination current regulation accuracy

t

TERM_DEG

t

QUAL

I

QUAL

Deglitch time for termination (both edges) 100 ms
Termination qualification time V
Termination qualification current Discharge current once termination is detected 2 mA

INPUT UNDER-VOLTAGE LOCK-OUT COMPARATOR (UVLO)

V

UVLO

V

UVLO_HYS

AC under-voltage rising threshold Measure on AVCC 3.4 3.6 3.8 V
AC under-voltage hysteresis, falling Measure on AVCC 300 mV

SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)

V

SLEEP

V

SLEEP_HYS

t

SLEEP_FALL_CD

t

SLEEP_FALL_FETOFF

t

SLEEP_FALL

t

SLEEP_PWRUP

SLEEP mode threshold V
SLEEP mode hysteresis V
SLEEP deglitch to disable charge V
SLEEP deglitch to turn off input FETs V
Deglitch to enter SLEEP mode, disable

VREF and enter low quiescent mode
Deglitch to exit SLEEP mode, and enable

VREF

ACN-SRN COMPARATOR

V

ACN-SRN

V

ACN-SRN_HYS

t

BATFETOFF_DEG

t

BATFETON_DEG

Threshold to turn on BATFET V
Hysteresis to turn off BATFET V
Deglitch to turn on BATFET V
Deglitch to turn off BATFET V

BAT LOWV COMPARATOR

V

LOWV

V

LOWV_HYS

t

pre2fas

t

fast2pre

Precharge to fast charge transition CELL floating, 2 cells, measure on SRN 5.74 5.8 5.86 V

Fast charge to precharge hysteresis CELL floating, 2 cells, measure on SRN 400 mV

V

rising deglitch Delay to start fast charge current 25 ms

LOWV

V

falling deglitch Delay to start precharge current 25 ms

LOWV

RECHARGE COMPARATOR

V

RECHG

t

RECH_RISE_DEG

t

RECH_FALL_DEG

Recharge Threshold, below regulation
voltage limit, V

V

RECHG

V

RECHG

BAT_REG-VSRN

rising deglitch SRN decreasing below V
falling deglitch SRN increasing above V

(3) The minimum current is 120 mA on 10mΩ sense resistor.

V

= 4 mV –25% 25%

SRP-SRN

V

= 2 mV –40% 40%

SRP-SRN

> V

and I

SRN

RECH

– V

AVCC

SRN

– V

AVCC

SRN

– V

AVCC

SRN

– V

AVCC

SRN

V

– V

AVCC

SRN

V

– V

AVCC

SRN

falling 150 220 300 mV

ACN-SRN

rising 100 mV

ACN-SRN

falling 2 ms

ACN-SRN

rising 50 µs

ACN-SRN

< I

CHG

TERM

falling 50 90 150 mV
rising 200 mV
falling 1 ms
falling 5 ms

falling 100 ms

rising 30 ms

CELL to AGND, 1 cell, measure on SRN 2.87 2.9 2.93

CELL to VREF, 3 cells, measure on SRN 8.61 8.7 8.79
CELL to AGND, 1 cell, measure on SRN 200

CELL to VREF, 3 cells, measure on SRN 600

CELL to AGND, 1 cell, measure on SRN 70 100 130
CELL floating, 2 cells, measure on SRN 140 200 260 mV
CELL to VREF, 3 cells, measure on SRN 210 300 390

RECHG

RECHG

(3)

250 ms

10 ms
10 ms

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SLUSAF7B –DECEMBER 2010– REVISED MAY 2011

ELECTRICAL CHARACTERISTICS (continued)

4.5V ≤ V(PVCC, AVCC) ≤ 17V, –40°C < TJ+ 125°C, typical values are at TA= 25°C, with respect to AGND (unless otherwise

noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

BAT OVER-VOLTAGE COMPARATOR

V

OV_RISE

V

OV_FALL

INPUT OVER-VOLTAGE COMPARATOR (ACOV)

V

ACOV

V

ACOV_HYS

t

ACOV_RISE_DEG

t

ACOV_FALL_DEG

INPUT UNDER-VOLTAGE COMPARATOR (ACUV)

V

ACUV

V

ACUV_HYS

t

ACOV_FALL_DEG

t

ACOV_RISE_DEG

THERMAL REGULATION

T

J_REG

THERMAL SHUTDOWN COMPARATOR

T

SHUT

T

SHUT_HYS

t

SHUT_RISE_DEG

t

SHUT_FALL_DEG

THERMISTOR COMPARATOR

V

LTF

V

LTF_HYS

V

HTF

V

TCO

t

TS_CHG_SUS

t

TS_CHG_RESUME

CHARGE OVER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)

V

OCP_CHRG

V

OCP_MIN

V

OCP_MAX

HSFET OVER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)

I

OCP_HSFET

CHARGE UNDER-CURRENT COMPARATOR (CYCLE-BY-CYCLE)

V

UCP

Over-voltage rising threshold As percentage of V
Over-voltage falling threshold As percentage of V

AC Over-Voltage Rising Threshold to turn
off ACFET

OVPSET rising 1.55 1.6 1.65 V

BAT_REG
SRN

104%
102%

AC over-voltage falling hysteresis OVPSET falling 50 mV
AC Over-Voltage Rising Deglitch to turn off

ACFET and Disable Charge
AC Over-Voltage Falling Deglitch to Turn on

ACFET

AC Under-Voltage Falling Threshold to turn
off ACFET

OVPSET rising 1 µs

OVPSET falling 30 ms

OVPSET falling 0.45 0.5 0.55 V

AC Under-Voltage Rising Hysteresis OVPSET rising 100 mV
AC Under-Voltage Falling Deglitch to turn

off ACFET and Disable Charge
AC Under-Voltage Rising Deglitch to turn on

ACFET

OVPSET falling 1 µs

OVPSET rising 30 ms

Junction Temperature Regulation Accuracy ISET > 120mV, Charging 120 °C

Thermal shutdown rising temperature Temperature rising 150 °C
Thermal shutdown hysteresis Temperature falling 20 °C
Thermal shutdown rising deglitch Temperature rising 100 µs
Thermal shutdown falling deglitch Temperature falling 10 ms

Cold Temperature Threshold, TS pin Charger suspends charge. As percentage to
Voltage Rising Threshold V

Cold Temperature Hysteresis, TS pin
Voltage Falling

Hot Temperature TS pin voltage rising
Threshold

Cut-off Temperature TS pin voltage falling
Threshold

Deglitch time for Temperature Out of Range VTS> V
Detection VTS< V

Deglitch time for Temperature in Valid VTS< V
Range Detection V

Charge Over-Current Rising Threshold,
V

>2.2V

SRP

Charge Over-Current Limit Min, V
Charge Over-Current Limit Max, V

<2.2V Measure V

SRP

>2.2V Measure V

SRP

VREF

As percentage to V

As percentage to V

As percentage to V

LTF
HTF

LTF

HTF

VREF

VREF

VREF

, or VTS< V

– V

LTF_HYS

, or

TCO

or VTS>V

TCO

, or V

TS

Current as percentage of fast charge current 160%

SRP-SRN
SRP-SRN

72.5% 73.5% 74.5%

0.2% 0.4% 0.6%

46.6% 47.2% 48.8%

44.2% 44.7% 45.2%

>

20 ms

400 ms

45 mV
75 mV

Current limit on HSFET Measure on HSFET 6 A

Charge under-current falling threshold Measure on V

(SRP-SRN)

1 5 9 mV

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SLUSAF7B –DECEMBER 2010– REVISED MAY 2011

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ELECTRICAL CHARACTERISTICS (continued)

4.5V ≤ V(PVCC, AVCC) ≤ 17V, –40°C < TJ+ 125°C, typical values are at TA= 25°C, with respect to AGND (unless otherwise

noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

BAT SHORT COMPARATOR

V

BATSHT

V

BATSHT_HYS

t

BATSHT_DEG

V

BATSHT

VREF REGULATOR

V

VREF_REG

I

VREF_LIM

REGN REGULATOR

V

REGN_REG

I

REGN_LIM

TTC INPUT

t

prechrg

t

fastchrg

K

TTC

V

TTC_LOW

I

TTC

V

TTC_OSC_HI

V

TTC_OSC_LO

BATTERY SWITCH (BATFET) DRIVER

R

DS_BAT_OFF

R

DS_BAT_ON

V

BATDRV_REG

t

BATFET_DEG

AC SWITCH (ACFET) DRIVER

I

ACFET

V

ACDRV_REG

R

ACDRV_LOAD

AC/BAT SWITCH DRIVER TIMING

t

DRV_DEAD

BATTERY DETECTION

t

WAKE

I

WAKE

t

DISCHARGE

I

DISCHARGE

I

FAULT

V

WAKE

V

DISCH

(4) The minimum current is 120 mA on 10mΩ sense resistor.

Battery short falling threshold Measure on SRN 2 V
Battery short rising hysteresis Measure on SRN 200 mV
Deglitch on both edges 1 µs
Charge Current during BATSHORT Percentage of fast charge current 10%

VREF regulator voltage V
VREF current limit V

REGN regulator voltage V
REGN current limit V

> V

AVCC
VREF

AVCC
REGN

, No load 3.267 3.3 3.333 V

UVLO

= 0 V, V

AVCC

> V

UVLO

35 90 mA

> 10 V, ISET > 120 mV 5.7 6.0 6.3 V
= 0 V, V

> 10 v, ISET > 120 mV 40 120 mA

AVCC

(4)

Precharge Safety Timer Precharge time before fault occurs 1620 1800 1980 Sec
Fast Charge Timer Range T

chg=CTTC*KTTC

1 10 hr
Fast Charge Timer Accuracy -10% 10%
Timer Multiplier 5.6 min/nF
TTC Low Threshold TTC falling 0.4 V
TTC Source/Sink Current 45 50 55 µA
TTC oscillator high threshold 1.5 V
TTC oscillator low threshold 1 V

BATFET Turn-off Resistance V
BATFET Turn-on Resistance V

BATFET Drive Voltage 4.2 7 V
BATFET Power-up Delay to turn off

BATFET after adapter is detected

ACDRV Charge Pump Current Limit V
Gate Drive Voltage on ACFET V
Maximum load between ACDRV and

CMSRC

Driver Dead Time 10 µs

> 5V 100 Ω

AVCC

> 5V 20 kΩ

AVCC

V

BATDRV_REG=VACN

and BATFET is on

- V

BATDRV

when V

AVCC

> 5V

30 ms

ACDRV
ACDRV

- V

- V

= 5V 60 µA

CMSRC
CMSRC

when V

AVCC

> V

UVLO

4.2 6 V

500 kΩ

Dead Time when switching between ACFET and
BATFET

Wake timer Max time charge is enabled 500 ms
Wake current R

= 10 mΩ 50 125 200 mA

SENSE

Discharge timer Maxtime discharge current is applied 1 sec
Discharge current 8 mA
Fault current after a timeout fault 2 mA
Wake threshold with respect to V

detect battery absent during WAKE
Discharge Threshold to detect battery

absent during discharge

REG

To

Measure on SRN 100 mV/cell

Measure on SRN 2.9 V/cell

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SLUSAF7B –DECEMBER 2010– REVISED MAY 2011

ELECTRICAL CHARACTERISTICS (continued)

4.5V ≤ V(PVCC, AVCC) ≤ 17V, –40°C < TJ+ 125°C, typical values are at TA= 25°C, with respect to AGND (unless otherwise
noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

INTERNAL PWM

fsw PWM Switching Frequency 1360 1600 1840 kHz
t

SW_DEAD

R

DS_HI

R

DS_LO

V

BTST_REFRESH

Driver Dead Time
High Side MOSFET On Resistance V

Low Side MOSFET On Resistance 95 160 mΩ

Bootstrap Refresh Comparator Threshold
Voltage

(5)

INTERNAL SOFT START (8 steps to regulation current ICHG)

SS_STEP Soft start steps 8 step
T

SS_STEP

Soft start step time 1.6 3 ms

CHARGER SECTION POWER-UP SEQUENCING

t

CE_DELAY

Delay from ISET above 120mV to start
charging battery

INTEGRATED BTST DIODE

V

F

V

R

Forward Bias Voltage IF=120mA at 25°C 0.85 V
Reverse breakdown voltage IR=2uA at 25°C 20 V

LOGIC IO PIN CHARACTERISTICS

V

OUT_LO

V

CELL_LO

V

CELL_MID

V

CELL_HI

STAT Output Low Saturation Voltage Sink Current = 5 mA 0.5 V
CELL pin input low threshold, 1 cell CELL pin voltage falling edge 0.5 V
CELL pin input mid threshold, 2 cells CELL pin voltage rising for MIN, falling for MAX 0.8 1.8 V
CELL pin input high threshold, 3 cells CELL pin voltage rising edge 2.5 V

(5) Specified by design

Dead time when switching between LSFET and
HSFET no load

– VSW= 4.5 V 80 150 mΩ

BTST

V

– VSWwhen low side refresh pulse is

BTST

requested, V
V

– VSWwhen low side refresh pulse is

BTST

requested, V

AVCC

AVCC

=4.5V

>6V

3

4

30 ns

1.5 s

V

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