Texas Instruments AM571 Series User Manual

AM571x Industrial Development Kit (IDK) Evaluation Module (EVM) Hardware

User's Guide

Literature Number: SPRUI97A

May 2017

Contents

Preface ........................................................................................................................................ 5

1 Introduction......................................................................................................................... 6

1.1 Description ................................................................................................................ 6

1.2 System View .............................................................................................................. 7

2 Functional Description........................................................................................................ 11

2.1 Processor................................................................................................................ 12

2.2 Clocks.................................................................................................................... 12

2.3 Reset Signals ........................................................................................................... 12

3 Power Supplies .................................................................................................................. 13

3.1 Power Source ........................................................................................................... 13

3.2 TPS6590377 PMIC..................................................................................................... 13

3.3 AVS Control ............................................................................................................. 13

3.4 Other Power Supplies.................................................................................................. 14

4 Configuration/Setup............................................................................................................ 15

4.1 Boot Configuration...................................................................................................... 15

4.2 I2C Address Assignments ............................................................................................. 15

4.3 SEEPROM Header ..................................................................................................... 16

4.4 JTAG Emulation ........................................................................................................ 16

5 Memories Supported........................................................................................................... 17

5.1 DDR3L SDRAM......................................................................................................... 17

5.2 SPI NOR Flash.......................................................................................................... 17

5.3 Board Identity Memory................................................................................................. 17

5.4 SD/MMC ................................................................................................................. 17

5.5 eMMC NAND Flash .................................................................................................... 17

6 Ethernet Ports.................................................................................................................... 18

6.1 100Mb Ethernet Ports on PRU-ICSS ................................................................................ 18

6.2 Gigabit (1000Mb) Ethernet Ports..................................................................................... 18

7 USB Ports.......................................................................................................................... 19

7.1 Processor USB Port 1.................................................................................................. 19

7.2 Processor USB Port 2.................................................................................................. 19

7.3 FTDI USB Port .......................................................................................................... 19

8 PCIe.................................................................................................................................. 20

9 Video Input and Output....................................................................................................... 20

9.1 Camera................................................................................................................... 20

9.2 HDMI ..................................................................................................................... 20

9.3 LCD....................................................................................................................... 20

10 Industrial Interfaces............................................................................................................ 21

10.1 Profibus .................................................................................................................. 21

10.2 DCAN..................................................................................................................... 21

10.3 RS-485................................................................................................................... 21

11 User Interfaces................................................................................................................... 21

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11.1 Tri-color LEDs........................................................................................................... 21

11.2 Industrial Inputs ......................................................................................................... 21

11.3 Industrial Outputs / LEDs.............................................................................................. 21

12 Pin Use Description............................................................................................................ 22

12.1 Functional Interface Mapping ......................................................................................... 22

12.2 GPIO Pin Mapping...................................................................................................... 22

13 Board Connectors .............................................................................................................. 24

14 EVM Important Notice ......................................................................................................... 37

Appendix A Known Deficiencies in AM571x IDK EVM ..................................................................... 38

A.1 Power solution not sufficient for full PCIe plug-in card compliance............................................. 38

A.2 Early versions of the AM571x IDK EVM not installed with SOC devices rated for the full industrial

temperature range...................................................................................................... 38

A.3 AM571x IDK EVM does not support eMMC HS200 mode....................................................... 38

A.4 PCIe PERSTn line not in proper state at start-up................................................................. 38

A.5 EDIO connectors J4 and J7 should support real-time debugging for both PRU1 and PRU2............... 38

A.6 HDQ implementation not correct.................................................................................... 38

A.7 Removing the power plug and inserting it again while the power supply is energized may cause

damage .................................................................................................................. 38

A.8 Software shutdown of PMIC not operational ...................................................................... 39

A.9 CCS System Reset fails ............................................................................................. 39

A.10 AM571x IDK EVM design contains 2 clamp circuits that may not be necessary ............................. 39

A.11 Crystal connected to osc0 needs to have 50ppm or better long term accuracy .............................. 39

A.12 Software must program the CDCE913 for 0pf load capacitance................................................ 39

A.13 Protection diode D2 should be rated for 5V ....................................................................... 39

A.14 PHY address LSB for U9 and U15 can be latched incorrectly .................................................. 40

A.15 3.3V clamp circuit needs more margin ............................................................................. 40

A.16 Current PMIC does not provide the mandated power down sequence ........................................ 40

A.17 Power supply droop may cause board reset ...................................................................... 40

A.18 AM5718 pin N21 must be connected to 1.8V, as it is VDDS18V_DDR1 and not N/C....................... 40

A.19 VOUT1 is used at 3.3V, which violates erratum i920............................................................. 40

Revision History.......................................................................................................................... 41

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Contents

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List of Figures

1 AM571x IDK EVM - Top View.............................................................................................. 7

2 AM571x IDK EVM - Bottom View.......................................................................................... 8

3 AM571x IDK EVM with Camera Board Installed......................................................................... 9

4 AM571x IDK EVM with LCD Display Assembly Attached ............................................................ 10

5 AM571x IDK EVM Block Diagram ....................................................................................... 11

6 Connections from the TPS6590377 PMIC to the AM571x Processor............................................... 14

List of Tables

1 I2C1/IND_I2C ............................................................................................................... 15

2 I2C2/AM571X_HDMI_DDC ............................................................................................... 15

3 SEEPROM Header......................................................................................................... 16

4 PRU-ICSS Ethernet Ports................................................................................................. 18

5 GPIO Pin Mapping ......................................................................................................... 23

6 Expansion Connector - J21 ............................................................................................... 24

7 I/O Expansion Header Connector - J37................................................................................. 26

8 MicroSD Connector - J15 ................................................................................................. 27

9 Power Jack Connector - J1 ............................................................................................... 27

10 Power Terminal Block Connector - J2................................................................................... 27

11 PRU1ETH0 RJ45 Connector - J3........................................................................................ 28

12 PRU1ETH1 RJ45 Connector - J5........................................................................................ 28

13 PRU2ETH0 RJ45 Connector - J6........................................................................................ 29

14 PRU2ETH1 RJ45 Connector - J8........................................................................................ 29

15 PRU2ETH0 Test Header Connector - J7 ............................................................................... 30

16 PRU2ETH1 Test Header Connector - J4 ............................................................................... 30

17 Camera Connector - J9.................................................................................................... 30

18 GigE RJ45 Connector - J10............................................................................................... 31

19 GigE RJ45 Connector - J12............................................................................................... 31

20 LCD Module FFC Connector - J16....................................................................................... 32

21 Touchscreen Controller FFC Connector - J17 ......................................................................... 32

22 HDMI Standard A-type Connector - J24 ................................................................................ 33

23 CTI-20 JTAG Connector - J18............................................................................................ 33

24 JTAG USB Micro-AB Connector - J19 .................................................................................. 34

25 USB Port 1 USB2.1 Standard A-type Connector - J23................................................................ 34

26 USB Port 2 USB2.1 Micro-AB Connector - J45 ........................................................................ 34

27 CAN Header Connector - J38 ............................................................................................ 35

28 Profibus DB9F Connector - J14.......................................................................................... 35

29 RS-485 Header Connector - J39......................................................................................... 35

30 PCIe Connector – J52..................................................................................................... 36

List of Figures

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About This Manual

This document describes the hardware architecture of the AM571x Industrial Development Kit (IDK) Evaluation Module (EVM) (Part# TMDXIDK571x) that supports the Texas Instruments Sitara™ ARM Cortex®-A15 AM571x processor family.

Glossary

TI Glossary —This glossary lists and explains terms, acronyms, and definitions.

Related Documentation From Texas Instruments

For product information, visit the Texas Instruments website at http://www.ti.com.

SPRS957— AM571x Sitara Processors Silicon Revision 2.0 Data Manual SPRZ436— AM571x Sitara Processors Silicon Errata. Describes the known exceptions to the functional

specifications for the device.

SPRUHZ7— AM571x Sitara Processors Silicon Revision 2.0, 1.0 Technical Reference Manual. Details

the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the device.

Preface

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Read This First

Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

TI E2E™ Online Community— TI's Engineer-to-Engineer (E2E) Community. Created to foster

collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.

TI Embedded Processors Wiki— Texas Instruments Embedded Processors Wiki. Established to help

developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.

Trademarks

Sitara, E2E, Code Composer Studio, SmartReflex are trademarks of Texas Instruments. ARM, Cortex are registered trademarks of ARM Limited. Windows is a registered trademark of Microsoft Corporation.

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Preface

1 Introduction

1.1 Description

The AM571x IDK is a standalone test, development, and evaluation module that enables developers to write software and develop hardware for industrial control and industrial communications applications. It has been equipped with a TI AM5718 processor and a defined set of features to allow you to experience industrial communication solutions using various serial or Ethernet based interfaces. Using standard interfaces, the AM571x IDK may interface to other processors or systems and act as a communication gateway or controller. In addition, it can directly operate as a standard remote I/O system or a sensor connected to an industrial communication network.

The AM571x IDK contains embedded emulation circuitry to quickly enable developers to begin using this IDK. The embedded emulation logic allows emulation and debug using standard development tools such as the Texas Instruments Code Composer Studio™ integrated development environment (IDE) by simply connecting a USB cable to a Windows®-based computer.

The standard (4-port Ethernet) configuration for the AM571x IDK EVM provides the following functionality:

• Two Gigabit (1000Mb) metallic ports connected via PHY/RGMII to the on-chip Ethernet switch

• Two 100Mb metallic ports connected via PHY/MII to the PRU-ICSS subsystems

• LCD panel output from Display Parallel Interface (DPI) Video Output 1 Reconfiguration through header shunt removal provides an alternate 6-port Ethernet configuration:

• Two Gigabit (1000Mb) metallic ports connected via PHY/RGMII to the on-chip Ethernet switch

• Four 100Mb metallic ports connected via PHY/MII to the PRU-ICSS subsystems Software support for the AM571x IDK EVM is provided within the Processor Software Development Kit

(SDK) package. This includes both Linux and RTOS support.

User's Guide

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AM571x Industrial Development Kit (IDK)

Evaluation Module (EVM) Hardware

AM571x Industrial Development Kit (IDK) Evaluation Module (EVM) Hardware

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1.2 System View

The system view of the AM571x IDK EVM consists of the main board and the camera board. There is also an optional LCD panel and touch screen assembly that can be attached to the AM571x IDK EVM.

The top and the bottom views of the AM571x IDK EVM are provided in Figure 1 and Figure 2, respectively.

The top view of the AM571x IDK EVM with the camera board installed is provided in Figure 3. The side view of the AM571x IDK EVM with the optional LCD display assembly attached is provided in Figure 4.

Introduction

Figure 1. AM571x IDK EVM - Top View

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Introduction

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Figure 2. AM571x IDK EVM - Bottom View

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Introduction

Figure 3. AM571x IDK EVM with Camera Board Installed

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Introduction

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Figure 4. AM571x IDK EVM with LCD Display Assembly Attached

AM571x Industrial Development Kit (IDK) Evaluation Module (EVM) Hardware

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AM571x

DDR1

QSPI

RGMII0

MMC1

HDMI / I2C2

PCIe / I2C1

HDMI

PCIe x2

GbE

MMC2

I2C

QSPI

32MB

eMMC

16GB

uSD

EEPROM

USB2.0

MicroAB

I2C

USB2

UART

Camera Header

VIN4B / I2C1

JTAG

(60-pin)

ICs

TI ICs

Connectors

ISO1176T

Profibus

DB9

PRU UART

TPS6590377

PMIC

KSZ9031

DDR3

1GB

w/ECC

Warm RESET

INT

RGY LED ENET Status

GPIO

RGMII1

GbE

KSZ9031

DCAN1

USB1

USB2.0

Std A

FTDI

USB

SN65HVD78D

RS485

Header

UART2

Industrial Inputs &

Outputs/LEDs

SPI3 / I2C1

LCD &

Touch Panel

MIPI

Serializer

VOUT1/PR1_MII0_1

ISO1050

TPD6E001

TPD4S012

TPD2EUSB30

DCAN

Header

TPD12S016

TLK105L

ICSS0

RJ45

TLK105L

ICSS0

RJ45

TLK105L

ICSS1

RJ45

PR2_MII0

TLK105L

ICSS1

RJ45

PR2_MII1

ICSS Header

prx_mii0/1_txen/rxdv,

prx_edio_data_out + sync

FET Switches

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2 Functional Description

The AM571x IDK EVM is implemented on a single board with interface circuitry, memory ICs, and connectors around the AM5718 processor. The board also contains power conversion circuitry to efficiently create the needed power supply voltages from a single +5V input. As stated previously, this EVM ships with a separate camera module that plugs in to the main board. An optional LCD panel and touch screen assembly can be purchased separately and mounted on to the main board.

Figure 5 shows the functional block diagram of the AM571x IDK EVM.

Functional Description

Figure 5. AM571x IDK EVM Block Diagram

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Functional Description

2.1 Processor

The AM5718 processor is the central processing unit for this IDK EVM. The interface circuitry, memory ICs, and connectors implemented on the board around the AM5718 processor provide development support for the many industrial communication interfaces available on this platform. See the AM571x

Sitara Processors Silicon Revision 2.0 Data Manual (SPRS957) and the AM571x Sitara Processors Technical Reference Manual (SPRUHZ7) for details about the processor.

The AM571x IDK EVM contains system configuration for the boot mode control inputs SYSBOOT[15..0]. These can be strapped using resistors. The default configuration will meet the needs of most developers. Resistor reconfiguration is supported so that you can explore other boot configurations of the AM571x processor. See Section 4 for more details.

2.2 Clocks

The main clock for the processor is derived from a 20-MHz crystal. An on-board oscillator in the AM571x processor generates the base clock and the subsequent module clocks as needed within the AM571x processor. The board design supports a crystal attached to the RTC block, but this is not needed since RTC-only mode is not supported in this device.

2.3 Reset Signals

The AM571x processor contains 3 reset inputs and an output indicating a reset is in progress. The reset pins are:

• PORz: PORz is a hard reset that resets everything including emulation logic. It also tri-states most outputs.

• RESETn: RESETn is a device reset commonly driven by control logic or emulation.

• RTC_PORz: Separate PORz for the RTC module that must be driven at the same time as PORz. (Note that PORz and RTC_PORz can only be directly connected as long as VDDSHV3 and VDDSHV5 are driven at the same voltage.)

• RSTOUTn: Output signal from SOC indicating that the device has entered reset. This is used to reset other circuits that must be reset at the same time as the processor.

More details about the behavior of these reset pins within the AM571x processor can be found in the

AM571x Sitara Processors Silicon Revision 2.0 Data Manual (SPRS957). There are push buttons on the

IDK that can initiate either a RESETn or PORz input. SW1 can drive PORz active (low) and SW2 can drive RESETn active (low).

There is a device erratum in all of the AM571x devices that prevents use of RESETn independent from PORz (see i862, Reset Should Use PORz, in the AM571x Sitara Processors Silicon Errata (SPRZ436). The workaround is to generate PORz whenever a device reset occurs even if it is from an internal initiator. This is accomplished through cooperation with the PMIC paired with the AM571x device on the IDK EVM. The RSTOUTn output from the AM571x device is connected to the NRESWARM input of the PMIC. This initiates a re-start that drives RESET_OUT low and resets all voltages to their initial values. Since RESET_OUT from the PMIC is connected to PORz in the AM571x device, a hard reset is forced on the SOC that meets the needs of the erratum workaround.

The AM571x IDK EVM is started by pressing the start-up push button, SW3. The POWERHOLD input can be connected to VRTC_OUT in customer designs to cause the board to power-on as soon as the main supply is stable.

The configuration of the PMIC to provide RESET_OUT from the NRESWARM input creates an always-on implementation. This always-on mode of operation prevents software shut-down of the IDK. Customer designs should have power-good monitoring circuitry such as a TPS3808 connected to the main supply to the PMIC that is connected to the PMIC RESET_IN, as shown in the AM571x IDK EVM schematic (v1.3). The TPS3808 can detect the main supply voltage dropping and then trigger the PMIC to execute a controlled shut-down that meets the requirements in the AM571x Sitara Processors Silicon Revision 2.0

Data Manual (SPRS957).

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3 Power Supplies

This section describes how the power supplies required for the design are generated.

3.1 Power Source

The AM571x IDK EVM uses an external 5V power supply. The 5V power input is converted into different voltage levels to provide power inputs to the AM571x processor and other circuitry.

Early versions of the AM571x IDK EVM shipped with the GlobTek, Inc. external power supply with the part number TR9CA6500LCP-N, model number GT-43008-3306-1.0-T3. This external power supply is rated for an output voltage of +5VDC with an output current up to 6.5A. This external power supply contains applicable regional product regulatory/safety certification requirements for most worldwide locations. If you cannot use this supply, one with equivalent ratings that is approved for your location must be obtained.

The AM571x IDK EVM contains a right angle mounted power connector that accepts the +5VDC supply input on the center pin with the outer shell as the common return. The power connector accepts a mating plug with a 2.5-mm ID and a 5.5-mm OD.

Removing the power plug and inserting it again while the power supply is energized may damage the AM571x IDK EVM and/or other devices attached to the board such as emulators that provide an alternate path to ground. Removal of AC power from the external power supply is a safer method, if required.

It is recommended that the external power supply have the common return bonded to earth ground. If this is not possible, a separate connection from the board ground to earth ground may need to be provided. Terminal block J53 is added for this purpose.

Power Supplies

3.2 TPS6590377 PMIC

The power requirements of the processor are met by the TPS6590377 Power Management IC (PMIC). The power sequencing requirements of the AM571x processor are also handled by the TPS6590377 PMIC. Figure 6 shows the supply connections from the TPS6590377 PMIC to the AM571x processor.

Refer to the AM571x Sitara Processors Silicon Revision 2.0 Data Manual (SPRS957) for more information about the required supply voltages and supply sequencing. Also refer to the TPS659037 Power

Management Unit (PMU) for Processor Data Manual (SLIS165) and the TPS659037 User's Guide to Power AM572x and AM571x User’s Guide (SLIU011) for details about its operation.

Note that the production version of the AM571x IDK EVM uses the TPS6590377 PMIC that supplies the voltages needed for the latest silicon version of the AM5718 processor. Beta prototype IDK EVM units used the TPS6590375 PMIC and Alpha prototype IDK EVM units used the TPS6590372 PMIC.

3.3 AVS Control

The AM571x processor consumes most of its power in its core logic. Therefore, minimizing the voltage supplied to this core logic can minimize power consumption. SmartReflex™ technology is used to provide this optimized solution.

This core logic is separated into multiple segments that can each be controlled separately. In this way, applications that need more performance in some processing blocks can operate at higher performance levels by increasing the supply voltage, while other processing blocks that do not require the same level of performance can operate at lower voltage thus further optimizing system power consumption.

The TPS6590377 PMIC is connected to the I2C1 on the AM5718 processor. This allows the application software to individually control the AVS supply outputs. It also allows the application to control the voltage generated by LDO1 that is used for the SDIO interface that operates at either 1.8V or 3.3V depending on the operating mode.

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5-V Input

Power

SMPS1, SMPS2

AVS (6 A max)

SMPS4, SMPS5

AVS (4 A max)

SMPS6

AVS (3 A max)

SMPS8

AVS (1 A max)

SMPS7

AVS (2 A max)

LDO9

(50 mA max)

LDOLN

(100 mA max)

LDO3

(200 mA max)

LDOVRTC

(25 mA max)

LDO1

(300 mA max)

LDOUSB

(100 mA max)

SMPS3

(3 A max)

PMIC

TPS659037

TPS51200

5 V

VDD_MPU

VDD_DSPEVE

VDD_GPU VDD_IVAHD VDD_CORE

VDD_RTC

VDDSHV8 (SDIO)

VDDA_USB3V3

VDD_DDR

Dual-Voltage Rails

(set to 3.3 V)

1V8

3V3

5V0

EMIF1 EMIF2

VTT

DDR

Other Domains

Processor

Core Domains

1.06 V

1.15 V

1.05 V

1.06 V

1.35 V or 1.5 V

1.8 V

1.35 V or 1.5 V

1.8 V

3.3 V

1.8 V

0.675 V or 0.75 V

1.8 V

Peripherals

DDR_REF

SMPS9

(1 A max)

LDO2

(300 mA max)

VDDSHV5 (RTC I/O)

3.3 V

VREF

0.675 V or 0.75 V

VDD_1V8

VDDA_1V8 (PLLs)

1V8_PHY (USB/SATA)

VDDA_RTC

1.8-V Domains

1V8_PHY (HDMI/PCIe)

LDO4

(200 mA max)

OSC16MIN

OSC16MOUT

1.8 V

3.3V Input Power

TPS22965

(Power Switch)

REGEN1

Power Supplies

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Figure 6. Connections from the TPS6590377 PMIC to the AM571x Processor

3.4 Other Power Supplies

The AM571x IDK EVM contains 8 other power conversion devices that support the interface and memory circuitry:

• TPS63010 Buck-Boost Converter: This converter generates 5.0V from the main supply input. It supplies this voltage to the industrial interface circuits, the HDMI interface and to the USB master ports.

• TPS61085 Boost Converter: This converter generates 12.0V from the main supply input. It supplies voltage to the industrial interface circuits and the PCIe card connector.

• TPS51200 DDR Termination Voltage LDO (2 each): This LDO provides the push/pull termination current required for the DDR3 memory interfaces. There is one implemented for each DDR3 EMIF.

• LP38693ADJ Low-Dropout Regulator: This LDO generates the 3.7V LCD bias voltage.

• TPS61081DRC LCD Backlight Generator: This Boost converter generates the LCD backlight supply.

• TPS71712 Low-Dropout Regulator: This LDO generates the 1.2V supply needed for the LCD driver logic.

• TPS76650 Low-Dropout Regulator: This LDO generates the 5.0V supply needed for the Profibus interface.

• R1Z-3.305HP Isolated DC-DC Supply: This converter generates 5.0V isolated from the primary

3.3V DC supply on board for the DCAN interface.

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4 Configuration/Setup

This section discusses the board configuration.

4.1 Boot Configuration

Various boot configurations can be set using the pull-up/pull-down resistor combinations provided on the SYSBOOT[15..0] pins. Boot configuration pins are latched upon de-assertion of the PORz pin. Refer to the AM571x Sitara Processors Silicon Revision 2.0 Data Manual (SPRS957) for more details. The AM571x IDK EVM is configured by default to 0x8106 to enable UBOOT/Linux boot from the SDCARD. The secondary boot device selected by this boot mode is QSPI1.

4.2 I2C Address Assignments

The AM571x IDK EVM contains multiple I2C buses connected to a master port on the processor. Each bus contains one or more I2C slave devices that must have unique addresses to prevent contention.

Table 1 and Table 2 list the addresses of the I2C slave devices attached to buses I2C1 and I2C2,

respectively.

I2C Slave Device Address(es)

TPS590377 PMIC, U3 0x58, 0x59, 0x5A, 0x5B, 0x12

Camera Header, J9 Undefined

CDCE913 Ethernet Clock Generator A, U23 0x65

TPIC2810 Industrial Output Driver, U89 0x60

LCD Panel Driver TC358778, U73 0x0E Touchscreen FPC Connector, J17 —

ID Memory SEEPROM, U33 0x50

PCIe Card Connector, J52 Undefined Expansion Connector, J21 Undefined

Configuration/Setup

Table 1. I2C1/IND_I2C

CDCE913 Ethernet Clock Generator B, U25 0x65

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Table 2. I2C2/AM571X_HDMI_DDC

I2C Slave Device Address(es)

HDMI Bridge, U46 —

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