Texas Instruments AM571 Series User Manual

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AM571x Industrial Development Kit (IDK) Evaluation Module (EVM) Hardware

User's Guide

Literature Number: SPRUI97A

May 2017

Page 2

Contents

Preface ........................................................................................................................................ 5

1 Introduction......................................................................................................................... 6

1.1 Description ................................................................................................................ 6

1.2 System View .............................................................................................................. 7

2 Functional Description........................................................................................................ 11

2.1 Processor................................................................................................................ 12

2.2 Clocks.................................................................................................................... 12

2.3 Reset Signals ........................................................................................................... 12

3 Power Supplies .................................................................................................................. 13

3.1 Power Source ........................................................................................................... 13

3.2 TPS6590377 PMIC..................................................................................................... 13

3.3 AVS Control ............................................................................................................. 13

3.4 Other Power Supplies.................................................................................................. 14

4 Configuration/Setup............................................................................................................ 15

4.1 Boot Configuration...................................................................................................... 15

4.2 I2C Address Assignments ............................................................................................. 15

4.3 SEEPROM Header ..................................................................................................... 16

4.4 JTAG Emulation ........................................................................................................ 16

5 Memories Supported........................................................................................................... 17

5.1 DDR3L SDRAM......................................................................................................... 17

5.2 SPI NOR Flash.......................................................................................................... 17

5.3 Board Identity Memory................................................................................................. 17

5.4 SD/MMC ................................................................................................................. 17

5.5 eMMC NAND Flash .................................................................................................... 17

6 Ethernet Ports.................................................................................................................... 18

6.1 100Mb Ethernet Ports on PRU-ICSS ................................................................................ 18

6.2 Gigabit (1000Mb) Ethernet Ports..................................................................................... 18

7 USB Ports.......................................................................................................................... 19

7.1 Processor USB Port 1.................................................................................................. 19

7.2 Processor USB Port 2.................................................................................................. 19

7.3 FTDI USB Port .......................................................................................................... 19

8 PCIe.................................................................................................................................. 20

9 Video Input and Output....................................................................................................... 20

9.1 Camera................................................................................................................... 20

9.2 HDMI ..................................................................................................................... 20

9.3 LCD....................................................................................................................... 20

10 Industrial Interfaces............................................................................................................ 21

10.1 Profibus .................................................................................................................. 21

10.2 DCAN..................................................................................................................... 21

10.3 RS-485................................................................................................................... 21

11 User Interfaces................................................................................................................... 21

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11.1 Tri-color LEDs........................................................................................................... 21

11.2 Industrial Inputs ......................................................................................................... 21

11.3 Industrial Outputs / LEDs.............................................................................................. 21

12 Pin Use Description............................................................................................................ 22

12.1 Functional Interface Mapping ......................................................................................... 22

12.2 GPIO Pin Mapping...................................................................................................... 22

13 Board Connectors .............................................................................................................. 24

14 EVM Important Notice ......................................................................................................... 37

Appendix A Known Deficiencies in AM571x IDK EVM ..................................................................... 38

A.1 Power solution not sufficient for full PCIe plug-in card compliance............................................. 38

A.2 Early versions of the AM571x IDK EVM not installed with SOC devices rated for the full industrial

temperature range...................................................................................................... 38

A.3 AM571x IDK EVM does not support eMMC HS200 mode....................................................... 38

A.4 PCIe PERSTn line not in proper state at start-up................................................................. 38

A.5 EDIO connectors J4 and J7 should support real-time debugging for both PRU1 and PRU2............... 38

A.6 HDQ implementation not correct.................................................................................... 38

A.7 Removing the power plug and inserting it again while the power supply is energized may cause

damage .................................................................................................................. 38

A.8 Software shutdown of PMIC not operational ...................................................................... 39

A.9 CCS System Reset fails ............................................................................................. 39

A.10 AM571x IDK EVM design contains 2 clamp circuits that may not be necessary ............................. 39

A.11 Crystal connected to osc0 needs to have 50ppm or better long term accuracy .............................. 39

A.12 Software must program the CDCE913 for 0pf load capacitance................................................ 39

A.13 Protection diode D2 should be rated for 5V ....................................................................... 39

A.14 PHY address LSB for U9 and U15 can be latched incorrectly .................................................. 40

A.15 3.3V clamp circuit needs more margin ............................................................................. 40

A.16 Current PMIC does not provide the mandated power down sequence ........................................ 40

A.17 Power supply droop may cause board reset ...................................................................... 40

A.18 AM5718 pin N21 must be connected to 1.8V, as it is VDDS18V_DDR1 and not N/C....................... 40

A.19 VOUT1 is used at 3.3V, which violates erratum i920............................................................. 40

Revision History.......................................................................................................................... 41

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List of Figures

1 AM571x IDK EVM - Top View.............................................................................................. 7

2 AM571x IDK EVM - Bottom View.......................................................................................... 8

3 AM571x IDK EVM with Camera Board Installed......................................................................... 9

4 AM571x IDK EVM with LCD Display Assembly Attached ............................................................ 10

5 AM571x IDK EVM Block Diagram ....................................................................................... 11

6 Connections from the TPS6590377 PMIC to the AM571x Processor............................................... 14

List of Tables

1 I2C1/IND_I2C ............................................................................................................... 15

2 I2C2/AM571X_HDMI_DDC ............................................................................................... 15

3 SEEPROM Header......................................................................................................... 16

4 PRU-ICSS Ethernet Ports................................................................................................. 18

5 GPIO Pin Mapping ......................................................................................................... 23

6 Expansion Connector - J21 ............................................................................................... 24

7 I/O Expansion Header Connector - J37................................................................................. 26

8 MicroSD Connector - J15 ................................................................................................. 27

9 Power Jack Connector - J1 ............................................................................................... 27

10 Power Terminal Block Connector - J2................................................................................... 27

11 PRU1ETH0 RJ45 Connector - J3........................................................................................ 28

12 PRU1ETH1 RJ45 Connector - J5........................................................................................ 28

13 PRU2ETH0 RJ45 Connector - J6........................................................................................ 29

14 PRU2ETH1 RJ45 Connector - J8........................................................................................ 29

15 PRU2ETH0 Test Header Connector - J7 ............................................................................... 30

16 PRU2ETH1 Test Header Connector - J4 ............................................................................... 30

17 Camera Connector - J9.................................................................................................... 30

18 GigE RJ45 Connector - J10............................................................................................... 31

19 GigE RJ45 Connector - J12............................................................................................... 31

20 LCD Module FFC Connector - J16....................................................................................... 32

21 Touchscreen Controller FFC Connector - J17 ......................................................................... 32

22 HDMI Standard A-type Connector - J24 ................................................................................ 33

23 CTI-20 JTAG Connector - J18............................................................................................ 33

24 JTAG USB Micro-AB Connector - J19 .................................................................................. 34

25 USB Port 1 USB2.1 Standard A-type Connector - J23................................................................ 34

26 USB Port 2 USB2.1 Micro-AB Connector - J45 ........................................................................ 34

27 CAN Header Connector - J38 ............................................................................................ 35

28 Profibus DB9F Connector - J14.......................................................................................... 35

29 RS-485 Header Connector - J39......................................................................................... 35

30 PCIe Connector – J52..................................................................................................... 36

List of Figures

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About This Manual

This document describes the hardware architecture of the AM571x Industrial Development Kit (IDK) Evaluation Module (EVM) (Part# TMDXIDK571x) that supports the Texas Instruments Sitara™ ARM Cortex®-A15 AM571x processor family.

Glossary

TI Glossary —This glossary lists and explains terms, acronyms, and definitions.

Related Documentation From Texas Instruments

For product information, visit the Texas Instruments website at http://www.ti.com.

SPRS957— AM571x Sitara Processors Silicon Revision 2.0 Data Manual SPRZ436— AM571x Sitara Processors Silicon Errata. Describes the known exceptions to the functional

specifications for the device.

SPRUHZ7— AM571x Sitara Processors Silicon Revision 2.0, 1.0 Technical Reference Manual. Details

the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the device.

Preface

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Read This First

Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

TI E2E™ Online Community— TI's Engineer-to-Engineer (E2E) Community. Created to foster

collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.

TI Embedded Processors Wiki— Texas Instruments Embedded Processors Wiki. Established to help

developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.

Trademarks

Sitara, E2E, Code Composer Studio, SmartReflex are trademarks of Texas Instruments. ARM, Cortex are registered trademarks of ARM Limited. Windows is a registered trademark of Microsoft Corporation.

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Preface

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1 Introduction

1.1 Description

The AM571x IDK is a standalone test, development, and evaluation module that enables developers to write software and develop hardware for industrial control and industrial communications applications. It has been equipped with a TI AM5718 processor and a defined set of features to allow you to experience industrial communication solutions using various serial or Ethernet based interfaces. Using standard interfaces, the AM571x IDK may interface to other processors or systems and act as a communication gateway or controller. In addition, it can directly operate as a standard remote I/O system or a sensor connected to an industrial communication network.

The AM571x IDK contains embedded emulation circuitry to quickly enable developers to begin using this IDK. The embedded emulation logic allows emulation and debug using standard development tools such as the Texas Instruments Code Composer Studio™ integrated development environment (IDE) by simply connecting a USB cable to a Windows®-based computer.

The standard (4-port Ethernet) configuration for the AM571x IDK EVM provides the following functionality:

• Two Gigabit (1000Mb) metallic ports connected via PHY/RGMII to the on-chip Ethernet switch

• Two 100Mb metallic ports connected via PHY/MII to the PRU-ICSS subsystems

• LCD panel output from Display Parallel Interface (DPI) Video Output 1 Reconfiguration through header shunt removal provides an alternate 6-port Ethernet configuration:

• Two Gigabit (1000Mb) metallic ports connected via PHY/RGMII to the on-chip Ethernet switch

• Four 100Mb metallic ports connected via PHY/MII to the PRU-ICSS subsystems Software support for the AM571x IDK EVM is provided within the Processor Software Development Kit

(SDK) package. This includes both Linux and RTOS support.

User's Guide

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AM571x Industrial Development Kit (IDK)

Evaluation Module (EVM) Hardware

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1.2 System View

The system view of the AM571x IDK EVM consists of the main board and the camera board. There is also an optional LCD panel and touch screen assembly that can be attached to the AM571x IDK EVM.

The top and the bottom views of the AM571x IDK EVM are provided in Figure 1 and Figure 2, respectively.

The top view of the AM571x IDK EVM with the camera board installed is provided in Figure 3. The side view of the AM571x IDK EVM with the optional LCD display assembly attached is provided in Figure 4.

Introduction

Figure 1. AM571x IDK EVM - Top View

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Introduction

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Figure 2. AM571x IDK EVM - Bottom View

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Introduction

Figure 3. AM571x IDK EVM with Camera Board Installed

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Introduction

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Figure 4. AM571x IDK EVM with LCD Display Assembly Attached

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AM571x

DDR1

QSPI

RGMII0

MMC1

HDMI / I2C2

PCIe / I2C1

HDMI

PCIe x2

GbE

MMC2

I2C

QSPI

32MB

eMMC

16GB

uSD

EEPROM

USB2.0

MicroAB

I2C

USB2

UART

Camera Header

VIN4B / I2C1

JTAG

(60-pin)

ICs

TI ICs

Connectors

ISO1176T

Profibus

DB9

PRU UART

TPS6590377

PMIC

KSZ9031

DDR3

1GB

w/ECC

Warm RESET

INT

RGY LED ENET Status

GPIO

RGMII1

GbE

KSZ9031

DCAN1

USB1

USB2.0

Std A

FTDI

USB

SN65HVD78D

RS485

Header

UART2

Industrial Inputs &

Outputs/LEDs

SPI3 / I2C1

LCD &

Touch Panel

MIPI

Serializer

VOUT1/PR1_MII0_1

ISO1050

TPD6E001

TPD4S012

TPD2EUSB30

DCAN

Header

TPD12S016

TLK105L

ICSS0

RJ45

TLK105L

ICSS0

RJ45

TLK105L

ICSS1

RJ45

PR2_MII0

TLK105L

ICSS1

RJ45

PR2_MII1

ICSS Header

prx_mii0/1_txen/rxdv,

prx_edio_data_out + sync

FET Switches

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2 Functional Description

The AM571x IDK EVM is implemented on a single board with interface circuitry, memory ICs, and connectors around the AM5718 processor. The board also contains power conversion circuitry to efficiently create the needed power supply voltages from a single +5V input. As stated previously, this EVM ships with a separate camera module that plugs in to the main board. An optional LCD panel and touch screen assembly can be purchased separately and mounted on to the main board.

Figure 5 shows the functional block diagram of the AM571x IDK EVM.

Functional Description

Figure 5. AM571x IDK EVM Block Diagram

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Functional Description

2.1 Processor

The AM5718 processor is the central processing unit for this IDK EVM. The interface circuitry, memory ICs, and connectors implemented on the board around the AM5718 processor provide development support for the many industrial communication interfaces available on this platform. See the AM571x

Sitara Processors Silicon Revision 2.0 Data Manual (SPRS957) and the AM571x Sitara Processors Technical Reference Manual (SPRUHZ7) for details about the processor.

The AM571x IDK EVM contains system configuration for the boot mode control inputs SYSBOOT[15..0]. These can be strapped using resistors. The default configuration will meet the needs of most developers. Resistor reconfiguration is supported so that you can explore other boot configurations of the AM571x processor. See Section 4 for more details.

2.2 Clocks

The main clock for the processor is derived from a 20-MHz crystal. An on-board oscillator in the AM571x processor generates the base clock and the subsequent module clocks as needed within the AM571x processor. The board design supports a crystal attached to the RTC block, but this is not needed since RTC-only mode is not supported in this device.

2.3 Reset Signals

The AM571x processor contains 3 reset inputs and an output indicating a reset is in progress. The reset pins are:

• PORz: PORz is a hard reset that resets everything including emulation logic. It also tri-states most outputs.

• RESETn: RESETn is a device reset commonly driven by control logic or emulation.

• RTC_PORz: Separate PORz for the RTC module that must be driven at the same time as PORz. (Note that PORz and RTC_PORz can only be directly connected as long as VDDSHV3 and VDDSHV5 are driven at the same voltage.)

• RSTOUTn: Output signal from SOC indicating that the device has entered reset. This is used to reset other circuits that must be reset at the same time as the processor.

More details about the behavior of these reset pins within the AM571x processor can be found in the

AM571x Sitara Processors Silicon Revision 2.0 Data Manual (SPRS957). There are push buttons on the

IDK that can initiate either a RESETn or PORz input. SW1 can drive PORz active (low) and SW2 can drive RESETn active (low).

There is a device erratum in all of the AM571x devices that prevents use of RESETn independent from PORz (see i862, Reset Should Use PORz, in the AM571x Sitara Processors Silicon Errata (SPRZ436). The workaround is to generate PORz whenever a device reset occurs even if it is from an internal initiator. This is accomplished through cooperation with the PMIC paired with the AM571x device on the IDK EVM. The RSTOUTn output from the AM571x device is connected to the NRESWARM input of the PMIC. This initiates a re-start that drives RESET_OUT low and resets all voltages to their initial values. Since RESET_OUT from the PMIC is connected to PORz in the AM571x device, a hard reset is forced on the SOC that meets the needs of the erratum workaround.

The AM571x IDK EVM is started by pressing the start-up push button, SW3. The POWERHOLD input can be connected to VRTC_OUT in customer designs to cause the board to power-on as soon as the main supply is stable.

The configuration of the PMIC to provide RESET_OUT from the NRESWARM input creates an always-on implementation. This always-on mode of operation prevents software shut-down of the IDK. Customer designs should have power-good monitoring circuitry such as a TPS3808 connected to the main supply to the PMIC that is connected to the PMIC RESET_IN, as shown in the AM571x IDK EVM schematic (v1.3). The TPS3808 can detect the main supply voltage dropping and then trigger the PMIC to execute a controlled shut-down that meets the requirements in the AM571x Sitara Processors Silicon Revision 2.0

Data Manual (SPRS957).

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3 Power Supplies

This section describes how the power supplies required for the design are generated.

3.1 Power Source

The AM571x IDK EVM uses an external 5V power supply. The 5V power input is converted into different voltage levels to provide power inputs to the AM571x processor and other circuitry.

Early versions of the AM571x IDK EVM shipped with the GlobTek, Inc. external power supply with the part number TR9CA6500LCP-N, model number GT-43008-3306-1.0-T3. This external power supply is rated for an output voltage of +5VDC with an output current up to 6.5A. This external power supply contains applicable regional product regulatory/safety certification requirements for most worldwide locations. If you cannot use this supply, one with equivalent ratings that is approved for your location must be obtained.

The AM571x IDK EVM contains a right angle mounted power connector that accepts the +5VDC supply input on the center pin with the outer shell as the common return. The power connector accepts a mating plug with a 2.5-mm ID and a 5.5-mm OD.

It is recommended that the external power supply have the common return bonded to earth ground. If this is not possible, a separate connection from the board ground to earth ground may need to be provided. Terminal block J53 is added for this purpose.

Power Supplies

3.2 TPS6590377 PMIC

The power requirements of the processor are met by the TPS6590377 Power Management IC (PMIC). The power sequencing requirements of the AM571x processor are also handled by the TPS6590377 PMIC. Figure 6 shows the supply connections from the TPS6590377 PMIC to the AM571x processor.

Refer to the AM571x Sitara Processors Silicon Revision 2.0 Data Manual (SPRS957) for more information about the required supply voltages and supply sequencing. Also refer to the TPS659037 Power

Management Unit (PMU) for Processor Data Manual (SLIS165) and the TPS659037 User's Guide to Power AM572x and AM571x User’s Guide (SLIU011) for details about its operation.

Note that the production version of the AM571x IDK EVM uses the TPS6590377 PMIC that supplies the voltages needed for the latest silicon version of the AM5718 processor. Beta prototype IDK EVM units used the TPS6590375 PMIC and Alpha prototype IDK EVM units used the TPS6590372 PMIC.

3.3 AVS Control

The AM571x processor consumes most of its power in its core logic. Therefore, minimizing the voltage supplied to this core logic can minimize power consumption. SmartReflex™ technology is used to provide this optimized solution.

This core logic is separated into multiple segments that can each be controlled separately. In this way, applications that need more performance in some processing blocks can operate at higher performance levels by increasing the supply voltage, while other processing blocks that do not require the same level of performance can operate at lower voltage thus further optimizing system power consumption.

The TPS6590377 PMIC is connected to the I2C1 on the AM5718 processor. This allows the application software to individually control the AVS supply outputs. It also allows the application to control the voltage generated by LDO1 that is used for the SDIO interface that operates at either 1.8V or 3.3V depending on the operating mode.

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5-V Input

Power

SMPS1, SMPS2

AVS (6 A max)

SMPS4, SMPS5

AVS (4 A max)

SMPS6

AVS (3 A max)

SMPS8

AVS (1 A max)

SMPS7

AVS (2 A max)

LDO9

(50 mA max)

LDOLN

(100 mA max)

LDO3

(200 mA max)

LDOVRTC

(25 mA max)

LDO1

(300 mA max)

LDOUSB

(100 mA max)

SMPS3

(3 A max)

PMIC

TPS659037

TPS51200

5 V

VDD_MPU

VDD_DSPEVE

VDD_GPU VDD_IVAHD VDD_CORE

VDD_RTC

VDDSHV8 (SDIO)

VDDA_USB3V3

VDD_DDR

Dual-Voltage Rails

(set to 3.3 V)

1V8

3V3

5V0

EMIF1 EMIF2

VTT

DDR

Other Domains

Processor

Core Domains

1.06 V

1.15 V

1.05 V

1.06 V

1.35 V or 1.5 V

1.8 V

1.35 V or 1.5 V

1.8 V

3.3 V

1.8 V

0.675 V or 0.75 V

1.8 V

Peripherals

DDR_REF

SMPS9

(1 A max)

LDO2

(300 mA max)

VDDSHV5 (RTC I/O)

3.3 V

VREF

0.675 V or 0.75 V

VDD_1V8

VDDA_1V8 (PLLs)

1V8_PHY (USB/SATA)

VDDA_RTC

1.8-V Domains

1V8_PHY (HDMI/PCIe)

LDO4

(200 mA max)

OSC16MIN

OSC16MOUT

1.8 V

3.3V Input Power

TPS22965

(Power Switch)

REGEN1

Power Supplies

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Figure 6. Connections from the TPS6590377 PMIC to the AM571x Processor

3.4 Other Power Supplies

The AM571x IDK EVM contains 8 other power conversion devices that support the interface and memory circuitry:

• TPS63010 Buck-Boost Converter: This converter generates 5.0V from the main supply input. It supplies this voltage to the industrial interface circuits, the HDMI interface and to the USB master ports.

• TPS61085 Boost Converter: This converter generates 12.0V from the main supply input. It supplies voltage to the industrial interface circuits and the PCIe card connector.

• TPS51200 DDR Termination Voltage LDO (2 each): This LDO provides the push/pull termination current required for the DDR3 memory interfaces. There is one implemented for each DDR3 EMIF.

• LP38693ADJ Low-Dropout Regulator: This LDO generates the 3.7V LCD bias voltage.

• TPS61081DRC LCD Backlight Generator: This Boost converter generates the LCD backlight supply.

• TPS71712 Low-Dropout Regulator: This LDO generates the 1.2V supply needed for the LCD driver logic.

• TPS76650 Low-Dropout Regulator: This LDO generates the 5.0V supply needed for the Profibus interface.

• R1Z-3.305HP Isolated DC-DC Supply: This converter generates 5.0V isolated from the primary

3.3V DC supply on board for the DCAN interface.

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4 Configuration/Setup

This section discusses the board configuration.

4.1 Boot Configuration

Various boot configurations can be set using the pull-up/pull-down resistor combinations provided on the SYSBOOT[15..0] pins. Boot configuration pins are latched upon de-assertion of the PORz pin. Refer to the AM571x Sitara Processors Silicon Revision 2.0 Data Manual (SPRS957) for more details. The AM571x IDK EVM is configured by default to 0x8106 to enable UBOOT/Linux boot from the SDCARD. The secondary boot device selected by this boot mode is QSPI1.

4.2 I2C Address Assignments

The AM571x IDK EVM contains multiple I2C buses connected to a master port on the processor. Each bus contains one or more I2C slave devices that must have unique addresses to prevent contention.

Table 1 and Table 2 list the addresses of the I2C slave devices attached to buses I2C1 and I2C2,

respectively.

I2C Slave Device Address(es)

TPS590377 PMIC, U3 0x58, 0x59, 0x5A, 0x5B, 0x12

Camera Header, J9 Undefined

CDCE913 Ethernet Clock Generator A, U23 0x65

TPIC2810 Industrial Output Driver, U89 0x60

LCD Panel Driver TC358778, U73 0x0E Touchscreen FPC Connector, J17 —

ID Memory SEEPROM, U33 0x50

PCIe Card Connector, J52 Undefined Expansion Connector, J21 Undefined

Configuration/Setup

Table 1. I2C1/IND_I2C

CDCE913 Ethernet Clock Generator B, U25 0x65

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Table 2. I2C2/AM571X_HDMI_DDC

I2C Slave Device Address(es)

HDMI Bridge, U46 —

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Configuration/Setup

4.3 SEEPROM Header

Each of the AM571x IDK EVMs has a unique serial number. This serial number is printed on a sticker attached to the IDK and it is programmed into a SEEPROM memory device connected to the AM5718 processor over the I2C bus. The SEEPROM also contains board details such as board type, version, configuration, and so on. This information is stored in a structure at the beginning of the SEEPROM in a known format that can be read by the application software. These values are all stored with the first character or MSB stored at the lowest addressable location in each field. Table 3 lists all of the fields in this header definition.

Name Size (bytes) Contents

Header 4 MSB 0xEE3355AA LSB Board Name 8 Name for board in ASCII “AM571IDK” = AM571x Industrial Development Kit EVM. Version 4 Hardware version code for board in ASCII “1.3A” = revision 01.3A Serial Number 12 Serial number of the board. This is a 12-character string that is: WWYY4P52nnnn, where

Configuration Option 32 Codes to show the configuration setup on this board. Reserved. Ethernet MAC

Address #0 Ethernet MAC

Address #5 Available 32696 Available user space for other non-volatile codes/data.

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Table 3. SEEPROM Header

WW = 2 digit week of the year of production, YY = 2 digit year of production, nnnn = incrementing board number.

6 Ethernet MAC Address #0 assigned to the AM571x IDK EVM. This is the first of a block of

addresses available for the Industrial Interface ports.

6 Ethernet MAC Address #5 assigned to the AM571x IDK EVM. This is the last of a block of

6 contiguous addresses available for the industrial interface ports.

4.4 JTAG Emulation

The AM571x IDK EVM supports embedded XDS100V2 USB Emulation through the USB Micro-AB connector, J19, and the FTDI controller. This controller is powered from the USB VBUS, thus the emulator connection to the PC is retained whenever the IDK is power cycled.

The AM571x IDK EVM also has a 20-pin CTI JTAG connector, J18, to support standard external emulators that may operate more efficiently than the embedded XDS100V2 emulation. The AM571x IDK EVM does not support emulation trace capability.

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5 Memories Supported

The AM571x IDK EVM supports on-board memories including DDR3L SDRAM, SPI NOR Flash, eMMC NAND Flash, and I2C SEEPROM. It also supports a MicroSD card socket that can add memory storage.

5.1 DDR3L SDRAM

The AM571x IDK EVM design supports a single bank of DDR3L SDRAM that is attached to the EMIF on the AM5718 processor. The EMIF can support up to 2GB of DDR3L SDRAM memory at speeds up to 1333MT/s. The SDRAM implemented on the EMIF on the IDK EVM contains two 4Gbit (256M × 16) SDRAMs for a total of 1GB of DDR3L SDRAM memory. The part number for the DDR3L SDRAM memory used is MT41K256M16HA-125 that contains timing for 1600MT/s operation. The package used is the 96ball TFBGA package. See the AM571x Sitara Processors Technical Reference Manual (SPRUHZ7) for memory locations for this memory.

The EMIF also contains an SDRAM attached to the ECC byte lane. Use of ECC on the DDR3L interface is currently highly constrained by limitations in the AM571x devices. Refer to the AM571x Sitara Processors

Silicon Errata (SPRZ436) for more details.

5.2 SPI NOR Flash

The AM571x IDK EVM supports a 256Mbit (32MB) SPI Flash Memory from Spansion (S25FL256S) in a 16-pin SOIC package. It is connected to the QSPI port of the AM5718 device.

5.3 Board Identity Memory

Each of the AM571x IDK EVM boards contains a 256Kb (32KB) Serial EEPROM that contains boardspecific data. This data allows the application software to automatically detect the type of board that it is running on and also to determine its version and, potentially, optional features. Other hardware specific data can be stored on this memory device as well. The part number of the memory device is CAT24C256WI-G in a SOIC-8 package. Refer to Section 4 for details on the data stored in this memory.

Memories Supported

5.4 SD/MMC

The SD/MMC connector on the AM571x IDK EVM is a MicroSD connector (part number SCHA5B0200). This is a standard SD/MMC card type of connector. It is connected to the MMC1 port of the AM571x processor that is optimized for this use. Refer to the AM571x Sitara Processors Silicon Revision 2.0 Data

Manual (SPRS957) and the AM571x Sitara Processors Technical Reference Manual (SPRUHZ7) for

supported card types and densities. The SDWP input pin to the MMC1 port is connected to a 2-pin header, J44. The default state has the pin

pulled high. Shorting the header pulls the pin low. The polarity of this input is programmable; thus, the hardware does not define whether a high or low level indicates Write Protest is active or not.

The transient protection implemented at the SDCARD connector is the TPD6E001.

5.5 eMMC NAND Flash

The MMC2 port on the AM571x processor supports eMMC memory devices, since it has 8 data lines. The eMMC footprint is compliant with the JEDEC/MMC standard. Boards have been assembled and successfully tested with the Kingston EMMC16G-S100 and the Micron MTFC16GAKAECN-2M WT. These are 16GB eMMC NAND Flash memories that are standard version 5.0 compliant.

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Ethernet Ports

6 Ethernet Ports

The AM571x IDK EVM supports up to four 100Mb Industrial Ethernet ports attached to the PRU-ICSS subsystems and up to two Gigabit (1000Mb) Ethernet ports connected to the integrated Ethernet switch. The final number of available ports depends on the configuration selection:

• 4-port Ethernet mode: provides two 100Mb Industrial Ethernet ports and two Gigabit (1000Mb) Ethernet ports.

• 6-port Ethernet mode: provides four 100Mb Industrial Ethernet ports and two Gigabit (1000Mb) Ethernet ports.

Selection between these Ethernet modes is controlled by header J51. Installing a shunt on header J51 that shorts these pins together enables 4-port Ethernet mode. Removing the shunt from these pins enables 6-port Ethernet mode. The LCD output is only available when 4-port Ethernet mode is selected.

6.1 100Mb Ethernet Ports on PRU-ICSS

The AM571x IDK EVM contains four 100Mb Ethernet ports that each connect to an industrial PHY/Transceiver (TLK105L), which then connect to RJ45 metallic connectors, with integrated magnetics, J3, J5, J6, and J8. These Ethernet transceivers are connected to the PRU1 and PRU2 subsystems within the AM5718 processor. Table 4 shows the mapping from the PRU-ICSS ports to the RJ45 connectors.

The COL functionality on the MII interface is not used. The TLK105L contains a feature that must be enabled via software that provides rapid link status on the COL pin. Therefore, this pin is connected to the RXLINK input to the PRU-ICSS ports for this purpose.

Test headers J4 and J7 are available to support real-time code development. The signals contained are available for simplified probing.

The reset for the transceivers is driven low coincident with the PORz reset to the AM5718 processor. The reset for each transceiver can also be driven low individually by separate GPIO signals from the processor. A 25-MHz clock is provided into each of the TLK105L industrial transceivers.

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Table 4. PRU-ICSS Ethernet Ports

Connector PRU-ICSS Port MDIO Address Notes

J3 PRU1ETH0 0x0 on PRU1 Not available in all configuration selections. MII pins multiplexed with VOUT1

J5 PRU1ETH1 0x1 on PRU1 Not available in all configuration selections. MII pins multiplexed with VOUT1

J6 PRU2ETH0 0x0 on PRU2 J8 PRU2ETH1 0x1 on PRU2

6.2 Gigabit (1000Mb) Ethernet Ports

The AM571x IDK EVM contains two Gigabit (1000Mb) Ethernet PHY/Transceivers (KSZ9031RN) interfaced to connectors J10 (RGMII0) and J12 (RGMII1). These Gigabit Ethernet transceivers are connected over RGMII0 and RGMII1 to the Ethernet switch block within the AM5718 processor.

The resets for the transceivers are driven low coincident with the PORz reset to the AM5718 processor. A 25-MHz clock is provided into each of the KSZ9031RN Gigabit transceivers.

to the LCD bridge.

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7 USB Ports

The AM571x IDK EVM contains three USB ports. Two ports are attached to the USB peripherals USB1 and USB2 on the AM5718 processor. The third port provides both XDS100V2 JTAG emulation and UART Console over the USB. This port simplifies the development environment for programmers using computers that support this capability such as Windows®-based computers.

7.1 Processor USB Port 1

Processor port USB1 is implemented only as a USB host (master). It supports only the USB2.1 (high speed and lower) data rates. The connector on the board, J23, is a USB2.1 Standard A-type connector. The ESD devices implemented on this USB port are the TPD2EUSB30 for the DP and DM lines.

Since processor USB port 1 supports host mode, it has the capability to drive 5.0V power on the VBUS pin. The TPS2065D load switch is controlled by the USB1_DRVVBUS pin for this purpose.

7.2 Processor USB Port 2

Processor port USB2 is implemented as either USB host (master) or USB device (slave). It supports only the USB2.1 (high speed and lower) data rates. The connector on the board, J45, is a USB2.1 Micro-AB connector. The ESD device implemented on this USB port is the TPD4S012.

Since processor USB port 2 supports host mode, it has the capability to drive 5.0V power on the VBUS pin. The TPS2051 load switch is controlled by the USB2_DRVVBUS pin for this purpose.

The USB2.1 standard defines different ranges of capacitance for the VBUS pin depending on whether it is host or device. Since this port can do either, the AM571x IDK EVM provides the capability to meet either requirement. The VBUS pin from the connector contains a 4.7µF capacitor that is appropriate for device mode operation. When operating in host mode, 2-pin header J50 can be shorted to add 150µF of additional capacitance to the VBUS pin. The shunt for this header is shown on the schematic as M2. It is not installed on units when shipped as we expect this port to primarily be used in device mode.

USB Ports

7.3 FTDI USB Port

The FTDI bridge device provides both XDS100V2 JTAG emulation and UART Console over the USB. The connector on the board, J19, is a USB Micro-AB connector but it only operates in device (slave) mode with the FTDI bridge device. The ESD device implemented on this USB port to the FTDI bridge is the TPD2E001. Refer to Section 4.4 for more details on this functionality.

The FTDI USB device is implemented so that it operates from the VBUS power provided over the USB cable. This allows the FTDI device to remain fully operational during an AM571x IDK EVM power cycle. This in turn allows the console port to the PC to remain active to allow logging from the serial port immediately as the AM5718 device boots. It also provides faster re-connect for the XDS100V2 JTAG emulator.

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PCIe

8 PCIe

The AM571x processors contain two lanes of peripheral component interconnect express (PCIe). These can be implemented either as a single, dual-lane port or as two single-lane ports. The PCIe peripheral can be configured to either be a Root Complex (master) or an Endpoint (slave). The AM571x IDK EVM implements a single dual-lane port as a Root Complex. The AM571x IDK EVM terminates this dual-lane port in a ×4 PCIe female connector that accepts standard PCIe Endpoint cards.

A 2-pin header, J49, is available to provide the 3V3_AUX power separate from the primary 3V3 supply. This is needed for some cards and PCIe driver configurations. The shunt, shown on the schematic as M1, should be installed when the board is received since 3V3_AUX will be needed in most cases. Please refer to the documentation for the card being installed to determine whether this shunt should remain installed.

The PERSTn reset for the connector is driven low coincident with the PORz reset to the AM5718 processor. The PERSTn reset to the connector can also be driven low by a GPIO signal from the processor. This reset can also be blocked by a GPIO signal from the processor.

A 100-MHz clock is provided separately to both the PCIe peripheral and to the PCIe connector. These clocks are buffered outputs from the same low-jitter source.

The AM571x IDK EVM is compatible with standard PCIe plug-in cards but not fully compliant with the PCIe CEM standard. It does not support hot-plug and also does not provide sufficient current on the 3.3V and 12V pins for all plug-in cards. It is currently limited to about 0.5A on each supply.

9 Video Input and Output

The AM571x processor family supports industrial video capture and display in addition to its industrial communications capabilities. The AM571x IDK EVM contains a camera header for attaching a module containing a camera sensor as well as support for an LCD panel display and HDMI video output.

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9.1 Camera

The AM571x IDK EVM supports a camera daughterboard that attaches to a 24-pin (2 × 24) header, J9. The custom-designed camera module from TI, previously designed for the AM437x IDK EVM, mounts on this header. This header is connected to VIN4B on the AM5718 processor.

The 2Mp camera board contains the Darling Industrial camera module (part number DC-OVBD420AH). The camera module contains the OmniVision OV2659 camera sensor. Please contact OmniVision for the latest documentation on this sensor.

9.2 HDMI

The AM571x IDK EVM supports an HDMI connector driven from the HDMI port on the AM5718 processor. The connector on the board, J24, is an HDMI Standard A-type connector. It is implemented with the TPD12S016 HDMI companion chip. This companion chip provides I2C level shifting buffers, 5V load switch, and multi-channel ESD protection.

9.3 LCD

The AM571x IDK EVM is available with an optional LCD panel that also has a capacitive touch overlay. The video output driven for the LCD panel from the AM5718 processor is on VOUT1. A MIPI bridge device from Toshiba, TC358778, is implemented to convert from the 24-bit RGB presented on the VOUT1 pins to serial MIPI RGB streams. The LCD panel is shipped with FPC cables that plug into J16 for the MIPI video and into J17 for the touchscreen controller. Both the MIPI bridge device and the touchscreen controller are connected to the IND_I2C chain from processor port I2C1.

The LCD output functionality is available only when the AM571x IDK EVM is configured for the 4-port Ethernet mode. When the AM571x IDK EVM is configured for the 6-port Ethernet mode, the LCD output is no longer available since the same pins on the AM5718 device are used for both functions.

NOTE: Installing a shunt on header J51 that shorts these pins together enables 4-port Ethernet

mode. Removing the shunt from these pins enables 6-port Ethernet mode.

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10 Industrial Interfaces

There are additional industrial interfaces implemented on the AM571x IDK EVM to help showcase the flexibility of the AM57xx line of processors.

10.1 Profibus

A compliant Profibus interface is implemented using the ISO1176T isolation device, transformer and TPS76650 LDO regulator. This circuit terminates to a DB9F connector, J14. This Profibus interface is driven by UART0 from the first PRU-ICSS block, PR1.

10.2 DCAN

The AM5718 processor contains two Controller Area Network (DCAN) interfaces. DCAN port 1 is routed out to the ISO1050 isolation device and then to the 5-pin header, J38. The R1Z-3.305HP isolated DC-DC supply provides an isolated 3.3V supply for this DCAN interface.

10.3 RS-485

The AM571x IDK EVM contains an RS-485 interface on 3-pin header, J39. This is enabled by the SN65HVD78D Half-Duplex RS-485 Transceiver. The transceiver controls the half-duplex communication and also provides high-voltage transient protection. This interface is attached to the SOC-level UART2 port for RX and TX data. The UART TX data line is monitored by PR2_PRU1, so that PRU code can monitor TX activity and then control the DE and REn lines into the transceiver.

Industrial Interfaces

11 User Interfaces

The AM571x IDK EVM contains GPIO expanders that provide industrial inputs and outputs to support development. The outputs contain LEDs for immediate feedback. There are also tri-color LEDs connected to GPIOs to support development.

11.1 Tri-color LEDs

There are 6 tri-color LEDs connected to SOC GPIO pins that can be used to support development. There is a separate GPIO assigned for each color: red, green, and yellow. Color mixing by turning on more than one GPIO at a time will not provide the expected result since the separate colors have different intensities due to the physics of the LED composition. Tri-color LEDs D16, D17, D18, and D19 are designated Industrial LEDs. Tri-color LEDs D22 and D23 are designated Status LEDs.

11.2 Industrial Inputs

For industrial 24v digital inputs, an SN65HVS882 Digital-input Serializer for industrial digital inputs is used to accept standard signals from the 30-pin (15 × 2) I/O Expansion Header, J37. The input values are clocked into the SPI3 port of the AM5718 processor.

11.3 Industrial Outputs / LEDs

I2C to 8-bit LED driver TPIC2810 is used to drive the eight Industrial output LEDs D5 to D12. The I2C interface is connected to the I2C1 port of the AM5718 processor along with the other devices on the IND_I2C bus. The eight LED driver outputs are also driven to the I/O Expansion Header, J37. All the LEDs are green in color.

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Pin Use Description

12 Pin Use Description

12.1 Functional Interface Mapping

Some signals of the AM5718 device are connected to a fixed device on the EVM where it cannot be changed. However, some of the signals of the AM5718 device are connected to devices on the AM571x IDK EVM based on the profile setting.

12.2 GPIO Pin Mapping

The developer can enable GPIO pins individually, as needed, as output, input, or both. Most of the LVCMOS pins not currently allocated for other peripheral use can be defined as GPIO pins. Table 5 is a compliment to the schematic and the recommended settings in the pinmux tool. Each of the defined GPIO pins are listed along with the associated pin name and ball number and mode. The last column lists the available physical pull-up (PU) or pull-down (PD) resistor attached or the recommended internal pull-up or pull-down resistor defined in the pinmux file provided for the AM571x IDK EVM.

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Pin Use Description

Table 5. GPIO Pin Mapping

Pin Name GPIO # Pin # IDK Net Name / Function Direction

MCASP2_AXR4 GPIO1_4 D15 AM57XX_INDETHER_LED0_YEL Output EXT PD MCASP2_AXR7 GPIO1_5 A17 AM57XX_INDETHER_LED1_YEL Output EXT PD

GPMC_CS0 GPIO2_19 T1 AM57XX_STATUSLED1_YEL Output EXT PD GPMC_CS3 GPIO2_21 P1 AM57XX_STATUSLED1_GRN Output EXT PD GPMC_CLK GPIO2_22 P7 6PORT_LCDn Input EXT PU

GPMC_ADVN_ALE GPIO2_23 N1 GPIO_IND_LDn Output EXT PU

GPMC_OEN_REN GPIO2_24 M5 GPIO_VPP_PWR_EN Output EXT PD

GPMC_WEN GPIO2_25 M3 AM57XX_STATUSLED0_RED Output EXT PD GPMC_BEN0 GPIO2_26 N6 AM57XX_STATUSLED0_GRN Output EXT PD GPMC_BEN1 GPIO2_27 M4 AM57XX_STATUSLED0_YEL Output EXT PD

GPMC_WAIT0 GPIO2_28 N2 AM57XX_STATUSLED1_RED Output EXT PD

MCASP2_AXR6 GPIO2_29 B17 AM57XX_INDETHER_LED1_GRN Output EXT PD

VIN2A_CLK0 GPIO3_28 E1 PRU1ETH0_INTn Input INT PU

VIN2A_DE0 GPIO3_29 G2 PRU1ETH1_INTn Input INT PU

VIN2A_FLD0 GPIO3_30 H7 PRU2ETH0_INTn Input INT PU

VIN2A_HSYNC0 GPIO3_31 G1 PRU2ETH1_INTn Input INT PU VIN2A_VSYNC0 GPIO4_0 G6 AM57XX_INDETHER_LED0_GRN Output EXT PD

VOUT1_FLD GPIO4_21 B11 eMMC_RSTn Output EXT PU

MCASP1_ACLKR GPIO5_0 B14 GB_ETH0_INTn Input EXT PU

MCASP1_FSR GPIO5_1 J14 GB_ETH1_INTn Input EXT PU MCASP1_AXR2 GPIO5_4 G13 PCIE_CRDPRESENT Input EXT PU MCASP1_AXR3 GPIO5_5 J11 PCIE_WAKEn Input EXT PU MCASP1_AXR4 GPIO5_6 E12 TOUCH_INT Input INT PU MCASP1_AXR5 GPIO5_7 F13 GPIO_AM571X_USB2_ID I/O EXT PU MCASP1_AXR6 GPIO5_8 C12 GPIO_PRU1_ETH_RESETn Output EXT PU MCASP1_AXR7 GPIO5_9 D12 GPIO_PRU2_ETH_RESETn Output EXT PU

UART3_RXD GPIO5_18 V2 GPIO_PCIE_SWRSTn Output INT PU UART3_TXD GPIO5_19 Y1 GPIO_PCIE_RSTDRVn Output INT PU

MCASP2_AXR5 GPIO6_7 B16 AM57XX_INDETHER_LED1_RED Output EXT PD

GPIO6_14 GPIO6_14 E21 CAM_ENn Output PU/PD on camera

GPIO6_15 GPIO6_15 F20 GPIO_TOUCH_RESETn Output EXT PU GPIO6_16 GPIO6_16 F21 PMIC_INT Input INT PU

XREF_CLK2 GPIO6_19 B26 AM57XX_INDETHER_LED0_RED Output EXT PD

SPI1_SCLK GPIO7_7 A25 AM57XX_AUDIOBUZZER_TRIG Output EXT PD

SPI1_D1 GPIO7_8 F16 AM57XX_INDETHER_LED2_GRN Output EXT PD

SPI1_D0 GPIO7_9 B25 AM57XX_INDETHER_LED2_RED Output EXT PD SPI1_CS0 GPIO7_10 A24 AM57XX_INDETHER_LED2_YEL Output EXT PD SPI1_CS1 GPIO7_11 A22 AM57XX_INDETHER_LED3_RED Output EXT PD

UART1_RXD GPIO7_22 B27 GPIO_USB2_VBUS_DET Input EXT PU UART1_CTSN GPIO7_24 E25 AM57XX_INDETHER_LED3_YEL Output EXT PD UART1_RTSN GPIO7_25 C27 AM57XX_INDETHER_LED3_GRN Output EXT PD

Pull Up /

Pull Down

board

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Board Connectors

13 Board Connectors

This section shows the pin-outs for the connectors on the AM571x IDK EVM.

Pin Signal Name Secondary Signal Name

1 V3_3D — 2 V5_0D — 3 AM571X_PRU1ETH1_COL PR1_EDC_LATCH0 4 GPMC_CS0 ETH_MDIO_CLK 5 PR1_MII1_CRS — 6 GPMC_CS3 ETH_MDIO_DATA 7 PR1_MII1_MR1_CLK — 8 GPMC_ADVN_ALE UART1_TXD

9 PR1_MII1_RXDV — 10 GPMC_OEN_REN UART1_TXD 11 PR1_MII1_RXD3 — 12 GPMC_WEN PR1_MII0_RXER 13 PR1_MII1_RXD2 PR2_EDC_LATCH0 14 GPMC_BEN0 PR1_MII0_RXLINK 15 PR1_MII1_RXD1 PR2_EDC_LATCH1 16 GPMC_BEN1 PR1_MII0_COL 17 PR1_MII1_RXD0 PR2_EDC_SYNC0 18 AM57XX_PRU2ETH1_CRS AM571X_RGMII0_TXCLK 19 PR1_MII_MT0_CLK PR2_EDC_SYNC1 20 AM57XX_PRU2ETH1_COL AM571X_RGMII0_TXCTL 21 PR1_MII0_TXD3 — 22 DGND — 23 PR1_MII0_TXD2 — 24 SPI2_SCLK AM571X_RGMII0_TD0 25 SYS_RESETn — 26 SPI2_DIN AM571X_RGMII0_TD1 27 IND_I2C_SCL — 28 SPI2_DOUT AM571X_RGMII0_TD2 29 IND_I2C_SDA — 30 SPI2_CS0n AM571X_RGMII0_TD3 31 AM57XX_GPMC_AD0 PR1_MII0_TXEN 32 AM57XX_GPMC_AD8 AM571X_VIN2A_CLK0 33 AM57XX_GPMC_AD1 PR1_MII0_TXD1 34 AM57XX_GPMC_AD9 AM571X_VIN2A_DE0 35 AM57XX_GPMC_AD2 PR1_MII0_TXD0 36 AM57XX_GPMC_AD10 AM571X_VIN2A_FLD0 37 AM57XX_GPMC_AD3 PR1_MII_MR0_CLK 38 AM57XX_GPMC_AD11 AM571X_VIN2A_HSYNC0 39 DGND — 40 DGND — 41 CAN1_RXDF — 42 AM57XX_GPMC_AD12 AM571X_VIN2A_VSYNC0 43 CAN1_TXDF — 44 AM57XX_GPMC_AD13 AM57XX_PR1_UART0_RXD

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Table 6. Expansion Connector - J21

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Table 6. Expansion Connector - J21 (continued)

Pin Signal Name Secondary Signal Name

45 PR1_MII0_RXDV — 46 AM57XX_GPMC_AD14 AM57XX_PR1_UART0_TXD 47 PR1_MII0_RXD3 — 48 AM57XX_GPMC_AD15 AM571X_VIN2A_D2 49 AM57XX_PR2_PROFI_TXEN — 50 HDQ AM571X_RGMII0_RXCLK 51 AM57XX_GPMC_AD4 PR1_MII0_RXD2 52 GPMC_WAIT0 — 53 AM57XX_GPMC_AD5 PR1_MII0_RXD1 54 AM571X_PRU1ETH1_TXD1 AM57XX_PRU2ETH0_CRS 55 AM57XX_GPMC_AD6 PR1_MII0_RXD0 56 AM571X_PRU1ETH1_TXD0 AM57XX_PRU2ETH0_COL 57 AM57XX_GPMC_AD7 — 58 GPMC_CLK — 59 DGND — 60 DGND —

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Table 7. I/O Expansion Header Connector - J37

Pin Signal Name

1 INDUS_INPUT0 2 V12_0D 3 INDUS_INPUT1 4 V12_0D 5 INDUS_INPUT2 6 V12_0D 7 INDUS_INPUT3 8 V12_0D

9 INDUS_INPUT4 10 V12_0D 11 INDUS_INPUT5 12 V12_0D 13 INDUS_INPUT6 14 V12_0D 15 INDUS_INPUT7 16 V12_0D 17 DGND 18 No Connect 19 DRAIN0 20 DRAIN1 21 DRAIN2 22 DRAIN3 23 DRAIN4 24 DRAIN5 25 DRAIN6 26 DRAIN7 27 V5_0D 28 V5_0D 29 DGND 30 DGND

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Board Connectors

Table 8. MicroSD Connector - J15

Pin Pin Name Signal Name

1 DAT2 MMC_D2 2 DAT3 MMC_D3 3 CMD MMC_CMD 4 VDD V3_3D 5 CLOCK MMC_CLK 6 DGND VSS 7 DAT0 MMC_D0 8 DAT1 MMC_D1

9 GND DGND 10 CD MMC1_SDCD 11 GND3 DGND 12 GND4 DGND 13 GND5 DGND 14 GND6 DGND 15 GND7 DGND 16 GND8 DGND

Table 9. Power Jack Connector - J1

Pin Signal Name

1 VPWRIN_JCK 2 DGND 3 DGND

Table 10. Power Terminal Block Connector - J2

Pin Signal Name

1 VPWRIN_JCK 2 DGND

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Table 11. PRU1ETH0 RJ45 Connector - J3

Pin Pin Name Signal Name

1 RD+ PRU1ETHER0_RDP

2 RD- PRU1ETHER0_RDN

3 RCT V3_3D

4 TCT V3_3D

5 TD+ PRU1ETHER0_TDP

6 TD- PRU1ETHER0_TDN

7 N/C No connect

8 AC GND DGND

9 YEL LED Anode V3_3D 10 YEL LED Cathode RXLINK 11 GRN LED Anode V3_3D 12 GRN LED Cathode PRU1ETH0_LINKLED

SHLD1 Shield AGNDFRAME_PRU1ETH0 SHLD2 Shield AGNDFRAME_PRU1ETH0

Table 12. PRU1ETH1 RJ45 Connector - J5

Pin Pin Name Signal Name

1 RD+ PRU1ETHER1_RDP

2 RD- PRU1ETHER1_RDN

3 RCT V3_3D

4 TCT V3_3D

5 TD+ PRU1ETHER1_TDP

6 TD- PRU1ETHER1_TDN

7 N/C No connect

8 AC GND DGND

9 YEL LED Anode V3_3D 10 YEL LED Cathode RXLINK 11 GRN LED Anode V3_3D 12 GRN LED Cathode PRU1ETH1_LINKLED

SHLD1 Shield AGNDFRAME_PRU1ETH1 SHLD2 Shield AGNDFRAME_PRU1ETH1

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Table 13. PRU2ETH0 RJ45 Connector - J6

Pin Pin Name Signal Name

1 RD+ PRU2ETHER0_RDP

2 RD- PRU2ETHER0_RDN

3 RCT V3_3D

4 TCT V3_3D

5 TD+ PRU2ETHER0_TDP

6 TD- PRU2ETHER0_TDN

7 N/C No connect

8 AC GND DGND

9 YEL LED Anode V3_3D 10 YEL LED Cathode RXLINK 11 GRN LED Anode V3_3D 12 GRN LED Cathode PRU2ETH0_LINKLED

SHLD1 Shield AGNDFRAME_PRU2ETH0 SHLD2 Shield AGNDFRAME_PRU2ETH0

Table 14. PRU2ETH1 RJ45 Connector - J8

Pin Pin Name Signal Name

1 RD+ PRU2ETHER1_RDP

2 RD- PRU2ETHER1_RDN

3 RCT V3_3D

4 TCT V3_3D

5 TD+ PRU2ETHER1_TDP

6 TD- PRU2ETHER1_TDN

7 N/C No connect

8 AC GND DGND

9 YEL LED Anode V3_3D 10 YEL LED Cathode RXLINK 11 GRN LED Anode V3_3D 12 GRN LED Cathode PRU2ETH1_LINKLED

SHLD1 Shield AGNDFRAME_PRU2ETH1 SHLD2 Shield AGNDFRAME_PRU2ETH1

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Table 15. PRU2ETH0 Test Header Connector - J7

Pin Signal Name Net Name

1 RT2_MII0_TXEN AM57XX_PRU2ETH0_TXEN

2 RT2_MII0_RXDV AM57XX_PRU2ETH0_RXDV

3 RT2_MII0_EDIO_DATA0 AM571X_VIN2A_VSYNC0

4 RT2_MII0_EDIO_DATA1 AM57XX_PR1_UART0_TXD

5 DGND —

Table 16. PRU2ETH1 Test Header Connector - J4

Pin Signal Name Net Name

1 RT2_MII1_TXEN PRU2ETH1_TXEN

2 RT2_MII1_RXDV PRU2ETH1_RXDV

3 RT2_MII1_EDIO_DATA0 AM57XX_VIN2A_HSYNC0

4 RT2_MII1_EDIO_DATA1 AM57XX_VIN2A_DE0

5 DGND DGND

Table 17. Camera Connector - J9

Pin Pin Name Signal Name

1 Power VMAIN

2 CAM1_VSYNC DGND

3 CAM1_DATA0 AM571X_VIN4B_DATA0

4 CAM1_HSYNC —

5 CAM1_DATA1 AM571X_VIN4B_DATA1

6 CAM1_DATA6 AM571X_VIN4B_DATA6

7 CAM1_DATA2 AM571X_VIN4B_DATA2

8 CAM1_DATA7 AM571X_VIN4B_DATA7

9 CAM1_PCLK AM571X_VIN4B_PCLK 10 No Connect — 11 GND DGND 12 GND DGND 13 CAM1_DATA3 AM571X_VIN4B_DATA3 14 No Connect — 15 CAM1_DATA4 AM571X_VIN4B_DATA4 16 CAM1_GIO0 PU to V3_3D 17 CAM1_WEN AM571X_VIN4B_DATA5 18 CAM1_GIO1 CAM_ENn 19 CAM1_DATA5 AM571X_VIN4B_DE 20 CAM1_FIELD AM571X_VIN4B_FLD 21 GND DGND 22 I2C_SCL IND_I2C_SCL 23 Clock 20.000 MHz Osc Out 24 I2C_SDA IND_I2C_SDA

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Board Connectors

Table 18. GigE RJ45 Connector - J10

Pin Pin Name Signal Name

1 CH-GND DGND

2 VCC No connect

3 MX3+ ETHER0_D3P

4 MX3- ETHER0_D3N

5 MX2+ ETHER0_D2P

6 MX2- ETHER0_D2N

7 MX1+ ETHER0_D1P

8 MX1- ETHER0_D1N

9 MX0+ ETHER0_D0P 10 MX0- ETHER0_D0N 11 RT GRN Anode PU to PHY0_LED_ACTn 12 RT YEL Anode DGND 13 LEFT GRN Anode DGND 14 LEFT YEL Anode PU to PHY0_LED_LINKn

SHLD1 Shield AGND_GBETH0 SHLD2 Shield AGND_GBETH0

Table 19. GigE RJ45 Connector - J12

Pin Pin Name Signal Name

1 CH-GND DGND

2 VCC No connect

3 MX3+ ETHER1_D3P

4 MX3- ETHER1_D3N

5 MX2+ ETHER1_D2P

6 MX2- ETHER1_D2N

7 MX1+ ETHER1_D1P

8 MX1- ETHER1_D1N

9 MX0+ ETHER1_D0P 10 MX0- ETHER1_D0N 11 RT GRN Anode PU to PHY1_LED_ACTn 12 RT YEL Anode DGND 13 LEFT GRN Anode DGND 14 LEFT YEL Anode PU to PHY1_LED_LINKn

SHLD1 Shield AGND_GBETH1 SHLD2 Shield AGND_GBETH1

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Table 20. LCD Module FFC Connector - J16

Pin Pin Name Signal Name

1 — No Connect

2 — No Connect

3 VCC V3_7LCD

4 VCC V3_7LCD

5 VCC V3_7LCD

6 — No Connect

7 GND DGND

8 MIPI_LN3_N LCD_MIPI3N

9 MIPI_LN3_P LCD_MIPI3P 10 GND DGND 11 MIPI_LN2_N LCD_MIPI2N 12 MIPI_LN2_P LCD_MIPI2P 13 GND DGND 14 MIPI_LN1_N LCD_MIPI1N 15 MIPI_LN1_P LCD_MIPI1P 16 GND DGND 17 MIPI_LN0_N LCD_MIPI0N 18 MIPI_LN0_P LCD_MIPI0P 19 GND DGND 20 MIPI_CLK_N LCD_CLKN 21 MIPI_CLK_P LCD_CLKP 22 GND DGND 23 LED_CATHODE VLED24 LED_CATHODE VLED25 LED_CATHODE VLED26 LED_CATHODE VLED27 LED_CATHODE VLED28 LED_CATHODE VLED29 LED Anode Supply VLED+ 30 LED Anode Supply VLED+ 31 — No Connect 32 — No Connect

Table 21. Touchscreen Controller FFC Connector - J17

Pin Pin Name Signal Name

1 SDA IND_I2C_SDA

2 SCL IND_I2C_SCL

3 TSC_RESETn GPIO_TOUCH_RESETn

4 TSC_INT TOUCH_INT

5 V+ V3_3D

6 GND DGND

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Board Connectors

Table 22. HDMI Standard A-type Connector - J24

Pin Pin Name Signal Name

1 DAT2+ HDMI_TX2+

2 DAT2_S DGND

3 DAT2- HDMI_TX2-

4 DAT1+ HDMI_TX1+

5 DAT1_S DGND

6 DAT1- HDMI_TX1-

7 DAT0+ HDMI_TX0+

8 DAT0_S DGND

9 DAT0- HDMI_TX010 CLK+ HDMI_CLK+ 11 CLK_S DGND 12 CLK- HDMI_CLK13 CEC HDMICONN_CEC 14 N/C No Connect 15 SCL HDMICONN_I2CSCL 16 SDA HDMICONN_I2CSDA 17 DDC/CEC GND DGND 18 +5V V5_0HDMICONN 19 HPLG HDMICONN_HPLG

MTG1 Shield DGND MTG2 Shield DGND MTG3 Shield DGND MTG4 Shield DGND

Table 23. CTI-20 JTAG Connector - J18

Pin Pin Name Signal Name

1 TMS JTAG_TMS

2 TRSTn JTAG_TRSTn

3 TDI JTAG_TDI

4 TDIS PD to GND

5 TVDD PU to V3_3D

6 PU to V3_3D —

7 TDO JTAG_TDO

8 DGND —

9 TCKRTN RTCK 10 DGND EMU_DET 11 TCK JTAG_TCK 12 DGND — 13 EMU0 JTAG_EMU0 14 EMU1 JTAG_EMU1 15 SRST EMU_RSTn 16 DGND — 17 EMU2 No Connect 18 EMU3 No Connect 19 EMU4 No Connect 20 DGND —

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Table 24. JTAG USB Micro-AB Connector - J19

Pin Pin Name Signal Name

1 VBUS VUSB_JTAG

2 DM EMU_USB_DM

3 DP EMU_USB_DP

4 ID No Connect

5 GND DGND S1 S1 GNDUSBJ S2 S2 GNDUSBJ S3 S3 GNDUSBJ S4 S4 GNDUSBJ

Table 25. USB Port 1 USB2.1 Standard A-type Connector - J23

Pin Pin Name Signal Name

1 VBUS VUSB_VBUS1

2 DM USB1_CONN_DM

3 DP USB1_CONN_DP

4 GND DGND S1 S1 GNDUSB1 S2 S2 GNDUSB1

Table 26. USB Port 2 USB2.1 Micro-AB Connector - J45

Pin Pin Name Signal Name

1 VBUS VUSB_VBUS2

2 DM USB2_CONN_DM

3 DP USB2_CONN_DP

4 ID USB2_ID

5 GND DGND S1 S1 GNDUSB2 S2 S2 GNDUSB2 S3 S3 GNDUSB2 S4 S4 GNDUSB2

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Board Connectors

Table 27. CAN Header Connector - J38

Pin Signal Name

1 VCAN1 2 CAN1_H 3 CAN1_L 4 GND_CAN1 5 No Connect

Table 28. Profibus DB9F Connector - J14

Pin Signal Name

1 No Connect 2 No Connect 3 PROFIBUS_A 4 No Connect 5 GND_PROFI 6 VPROFI 7 No Connect 8 PROFIBUS_B 9 No Connect

Table 29. RS-485 Header Connector - J39

Pin Signal Name

1 RS485_A 2 RS485_B 3 DGND

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Table 30. PCIe Connector – J52

Pin Pin Nmae Signal Name

B1 +12 V V12_0D B2 +12 V V12_0D B3 +12 V V12_0D B4 Ground DGND B5 SMCLK PCIE_SMB_CLK B6 SMDAT PCIE_SMB_DATA B7 Ground DGND B8 +3.3V V3_3D B9 TRST# PCIE_TRSTn

B10 +3.3V AUX V3_3AUX_PCIE B11 WAKE# PCIE_WAKEn B12 CLKREQ# No Connect B13 Ground DGND B14 HSOp(0) PCIECONN_PETp0 B15 HSOn(0) PCIECONN_PETn0 B16 Ground DGND B17 PRSNT2# DGND B18 Ground DGND B19 HSOp(1) PCIECONN_PETp1 B20 HSOn(1) PCIECONN_PETn1 B21 Ground DGND B22 Ground DGND B23 HSOp(2) No Connect B24 HSOn(2) No Connect B25 Ground DGND B26 Ground DGND B27 HSOp(3) No Connect B28 HSOn(3) No Connect B29 Ground DGND B30 Reserved No Connect B31 PRSNT2# DGND B32 Ground DGND

A1 PRSNT1# PCIE_CRDPRESENT A2 +12 V V12_0D A3 +12 V V12_0D A4 Ground DGND A5 TCK PD to DGND A6 TDI PU to V3_3D A7 TDO TP20 A8 TMS PU to V3_3D A9 +3.3V V3_3D

A10 +3.3V V3_3D A11 PERST# PCIE_PERSTn A12 Ground DGND A13 REFCLK+ PCIE_REFCLKP A14 REFCLK- PCIE_REFCLKN A15 Ground DGND A16 HSIp(0) PCIE_PERp0

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EVM Important Notice

Table 30. PCIe Connector – J52 (continued)

Pin Pin Nmae Signal Name

A17 HSIn(0) PCIE_PERn0 A18 Ground DGND A19 Reserved No Connect A20 Ground DGND A21 HSIp(1) AM57XX_PCIE_PERp1 A22 HSIn(1) AM57XX_PCIE_PERn1 A23 Ground DGND A24 Ground DGND A25 HSIp(2) No Connect A26 HSIn(2) No Connect A27 Ground DGND A28 Ground DGND A29 HSIp(3) No Connect A30 HSIn(3) No Connect A31 Ground DGND A32 Reserved No Connect

14 EVM Important Notice

Refer to the STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES (SSZZ027).

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Appendix A

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Known Deficiencies in AM571x IDK EVM

A.1 Power solution not sufficient for full PCIe plug-in card compliance

The AM571x IDK EVM supports compatibility to PCIe x4 plug-in cards. It is not compliant with the PCIe Card Electro-Mechanical (CEM) specification. Specifically, the board does not provide the recommended power per the CEM. It provides up to 0.5A of current on the 3.3V/3.3V_AUX input pins and up to 0.5A on the 12V input pins. Also, the root complex design implemented does not support hot plug-in of cards.

A.2 Early versions of the AM571x IDK EVM not installed with SOC devices rated for the

full industrial temperature range

A.3 AM571x IDK EVM does not support eMMC HS200 mode

The interface voltage for the eMMC is fixed at 3.3V in all modes of operation. This prevents support of HS200 which requires a transition to 1.8V. The AM571x IDK EVM does support this voltage shift for the SDCARD attached to the MMC1 port. The MMC1 port is on VDDSHV8 supply that is attached to the LDO1 PMIC output that supports this voltage shift for higher speed modes. The eMMC is attached to the VDDSHV11 supply fixed at 3.3V. Board designs that require HS200 support for eMMC would need a solution to transition from 3.3V to 1.8V under software control.

A.4 PCIe PERSTn line not in proper state at start-up

The board does not contain pull-up or pull-down resistors to allow this line to be pulled-high at start-up. This can cause PCIe link training to fail. Future software releases need to properly control the GPIO output pins to enable this correctly at start-up.

A.5 EDIO connectors J4 and J7 should support real-time debugging for both PRU1 and

PRU2

The pins chosen provide visibility to the PRU2 MII0 and MII1 ports and PRU1 EDIO ports.

A.6 HDQ implementation not correct

HDQ was intended to be attached to the Expansion Connector. Since this pin is multiplexed with XREF_CLK3/CLKOUT3 used with the Camera connector, the clock options implemented for the camera connector prevent use of HDQ without addition of a wire. This can be enabled by adding a wire between the open pads of R905 and R300.

A.7 Removing the power plug and inserting it again while the power supply is energized

may cause damage

Removing the power plug and inserting it again while the power supply is energized may damage the AM571x IDK EVM and/or other devices attached to the board such as emulators that provide an alternate path to ground. Removal of AC power from the external power supply is a safer method, if required. It is also recommended that the external power supply have the common return bonded to earth ground. If this is not possible, a separate connection from the board ground to earth ground may need to be provided. Terminal block J53 is provided for this purpose. Test fixtures that repeatedly cycle main power on and off should have the board ground bonded to earth ground at all times during this testing.

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Software shutdown of PMIC not operational

A.8 Software shutdown of PMIC not operational

The PMIC is implemented to support PORz generation whenever any reset is initiated within the AM5718 SOC. This is enabled by pulling PMIC BOOT1 to VRTC. This has the side effect of requiring that PMIC GPIO7/POWERHOLD also be pulled high. This results in an “always on” design that cannot be shut-off by software. An external PORz pulse generator like that implemented on the X15 GP EVM would need to be used to enable this feature. Please refer to i862 in the errata document for more information.

A.9 CCS System Reset fails

Warm reset and emulation reset events configured for warm reset cause the Texas Instruments Code Composer Studio™ (CCS) integrated development environment (IDE) to issue an error message. This is due to the reset erratum that requires all resets to trigger a PORz low event. Since this is not expected by CCS when it initiates a warm reset, it loses its context and issues an error. Newer versions of CCS handle this event better but an error message will always be generated.

A.10 AM571x IDK EVM design contains 2 clamp circuits that may not be necessary

During early investigation of power shut-down sequencing, it was determined that clamps were required on every 3.3V supply to the dual-voltage I/O cell supplies (VDDSHVx). This would enforce the requirement shown in Figure 5-3 of the AM571x Sitara Processors Silicon Revision 2.0 Data Manual (SPRS957) that states that the 3.3V supply inputs must never be more than 2.0V above the VDDS18V supply, even during ramping up or ramping down. The AM571x IDK EVM design contains these clamp circuits on both V3_3D, that powers almost all VDDSHVx supplies, and VSDMMC, that powers VDDSHV8 used with the SDCARD on MMC1. Later it was determined that the only method to maintain device reliability was to fully enforce the supply sequence requirements shown in Figures 5-1 and 5-2 of the AM571x Sitara Processors Silicon

Revision 2.0 Data Manual (SPRS957). The companion PMIC, TPS6590377, was enhanced to provide a

shortened shut-down sequence that enforces the DM requirements in a time period (~1ms) that the PMIC input can hold up the supplies. The PMIC also has supply discharge resistors to pull down the supplies quickly when they are turning off. These 2 capabilities in the companion PMIC make the clamp circuits superfluous. However, designs that use REGEN1 to power the VDDSHVx supplies through a power switch will still need the clamp circuit. The power switches available do not discharge the supplies quick enough.

A.11 Crystal connected to osc0 needs to have 50ppm or better long term accuracy

The crystal connected to osc0 needs to have 50ppm or better long term accuracy since it generates clocks used for Ethernet interfaces. The current crystal has 30ppm accuracy and 50ppm temperature variation for a combined tolerance of 80ppm. It also has aging of 2ppm per year.

A.12 Software must program the CDCE913 for 0pf load capacitance

Software must program the CDCE913 for 0pf load capacitance to allow crystals to operate at their target frequency. Crystal load capacitors can be added to the oscillator circuit to allow the generated clock to output at the required nominal frequency so that this programming is not required. The default capacitance within the CDCE913 is 10pF so the capacitors C172, C173, C193, and C194 should be 8pF. Please refer to the CDCE(L)913: Flexible Low Power LVCMOS Clock Generator With SSC Support for EMI Reduction

Data Manual (SCAS849) for more information. Also note that these clock generators are used to drive

Ethernet circuitry, so the same crystal accuracy requirement from Section A.11 applies to these crystals as well.

A.13 Protection diode D2 should be rated for 5V

Protection diode D2 has the wrong value. It is meant to conduct current, if a voltage too large is connected to the IDK. This current surge should blow the fuse before ICs are damaged. The current part SMCJ26CA is rated for 26V. It should be replaced with SMCJ5.0A that is rated to protect a 5V-input power supply circuit.

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PHY address LSB for U9 and U15 can be latched incorrectly

A.14 PHY address LSB for U9 and U15 can be latched incorrectly

The PHY address LSB for U9 and U15 gets determined by the signal level at the PHY's COL pin during reset release. The PHY has a pull-down resistor connected to this pin to enable latching the value of 0. Unfortunately, this pin is also connected to one of the RJ-45 connector LEDs that pulls the signal to an undefined voltage of about 1.4V during the reset time. Therefore, the PHY address can incorrectly latch a value of 1. The LED circuit should be configured for active-high indication and the connections to the LED reversed with the cathode connected to ground. This allows the LSB of the address to be properly latched. Please refer to Section 6 of the TLK1XX Design and Layout Guide Application Report (SLVA531) for more information. The current software workaround programs the RXLINK pin with a pull-down resistor and then pulses the PHY reset from a GPIO, to cause it to latch the PHY address correctly.

A.15 3.3V clamp circuit needs more margin

The 3.3V clamp circuit is tuned too close such that if the 1.8V supply is 5% low and the 3.3V supply is 5% high, the clamp will begin conducting. Replacing resistors R897 and R801 with a 24.3Kohm resistor provides the proper tolerance, so the circuit will start conducting at a delta voltage of 1.75V rather than the current setting of 1.5V.

A.16 Current PMIC does not provide the mandated power down sequence

The current PMIC does not provide the mandated power down sequence as shown in the AM571x Sitara

Processors Silicon Revision 2.0 Data Manual (SPRS957). Production IDK EVMs contain the TPS6590377

PMIC, which powers off the DDR supply at the wrong time. The default programming has been corrected in the TPS6590379 PMIC. This part will be used for future builds.

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A.17 Power supply droop may cause board reset

The TPS3808G50 voltage supervisor circuit, U105, monitors the main power input and initiates a powerdown sequence, if the main input voltage drops below 4.65V. Since some external power supplies may droop during rapid changes in load current, this can trigger an unexpected shut-down and restart sequence that resets the SOC. U105 can be replaced with a TPS3808G33 voltage supervisor device that triggers at 3.07V. This is still above the minimum input voltage of the PMIC. However, this lower threshold voltage may require additional capacitance to be added at the input to the PMIC to allow the power-down sequence to complete before the input voltage collapses.

A.18 AM5718 pin N21 must be connected to 1.8V, as it is VDDS18V_DDR1 and not N/C

AM5718 pin N21 must be connected to 1.8V, as it is VDDS18V_DDR1 and is not N/C. The schematic symbol has this labeled incorrectly.

A.19 VOUT1 is used at 3.3V, which violates erratum i920

VOUT1 is used at 3.3V, which violates erratum i920. All VOUT ports can only be operated at 1.8V on AM571x devices per the device erratum. Operation at 3.3V may impact long-term reliability. Voltage-level translators must be used if these signals interface to circuits that require 3.3V signaling levels.

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Revision History

Changes from Original (October 2016) to A Revision .................................................................................................... Page

• Section 3.4: Changed last bullet to 5.0V.............................................................................................. 14

• Section 6: Added second paragraph.................................................................................................. 18

• Section 9.1: Added second paragraph................................................................................................ 20

• Section 9.3: Added NOTE.............................................................................................................. 20

• Section A.11: Added subsection....................................................................................................... 39

• Section A.12: Added subsection....................................................................................................... 39

• Section A.13: Added subsection....................................................................................................... 39

• Section A.14: Added subsection....................................................................................................... 40

• Section A.15: Added subsection....................................................................................................... 40

• Section A.16: Added subsection....................................................................................................... 40

• Section A.17: Added subsection....................................................................................................... 40

• Section A.18: Added subsection....................................................................................................... 40

• Section A.19: Added subsection....................................................................................................... 40

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STANDARD TERMS FOR EVALUATION MODULES

1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, and/or documentation which may be provided together or separately (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms set forth herein. User's acceptance of the EVM is expressly subject to the following terms.

1.1 EVMs are intended solely for product or software developers for use in a research and development setting to facilitate feasibility evaluation, experimentation, or scientific analysis of TI semiconductors products. EVMs have no direct function and are not finished products. EVMs shall not be directly or indirectly assembled as a part or subassembly in any finished product. For clarification, any software or software tools provided with the EVM (“Software”) shall not be subject to the terms and conditions set forth herein but rather shall be subject to the applicable terms that accompany such Software

1.2 EVMs are not intended for consumer or household use. EVMs may not be sold, sublicensed, leased, rented, loaned, assigned, or otherwise distributed for commercial purposes by Users, in whole or in part, or used in any finished product or production system.

2 Limited Warranty and Related Remedies/Disclaimers:

2.1 These terms do not apply to Software. The warranty, if any, for Software is covered in the applicable Software License Agreement.

2.2 TI warrants that the TI EVM will conform to TI's published specifications for ninety (90) days after the date TI delivers such EVM to User. Notwithstanding the foregoing, TI shall not be liable for a nonconforming EVM if (a) the nonconformity was caused by neglect, misuse or mistreatment by an entity other than TI, including improper installation or testing, or for any EVMs that have been altered or modified in any way by an entity other than TI, (b) the nonconformity resulted from User's design, specifications or instructions for such EVMs or improper system design, or (c) User has not paid on time. Testing and other quality control techniques are used to the extent TI deems necessary. TI does not test all parameters of each EVM. User's claims against TI under this Section 2 are void if User fails to notify TI of any apparent defects in the EVMs within ten (10) business days after delivery, or of any hidden defects with ten (10) business days after the defect has been detected.

2.3 TI's sole liability shall be at its option to repair or replace EVMs that fail to conform to the warranty set forth above, or credit User's account for such EVM. TI's liability under this warranty shall be limited to EVMs that are returned during the warranty period to the address designated by TI and that are determined by TI not to conform to such warranty. If TI elects to repair or replace such EVM, TI shall have a reasonable time to repair such EVM or provide replacements. Repaired EVMs shall be warranted for the remainder of the original warranty period. Replaced EVMs shall be warranted for a new full ninety (90) day warranty period.

3 Regulatory Notices:

3.1 United States

3.1.1 Notice applicable to EVMs not FCC-Approved:

FCC NOTICE: This kit is designed to allow product developers to evaluate electronic components, circuitry, or software associated with the kit to determine whether to incorporate such items in a finished product and software developers to write software applications for use with the end product. This kit is not a finished product and when assembled may not be resold or otherwise marketed unless all required FCC equipment authorizations are first obtained. Operation is subject to the condition that this product not cause harmful interference to licensed radio stations and that this product accept harmful interference. Unless the assembled kit is designed to operate under part 15, part 18 or part 95 of this chapter, the operator of the kit must operate under the authority of an FCC license holder or must secure an experimental authorization under part 5 of this chapter.

3.1.2 For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant:

CAUTION

This device complies with part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.

Changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to operate the equipment.

FCC Interference Statement for Class A EVM devices

NOTE: This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense.

Page 43

FCC Interference Statement for Class B EVM devices

NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

• Reorient or relocate the receiving antenna.

• Increase the separation between the equipment and receiver.

• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

• Consult the dealer or an experienced radio/TV technician for help.

3.2 Canada

3.2.1 For EVMs issued with an Industry Canada Certificate of Conformance to RSS-210 or RSS-247

Concerning EVMs Including Radio Transmitters:

This device complies with Industry Canada license-exempt RSSs. Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may

cause undesired operation of the device.

Concernant les EVMs avec appareils radio:

Le présent appareil est conforme aux CNR d'Industrie Canada applicables aux appareils radio exempts de licence. L'exploitation est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement.

Concerning EVMs Including Detachable Antennas:

Under Industry Canada regulations, this radio transmitter may only operate using an antenna of a type and maximum (or lesser) gain approved for the transmitter by Industry Canada. To reduce potential radio interference to other users, the antenna type and its gain should be so chosen that the equivalent isotropically radiated power (e.i.r.p.) is not more than that necessary for successful communication. This radio transmitter has been approved by Industry Canada to operate with the antenna types listed in the user guide with the maximum permissible gain and required antenna impedance for each antenna type indicated. Antenna types not included in this list, having a gain greater than the maximum gain indicated for that type, are strictly prohibited for use with this device.

Concernant les EVMs avec antennes détachables

Conformément à la réglementation d'Industrie Canada, le présent émetteur radio peut fonctionner avec une antenne d'un type et d'un gain maximal (ou inférieur) approuvé pour l'émetteur par Industrie Canada. Dans le but de réduire les risques de brouillage radioélectrique à l'intention des autres utilisateurs, il faut choisir le type d'antenne et son gain de sorte que la puissance isotrope rayonnée équivalente (p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante. Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel d’usage et ayant un gain admissible maximal et l'impédance requise pour chaque type d'antenne. Les types d'antenne non inclus dans cette liste, ou dont le gain est supérieur au gain maximal indiqué, sont strictement interdits pour l'exploitation de l'émetteur

3.3 Japan

3.3.1 Notice for EVMs delivered in Japan: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page 日本国内に

輸入される評価用キット、ボードについては、次のところをご覧ください。

http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_01.page

3.3.2 Notice for Users of EVMs Considered “Radio Frequency Products” in Japan: EVMs entering Japan may not be certified by TI as conforming to Technical Regulations of Radio Law of Japan.

If User uses EVMs in Japan, not certified to Technical Regulations of Radio Law of Japan, User is required to follow the instructions set forth by Radio Law of Japan, which includes, but is not limited to, the instructions below with respect to EVMs (which for the avoidance of doubt are stated strictly for convenience and should be verified by User):

1. Use EVMs in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and Communications on March 28, 2006, based on Sub-section 1.1 of Article 6 of the Ministry’s Rule for Enforcement of Radio Law of Japan,

2. Use EVMs only after User obtains the license of Test Radio Station as provided in Radio Law of Japan with respect to EVMs, or

3. Use of EVMs only after User obtains the Technical Regulations Conformity Certification as provided in Radio Law of Japan with respect to EVMs. Also, do not transfer EVMs, unless User gives the same notice above to the transferee. Please note that if User does not follow the instructions above, User will be subject to penalties of Radio Law of Japan.

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【無線電波を送信する製品の開発キットをお使いになる際の注意事項】開発キットの中には技術基準適合証明を受けていないものがあります。技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。

1. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。

2. 実験局の免許を取得後ご使用いただく。

3. 技術基準適合証明を取得後ご使用いただく。

なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。

上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。日本テキサス・インスツルメンツ株式会社東京都新宿区西新宿６丁目２４番１号西新宿三井ビル

3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page

電力線搬送波通信についての開発キットをお使いになる際の注意事項については、次のところをご覧ください。http:/

/www.tij.co.jp/lsds/ti_ja/general/eStore/notice_02.page

3.4 European Union

3.4.1 For EVMs subject to EU Directive 2014/30/EU (Electromagnetic Compatibility Directive): This is a class A product intended for use in environments other than domestic environments that are connected to a

low-voltage power-supply network that supplies buildings used for domestic purposes. In a domestic environment this product may cause radio interference in which case the user may be required to take adequate measures.

4 EVM Use Restrictions and Warnings:

4.1 EVMS ARE NOT FOR USE IN FUNCTIONAL SAFETY AND/OR SAFETY CRITICAL EVALUATIONS, INCLUDING BUT NOT LIMITED TO EVALUATIONS OF LIFE SUPPORT APPLICATIONS.

4.2 User must read and apply the user guide and other available documentation provided by TI regarding the EVM prior to handling or using the EVM, including without limitation any warning or restriction notices. The notices contain important safety information related to, for example, temperatures and voltages.

4.3 Safety-Related Warnings and Restrictions:

4.3.1 User shall operate the EVM within TI’s recommended specifications and environmental considerations stated in the user guide, other available documentation provided by TI, and any other applicable requirements and employ reasonable and customary safeguards. Exceeding the specified performance ratings and specifications (including but not limited to input and output voltage, current, power, and environmental ranges) for the EVM may cause personal injury or death, or property damage. If there are questions concerning performance ratings and specifications, User should contact a TI field representative prior to connecting interface electronics including input power and intended loads. Any loads applied outside of the specified output range may also result in unintended and/or inaccurate operation and/or possible permanent damage to the EVM and/or interface electronics. Please consult the EVM user guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative. During normal operation, even with the inputs and outputs kept within the specified allowable ranges, some circuit components may have elevated case temperatures. These components include but are not limited to linear regulators, switching transistors, pass transistors, current sense resistors, and heat sinks, which can be identified using the information in the associated documentation. When working with the EVM, please be aware that the EVM may become very warm.

4.3.2 EVMs are intended solely for use by technically qualified, professional electronics experts who are familiar with the dangers and application risks associated with handling electrical mechanical components, systems, and subsystems. User assumes all responsibility and liability for proper and safe handling and use of the EVM by User or its employees, affiliates, contractors or designees. User assumes all responsibility and liability to ensure that any interfaces (electronic and/or mechanical) between the EVM and any human body are designed with suitable isolation and means to safely limit accessible leakage currents to minimize the risk of electrical shock hazard. User assumes all responsibility and liability for any improper or unsafe handling or use of the EVM by User or its employees, affiliates, contractors or designees.

4.4 User assumes all responsibility and liability to determine whether the EVM is subject to any applicable international, federal, state, or local laws and regulations related to User’s handling and use of the EVM and, if applicable, User assumes all responsibility and liability for compliance in all respects with such laws and regulations. User assumes all responsibility and liability for proper disposal and recycling of the EVM consistent with all applicable international, federal, state, and local requirements.

5. Accuracy of Information: To the extent TI provides information on the availability and function of EVMs, TI attempts to be as accurate as possible. However, TI does not warrant the accuracy of EVM descriptions, EVM availability or other information on its websites as accurate, complete, reliable, current, or error-free.

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6. Disclaimers:

6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY MATERIALS PROVIDED WITH THE EVM (INCLUDING, BUT NOT LIMITED TO, REFERENCE DESIGNS AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY EPIDEMIC FAILURE WARRANTY OR IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS.

6.2 EXCEPT FOR THE LIMITED RIGHT TO USE THE EVM SET FORTH HEREIN, NOTHING IN THESE TERMS SHALL BE CONSTRUED AS GRANTING OR CONFERRING ANY RIGHTS BY LICENSE, PATENT, OR ANY OTHER INDUSTRIAL OR INTELLECTUAL PROPERTY RIGHT OF TI, ITS SUPPLIERS/LICENSORS OR ANY OTHER THIRD PARTY, TO USE THE EVM IN ANY FINISHED END-USER OR READY-TO-USE FINAL PRODUCT, OR FOR ANY INVENTION, DISCOVERY OR IMPROVEMENT, REGARDLESS OF WHEN MADE, CONCEIVED OR ACQUIRED.

7. USER'S INDEMNITY OBLIGATIONS AND REPRESENTATIONS. USER WILL DEFEND, INDEMNIFY AND HOLD TI, ITS LICENSORS AND THEIR REPRESENTATIVES HARMLESS FROM AND AGAINST ANY AND ALL CLAIMS, DAMAGES, LOSSES, EXPENSES, COSTS AND LIABILITIES (COLLECTIVELY, "CLAIMS") ARISING OUT OF OR IN CONNECTION WITH ANY HANDLING OR USE OF THE EVM THAT IS NOT IN ACCORDANCE WITH THESE TERMS. THIS OBLIGATION SHALL APPLY WHETHER CLAIMS ARISE UNDER STATUTE, REGULATION, OR THE LAW OF TORT, CONTRACT OR ANY OTHER LEGAL THEORY, AND EVEN IF THE EVM FAILS TO PERFORM AS DESCRIBED OR EXPECTED.

8. Limitations on Damages and Liability:

8.1 General Limitations. IN NO EVENT SHALL TI BE LIABLE FOR ANY SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL, OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF THESE TERMS OR THE USE OF THE EVMS , REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO, COST OF REMOVAL OR REINSTALLATION, ANCILLARY COSTS TO THE PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, RETESTING, OUTSIDE COMPUTER TIME, LABOR COSTS, LOSS OF GOODWILL, LOSS OF PROFITS, LOSS OF SAVINGS, LOSS OF USE, LOSS OF DATA, OR BUSINESS INTERRUPTION. NO CLAIM, SUIT OR ACTION SHALL BE BROUGHT AGAINST TI MORE THAN TWELVE (12) MONTHS AFTER THE EVENT THAT GAVE RISE TO THE CAUSE OF ACTION HAS OCCURRED.

8.2 Specific Limitations. IN NO EVENT SHALL TI'S AGGREGATE LIABILITY FROM ANY USE OF AN EVM PROVIDED HEREUNDER, INCLUDING FROM ANY WARRANTY, INDEMITY OR OTHER OBLIGATION ARISING OUT OF OR IN CONNECTION WITH THESE TERMS, , EXCEED THE TOTAL AMOUNT PAID TO TI BY USER FOR THE PARTICULAR EVM(S) AT ISSUE DURING THE PRIOR TWELVE (12) MONTHS WITH RESPECT TO WHICH LOSSES OR DAMAGES ARE CLAIMED. THE EXISTENCE OF MORE THAN ONE CLAIM SHALL NOT ENLARGE OR EXTEND THIS LIMIT.

9. Return Policy. Except as otherwise provided, TI does not offer any refunds, returns, or exchanges. Furthermore, no return of EVM(s) will be accepted if the package has been opened and no return of the EVM(s) will be accepted if they are damaged or otherwise not in a resalable condition. If User feels it has been incorrectly charged for the EVM(s) it ordered or that delivery violates the applicable order, User should contact TI. All refunds will be made in full within thirty (30) working days from the return of the components(s), excluding any postage or packaging costs.

10. Governing Law: These terms and conditions shall be governed by and interpreted in accordance with the laws of the State of Texas, without reference to conflict-of-laws principles. User agrees that non-exclusive jurisdiction for any dispute arising out of or relating to these terms and conditions lies within courts located in the State of Texas and consents to venue in Dallas County, Texas. Notwithstanding the foregoing, any judgment may be enforced in any United States or foreign court, and TI may seek injunctive relief in any United States or foreign court.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES

Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you (individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of this Notice.

TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources.

You understand and agree that you remain responsible for using your independent analysis, evaluation and judgment in designing your applications and that you have full and exclusive responsibility to assure the safety of your applications and compliance of your applications (and of all TI products used in or for your applications) with all applicable regulations, laws and other applicable requirements. You represent that, with respect to your applications, you have all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. You agree that prior to using or distributing any applications that include TI products, you will thoroughly test such applications and the functionality of such TI products as used in such applications. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource.

You are authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.

TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING TI RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.

TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY YOU AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

You agree to fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of your noncompliance with the terms and provisions of this Notice.

This Notice applies to TI Resources. Additional terms apply to the use and purchase of certain types of materials, TI products and services. These include; without limitation, TI’s standard terms for semiconductor products http://www.ti.com/sc/docs/stdterms.htm), evaluation

modules, and samples (http://www.ti.com/sc/docs/sampterms.htm).

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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