Texas instruments AM3517, AM3505 User Manual

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

AM3517/05 ARM Microprocessor

Check for Samples: AM3517, AM3505

1 AM3517/05 ARM Microprocessor

1.1 Features

1234

• AM3517/05 ARM Microprocessor: – Software Compatible with OMAPTM3

Processors

– MPU Subsystem

• 600-MHz ARM CortexTM-A8 Core

• NEONTMSIMD Coprocessor and Vector floating point (FP) co-processor

– Memory Interfaces:

• 16/32- bit mDDR/DDR2 Interface with 1 GByte total addressable space

• General Purpose Memory Interface supporting 16-bit Wide Multiplexed Address/Data bus

• 64 K-Byte SRAM

• 3 Removable Media Interfaces [MMC/SD/SDIO]

– IO Voltage:

• mDDR/DDR2 IOs: 1.8V

• Other IOs: 1.8V and 3.3V

– Core Voltage: 1.2V – Commercial and Industrial Temperature

Grade

• Display subsystem – Parallel Digital Output – Up to 24-Bit RGB – Supports Up to 2 LCD Panels

(operating restrictions apply) – Support for Remote Frame Buffer Interface

– 16-bit Video Input Port capable of capturing

HD video – Two 10-bit Digital-to-Analog Converters – HD resolution Display Subsystem – Serial Communication

• High-End CAN Controller

• 10/100 Mbit Ethernet MAC

• USB OTG subsystem with standard

– Rotation 90, 180, and 270 degrees – Resize Images From 1/4x to 8x

DP/DM interface [HS/FS/LS] – Color Space Converter

• Multiport USB Host Subsystem – 8-bit Alpha Blending [HS/FS/LS]

• Video Processing Front End (VPFE) 16-bit

– 12-pin ULPI or 6/4/3-pin Serial Video Input Port

Interface

• Four Master/Slave Multichannel Serial Port Interface (McSPI) Ports

• Five Multichannel Buffered Serial Ports

– RAW Data Interface – 75-MHz Maximum Pixel Clock – Supports REC656/CCIR656 Standard – Supports YCbCr422 Format (8-bit or 16-bit

– 512-Byte Transmit/Receive Buffer

(McBSP1/3/4/5)

– 5K-Byte Transmit/Receive Buffer

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2POWERVR SGX is a trademark of Imagination Technologies Ltd. 3 is a registered trademark of ~#IMPLIED. 4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testingof all parameters.

– Generates Optical Black Clamping Signals

(McBSP2)

– SIDETONE Core Support (McBSP2 and

3 Only) For Filter, Gain, and Mix

Operations – 128-Channel Transmit/Receive Mode – Direct Interface to I2S and PCM Device

and TDM Buses

• HDQ/1-Wire Interface

• 4 UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)

• 3 Master/Slave High-Speed Inter-Integrated Circuit (I2C) Controllers

• 12 32-bit General Purpose Timers

• 1 32-bit Watchdog Timer

• 1 32-bit 32-kHz Sync Timer

• Up to 186 General-Purpose I/O (GPIO) Pins

(RFBI) LCD Panels

(DACs) Supporting

• Composite NTSC/PAL Video

• Luma/Chroma Separate Video (S-Video)

With Discrete Horizontal and Vertical Sync Signals)

AM3517, AM3505

SPRS550B–OCTOBER 2009–REVISED JULY 2010

– Built-in Digital Clamping and Black Level – ARM Instructions - Little Endian

Compensation – 10-bit to 8-bit A-law Compression Hardware – Supports up to 16K Pixels (Image Size) in

Horizontal and Vertical Directions

• System Direct Memory Access (sDMA) Controller (32 Logical Channels With Configurable Priority)

• Comprehensive Power, Reset and Clock Management

• ARM CortexTM-A8 Memory Architecture – ARMv7 Architecture

• TrustZone

• Thumb®-2

– ARM Data – Configurable

• SDRC Memory Controller – 16/32-bit Memory Controller With 1G-Byte

Total Address Space

– Double Data Rate (DDR2) SDRAM, mobile

Double Data Rate (mDDR)SDRAM

– SDRAM Memory Scheduler (SMS) and

Rotation Engine

• General Purpose Memory Controller (GPMC) – 16-bit Wide Multiplexed Address/Data Bus – Up to 8 Chip Select Pins With 128M-Byte

Address Space per Chip Select Pin

– Glueless Interface to NOR Flash, NAND

• MMU Enhancements Flash (With ECC Hamming Code

– In-Order, Dual-Issue, Superscalar

Calculation), SRAM and Pseudo-SRAM

Microprocessor Core – Flexible Asynchronous Protocol Control for – NEONTMMultimedia Architecture – Over 2x Performance of ARMv6 SIMD – Supports Both Integer and Floating Point

SIMD – Jazelle®RCT Execution Environment

Architecture – Dynamic Branch Prediction with Branch

Target Address Cache, Global history buffer

Interface to Custom Logic (FPGA, CPLD, ASICs, etc.)

– Nonmultiplexed Address/Data Mode (Limited

2K-Byte Address Space)

• Test Interfaces – IEEE-1149.1 (JTAG) Boundary-Scan

Compatible

– Embedded Trace Macro Interface (ETM)

and 8 entry return stack • 65-nm CMOS technology

– Embedded Trace Macrocell [ETM] support • Packages:

for Non_invasive Debug

– 491-pin BGA (17x17, 0.65mm pitch)

– 16K-Byte instruction Cache (4-Way set- [ZCN suffix]

associative) with via channel array technology

– 16K-Byte Data Cache (4-Way – 484-pin PBGA (23x23, 1mm pitch)

Set-Associative) [ZER suffix]

– 256K-Byte L2 Cache • Applications:

• POWERVR SGX™ Graphics Accelerator – Single Board Computers – Tile Based Architecture Delivering up to 10 – Industrial and Home Automation

MPoly/sec

– Universal Scalable Shader Engine:

Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality

– Industry Standard API Support: OpenGLES

1.1 and 2.0, OpenVG1.0

– Fine Grained Task Switching, Load

Balancing, and Power Management

– Programmable, High-Quality Image

Anti-Aliasing

• Endianess

– Digital Signage – Point of Service – Portable Media Player – Portable Industrial – Transportation – Navigation – Smart White Goods – Digital TV – Digital Video Camera – Gaming

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1.2 Description

AM3517/05 high-performance, industrial applications processors with video, image, and graphics processing sufficient to support the following:

• Single Board Computers

• Home and Industrial automation

• Digital Signage The device supports high-level operating systems (OSs), such as:

• Linux

• Windows CE The following subsystems are part of the device:

• Microprocessor unit (MPU) subsystem based on the ARM Cortex-A8 microprocessor

• POWERVR SGX™ Graphics Accelerator (AM3517 Device only) Subsystem for 3D graphics acceleration to support display and gaming effects (AM3517 only)

• Display subsystem with several features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC/PAL video out.

• High performance interconnects provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals. The device also offers a comprehensive clock-management scheme.

SPRS550B–OCTOBER 2009–REVISED JULY 2010

AM3517/05 devices are available in a 491-pin BGA package and a 484-pin PBGA package. This AM3517/05 data manual presents the electrical and mechanical specifications for the AM3517/05

ARM Microprocessor.

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Async

L2$

256K

MPU

Subsystem

ARM Cortex-

Core

16K/16K L1$

POWERVR

SGX

Graphics

Accelerator

( only)

AM3517

Channel

System

DMA

3232

Analog

DAC

LCD Panel

CVBS

S-Video

Dual Output 3-Layer

Display Processor

(1xGraphics, 2xVideo)

Temporal Dithering

SDTV → QCIF Support

HS/FS/

USB

Host

L3 Interconnect Network-Hierarchial, Performance, and Power Driven

64K

On-Chip

RAM

132K

On-Chip

BOOT

ROM

SMS: SDRAM Memory

Scheduler/

Rotation

EMIF

Controller

L4 Interconnect

System

Controls

PRCM

External

Peripherals

Interfaces

Peripherals:

4xUART, 3xHigh-Speed I2C,

5xMcBSP

(2x with Sidetone/Audio Buffer)

4xMcSPI, 186xGPIO,

3xHigh-Speed MMC/SDIO,

HDQ/1 Wire,

12xGPTimers, 1xWDT,

32K Sync Timer

GPMC:

General Purpose Memory

Controller

Emulation

Debug: ETM, JTAG

External

DDR2/ mDDR

SPRS550-006

Parallel

HECC

EMAC

VPFE

USB PHY

USB OTG

Controller

DDR PHY

NAND/NOR/

FLASH,

SRAM

USB transceivers / device ports [3]

AM3517, AM3505

SPRS550B–OCTOBER 2009–REVISED JULY 2010

1.3 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the AM3517/05 ARM Microprocessor.

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Figure 1-1. AM3517/05 Functional Block Diagram

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1.4 ZCN and ZER Package Differences

Table 1-1 shows the ZER and ZCN package differences on the device.

Table 1-1. ZCN and ZER Package Differences

FEATURE ZCN PACKAGE ZER PACKAGE

Pin Assignments For ZCN package pin assignments, see For ZER package pin assignments, see

Video Interfaces TV signals available TV signals not available

SPRS550B–OCTOBER 2009–REVISED JULY 2010

Terminal Description Terminal Description

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

1 AM3517/05 ARM Microprocessor .................... 1

1.1 Features .............................................. 1 4.4 DPLL Specifications ................................ 97

1.2 Description ........................................... 3

1.3 Functional Block Diagram ............................ 4

1.4 ZCN and ZER Package Differences ................. 5

Revision History .............................................. 7

2 TERMINAL DESCRIPTION ............................. 9

2.1 Pin Assignments ..................................... 9

2.2 Ball Characteristics ................................. 18

2.3 Multiplexing Characteristics ........................ 52

2.4 Signal Description .................................. 58

3 ELECTRICAL CHARACTERISTICS ................. 81

3.1 Absolute Maximum Ratings ........................ 81

3.2 Recommended Operating Conditions .............. 83

3.3 DC Electrical Characteristics ....................... 85

3.4 Core Voltage Decoupling ........................... 86

3.5 Power-up and Power-down ......................... 88

4 CLOCK SPECIFICATIONS ........................... 91

4.1 Oscillator ............................................ 93

4.2 Input Clock Specifications .......................... 93

4.3 Output Clock Specifications ........................ 95

5 VIDEO DAC SPECIFICATIONS .................... 100

5.1 Interface Description .............................. 101

5.2 Electrical Specifications Over Recommended

Operating Conditions .............................. 102

5.3 Analog Supply (vdda_dac) Noise Requirements

..................................................... 104

5.4 External Component Value Choice ............... 105

6 TIMING REQUIREMENTS AND SWITCHING

CHARACTERISTICS ................................. 106

6.1 Timing Test Conditions ............................ 106

6.2 Interface Clock Specifications ..................... 106

6.3 Timing Parameters ................................ 107

6.4 External Memory Interfaces ....................... 108

6.5 Video Interfaces ................................... 150

6.6 Serial Communications Interfaces ................ 155

6.7 Removable Media Interfaces ...................... 196

6.8 Test Interfaces .................................... 210

7 PACKAGE CHARACTERISTICS ................... 214

7.1 Package Thermal Resistance ..................... 214

7.2 Device Support .................................... 214

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This data manual revision history table highlights the technical changes made to the SPRS550A device-specific data manual to make it an SPRS550B revision.

Scope: Applicable updates to the AM35x device family, which is now in the Production Data (PD) stage of development, have been incorporated.

SPRS550B–OCTOBER 2009–REVISED JULY 2010

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

SEE ADDITIONS/MODIFICATIONS/DELETIONS

Global

Section 2 Updated/Changed the following:

• Changed all fsusb1x_x signals to mm_fsusbx_x

• Removed all instances of dssvenc656_datax

• Changed ARM11 to ARM CortexTM-A8

• Changed all instances of "trunk" to "trunc"

• Added following signals to Ball Characteristics (ZER Package) – hw_dbg[17:0] – i2c3_scl – i2c3_sda – uart1_cts – uart1_rts – dss_data4 – dss_data3 – dss_data2 – dss_data1 – dss_data5 – uart3_rx_irrx – uart3_tx_irtx – uart1_tx – uart1_rx – uart3_rts_sd – uart1_cts – mcbsp3_clkx – mcbsp3_dr – mcbsp3_dx – mcbsp3_fsx – mmc2_dir_dat0 – mmc2_dir_dat1 – mmc2_dir_cmd – mmc2_clkin – sdrc_cke0_safe – mmc2_dir_dat2 – mmc2_dir_dat3 – mcspi4_clk – mcbsp3_dx – mcbsp3_dr – mcbsp3_fsx – uart2_tx – mcbsp3_clkx – gpt11_pwm_evt – gpio_146 – uart3_tx_irtx

• Table 2-3, Multiplexing Characteristics – Added note to the usb0_dm and usb0_dp signals – Updated uart3_cts_crtx to uart3_cts_rctx – Added safe mode to uart3_rx_irrx signal

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SEE ADDITIONS/MODIFICATIONS/DELETIONS

Section 3 Updated/Changed the following:

• Deleted "Minimum pass level for HBM is 2 kV"

• Absolute Maximum Ratings Over Operating Junction Temperature Range – Updated footnotes 2 and 3. Deleted footnote 5.

• Table 3-4, DC Electrical Characteristics – Changed VHHSHV to VDDSHV. – Updated VILVDDSHV = 3.3V value from 0.6 to 0.8 – Updated VILVDDSHV = 1.8V value from .3 x VDDSHV to .35 x VDDSHV – Removed II(Input current) – Added "Normal Mode" and High-Speed Mode" values to Transition Time (tT) parameter

Section 6 Added RMII Timing Conditions table to EMAC Electrical Data section.

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2 TERMINAL DESCRIPTION

2.1 Pin Assignments

2.1.1 Pin Map (Top View)

The following illustrations show the top and bottom views of the 484-pin [ZER] and 491-pin [ZCN] package pin assignments in four quadrants (A, B, C, and D).

Note: A pin with an "NC" designator indicates No Connection. For proper device operation, these pins must be left unconnected.

SPRS550B–OCTOBER 2009–REVISED JULY 2010

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1415162223

2425

21 17181920

VDDS

VSS

SYS_

CLKOUT1

VDDS_ DPLL_MPU _USBHOST

VDDSHV

1516

181920

2122

AE VSS

VSS

VDDSHV

VDDSHV VDDSHV

VSS VSSVSS

VDDS_DPLL_

PER_CORE

VDDSHV VSS

VDDSHV VDDSHV VSSVSS VSSVSS VSS

VDD_CORE VDD_CORE

VSSVSS VSS

VDD_CORE

VSS

VDD_COREVDD_CORE

VSS

VDD_CORE

VSSVSS

VDD_COREVDD_CORE

VDDSHV

VDDSHVVDDSHV

VDDS

DSS_ACBIAS DSS_PCLK

ETK_D15 ETK_D12 ETK_D8

ETK_D5 ETK_CTL

MCSPI2_

CS1

MCSPI1_

CS3

MCSPI1_

CS2

MCSPI1_

CLK

DSS_DATA1 DSS_DATA0

DSS_VSYNC DSS_HSYNC

ETK_D13 ETK_D9 ETK_D6 ETK_D0

ETK_CLK

MCSPI2_

CLK

MCSPI1_

SIMO

MCSPI1_

CS1

DSS_DATA4 DSS_DATA3

DSS_DATA2

ETK_D14 ETK_D10 ETK_D1

MCSPI2_

SIMO

MCSPI1_

SOMI

DSS_DATA6

DSS_DATA5

ETK_D11

ETK_D7

ETK_D2 MCSPI2_

SOMI

MCSPI1_CS0

DSS_DATA9 DSS_DATA8

DSS_DATA7

UART1_TX ETK_D3 MCSPI2_

CS0

DSS_DATA13 DSS_DATA12

DSS_DATA11

DSS_DATA10 UART1_CTS UART1_RTS

ETK_D4

DSS_DATA18 DSS_DATA17 DSS_DATA16

DSS_DATA15 DSS_DATA14

UART1_RX

DSS_DATA20 DSS_DATA19

JTAG_TCK JTAG_NTRST

DSS_

DATA23

DSS_

DATA22

DSS_

DATA21

JTAG_EMU0

JTAG_TDO JTAG_TDI

JTAG_TMS

_TMSC

JTAG_RTCK

MCBSP1_

CLKR

JTAG_

EMU1

MCBSP_

CLKS

MCBSP1_

FSX

MCBSP1_DRMCBSP1_

MCBSP1_

FSR

MCBSP1_

CLKX

SYS_

CLKOUT2

VSS VSSVDD_CORE

SYS_

CLKREQ

VSS VSS

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

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Figure 2-1. ZCN Pin Map [Quadrant A]

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10 9 8

CCDC_ PCLK

12 11

6 5

2 1

CCDC_ FIELD

CCDC_ VD

CCDC_ DATA0

CCDC_ DATA3

RMII_MDIO

_CLK

RMII_TXD0

RMII_TXEN

MMC1_ DAT1

MMC1_ DAT6

MMC2_CLK

MMC2_ DAT2

MMC2_ DAT6

VSS

VSS VSS

VSS

VDDSHV

VSS

VSS VSS VSS VSS VSS VDDSHV

VDDSHV

GPMC_ NCS5

GPMC_ NCS4

GPMC_ NCS3

GPMC_ NCS2

GPMC_ NCS7

GPMC_ NCS6

GPMC_CLK

UART3_CTS

_RCTX

UART3_RTS

_SD

UART3_RX

_IRRX

UART3_TX

_IRTX

GPMC_NADV

_ALE

GPMC_

NBE1

GPMC_

WAIT3

I2C2_SCL

SYS_NIRQ

SYS_ BOOT1

SYS_ BOOT4

SYS_ BOOT6

SYS_ BOOT7

SYS_ BOOT5

SYS_ BOOT2

SYS

_NRES

PWRON

SYS_ BOOT8

12 11

10 9 8

6 5

2 1

CCDC_ HD

VSS

CCDC_ WEN

CCDC_ DATA1

CCDC_ DATA4

RMII_MDIO

_DATA

RMII_TXD1

RMII_50MHZ

_CLK

MMC1_ DAT2

MMC1_ DAT7

MMC2_ CMD

MMC2_ DAT3

MMC2_ DAT7

MMC2_ DAT1

MMC2_ DAT5

MMC2_ DAT0

MMC2_ DAT4

VDDS_SRAM

_MPU

CAP_VDD_

SRAM_MPU

VDDSHV

MMC1_ DAT0

MMC1_ DAT5

MMC1_ CMD

MMC1_ DAT4

MMC1_CLK

MMC1_ DAT3

VDDSHV

VDDS

VDD_CORE VDD_CORE

VDD_CORE

VSS

VDD_CORE

VSS VSS

VSS VSSVSS VSS

VSS VSS

CCDC_ DATA2

CCDC_ DATA7

CCDC_ DATA6

CCDC_ DATA5

VDDSHV

RMII_RXER

RMII_CRS_

RMII_RXD1

RMII_RXD0

VDDSHV

I2C3_SDA

I2C1_SDA

I2C3_SCL

I2C1_SCL

SYS_ BOOT3

SYS

_NRES

WARM

SYS_ BOOT0

I2C2_SDA

HECC1_ TXD

HECC1_ RXD

GPMC_

NWP

GPMC_

WAIT0

GPMC_

WAIT1

GPMC_

WAIT2

VDDS

GPMC_NBE0

_CLE

GPMC_

NWE

GPMC_

NOE

RESERVED

AM3517, AM3505

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Figure 2-2. ZCN Pin Map [Quadrant B]

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1718

2021

2425

B B

181920

VSS

HDQ_ SIO

VDDSHV

VDD_CORE

VSS

TV_ OUT1

VSS

VDD_CORE

VDD_COREVDD_CORE

VDDSHV

VSS VSS

VDDSHV

VDDS

VDDS VDDS

UART2_RTS

SYS_ XTALIN

SYS_32K

VSSOSC

SYS_ XTALOUT

TV_ OUT2

TV_VFB2

VSSA_DAC VDDA_DAC

TV_VFB1

VSS

USB0_ID

USB0_DP

USB0_ DRVVBUS

MCBSP2_ FSX

MCBSP2_ CLKX

MCBSP2_DR

VSS

MCBSP3_ CLKX

MCBSP3_DX

MCBSP3_ DR

MCBSP2_ DX

UART2 _TX

MCBSP4_ DR

MCBSP4_ CLKX

MCBSP3_ FSX

UART2_RX

VDDA3P3V

_USBPHY

VDDA1P8V _USBPHY

CAP_

VDDA1P2LDO

_USBPHY

MCBSP4_ FSX

SDRC_ D1

SDRC_ DQS0N

SDRC_ STRBEN0

SDRC_

STRBEN

_DLY0

SDRC_ DQS1N

SDRC_ D14

SDRC_

D15

SDRC_ NCS1

SDRC_ NWE

SDRC_ DM1

SDRC_ D13

SDRC_ DQS1P

SDRC_ D8

SDRC_ D7

SDRC_ DQS0P

SDRC_ D0

MCBSP4_ DX

SDRC_DM0 SDRC_D3 SDRC_D6

SDRC_D10

SDRC_D12 SDRC_NRAS

SDRC_CKE0

SDRC_NCAS

VREFSSTL

SDRC_D2 SDRC_D5

SDRC_D9

SDRC_D11

SDRC_D4

VDDS_SRAM

_CORE_BG

CAP_VDD_

SRAM_CORE

USB0_DM

UART2_CTS

USB0_ VBUS

VDDSHV

VDDSOSC

TV_VREF

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Figure 2-3. ZCN Pin Map [Quadrant C]

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12 11

6 5

12 11

10 9 8

6 5

10 9 8

2 1

VSS

VSS VSS

VDD_CORE VDD_CORE

VDD_CORE

VDDSHV VDDSHV VDDSHV

VDDSHVVSSVSS

VDDSVSS

VDDS

GPMC_ NCS0

GPMC_ NCS1

GPMC_D12

GPMC_D13 GPMC_D14

GPMC_D15

GPMC_D11GPMC_D10

GPMC_D8 GPMC_D9

GPMC_D7

GPMC_D6

GPMC_D5

GPMC_D4

GPMC_D3GPMC_D1 GPMC_D2GPMC_D0

GPMC_A9GPMC_A8

GPMC_A7

GPMC_A6

GPMC_A5

GPMC_A4

GPMC_A3GPMC_A2

GPMC_A1

SDRC_DM3

VSS

VDD_CORE VDD_CORE

VSS

VDD_CORE VDD_CORE

VDDSVDDS

VDDS VDDS

VDDS

SDRC_BA0

SDRC_CLK

SDRC_ NCLK

SDRC_BA1

SDRC_BA2

SDRC_ NCS0

DDR_ PADREF

SDRC_A0

SDRC_A1

SDRC_A2

SDRC_A3

SDRC_ A4

SDRC_ A9

SDRC_A8

SDRC_A7

SDRC_A6

SDRC_A5

SDRC_A11

SDRC_ A10

SDRC_ A12

SDRC_ A13

SDRC_ ODT

SDRC_A14

SDRC_DM2

SDRC_D19

SDRC_D18

SDRC_ D17

SDRC_ D16

GPMC_A10

SDRC_D21

SDRC_D20

SDRC_ DQS2N

SDRC_ DQS2P

SDRC_ STRBEN1

SDRC_D22

SDRC_D23

SDRC_24

SDRC_

STRBEN

_DLY1

SDRC_D25

SDRC_D26

SDRC_D27

SCRC_D29

SDRC_D28

SDRC_ DQS3N

SDRC_ DQS3P

SDRC_D30

SDRC_D31

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Figure 2-4. ZCN Pin Map [Quadrant D]

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VSS

MMC2_DAT4

VDDS_DPLL_

MPU_

USBHOST

HGF

VSS

VDDS_

SRAM_MPU

VSS VDDS

VSS

VDD_CORE

VSS

VDD_CORE

VSS

VDD_CORE

VSS

VDD_COREVDD_CORE

VSS

VSSVSS

VSS

VDDSHVVSS

VDDSHV

DSS_PCLK

UART1_TX ETK_D8 ETK_D10 ETK_D1

ETK_CLK

MCSPI2_

SOMI

MCSPI2_CLK MCSPI1_CLK

VDDSHV

DSS_HSYNC UART1_RTS

ETK_D9

ETK_D7 ETK_D5

ETK_CTL MCSPI2_CS0 MCSPI1_CS3 MMC2_DAT3 MMC2_DAT6

DSS_DATA0 DSS_VSYNC

UART1_RX ETK_D11 ETK_D2

MCSPI2_

SIMO

MMC2_DAT0 MMC2_DAT5

DSS_DATA1 DSS_ACBIAS

ETK_D6 ETK_D3

MCSPI2_CS1

MCSPI1_SIMO

MMC2_DAT1

DSS_DATA2 DSS_DATA3 DSS_DATA5

VSS VDDSHV

MCSPI1_CS0

DSS_DATA4 DSS_DATA8 DSS_DATA9 DSS_DATA6

VSS VDDSHV VSS

DSS_DATA13 DSS_DATA7 DSS_DATA10 DSS_DATA11

VSS VDDS

DSS_DATA16 DSS_DATA15

DSS_DATA17 DSS_DATA23 DSS_DATA22 DSS_DATA12 JTAG_TCK

DSS_DATA20 DSS_DATA21 DSS_DATA18 JTAG_NTRST JTAG_EMU0

JTAG_TMS_

TMSC

JTAG_TDI

HGF

ETK_D13 ETK_D0

MCSPI1_CS1

UART1_CTS

ETK_D14

ETK_D4

MCSPI1_CS2

ETK_D15 ETK_D12

VDDSHV

MCSPI1_

SOMI

VDDSHV VDDSHV

VSS

VDD_CORE

DSS_DATA19 DSS_DATA14

VDDSHV VSS VDDS

VDD_CORE

VSS

JTAG_RTCK

JTAG_TDO

JTAG_EMU1

VDDSHV VDDSHV

AM3517, AM3505

SPRS550B–OCTOBER 2009–REVISED JULY 2010

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Figure 2-5. ZER Pin Map [Quadrant A]

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CCDC_FIELD

CCDC_

PCLK

CCDC_HDCCDC_WEN

CCDC_

DATA2

RMII_

MDIO_DATA

RMII_

CRS_DV

RMII_

50MHZ_CLK

MMC1_DAT0MMC1_CMDMMC2_CLK

VSS

GPMC_CLK

GPMC_NOE

HECC1_TXD

HECC1_RXD

I2C1_SDA

SYS_NIRQ

SYS_BOOT0

SYS_BOOT1SYS_BOOT7

SYS_BOOT3

SYS_NRES

PWRON

I2C1_SCL

SYS_BOOT8

N P R

U V

AA AB

VDDSHV VSS

CCDC_VD

CCDC_

DATA0

CCDC_

DATA4

RMII_

MDIO_CLK

RMII_TXD0

RMII_RXER

MMC1_CLKMMC1_DAT4

VSS

MMC1_DAT3MMC1_DAT1

MMC1_DAT2MMC1_DAT5

MMC1_DAT7

MMC1_DAT6

VSS

VDDSHV VSS

VDDSHV

VDD_CORE VDD_CORE

VSS

VDD_CORE

VSS

VDD_CORE

VSS

VDD_CORE

VSS

VDD_CORE VDD_CORE

VSS VSS

CCDC_ DATA6

CCDC_

DATA5

CCDC_

DATA7

VSS

VDDSHV

VSS

VDDSHV

RMII_RXD1

RMII_RXD0

VSS

VDDSHV

VDDS

VDDSHV

VSS

RESERVED

I2C3_SCL

UART3_CTS

_RCTX

SYS_NRE

SWARM

I2C2_SCLI2C3_SDA

GPMC_

WAIT1

GPMC_NWEGPMC_NBE1

GPMC_

NADV_ALE

UART3_RX

_IRRX

UART3_TX

_IRTX

UART3_RTS

_SD

GPMC_

WAIT0

GPMC_NCS3 GPMC_NCS5 GPMC_NCS2 GPMC_NCS6

N P R

U V

AA AB

MMC2_CMD

RMII_TXD1

CCDC_

DATA1

MMC2_DAT7

RMII_TXEN

CCDC_

DATA3

SYS_BOOT6 SYS_BOOT5

MMC2_DAT2

VDDSHV VDDSHV

SYS_BOOT4 SYS_BOOT2

CAP_VDD

_SRAM_MPU

VSS VDDSHV

VSS VDDSHV VSS

I2C2_SDA

VSS VDDSHV

GPMC_ WAIT3

GPMC_NWP

GPMC_ WAIT2

VDD_CORE

VSS

AM3517, AM3505

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Figure 2-6. ZER Pin Map [Quadrant B]

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HGF

VSS

MCBSP1

_CLKR

MCBSP1_FSX MCBSP1_FSR MCBSP_CLKS

VSS VSS

VSS

VDD_CORE

VSS

MCBSP1_DX

SYS_

CLKOUT2

VSS

VDD_CORE

VSSVDDSHV

VSS VSS

VDD_CORE

VSS

VDDS

VDDS_SRAM

_CORE_BG

SYS_XTALIN

VSSOSC

SYS_

XTALOUT

SYS_32K

SYS_CLKREQ

MCBSP1

_CLKX

NC NC NC

VDDA3P3V

_USBPHY

CAP_VDDA1

P2LDO_

USBPHY

USB0_

DRVVBUS

USB0_DP

UART2_CTS

MCBSP3_FSX

MCBSP4

_CLKX

MCBSP4_DX

VSS VDDSHV

MCBSP4_FSX

MCBSP4_DR

MCBSP3_DR

UART2_RTS

SDRC_D6

SDRC_D3

SDRC_D2

MCBSP2_DR

UART2_RX

VDDA1P8V

_USBPHY

UART2_TX

SDRC_D7

SDRC_DQS0N

SDRC_

STRBEN

_DLY0

SDRC_D13

SDRC_DQS1N

SDRC_D15

SDRC_NRAS SDRC_CLK

SDRC_NCLK

SDRC_NWE

SDRC_DM1

SDRC_DQS1P

SDRC_D8

SDRC_

STRBEN0

SDRC_DQS0P

SDRC_D5

SDRC_D0

SDRC_D4

SDRC_D9 SDRC_D14

SDRC_CKE0

SDRC_DM0 SDRC_D11

SDRC_NCS0 SDRC_NCS1

VSS

SDRC_BA2

SDRC_BA1

USB0_DM

VSS

USB0_ID

VSS

HGF

VDDS_

DPLL_PER

_CORE

VSS

VDD_CORE

HDQ_SIO

MCBSP1_DR

SYS_

CLKOUT1

VDDSOSC

VSS

VDDSHV

USB0_VBUS

VSS

CAP_VDD_

SRAM_CORE

MCBSP2

_CLKX

MCBSP2_FSX

VDDS

VREFSSTL

MCBSP3_DX

MCBSP3

_CLKX

MCBSP2_DX

SDRC_D12 SDRC_BA0

SDRC_D1 SDRC_D10

SDRC_NCAS

AM3517, AM3505

SPRS550B–OCTOBER 2009–REVISED JULY 2010

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Figure 2-7. ZER Pin Map [Quadrant C]

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N P

W Y

R T U

VDD_CORE

VSS

VDD_CORE

VSS

VDD_CORE

VDDSHV

VSS

VSS VDDSHV

GPMC_D14 GPMC_D8

GPMC_NCS0

GPMC_D15VSSVDDSHV

VDDSHVVSS

VDDS

GPMC_D12

GPMC_D10

GPMC_D3 GPMC_D9

GPMC_D13

GPMC_D0 GPMC_A9GPMC_D1

GPMC_A6GPMC_A7GPMC_A8

VSS

GPMC_A5

VSS

VDD_CORE

VDD_CORE VSS

VSS

VDD_CORE

VSS VDD_CORE

VDD_COREVDD_CORE

VDDS VSS

VSS

VDDS

VDDSVSS

DDR_

PADREF

SDRC_A0

SDRC_A1

SDRC_A2

SDRC_A4

SDRC_A8

SDRC_A7

SDRC_A6

SDRC_A9

VDDS VSS

SDRC_A13

SDRC_A12

SDRC_A11

SDRC_A10

SDRC_A14

SDRC_

ODT

SDRC_ DQS2P

SDRC_ DQS2N

SDRC_D17

SDRC_D18

VSS

SDRC_D22

SDRC_D19

SDRC_D21

SDRC_

D20

GPMC_D2

SDRC_D25

SDRC_D24

SDRC_

STRBEN

_DLY1

SDRC_

STRBEN1

SDRC_ DQS3P

SDRC_

DQS3N

SDRC_D26

SDRC_D28

VDDS VSS

SDRC_D31

SDRC_DM3

N P

W Y

ABR T U

GPMC_NCS7

GPMC_

NBE0_CLE

GPMC_NCS1 GPMC_NCS4

VDDSHV

VDD_CORE

VSS

GPMC_D11

VDDSHV

GPMC_D5 GPMC_D6

GPMC_D4

GPMC_D7

VSS

VDDSHV

GPMC_A10

VSSVSS

VDDS VDDS

GPMC_A1 GPMC_A2 GPMC_A4

GPMC_A3

SDRC_D27 SDRC_D30SDRC_DM2

SDRC_A5

SDRC_A3

SDRC_D16

SDRC_D23

SDRC_D29

AM3517, AM3505

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Figure 2-8. ZER Pin Map [Quadrant D]

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

2.2 Ball Characteristics

Table 2-1 describes the terminal characteristics and the signals multiplexed on each pin for the ZCN/ZER

package. The following list describes the table column headers.

1. BALL LOCATION: Ball number(s) on the bottom side associated with each signal(s) on the bottom.

2. PIN NAME: Names of signals multiplexed on each ball (also notice that the name of the pin is the signal name in mode 0). Note: The Ball Characteristics table does not take into account subsystem pin multiplexing options. Subsystem pin multiplexing options are described in Section 2.4, Signal Descriptions.

3. MODE: Multiplexing mode number. (a) Mode 0 is the primary mode; this means that when mode 0 is set, the function mapped on the pin

corresponds to the name of the pin. There is always a function mapped on the primary mode. Notice that primary mode is not necessarily the default mode.

Note: The default mode is the mode which is automatically configured on release of the internal GLOBAL_PWRON reset; also see the RESET REL. MODE column.

(b) Modes 1 to 7 are possible modes for alternate functions. On each pin, some modes are effectively

used for alternate functions, while some modes are not used and do not correspond to a functional configuration.

4. TYPE: Signal direction – I = Input

– O = Output – I/O = Input/Output – D = Open drain – DS = Differential – A = Analog

Note: In the safe_mode, the buffer is configured in high-impedance.

5. BALL RESET STATE: The state of the terminal at reset (power up). – 0: The buffer drives VOL(pulldown/pullup resistor not activated)

0(PD): The buffer drives VOLwith an active pulldown resistor.

– 1: The buffer drives VOH(pulldown/pullup resistor not activated)

1(PU): The buffer drives VOHwith an active pullup resistor. – Z: High-impedance – L: High-impedance with an active pulldown resistor – H : High-impedance with an active pullup resistor

6. BALL RESET REL. STATE: The state of the terminal at reset release. – 0: The buffer drives VOL(pulldown/pullup resistor not activated)

0(PD): The buffer drives VOLwith an active pulldown resistor.

– 1: The buffer drives VOH(pulldown/pullup resistor not activated)

1(PU): The buffer drives VOHwith an active pullup resistor. – Z: High-impedance – L: High-impedance with an active pulldown resistor – H : High-impedance with an active pullup resistor

7. RESET REL. MODE: This mode is automatically configured on release of the internal GLOBAL_PWRON reset.

8. POWER: The voltage supply that powers the terminal’s I/O buffers.

9. VOLTAGE: Supply voltage for associated pin.

10. HYS: Indicates if the input buffer is with hysteresis.

11. LOAD: Load capacitance of the associated output buffer.

12. PULL U/D - TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.

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13. IO CELL: IO cell information. Note: Configuring two pins to the same input signal is not supported as it can yield unexpected results.

This can be easily prevented with the proper software configuration.

Table 2-1. Ball Characteristics (ZCN Pkg.)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

B21 sdrc_d0 0 IO L Z 0 VDDS 1.8V Yes 4 PU/PD LVCMOS A21 sdrc_d1 0 IO L Z 0 VDDS 1.8V Yes 4 PU/PD LVCMOS D20 sdrc_d2 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C20 sdrc_d3 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS E19 sdrc_d4 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D19 sdrc_d5 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C19 sdrc_d6 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS B19 sdrc_d7 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS B18 sdrc_d8 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D17 sdrc_d9 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C17 sdrc_d10 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D16 sdrc_d11 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C16 sdrc_d12 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS B16 sdrc_d13 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS A16 sdrc_d14 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS A15 sdrc_d15 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS A7 sdrc_d16 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS B7 sdrc_d17 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D7 sdrc_d18 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS E7 sdrc_d19 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C6 sdrc_d20 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D6 sdrc_d21 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS B5 sdrc_d22 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C5 sdrc_d23 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS B4 sdrc_d24 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS A3 sdrc_d25 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS B3 sdrc_d26 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C3 sdrc_d27 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C2 sdrc_d28 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D2 sdrc_d29 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS B1 sdrc_d30 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C1 sdrc_d31 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS A12 sdrc_ba0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS C13 sdrc_ba1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS D13 sdrc_ba2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS A11 sdrc_a0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS B11 sdrc_a1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS C11 sdrc_a2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS D11 sdrc_a3 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS E11 sdrc_a4 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS A10 sdrc_a5 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS B10 sdrc_a6 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS C10 sdrc_a7 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS D10 sdrc_a8 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS E10 sdrc_a9 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS A9 sdrc_a10 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS B9 sdrc_a11 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS A8 sdrc_a12 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS B8 sdrc_a13 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS

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Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

D8 sdrc_a14 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS E13 sdrc_ncs0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS A14 sdrc_ncs1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS A13 sdrc_clk 0 O L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS B13 sdrc_nclk 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS D14 sdrc_cke0 0 O L PD 7 VDDS 1.8V Yes 8 PU/PD LVCMOS

sdrc_cke0_s 7 L

afe C14 sdrc_nras 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS E14 sdrc_ncas 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS B14 sdrc_nwe 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS C21 sdrc_dm0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS B15 sdrc_dm1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS E8 sdrc_dm2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS D1 sdrc_dm3 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS B20 sdrc_dqs0p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS B17 sdrc_dqs1p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS A6 sdrc_dqs2p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS A2 sdrc_dqs3p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS A20 sdrc_dqs0n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS A17 sdrc_dqs1n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS B6 sdrc_dqs2n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS B2 sdrc_dqs3n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS C8 sdrc_odt 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS A19 sdrc_strben0 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS A18 sdrc_strben_ 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS

A5 sdrc_strben1 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS A4 sdrc_strben_ 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS

B12 ddr_padref 0 A VDDS 1.8V E3 gpmc_a1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

E2 gpmc_a2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

E1 gpmc_a3 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

F7 gpmc_a4 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

F6 gpmc_a5 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

F4 gpmc_a6 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

F3 gpmc_a7 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

F2 gpmc_a8 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

F1 gpmc_a9 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

dly0

dly1

gpio_34 4 IO

safe_mode 7

gpio_35 4 IO

safe_mode 7

gpio_36 4 IO

safe_mode 7

gpio_37 4 IO

safe_mode 7

gpio_38 4 IO

safe_mode 7

gpio_39 4 IO

safe_mode 7

gpio_40 4 IO

safe_mode 7

gpio_41 4 IO

safe_mode 7

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Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

sys_ 1 I

ndmareq2

gpio_42 4 IO

safe_mode 7 G6 gpmc_a10 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

sys_ 1 I

ndmareq3

gpio_43 4 IO

safe_mode 7 G5 gpmc_d0 0 IO H PU 0 VDDSHV 1.8V/3.3V 30 PU/ PD LVCMOS G4 gpmc_d1 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS G3 gpmc_d2 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS G2 gpmc_d3 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS G1 gpmc_d4 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS H2 gpmc_d5 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS H1 gpmc_d6 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS J5 gpmc_d7 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS J4 gpmc_d8 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_44 4 IO J3 gpmc_d9 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_45 4 IO J2 gpmc_d10 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_46 4 IO J1 gpmc_d11 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_47 4 IO K4 gpmc_d12 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_48 4 IO K3 gpmc_d13 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_49 4 IO K2 gpmc_d14 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_50 4 IO K1 gpmc_d15 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_51 4 IO L2 gpmc_ncs0 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 NA LVCMOS L1 gpmc_ncs1 0 O H Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_52 4 IO M4 gpmc_ncs2 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpt9_pwm_e 2 IO

gpio_53 4 IO

safe_mode 7 M3 gpmc_ncs3 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

sys_ 1 I

ndmareq0

gpt10_pwm_ 2 IO

evt

gpio_54 4 IO

safe_mode 7 M2 gpmc_ncs4 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

sys_ 1 I

ndmareq1

gpt9_pwm_e 3 IO

gpio_55 4 IO

safe_mode 7

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Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

M1 gpmc_ncs5 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

sys_ 1 I

ndmareq2

gpt10_pwm_ 3 IO

evt

gpio_56 4 IO

safe_mode 7 N5 gpmc_ncs6 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

sys_ 1 I

ndmareq3

gpt11_pwm_ 3 IO

evt

gpio_57 4 IO

safe_mode 7 N4 gpmc_ncs7 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpmc_io_dir 1 O

gpt8_pwm_e 3 IO

gpio_58 4 IO

safe_mode 7 N1 gpmc_clk 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_59 4 IO R1 gpmc_nadv_ 0 O L Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS

R2 gpmc_noe 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS R3 gpmc_nwe 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS R4 gpmc_nbe0_ 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

T1 gpmc_nbe1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

T2 gpmc_nwp 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

T3 gpmc_wait0 0 I H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS T4 gpmc_wait1 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

T5 gpmc_wait2 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

U1 gpmc_wait3 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AE23 dss_pclk 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

AD22 dss_hsync 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

ale

cle

gpio_60 4 IO

gpio_61 4 IO

safe_mode 7

gpio_62 4 IO

uart4_tx 1 O

gpio_63 4 IO

safe_mode 7

uart4_rx 1 I

gpio_64 4 IO

safe_mode 7

sys_ 1 I

ndmareq1

uart3_cts_rct 2 I

gpio_65 4 IO

safe_mode 7

gpio_66 4 IO

hw_dbg12 5 O

safe_mode 7

gpio_67 4 IO

hw_dbg13 5 O

safe_mode 7

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

AD23 dss_vsync 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_68 4 IO

safe_mode 7 AE24 dss_acbias 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_69 4 IO

safe_mode 7 AD24 dss_data0 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

uart1_cts 2 I

gpio_70 4 IO

safe_mode 7 AD25 dss_data1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

uart1_rts 2 O

gpio_71 4 IO

safe_mode 7 AC23 dss_data2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_72 4 IO

safe_mode 7 AC24 dss_data3 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_73 4 IO

safe_mode 7 AC25 dss_data4 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

uart3_rx_ irrx 2 I

gpio_74 4 IO

safe_mode 7 AB24 dss_data5 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

uart3_tx_ irtx 2 O

gpio_75 4 IO

safe_mode 7 AB25 dss_data6 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

uart1_tx 2 O

gpio_76 4 IO

hw_dbg14 5 O

safe_mode 7 AA23 dss_data7 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

uart1_rx 2 I

gpio_77 4 IO

hw_dbg15 5 O

safe_mode 7 AA24 dss_data8 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_78 4 IO

hw_dbg16 5 O

safe_mode 7 AA25 dss_data9 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_79 4 IO

hw_dbg17 5 O

safe_mode 7 Y22 dss_data10 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_80 4 IO

safe_mode 7 Y23 dss_data11 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_81 4 IO

safe_mode 7 Y24 dss_data12 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_82 4 IO

safe_mode 7

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

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Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

Y25 dss_data13 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_83 4 IO

safe_mode 7 W21 dss_data14 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_84 4 IO

safe_mode 7 W22 dss_data15 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_85 4 IO

safe_mode 7 W23 dss_data16 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_86 4 IO

safe_mode 7 W24 dss_data17 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_87 4 IO

safe_mode 7 W25 dss_data18 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

mcspi3_clk 2 IO

dss_data4 3 O

gpio_88 4 IO

safe_mode 7 V24 dss_data19 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

mcspi3_ 2 IO

simo

dss_data3 3 O

gpio_89 4 IO

safe_mode 7 V25 dss_data20 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

mcspi3_ 2 IO

somi

dss_data2 3 O

gpio_90 4 IO

safe_mode 7 U21 dss_data21 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

mcspi3_cs0 2 IO

dss_data1 3 O

gpio_91 4 IO

safe_mode 7 U22 dss_data22 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

mcspi3_cs1 2 O

dss_data0 3 O

gpio_92 4 IO

safe_mode 7 U23 dss_data23 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

dss_data5 3 O

gpio_93 4 IO

safe_mode 7 H24 tv_out2 0 O 0 VDDA_DAC 1.8V NA 10-bit DAC K21 tv_out1 0 O 0 VDDA_DAC 1.8V NA 10-bit DAC K20 tv_vfb1 0 O Z NA 0 VDDA_DAC 1.8V NA 10-bit DAC H23 tv_vfb2 0 O Z NA 0 VDDA_DAC 1.8V NA 10-bit DAC H20 tv_vref 0 I Z NA 0 VDDA_DAC 1.8V NA 10-bit DAC AD2 ccdc_pclk 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS

gpio_94 4 IO

hw_dbg0 5 O

safe_mode 7

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

AD1 ccdc_field 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS

ccdc_data8 1 I

uart4_tx 2 O

i2c3_scl 3 IOD

gpio_95 4 IO

hw_dbg1 5 O

safe_mode 7 AE2 ccdc_ hd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS

uart4_rts 2 O

gpio_96 4 IO

safe_mode 7 AD3 ccdc_vd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS

uart4_cts 2 I

gpio_97 4 IO

hw_dbg2 5 O

safe_mode 7 AE3 ccdc_wen 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS

ccdc_data9 1 I

uart4_rx 2 I

gpio_98 4 IO

hw_dbg3 5 O

safe_mode 7 AD4 ccdc_data0 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS

i2c3_sda 3 IOD

gpio_99 4 I

safe_mode 7 AE4 ccdc_data1 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS

gpio_100 4 I

safe_mode 7 AC5 ccdc_data2 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS

gpio_101 4 IO

hw_dbg4 5 O

safe_mode 7 AD5 ccdc_data3 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS

gpio_102 4 IO

hw_dbg5 5 O

safe_mode 7 AE5 ccdc_data4 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS

gpio_103 4 IO

hw_dbg6 5 O

safe_mode 7 Y6 ccdc_data5 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS

gpio_104 4 IO

hw_dbg7 5 O

safe_mode 7 AB6 ccdc_data6 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS

gpio_105 4 IO

safe_mode 7 AC6 ccdc_data7 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS

gpio_106 4 IO

safe_mode 7 AE6 rmii_mdio_da 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS

ccdc_data8 1 I

gpio_107 4 IO

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

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Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

safe_mode 7 AD6 rmii_mdio_cl 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS

Y7 rmii_rxd0 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS

AA7 rmii_rxd1 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS

AB7 rmii_crs_dv 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS

AC7 rmii_rxer 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS

AD7 rmii_txd0 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS

AE7 rmii_txd1 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS

AD8 rmii_txen 0 O H PU 7 VDDSHV 1.8V/3.3V 25 PU/PD LVCMOS

AE8 rmii_50mhz_ 0 I H PU 7 VDDSHV 1.8V/3.3V 25 PU/ PD LVCMOS

D25 mcbsp2_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

C25 mcbsp2_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

B25 mcbsp2_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

D24 mcbsp2_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AA9 mmc1_clk 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

ccdc_data9 1 I

gpio_108 4 IO

safe_mode 7

ccdc_data10 1 I

gpio_109 4 IO

hw_dbg8 5 O

safe_mode 7

ccdc_data11 1 I

gpio_110 4 IO

hw_dbg9 5 O

safe_mode 7

ccdc_data12 1 I

gpio_111 4 IO

safe_mode 7

ccdc_data13 1 I

gpio_167 4 IO

hw_dbg10 5 O

safe_mode 7

ccdc_ data14 1 I

gpio_126 4 IO

hw_dbg11 5 O

safe_mode 7

ccdc_data15 1 I

gpio_112 4 I

safe_mode 7

gpio_113 4 I NA

safe_mode 7

clk

gpio_114 4 I NA

safe_mode 7

gpio_116 4 IO

safe_mode 7

clkx

gpio_117 4 IO

safe_mode 7

gpio_118 4 IO

safe_mode 7

gpio_119 4 IO

safe_mode 7

gpio_120 4 IO

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

safe_mode 7 AB9 mmc1_cmd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_121 4 IO

safe_mode 7 AC9 mmc1_dat0 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcspi2_clk 1 IO

gpio_122 4 IO

safe_mode 7 AD9 mmc1_dat1 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcspi2_simo 1 IO

gpio_123 4 IO

safe_mode 7 AE9 mmc1_dat2 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcspi2_somi 1 IO

gpio_124 4 IO

safe_mode 7 AA10 mmc1_dat3 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcspi2_cs0 1 O

gpio_125 4 IO

safe_mode 7 AB10 mmc1_dat4 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS

gpio_126 4 IO

safe_mode 7 AC10 mmc1_dat5 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS

gpio_127 4 IO

safe_mode 7 AD10 mmc1_dat6 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS

gpio_128 4 IO

safe_mode 7 AE10 mmc1_dat7 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS

gpio_129 4 IO

safe_mode 7 AD11 mmc2_clk 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcspi3_clk 1 IO

uart4_cts 2 I

gpio_130 4 IO

safe_mode 7 AE11 mmc2_ cmd 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcspi3_ 1 IO

simo

uart4_rts 2 O

gpio_131 4 IO

safe_mode 7 AB12 mmc2_ dat0 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcspi3_ 1 IO

somi

uart4_tx 2 O

gpio_132 4 IO

safe_mode 7 AC12 mmc2_ dat1 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

uart4_rx 2 I

gpio_133 4 IO

safe_mode 7 AD12 mmc2_ dat2 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcspi3_cs1 1 O

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Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

gpio_134 4 IO

safe_mode 7 AE12 mmc2_ dat3 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcspi3_cs0 1 IO

gpio_135 4 IO

safe_mode 7 AB13 mmc2_ dat4 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mmc2_dir_da 1 O

mmc3_dat0 3 IO

gpio_136 4 IO

safe_mode 7 AC13 mmc2_ dat5 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mmc2_dir_da 1 O

mmc3_dat1 3 IO

gpio_137 4 IO

mm_fsusb3_r 6 IO

xdp

safe_mode 7 AD13 mmc2_ dat6 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mmc2_dir_ 1 O

cmd

mmc3_dat2 3 IO

gpio_138 4 IO

safe_mode 7 AE13 mmc2_ dat7 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mmc2_ clkin 1 I

mmc3_dat3 3 IO

gpio_139 4 IO

mm_fsusb3_r 6 IO

xdm

safe_mode 7 B24 mcbsp3_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

uart2_cts 1 I

gpio_140 4 IO

safe_mode 7 C24 mcbsp3_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

uart2_rts 1 O

gpio_141 4 IO

safe_mode 7 A24 mcbsp3_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

C23 mcbsp3_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

F20 uart2_cts 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

F19 uart2_rts 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

clkx

uart2_tx 1 O

gpio_142 4 IO

safe_mode 7

uart2_rx 1 I

gpio_143 4 IO

safe_mode 7

mcbsp3_dx 1 IO

gpt9_pwm_e 2 IO

gpio_144 4 IO

safe_mode 7

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

mcbsp3_dr 1 I

gpt10_pwm_ 2 IO

evt

gpio_145 4 IO

safe_mode 7 E24 uart2_tx 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcbsp3_ 1 IO

clkx

gpt11_pwm 2 IO

_evt

gpio_146 4 IO

safe_mode 7 E23 uart2_rx 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcbsp3_fsx 1 IO

gpt8_pwm_e 2 IO

gpio_147 4 IO

safe_mode 7 AA19 uart1_tx 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_148 4 IO

safe_mode 7 Y19 uart1_rts 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_149 4 IO

safe_mode 7 Y20 uart1_cts 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_150 4 IO

safe_mode 7 W20 uart1_rx 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcbsp1_ clkr 2 I

mcspi4_clk 3 IO

gpio_151 4 IO

safe_mode 7 B23 mcbsp4_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

A23 mcbsp4_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

B22 mcbsp4_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

A22 mcbsp4_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

R25 mcbsp1_ clkr 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

P21 mcbsp1_fsr 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

clkx

gpio_152 4 IO

mm_fsusb3_t 6 IO

xse0

safe_mode 7

gpio_153 4 IO

mm_fsusb3_r 6 IO

xrcv

safe_mode 7

gpio_154 4 IO

mm_fsusb3_t 6 IO

xdat

safe_mode 7

gpio_155 4 IO

mm_fsusb3_t 6 IO

xen_ n

safe_mode 7

mcspi4_clk 1 IO

gpio_156 4 IO

safe_mode 7

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

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Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

gpio_157 4 IO

safe_mode 7 P22 mcbsp1_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcspi4_ 1 IO

simo

mcbsp3_dx 2 IO

gpio_158 4 IO

safe_mode 7 P23 mcbsp1_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcspi4_ 1 IO

somi

mcbsp3_dr 2 I

gpio_159 4 IO

safe_mode 7 P25 mcbsp_clks 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_160 4 IO

uart1_cts 5 I

safe_mode 7 P24 mcbsp1_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcspi4_cs0 1 IO

mcbsp3_fsx 2 IO

gpio_161 4 IO

safe_mode 7 N24 mcbsp1_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

N2 uart3_cts_ 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

N3 uart3_rts_ sd 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

P1 uart3_rx_ irrx 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

P2 uart3_tx_ irtx 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

F25 usb0_dp 0 IO 5.0V Yes PU/ PD LVCMOS

F24 usb0_dm 0 IO 5.0V Yes PU/ PD LVCMOS

G24 usb0_vbus 0 A VDDA3P3V_ 5.0V Yes PU/ PD LVCMOS

G25 usb0_id 0 A VDDA3P3V_ 3.3V Yes PU/ PD LVCMOS

E25 usb0_drvvbu 0 O L PD 7 VDDSHV 1.8V/3.3V 30

V2 hecc1_ txd 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 24 PU/ PD LVCMOS

clkx

mcbsp3_ 2 IO

clkx

gpio_162 4 IO

safe_mode 7

rctx

gpio_163 4 IO

safe_mode 7

gpio_164 4 IO

safe_mode 7

gpio_165 4 IO

safe_mode 7

gpio_166 4 IO

safe_mode 7

uart3_tx_ irtx 1 O

uart3_rx_ irrx 1 I

uart3_tx_ irtx 2 O

gpio_125 4 IO

safe_mode 7

uart3_rx_ irrx 2 I

gpio_130 4 IO

USBPHY

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

safe_mode 7 V3 hecc1_ rxd 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 24 PU/ PD LVCMOS

uart3_rts_ sd 2 O

gpio_131 4 IO

safe_mode 7 V4 i2c1_scl 0 IOD H PU 0 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain V5 i2c1_ sda 0 IOD H PU 0 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain W1 i2c2_scl 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain

gpio_168 4 IO

safe_mode 7 W2 i2c2_sda 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain

gpio_183 4 IO

safe_mode 7 W4 i2c3_scl 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain

gpio_184 4 IO

safe_mode 7 W5 i2c3_sda 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain

gpio_185 4 IO

safe_mode 7 L25 hdq_sio 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD LVCMOS

sys_altclk 1 I

i2c2_sccbe 2 O

i2c3_sccbe 3 O

gpio_170 4 IO

safe_mode 7 AE14 mcspi1_clk 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mmc2_dat4 1 IO

gpio_171 4 IO

safe_mode 7 AD15 mcspi1_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AC15 mcspi1_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AB15 mcspi1_cs0 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AD14 mcspi1_cs1 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AE15 mcspi1_cs2 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AE16 mcspi1_cs3 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

simo

mmc2_dat5 1 IO

gpio_172 4 IO

safe_mode 7

somi

mmc2_dat6 1 IO

gpio_173 4 IO

safe_mode 7

mmc2_dat7 1 IO

gpio_174 4 IO

safe_mode 7

mmc3_cmd 3 IO

gpio_175 4 IO

safe_mode 7

mmc3_clk 3 O

gpio_176 4 IO

safe_mode 7

hsusb2_ 3 IO

data2

gpio_177 4 IO

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

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Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

mm_fsusb2_t 5 IO

xdat

safe_mode 7 AD16 mcspi2_clk 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

hsusb2_ 3 IO

data7

gpio_178 4 IO

safe_mode 7 AC16 mcspi2_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AB16 mcspi2_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AA16 mcspi2_cs0 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AE17 mcspi2_cs1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

K24 sys_32k 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS K25 sys_xtalin 0 I Z Z 0 VDDSOSC 1.8V NA PU/ PD LVCMOS H25 sys_xtalout 0 O Z Z 0 VDDSOSC 1.8V NA PU/ PD LVCMOS M24 sys_clkreq 0 IO L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

Y1 sys_nirq 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

Y2 sys_ 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

Y3 sys_ 0 IO L PD 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

Y4 sys_boot0 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AA1 sys_boot1 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AA2 sys_boot2 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AA3 sys_boot3 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

simo

gpt9_pwm_e 1 IO

hsusb2_ 3 IO

data4

gpio_179 4 IO

safe_mode 7

somi

gpt10_pwm_ 1 IO

evt

hsusb2_ 3 IO

data5

gpio_180 4 IO

safe_mode 7

gpt11_pwm_ 1 IO

evt

hsusb2_ 3 IO

data6

gpio_181 4 IO

safe_mode 7

gpt8_pwm_e 1 IO

hsusb2_ 3 IO

data3

gpio_182 4 IO

mm_fsusb2_t 5 IO

xen_ n

safe_mode 7

gpio_1 4 IO

gpio_0 4 IO

safe_mode 7

nrespwron

nreswarm

gpio_30 4 IO Open Drain

gpio_2 4 IO

gpio_3 4 IO

gpio_4 4 IO

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

gpio_5 4 IO AB1 sys_boot4 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mmc2_dir_da 1 O

gpio_6 4 IO AB2 sys_boot5 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mmc2_dir_da 1 O

gpio_7 4 IO AC1 sys_boot6 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_8 4 IO AC2 sys_boot7 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/PD LVCMOS AC3 sys_boot8 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/PD LVCMOS N25 sys_clkout1 0 O H PD 0/7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_10 4 IO

safe_mode 7 M25 sys_clkout2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 10 PU/ PD LVCMOS

gpio_186 4 IO

safe_mode 7 U24 jtag_ntrst 0 I L PD 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS U25 jtag_tck 0 I L PD 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS T21 jtag_rtck 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS T22 jtag_tms_tms 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

T23 jtag_tdi 0 I H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS T24 jtag_tdo 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS T25 jtag_emu0 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

R24 jtag_emu1 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

AD17 etk_clk 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

AE18 etk_ctl 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

AD18 etk_d0 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

AC18 etk_d1 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

gpio_11 4 IO

gpio_31 4 IO

mcbsp5_ 1 IO

clkx

mmc3_clk 2 O

hsusb1_stp 3 O

gpio_12 4 IO

mmc3_cmd 2 IO

hsusb1_clk 3 O

gpio_13 4 IO

mm_fsusb1_r 5 IO

xdp

mcspi3_ 1 IO

simo

mmc3_dat4 2 IO

hsusb1_ 3 IO

data0

gpio_14 4 IO

mm_fsusb1_r 5 IO

xrcv

mcspi3_ 1 IO

somi

hsusb1_ 3 IO

data1

gpio_15 4 IO

mm_fsusb1_t 5 IO

xse0

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Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

AB18 etk_d2 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

mcspi3_cs0 1 IO

hsusb1_ 3 IO

data2

gpio_16 4 IO

mm_fsusb1_t 5 IO

xdat AA18 etk_d3 0 O L PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

mcspi3_clk 1 IO

mmc3_dat3 2 IO

hsusb1_ 3 IO

data7

gpio_17 4 IO Y18 etk_d4 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

mcbsp5_dr 1 I

mmc3_dat0 2 IO

hsusb1_ 3 IO

data4

gpio_18 4 IO AE19 etk_d5 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

mcbsp5_fsx 1 IO

mmc3_dat1 2 IO

hsusb1_ 3 IO

data5

gpio_19 4 IO AD19 etk_d6 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

mcbsp5_dx 1 IO

mmc3_dat2 2 IO

hsusb1_ 3 IO

data6

gpio_20 4 IO AB19 etk_d7 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

mcspi3_cs1 1 O

mmc3_dat7 2 IO

hsusb1_ 3 IO

data3

gpio_21 4 IO

mm_fsusb1_t 5 IO

xen_n AE20 etk_d8 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

mmc3_dat6 2 IO

hsusb1_dir 3 I

gpio_22 4 IO AD20 etk_d9 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

mmc3_dat5 2 IO

hsusb1_nxt 3 I

gpio_23 4 IO

mm_fsusb1_r 5 IO

xdm AC20 etk_d10 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

uart1_rx 2 I

hsusb2_clk 3 O

gpio_24 4 IO AB20 etk_d11 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

mcspi3_clk 1 IO

hsusb2_stp 3 O

gpio_25 4 IO

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

mm_fsusb2_r 5 IO

xdp AE21 etk_d12 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

hsusb2_dir 3 I

gpio_26 4 IO AD21 etk_d13 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

hsusb2_nxt 3 I

gpio_27 4 IO

mm_fsusb2_r 5 IO

xdm AC21 etk_d14 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

hsusb2_ 3 IO

data0

gpio_28 4 IO

mm_fsusb2_r 5 IO

xrcv AE22 etk_d15 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

hsusb2_ 3 IO

data1

gpio_29 4 IO

mm_fsusb2_t 5 IO

xse0 V16, V15, VDD_CORE 0 PWR 1.2V

V11, V10, U16, U15, U11, U10, T18, T17, T9, T8, R18, R17, R9, R8, M18, L18, L9, L8, K18, K17, K9, K8, J16, J15, J11, J10, H15, H11, H10

AA13 VDDS_SRA 0 PWR 1.8V

E17 VDDS_SRA 0 PWR 1.8V

AA12 CAP_VDD_S 0 PWR 1.2V

E16 CAP_VDD_S 0 PWR 1.2V

AA15 VDDS_DPLL 0 PWR 1.8V

N20 VDDS_DPLL 0 PWR 1.8V

H21 VDDA_DAC 0 PWR 1.8V F23 VDDA3P3V_ 0 PWR 3.3V

G22 VDDA1P8V_ 0 PWR 1.8V

F22 CAP_VDDA1 0 PWR 1.2V

M_MPU

M_CORE_B

RAM_MPU

RAM_CORE

_MPU_USB

HOST

_PER_CORE

USBPHY

P2LDO_USB

PHY

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

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Table 2-1. Ball Characteristics (ZCN Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

Y16, Y15, VDDSHV 0 PWR 1.8V/3.3V Y13, Y12, Y10, W16, W15, W13, W12,W10, W9, W6, V7, V6, U19, T20, T19, T7, T6, R7, R6, P20, P19, N19, N7, N6, M7, M6, M5, L19, K19, K7, K6, K5, J7, H18, H17

Y9, W18, VDDS 0 PWR 1.8V U20, R5, H16, H8, G17, G16, G14, G13, G11, G10, G8, F16, F13, F11, F10, F8

F14 VREFSSTL 0 I L20 VDDSOSC 0 PWR 1.8V J25 VSSOSC O GND 1.8V AE25, AE1, VSS 0 GND

V18, V17, V14, V13, V12, V9, V8, U18, U17, U14, U13, U12, U9, U8, T14, T13, T12, R16, R15, R14, R13, R12, R11, R10, P18, P17, P16, P15, P14, P13, P12, P11, P10, P9, P8, N18, N17, N14, N13, N12, N9, N8, M17, M16, M15, M14, M13,M12, M11, M10, M9, M8, L17, L16, L15, L14, L13, L12, L11, L10, K14, K13, K12, J18, J17, J14, J13, J12, J9, J8, H14, H13, H12, H9, A25, A1, N23, G20, G21

H22 VSSA_DAC 0 GND L24, L23, NC

L22, L21, K23, K22, H19, N22,N21,F17

(2)

(1) "NC" indicates "No Connect". For proper device operation, these pins must be left unconnected. (2) For proper device operation, this pin must be pulled up via a 10k-Ω resistor.

(1)

Reserved

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Table 2-2. Ball Characteristics (ZER Pkg.)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

E3 sdrc_d0 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D3 sdrc_d1 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C3 sdrc_d2 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C2 sdrc_d3 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS F3 sdrc_d4 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D2 sdrc_d5 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS C1 sdrc_d6 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS D1 sdrc_d7 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS G2 sdrc_d8 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS G3 sdrc_d9 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS H3 sdrc_d10 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS G4 sdrc_d11 0 IO L Z 0 VDDS 1.8V Yes 4 PU/PD LVCMOS H4 sdrc_d12 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS G1 sdrc_d13 0 IO L Z 0 VDDS 1.8V Yes 4 PU/PD LVCMOS J3 sdrc_d14 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS J1 sdrc_d15 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS T3 sdrc_d16 0 IO L Z 0 VDDS 1.8V Yes 4 PU/PD LVCMOS U3 sdrc_d17 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS U4 sdrc_d18 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS V4 sdrc_d19 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS V1 sdrc_d20 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS V2 sdrc_d21 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS V5 sdrc_d22 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS V3 sdrc_d23 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS W3 sdrc_d24 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS W4 sdrc_d25 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS Y3 sdrc_d26 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS Y4 sdrc_d27 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS AA2 sdrc_d28 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS AA3 sdrc_d29 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS AA4 sdrc_d30 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS AB2 sdrc_d31 0 IO L Z 0 VDDS 1.8V Yes 4 PU/ PD LVCMOS L4 sdrc_ba0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS K5 sdrc_ba1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS J5 sdrc_ba2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS M3 sdrc_a0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS M4 sdrc_a1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS M5 sdrc_a2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS N3 sdrc_a3 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS N2 sdrc_a4 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS N4 sdrc_a5 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS P3 sdrc_a6 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS P2 sdrc_a7 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS P1 sdrc_a8 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS P4 sdrc_a9 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS R1 sdrc_a10 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS R2 sdrc_a11 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS R3 sdrc_a12 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS R4 sdrc_a13 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS T2 sdrc_a14 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS J4 sdrc_ncs0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS K4 sdrc_ncs1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS L1 sdrc_clk 0 O L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS L2 sdrc_nclk 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS

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Table 2-2. Ball Characteristics (ZER Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

K3 sdrc_cke0 0 O L PD 7 VDDS 1.8V Yes 8 PU/ PD LVCMOS

sdrc_cke0_s 7 I

afe K1 sdrc_nras 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS L3 sdrc_ncas 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS K2 sdrc_nwe 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS F4 sdrc_dm0 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS J2 sdrc_dm1 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS T4 sdrc_dm2 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS AB3 sdrc_dm3 0 O L Z 0 VDDS 1.8V No 8 PU/ PD LVCMOS E2 sdrc_dqs0p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS H2 sdrc_dqs1p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS U1 sdrc_dqs2p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS Y1 sdrc_dqs3p 0 IO L Z 0 VDDS 1.8V Yes 8 PU/ PD LVCMOS E1 sdrc_dqs0n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS H1 sdrc_dqs1n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS U2 sdrc_dqs2n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS Y2 sdrc_dqs3n 0 IO L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS T1 sdrc_odt 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS F2 sdrc_strben0 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS F1 sdrc_strben_ 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS

W1 sdrc_strben1 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS W2 sdrc_strben_ 0 L Z 0 VDDS 1.8V 8 PU/ PD LVCMOS

W5 gpmc_a1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

Y5 gpmc_a2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AB4 gpmc_a3 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AA5 gpmc_a4 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AB5 gpmc_a5 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AB6 gpmc_a6 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AA6 gpmc_a7 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

W6 gpmc_a8 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AB7 gpmc_a9 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

Y6 gpmc_a10 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AA7 gpmc_d0 0 IO H PU 0 VDDSHV 1.8V/3.3V 30 PU/ PD LVCMOS Y7 gpmc_d1 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS W7 gpmc_d2 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS AA9 gpmc_d3 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS Y8 gpmc_d4 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS AA8 gpmc_d5 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS AB8 gpmc_d6 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS W8 gpmc_d7 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

dly0

dly1

gpio_34 4 IO

gpio_35 4 IO

gpio_36 4 IO

gpio_37 4 IO

gpio_38 4 IO

gpio_39 4 IO

gpio_40 4 IO

gpio_41 4 IO

sys_ 1 I

ndmareq2

gpio_42 4 IO

sys_ 1 I

ndmareq3

gpio_43 4 IO

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Table 2-2. Ball Characteristics (ZER Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

W10 gpmc_d8 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_44 4 IO AB9 gpmc_d9 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_45 4 IO AB10 gpmc_d10 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_46 4 IO W9 gpmc_d11 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_47 4 IO AA10 gpmc_d12 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_48 4 IO Y9 gpmc_d13 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_49 4 IO V10 gpmc_d14 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_50 4 IO V9 gpmc_d15 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_51 4 IO Y10 gpmc_ncs0 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 NA LVCMOS Y11 gpmc_ncs1 0 O H Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_52 4 IO Y12 gpmc_ncs2 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpt9_pwm_e 2 IO

gpio_53 4 IO V12 gpmc_ncs3 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

sys_ 1 I

ndmareq0

gpt10_pwm_ 2 IO

evt

gpio_54 4 IO AA11 gpmc_ncs4 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

sys_ 1 I

ndmareq1

gpt9_pwm_e 3 IO

gpio_55 4 IO W12 gpmc_ncs5 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

sys_ 1 I

ndmareq2

gpt10_pwm_ 3 IO

evt

gpio_56 4 IO AA12 gpmc_ncs6 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

sys_ 1 I

ndmareq3

gpt11_pwm_ 3 IO

evt

gpio_57 4 IO V11 gpmc_ncs7 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpmc_io_dir 1 O

gpt8_pwm_e 3 IO

gpio_58 4 IO AB13 gpmc_clk 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_59 4 IO AA14 gpmc_nadv_ 0 O L Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS

AB14 gpmc_noe 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS AA15 gpmc_nwe 0 O H Z 0 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS

ale

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

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Table 2-2. Ball Characteristics (ZER Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

W11 gpmc_nbe0_ 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

Y15 gpmc_nbe1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

W14 gpmc_nwp 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

V13 gpmc_wait0 0 I H PU 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS AA16 gpmc_wait1 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

Y14 gpmc_wait2 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

V14 gpmc_wait3 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

B22 dss_pclk 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

B21 dss_hsync 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

B20 dss_vsync 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

B19 dss_acbias 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

A20 dss_data0 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

A19 dss_data1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

A18 dss_data2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

B18 dss_data3 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

A17 dss_data4 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

C18 dss_data5 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

D17 dss_data6 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

B16 dss_data7 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

B17 dss_data8 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

cle

gpio_60 4 IO

gpio_61 4 IO

gpio_62 4 IO

uart4_tx 1 O

gpio_63 4 IO

uart4_rx 1 I

gpio_64 4 IO

sys_ 1 I

ndmareq1

uart3_cts_rct 2 I

gpio_65 4 IO

gpio_66 4 IO

hw_dbg12 5 O

gpio_67 4 IO

hw_dbg13 5 O

gpio_68 4 IO

gpio_69 4 IO

uart1_cts 2 I

gpio_70 4 IO

uart1_rts 2 O

gpio_71 4 IO

gpio_72 4 IO

gpio_73 4 IO

uart3_rx_irrx 2 I

gpio_74 4 IO

uart3_tx_irtx 2 O

gpio_75 4 IO

uart1_tx 2 O

gpio_76 4 IO

hw_dbg14 5 O

uart1_rx 2 I

gpio_77 4 IO

hw_dbg15 5 O

gpio_78 4 IO

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Table 2-2. Ball Characteristics (ZER Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

hw_dbg16 5 O C17 dss_data9 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_79 4 IO

hw_dbg17 5 O C16 dss_data10 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_80 4 IO D16 dss_data11 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_81 4 IO D14 dss_data12 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_82 4 IO A16 dss_data13 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_83 4 IO D15 dss_data14 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_84 4 IO B15 dss_data15 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_85 4 IO A15 dss_data16 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_86 4 IO A14 dss_data17 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

gpio_87 4 IO C13 dss_data18 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

mcspi3_clk 2 IO

dss_data4 3 O

gpio_88 4 IO C15 dss_data19 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

mcspi3_ 2 IO

simo

dss_data3 3 O

gpio_89 4 IO A13 dss_data20 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

mcspi3_ 2 IO

somi

dss_data2 3 O

gpio_90 4 IO B13 dss_data21 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

mcspi3_cs0 2 IO

dss_data1 3 O

gpio_91 4 IO C14 dss_data22 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

mcspi3_cs1 2 O

gpio_92 4 IO B14 dss_data23 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

dss_data5 3 O

gpio_93 4 IO AB21 ccdc_pclk 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS

gpio_94 4 IO

hw_dbg0 5 O AA21 ccdc_field 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS

ccdc_data8 1 I

uart4_tx 2 O

i2c3_scl 3 IO

gpio_95 4 IO

hw_dbg1 5 O Y21 ccdc_ hd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS

uart4_rts 2 O

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

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Table 2-2. Ball Characteristics (ZER Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

gpio_96 4 IO Y22 ccdc_vd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS

uart4_cts 2 I

gpio_97 4 IO

hw_dbg2 5 O W21 ccdc_wen 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS

ccdc_data9 1 I

uart4_rx 2 I

gpio_98 4 IO

hw_dbg3 5 O W22 ccdc_data0 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS

i2c3_sda 3 IO

gpio_99 4 I W20 ccdc_data1 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS

gpio_100 4 I V21 ccdc_data2 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS

gpio_101 4 IO

hw_dbg4 5 O V19 ccdc_data3 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS

gpio_102 4 IO

hw_dbg5 5 O V22 ccdc_data4 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS

gpio_103 4 IO

hw_dbg6 5 O U20 ccdc_data5 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/ PD LVCMOS

gpio_104 4 IO

hw_dbg7 5 O V20 ccdc_data6 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS

gpio_105 4 IO U19 ccdc_data7 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 15 PU/PD LVCMOS

gpio_106 4 IO U21 rmii_mdio_da 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS

U22 rmii_mdio_clk 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS

T19 rmii_rxd0 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS

T20 rmii_rxd1 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS

T21 rmii_crs_dv 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS

R22 rmii_rxer 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS

T22 rmii_txd0 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/ PD LVCMOS

ccdc_data8 1 I

gpio_107 4 IO 8

ccdc_data9 1 I 8

gpio_108 4 IO

ccdc_data10 1 I

gpio_109 4 IO

hw_dbg8 5 O

ccdc_data11 1 I

gpio_110 4 IO

hw_dbg9 5 O

ccdc_data12 1 I

gpio_111 4 IO

ccdc_data13 1 I

gpio_167 4 IO

hw_dbg10 5 O

ccdc_ data14 1 I

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Table 2-2. Ball Characteristics (ZER Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

gpio_126 4 IO

hw_dbg11 5 O R20 rmii_txd1 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 25 PU/PD LVCMOS

ccdc_data15 1 I

gpio_112 4 I R19 rmii_txen 0 O H PU 7 VDDSHV 1.8V/3.3V 25 PU/PD LVCMOS

gpio_113 4 I NA R21 rmii_50mhz_ 0 I H PU 7 VDDSHV 1.8V/3.3V 25 PU/ PD LVCMOS

E5 mcbsp2_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

D5 mcbsp2_ clkx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

C5 mcbsp2_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

E4 mcbsp2_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

P22 mmc1_clk 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

N21 mmc1_cmd 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

P21 mmc1_dat0 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

N20 mmc1_dat1 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

P19 mmc1_dat2 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

P20 mmc1_dat3 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

N22 mmc1_dat4 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS

N19 mmc1_dat5 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS

N18 mmc1_dat6 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS

P18 mmc1_dat7 0 IO L PD 7 VDDSHV 1.8V/3.3V No 30 PU/ PD LVCMOS

M21 mmc2_clk 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

M20 mmc2_ cmd 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

K20 mmc2_ dat0 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

clk

gpio_114 4 I NA

gpio_116 4 IO

gpio_117 4 IO

gpio_118 4 IO

gpio_119 4 IO

gpio_120 4 IO

gpio_121 4 IO

mcspi2_clk 1 IO

gpio_122 4 IO

mcspi2_simo 1 IO

gpio_123 4 IO

mcspi2_somi 1 IO

gpio_124 4 IO

mcspi2_cs0 1 O

gpio_125 4 IO

gpio_126 4 IO

gpio_127 4 IO

gpio_128 4 IO

gpio_129 4 IO

mcspi3_clk 1 IO

uart4_cts 2 I

gpio_130 4 IO

mcspi3_ 1 IO

simo

uart4_rts 2 O

gpio_131 4 IO

mcspi3_ 1 IO

somi

uart4_tx 2 O

gpio_132 4 IO

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

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Table 2-2. Ball Characteristics (ZER Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

L19 mmc2_ dat1 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

uart4_rx 2 I

gpio_133 4 IO M18 mmc2_ dat2 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcspi3_cs1 1 O

gpio_134 4 IO K21 mmc2_ dat3 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcspi3_cs0 1 IO

gpio_135 4 IO L18 mmc2_ dat4 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mmc2_dir_da 1 O

mmc3_dat0 3 IO

gpio_136 4 IO L20 mmc2_ dat5 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mmc2_dir_da 1 O

mmc3_dat1 3 IO

gpio_137 4 IO

mm_fsusb3_r 6 IO

xdp L21 mmc2_ dat6 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mmc2_dir_c 1 O

mmc3_dat2 3 IO

gpio_138 4 IO M19 mmc2_ dat7 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mmc2_clkin 1 I

mmc3_dat3 3 IO

gpio_139 4 IO

mm_fsusb3_r 6 IO

xdm C4 mcbsp3_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

uart2_cts 1 I

gpio_140 4 IO B4 mcbsp3_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

uart2_rts 1 O

gpio_141 4 IO D4 mcbsp3_ clkx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

uart2_tx 1 O

gpio_142 4 IO A4 mcbsp3_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

uart2_rx 1 I

gpio_143 4 IO A5 uart2_cts 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcbsp3_dx 1 IO

gpt9_pwm_e 2 IO

gpio_144 4 IO B5 uart2_rts 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcbsp3_dr 1 I

gpt10_pwm_ 2 IO

evt

gpio_145 4 IO D6 uart2_tx 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcbsp3_clkx 1 IO

gpt11_pwm 2 IO

_evt

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Table 2-2. Ball Characteristics (ZER Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

gpio_146 4 IO C6 uart2_rx 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcbsp3_fsx 1 IO

gpt8_pwm_e 2 IO

gpio_147 4 IO C22 uart1_tx 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_148 4 IO C21 uart1_rts 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_149 4 IO C19 uart1_cts 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_150 4 IO C20 uart1_rx 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcbsp1_ clkr 2 I

mcspi4_clk 3 IO

gpio_151 4 IO A3 mcbsp4_ clkx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_152 4 IO

mm_fsusb3_t 6 IO

xse0 B3 mcbsp4_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_153 4 IO

mm_fsusb3_r 6 IO

xrcv A2 mcbsp4_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_154 4 IO

mm_fsusb3_t 6 IO

xdat B2 mcbsp4_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_155 4 IO

mm_fsusb3_t 6 IO

xen_n B11 mcbsp1_ clkr 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcspi4_clk 1 IO

gpio_156 4 IO D11 mcbsp1_fsr 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_157 4 IO C10 mcbsp1_dx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcspi4_ 1 IO

simo

mcbsp3_dx 2 I

gpio_158 4 IO C9 mcbsp1_dr 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcspi4_ 1 IO

somi

mcbsp3_dr 2 I

gpio_159 4 IO E11 mcbsp_clks 0 I L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_160 4 IO

uart1_cts 5 I C11 mcbsp1_fsx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcspi4_cs0 1 IO

mcbsp3_fsx 2 IO

gpio_161 4 IO C8 mcbsp1_ clkx 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mcbsp3_clkx 2 IO

gpio_162 4 IO

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Product Folder Link(s): AM3517 AM3505

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

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Table 2-2. Ball Characteristics (ZER Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

W15 uart3_cts_rct 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

W13 uart3_rts_sd 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AA13 uart3_rx_irrx 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

Y13 uart3_tx_irtx 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

A6 usb0_dp 0 IO 5.0V Yes PU/ PD LVCMOS B6 usb0_dm 0 IO 5.0V Yes PU/ PD LVCMOS C7 usb0_vbus 0 A VDDA3P3V_ 3.3V Yes PU/ PD LVCMOS

B7 usb0_id 0 A VDDA3P3V_ 3.3V Yes PU/ PD LVCMOS

A7 usb0_drvvbu 0 O L PD 7 VDDSHV 1.8V/3.3V 30

AB15 hecc1_ txd 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 24 PU/ PD LVCMOS

AB16 hecc1_ rxd 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 24 PU/ PD LVCMOS

AA17 i2c1_scl 0 IOD H PU 0 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain AB17 i2c1_ sda 0 IOD H PU 0 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain Y17 i2c2_scl 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain

Y16 i2c2_sda 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain

W16 i2c3_scl 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain

W17 i2c3_sda 0 IOD H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD Open Drain

B9 hdq_sio 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 40 PU/ PD LVCMOS

K22 mcspi1_clk 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

K19 mcspi1_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

J18 mcspi1_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

K18 mcspi1_cs0 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

J20 mcspi1_cs1 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_163 4 IO

gpio_164 4 IO

gpio_165 4 IO

gpio_166 4 IO

USBPHY

uart3_tx_irtx 2 O

gpio_125 4 IO

uart3_rx_irrx 2 I

gpio_130 4 IO

uart3_rts_sd 2 O

gpio_131 4 IO

gpio_168 4 IO

gpio_183 4 IO

gpio_184 4 IO

gpio_185 4 IO

sys_altclk 1 I

i2c2_sccbe 2 O

i2c3_sccbe 3 O

gpio_170 4 IO

mmc2_dat4 1 IO

gpio_171 4 IO

simo

mmc2_dat5 1 IO

gpio_172 4 IO

somi

mmc2_dat6 1 IO

gpio_173 4 IO

mmc2_dat7 1 IO

gpio_174 4 IO

mmc3_cmd 3 IO

gpio_175 4 IO

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Table 2-2. Ball Characteristics (ZER Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

J19 mcspi1_cs2 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mmc3_clk 3 O

gpio_176 4 IO J21 mcspi1_cs3 0 O H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

hsusb2_ 3 IO

data2

gpio_177 4 IO

mm_fsusb2_t 5 IO

xdat J22 mcspi2_clk 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

hsusb2_ 3 IO

data7

gpio_178 4 IO H20 mcspi2_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

H22 mcspi2_ 0 IO L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

H21 mcspi2_cs0 0 IO H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

H19 mcspi2_cs1 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

A8 sys_32k 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS A10 sys_xtalin 0 I Z Z 0 VDDSOSC 1.8V NA PU/ PD LVCMOS A9 sys_xtalout 0 O Z Z 0 VDDSOSC 1.8V NA PU/ PD LVCMOS B8 sys_clkreq 0 IO L Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AB18 sys_nirq 0 I H PU 7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AA18 sys_ 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

Y18 sys_ 0 IO L PD 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AB19 sys_boot0 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AB20 sys_boot1 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

W18 sys_boot2 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

AA19 sys_boot3 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

simo

gpt9_pwm_e 1 IO

hsusb2_ 3 IO

data4

gpio_179 4 IO

somi

gpt10_pwm_ 1 IO

evt

hsusb2_ 3 IO

data5

gpio_180 4 IO

gpt11_pwm_ 1 IO

evt

hsusb2_ 3 IO

data6

gpio_181 4 IO

gpt8_pwm_e 1 IO

hsusb2_ 3 IO

data3

gpio_182 4 IO

mm_fsusb2_t 5 IO

xen_n

gpio_1 4 IO

gpio_0 4 IO

nrespwron

nreswarm

gpio_30 4 IO Open Drain

gpio_2 4 IO

gpio_3 4 IO

gpio_4 4 IO

gpio_5 4 IO

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Table 2-2. Ball Characteristics (ZER Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

V18 sys_boot4 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mmc2_dir_da 1 O

gpio_6 4 IO Y19 sys_boot5 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

mmc2_dir_da 1 O

gpio_7 4 IO W19 sys_boot6 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_8 4 IO AA20 sys_boot7 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/PD LVCMOS Y20 sys_boot8 0 I Z Z 0 VDDSHV 1.8V/3.3V Yes 30 PU/PD LVCMOS E9 sys_clkout1 0 O H PD 0/7 VDDSHV 1.8V/3.3V Yes 30 PU/ PD LVCMOS

gpio_10 4 IO E10 sys_clkout2 0 O L PD 7 VDDSHV 1.8V/3.3V Yes 10 PU/ PD LVCMOS

gpio_186 4 IO D13 jtag_ntrst 0 I L PD 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS E14 jtag_tck 0 I L PD 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS C12 jtag_rtck 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS A12 jtag_tms_tms 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

B12 jtag_tdi 0 I H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS D12 jtag_tdo 0 O L Z 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS E13 jtag_emu0 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

E12 jtag_emu1 0 IO H PU 0 VDDSHV 1.8V/3.3V Yes 20 PU/ PD LVCMOS

G22 etk_clk 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

G21 etk_ctl 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

G20 etk_d0 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

F22 etk_d1 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

F20 etk_d2 0 O H PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

gpio_11 4 IO

gpio_31 4 IO

mcbsp5_ clkx 1 IO

mmc3_clk 2 O

hsusb1_stp 3 O

gpio_12 4 IO

mmc3_cmd 2 IO

hsusb1_clk 3 O

gpio_13 4 IO

mm_fsusb1_r 5 IO

xdp

mcspi3_ 1 IO

simo

mmc3_dat4 2 IO

hsusb1_ 3 IO

data0

gpio_14 4 IO

mm_fsusb1_r 5 IO

xrcv

mcspi3_ 1 IO

somi

hsusb1_ 3 IO

data1

gpio_15 4 IO

mm_fsusb1_t 5 IO

xse0

mcspi3_cs0 1 IO

hsusb1_ 3 IO

data2

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Table 2-2. Ball Characteristics (ZER Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

gpio_16 4 IO

mm_fsusb1_t 5 IO

xdat G19 etk_d3 0 O L PU 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

mcspi3_clk 1 IO

mmc3_dat3 2 IO

hsusb1_ 3 IO

data7

gpio_17 4 IO E19 etk_d4 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

mcbsp5_dr 1 I

mmc3_dat0 2 IO

hsusb1_ 3 IO

data4

gpio_18 4 IO F21 etk_d5 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

mcbsp5_fsx 1 IO

mmc3_dat1 2 IO

hsusb1_ 3 IO

data5

gpio_19 4 IO F19 etk_d6 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

mcbsp5_dx 1 IO

mmc3_dat2 2 IO

hsusb1_ 3 IO

data6

gpio_20 4 IO E21 etk_d7 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

mcspi3_cs1 1 O

mmc3_dat7 2 IO

hsusb1_ 3 IO

data3

gpio_21 4 IO

mm_fsusb1_t 5 IO

xen_n D22 etk_d8 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

mmc3_dat6 2 IO

hsusb1_dir 3 I

gpio_22 4 IO D21 etk_d9 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

mmc3_dat5 2 IO

hsusb1_nxt 3 I

gpio_23 4 IO

mm_fsusb1_r 5 IO

xdm E22 etk_d10 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

uart1_rx 2 I

hsusb2_clk 3 O

gpio_24 4 IO E20 etk_d11 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

mcspi3_clk 1 IO

hsusb2_stp 3 O

gpio_25 4 IO

mm_fsusb2_r 5 IO

xdp E18 etk_d12 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

hsusb2_dir 3 I

gpio_26 4 IO

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Table 2-2. Ball Characteristics (ZER Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

D20 etk_d13 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

hsusb2_nxt 3 I

gpio_27 4 IO

mm_fsusb2_r 5 IO

xdm D19 etk_d14 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

hsusb2_ 3 IO

data0

gpio_28 4 IO

mm_fsusb2_r 5 IO

xrcv D18 etk_d15 0 O L PD 4 VDDSHV 1.8V/3.3V Yes 9, 25 PU/ PD LVCMOS

hsusb2_ 3 IO

data1

gpio_29 4 IO

mm_fsusb2_t 5 IO

xse0 M2 ddr_padref 0 A VDDS 1.8V J8, J10, VDD_CORE 0 PWR 1.2V

J12, J14, J16, K9, K11, K13, K15, L8, L10, L12, L14, M7, M9, M11, M13, M15, N8, N10, N12, N14, P7, P9, P11, P13, P15, R8, R10, R12, R14

L17 VDDS_SRA 0 PWR 1.8V

J6 VDDS_SRA 0 PWR 1.8V

M17 CAP_VDD_S 0 PWR 1.2V

K6 CAP_VDD_S 0 PWR 1.2V

K17 VDDS_DPLL 0 PWR 1.8V

F11 VDDS_DPLL 0 PWR 1.8V

F7 VDDA3P3V_ 0 PWR 3.3V

D7 VDDA1P8V_ 0 PWR 1.8V

E7 CAP_VDDA1 0 PWR 1.2V

A21, B1, VDDSHV 0 PWR 1.8V/3.3V E15, E17, F12, F14, F18, G10, G12, G13, G8, G17, H18, J17, L22, N16, P17, R16, R18, T9, T11, T13, T17, U8, U10, U12, U14, U16, U18, V7, V8, V17, AA22, AB11

M_MPU

M_CORE_B

RAM_MPU

RAM_CORE

_MPU_USBH

OST

_PER_CORE

USBPHY

P2LDO_USB

PHY

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Table 2-2. Ball Characteristics (ZER Pkg.) (continued)

BALL PIN NAME MODE [3] TYPE [4] BALL BALL RESET REL. POWER [8] VOLTAGE HYS [10] LOAD (pF) PULL U/D IO CELL [13] LOCATION [2] RESET RESET REL. MODE [7] [9] [11] TYPE [12] [1] STATE [5] STATE [6]

F5, F16, VDDS 0 PWR 1.8V G15, H5, K7, L6, L16, N1, N5, N6, P5, R6, T5, T7, T15, U6, AA1

L5 VREFSSTL 0 I G9 VDDSOSC O PWR 1.8V A1, A11, VSS 0 GND

A22, E6, E16, F6, F13, F15, F17, G5, G7, G11, G14, G16, G18, H6, H7, H8, H9, H10, H11, H12, H13, H14, H15, H16, H17, J9, J11, J13, J15, K8, K10, K12, K14, K16, L7, L9, L11, L13, L15, M1, M6, M8, M10, M12, M14, M16, M22, N7, N9, N11, N13, N15, N17, P6, P8, P10, P12, P14, P16, R5, R7, R9, R11, R13, R15, R17, T6, T8, T10, T12, T14, T16, T18, U5, U7, U9, U11, U13, U15, U17, V6, AB1, AB12, AB22

B10 VSSOSC 0 GND D8, D9, NC

D10, E8, F8, F9, F10, J7, G6

V15 Reserved V16 Reserved

(1) "NC" indicates "No Connect". For proper device operation, these pins must be left unconnected. (2) For proper device operation, this pin must be pulled up via a 10k-Ω resistor.

(1)

(2)

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2.3 Multiplexing Characteristics

Table 2-3 provides descriptions of the AM3517/05 pin multiplexing on the ZCN and ZER packages.

Table 2-3. Multiplexing Characteristics

ZER ZCN MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7 BALL NO BALL NO

E3 B21 sdrc_d0 D3 A21 sdrc_d1 C3 D20 sdrc_d2 C2 C20 sdrc_d3 F3 E19 sdrc_d4 D2 D19 sdrc_d5 C1 C19 sdrc_d6 D1 B19 sdrc_d7 G2 B18 sdrc_d8 G3 D17 sdrc_d9 H3 C17 sdrc_d10 G4 D16 sdrc_d11 H4 C16 sdrc_d12 G1 B16 sdrc_d13 J3 A16 sdrc_d14 J1 A15 sdrc_d15 T3 A7 sdrc_d16 U3 B7 sdrc_d17 U4 D7 sdrc_d18 V4 E7 sdrc_d19 V1 C6 sdrc_d20 V2 D6 sdrc_d21 V5 B5 sdrc_d22 V3 C5 sdrc_d23 W3 B4 sdrc_d24 W4 A3 sdrc_d25 Y3 B3 sdrc_d26 Y4 C3 sdrc_d27 AA2 C2 sdrc_d28 AA3 D2 sdrc_d29 AA4 B1 sdrc_d30 AB2 C1 sdrc_d31 L4 A12 sdrc_ba0 K5 C13 sdrc_ba1 J5 D13 sdrc_ba2 M3 A11 sdrc_a0 M4 B11 sdrc_a1 M5 C11 sdrc_a2 N3 D11 sdrc_a3 N2 E11 sdrc_a4 N4 A10 sdrc_a5 P3 B10 sdrc_a6 P2 C10 sdrc_a7 P1 D10 sdrc_a8 P4 E10 sdrc_a9 R1 A9 sdrc_a10 R2 B9 sdrc_a11 R3 A8 sdrc_a12 R4 B8 sdrc_a13 T2 D8 sdrc_a14 J4 E13 sdrc_ncs0

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SPRS550B–OCTOBER 2009–REVISED JULY 2010

Table 2-3. Multiplexing Characteristics (continued)

ZER ZCN MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7

K4 A14 sdrc_ncs1 L1 A13 sdrc_clk L2 B13 sdrc_nclk K3 D14 sdrc_cke0 sdrc_cke0_safe K1 C14 sdrc_nras L3 E14 sdrc_ncas K2 B14 sdrc_nwe F4 C21 sdrc_dm0 J2 B15 sdrc_dm1 T4 E8 sdrc_dm2 AB3 D1 sdrc_dm3 E2 B20 sdrc_dqs0p H2 B17 sdrc_dqs1p U1 A6 sdrc_dqs2p Y1 A2 sdrc_dqs3p E1 A20 sdrc_dqs0n H1 A17 sdrc_dqs1n U2 B6 sdrc_dqs2n Y2 B2 sdrc_dqs3n T1 C8 sdrc_odt F2 A19 sdrc_strben0 F1 A18 sdrc_strben_dly0 W1 A5 sdrc_strben1 W2 A4 sdrc_strben_dly1 W5 E3 gpmc_a1 gpio_34 safe_mode Y5 E2 gpmc_a2 gpio_35 safe_mode AB4 E1 gpmc_a3 gpio_36 safe_mode AA5 F7 gpmc_a4 gpio_37 safe_mode AB5 F6 gpmc_a5 gpio_38 safe_mode AB6 F4 gpmc_a6 gpio_39 safe_mode AA6 F3 gpmc_a7 gpio_40 safe_mode W6 F2 gpmc_a8 gpio_41 safe_mode AB7 F1 gpmc_a9 sys_ndmareq2 gpio_42 safe_mode Y6 G6 gpmc_a10 sys_ndmareq3 gpio_43 safe_mode AA7 G5 gpmc_d0 Y7 G4 gpmc_d1 W7 G3 gpmc_d2 AA9 G2 gpmc_d3 Y8 G1 gpmc_d4 AA8 H2 gpmc_d5 AB8 H1 gpmc_d6 W8 J5 gpmc_d7 W10 J4 gpmc_d8 gpio_44 AB9 J3 gpmc_d9 gpio_45 AB10 J2 gpmc_d10 gpio_46 W9 J1 gpmc_d11 gpio_47 AA10 K4 gpmc_d12 gpio_48 Y9 K3 gpmc_d13 gpio_49 V10 K2 gpmc_d14 gpio_50 V9 K1 gpmc_d15 gpio_51 Y10 L2 gpmc_ncs0 Y11 L1 gpmc_ncs1 gpio_52 Y12 M4 gpmc_ncs2 gpt9_pwm_evt gpio_53 safe_mode V12 M3 gpmc_ncs3 sys_ndmareq0 gpt10_pwm_evt gpio_54 safe_mode AA11 M2 gpmc_ncs4 sys_ndmareq1 gpt9_pwm_evt gpio_55 safe_mode W12 M1 gpmc_ncs5 sys_ndmareq2 gpt10_pwm_evt gpio_56 safe_mode

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Table 2-3. Multiplexing Characteristics (continued)

ZER ZCN MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7

AA12 N5 gpmc_ncs6 sys_ndmareq3 gpt11_pwm_evt gpio_57 safe_mode V11 N4 gpmc_ncs7 gpmc_io_dir gpt8_pwm_evt gpio_58 safe_mode AB13 N1 gpmc_clk gpio_59 AA14 R1 gpmc_nadv_ale AB14 R2 gpmc_noe AA15 R3 gpmc_nwe W11 R4 gpmc_nbe0_cle gpio_60 Y15 T1 gpmc_nbe1 gpio_61 safe_mode W14 T2 gpmc_nwp gpio_62 V13 T3 gpmc_wait0 AA16 T4 gpmc_wait1 uart4_tx gpio_63 safe_mode Y14 T5 gpmc_wait2 uart4_rx gpio_64 safe_mode V14 U1 gpmc_wait3 sys_ndmareq1 uart3_cts_rctx gpio_65 safe_mode B22 AE23 dss_pclk gpio_66 hw_dbg12 safe_mode B21 AD22 dss_hsync gpio_67 hw_dbg13 safe_mode B20 AD23 dss_vsync gpio_68 safe_mode B19 AE24 dss_acbias gpio_69 safe_mode A20 AD24 dss_data0 uart1_cts gpio_70 safe_mode A19 AD25 dss_data1 uart1_rts gpio_71 safe_mode A18 AC23 dss_data2 gpio_72 safe_mode B18 AC24 dss_data3 gpio_73 safe_mode A17 AC25 dss_data4 uart3_rx_irrx gpio_74 safe_mode C18 AB24 dss_data5 uart3_tx_irtx gpio_75 safe_mode D17 AB25 dss_data6 uart1_tx gpio_76 hw_dbg14 safe_mode B16 AA23 dss_data7 uart1_rx gpio_77 hw_dbg15 safe_mode B17 AA24 dss_data8 gpio_78 hw_dbg16 safe_mode C17 AA25 dss_data9 gpio_79 hw_dbg17 safe_mode C16 Y22 dss_data10 gpio_80 safe_mode D16 Y23 dss_data11 gpio_81 safe_mode D14 Y24 dss_data12 gpio_82 safe_mode A16 Y25 dss_data13 gpio_83 safe_mode D15 W21 dss_data14 gpio_84 safe_mode B15 W22 dss_data15 gpio_85 safe_mode A15 W23 dss_data16 gpio_86 safe_mode A14 W24 dss_data17 gpio_87 safe_mode C13 W25 dss_data18 mcspi3_clk dss_data4 gpio_88 safe_mode C15 V24 dss_data19 mcspi3_simo dss_data3 gpio_89 safe_mode A13 V25 dss_data20 mcspi3_somi dss_data2 gpio_90 safe_mode B13 U21 dss_data21 mcspi3_cs0 dss_data1 gpio_91 safe_mode C14 U22 dss_data22 mcspi3_cs1 dss_data0 gpio_92 safe_mode B14 U23 dss_data23 dss_data5 gpio_93 safe_mode NA K20 tv_vfb1 NA K21 tv_out1 NA H23 tv_vfb2 NA H24 tv_out2 NA H20 tv_vref AB21 AD2 ccdc_pclk gpio_94 hw_dbg0 safe_mode AA21 AD1 ccdc_field ccdc_data8 uart4_tx i2c3_scl gpio_95 hw_dbg1 safe_mode Y21 AE2 ccdc_hd uart4_rts gpio_96 safe_mode Y22 AD3 ccdc_vd uart4_cts gpio_97 hw_dbg2 safe_mode W21 AE3 ccdc_wen ccdc_data9 uart4_rx gpio_98 hw_dbg3 safe_mode W22 AD4 ccdc_data0 i2c3_sda gpio_99 safe_mode W20 AE4 ccdc_data1 gpio_100 safe_mode V21 AC5 ccdc_data2 gpio_101 hw_dbg4 safe_mode V19 AD5 ccdc_data3 gpio_102 hw_dbg5 safe_mode V22 AE5 ccdc_data4 gpio_103 hw_dbg6 safe_mode

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Table 2-3. Multiplexing Characteristics (continued)

ZER ZCN MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7

U20 Y6 ccdc_data5 gpio_104 hw_dbg7 safe_mode V20 AB6 ccdc_data6 gpio_105 safe_mode U19 AC6 ccdc_data7 gpio_106 safe_mode U21 AE6 rmii_mdio_data ccdc_data8 gpio_107 safe_mode U22 AD6 rmii_mdio_clk ccdc_data9 gpio_108 safe_mode T19 Y7 rmii_rxd0 ccdc_data10 gpio_109 hw_dbg8 safe_mode T20 AA7 rmii_rxd1 ccdc_data11 gpio_110 hw_dbg9 safe_mode T21 AB7 rmii_crs_dv ccdc_data12 gpio_111 safe_mode R22 AC7 rmii_rxer ccdc_data13 gpio_167 hw_dbg10 safe_mode T22 AD7 rmii_txd0 ccdc_data14 gpio_126 hw_dbg11 safe_mode R20 AE7 rmii_txd1 ccdc_data15 gpio_112 safe_mode R19 AD8 rmii_txen gpio_113 safe_mode R21 AE8 rmii_50mhz_clk gpio_114 safe_mode E5 D25 mcbsp2_fsx gpio_116 safe_mode D5 C25 mcbsp2_clkx gpio_117 safe_mode C5 B25 mcbsp2_dr gpio_118 safe_mode E4 D24 mcbsp2_dx gpio_119 safe_mode P22 AA9 mmc1_clk gpio_120 safe_mode N21 AB9 mmc1_cmd gpio_121 safe_mode P21 AC9 mmc1_dat0 mcspi2_clk gpio_122 safe_mode N20 AD9 mmc1_dat1 mcspi2_simo gpio_123 safe_mode P19 AE9 mmc1_dat2 mcspi2_somi gpio_124 safe_mode P20 AA10 mmc1_dat3 mcspi2_cs0 gpio_125 safe_mode N22 AB10 mmc1_dat4 gpio_126 safe_mode N19 AC10 mmc1_dat5 gpio_127 safe_mode N18 AD10 mmc1_dat6 gpio_128 safe_mode P18 AE10 mmc1_dat7 gpio_129 safe_mode M21 AD11 mmc2_clk mcspi3_clk uart4_cts gpio_130 safe_mode M20 AE11 mmc2_cmd mcspi3_simo uart4_rts gpio_131 safe_mode K20 AB12 mmc2_dat0 mcspi3_somi uart4_tx gpio_132 safe_mode L19 AC12 mmc2_dat1 uart4_rx gpio_133 safe_mode M18 AD12 mmc2_dat2 mcspi3_cs1 gpio_134 safe_mode K21 AE12 mmc2_dat3 mcspi3_cs0 gpio_135 safe_mode L18 AB13 mmc2_dat4 mmc2_dir_dat0 mmc3_dat0 gpio_136 safe_mode L20 AC13 mmc2_dat5 mmc2_dir_dat1 mmc3_dat1 gpio_137 mm_fsusb3_rxdp safe_mode L21 AD13 mmc2_dat6 mmc2_dir_cmd mmc3_dat2 gpio_138 safe_mode M19 AE13 mmc2_dat7 mmc2_clkin mmc3_dat3 gpio_139 mm_fsusb3_rxdm safe_mode C4 B24 mcbsp3_dx uart2_cts gpio_140 safe_mode B4 C24 mcbsp3_dr uart2_rts gpio_141 safe_mode D4 A24 mcbsp3_clkx uart2_tx gpio_142 safe_mode A4 C23 mcbsp3_fsx uart2_rx gpio_143 safe_mode A5 F20 uart2_cts mcbsp3_dx gpt9_pwm_evt gpio_144 safe_mode B5 F19 uart2_rts mcbsp3_dr gpt10_pwm_evt gpio_145 safe_mode D6 E24 uart2_tx mcbsp3_clkx gpt11_pwm_evt gpio_146 safe_mode C6 E23 uart2_rx mcbsp3_fsx gpt8_pwm_evt gpio_147 safe_mode C22 AA19 uart1_tx gpio_148 safe_mode C21 Y19 uart1_rts gpio_149 safe_mode C19 Y20 uart1_cts gpio_150 safe_mode C20 W20 uart1_rx mcbsp1_clkr mcspi4_clk gpio_151 safe_mode A3 B23 mcbsp4_clkx gpio_152 mm_fsusb3_txse safe_mode

B3 A23 mcbsp4_dr gpio_153 mm_fsusb3_rxrcv safe_mode A2 B22 mcbsp4_dx gpio_154 mm_fsusb3_txdat safe_mode B2 A22 mcbsp4_fsx gpio_155 mm_fsusb3_txen safe_mode

B11 R25 mcbsp1_clkr mcspi4_clk gpio_156 safe_mode D11 P21 mcbsp1_fsr gpio_157 safe_mode

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Table 2-3. Multiplexing Characteristics (continued)

ZER ZCN MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7

C10 P22 mcbsp1_dx mcspi4_simo mcbsp3_dx gpio_158 safe_mode C9 P23 mcbsp1_dr mcspi4_somi mcbsp3_dr gpio_159 safe_mode E11 P25 mcbsp_clks gpio_160 uart1_cts safe_mode C11 P24 mcbsp1_fsx mcspi4_cs0 mcbsp3_fsx gpio_161 safe_mode C8 N24 mcbsp1_clkx mcbsp3_clkx gpio_162 safe_mode W15 N2 uart3_cts_rctx gpio_163 safe_mode W13 N3 uart3_rts_sd gpio_164 safe_mode AA13 P1 uart3_rx_irrx gpio_165 safe_mode Y13 P2 uart3_tx_irtx gpio_166 A6 F25 usb0_dp B6 F24 usb0_dm C7 G24 usb0_vbus B7 G25 usb0_id A7 E25 usb0_drvvbus uart3_tx_irtx gpio_125 safe_mode AB15 V2 hecc1_txd uart3_rx_irrx gpio_130 safe_mode AB16 V3 hecc1_rxd uart3_rts_sd gpio_131 safe_mode AA17 V4 i2c1_scl AB17 V5 i2c1_sda Y17 W1 i2c2_scl gpio_168 safe_mode Y16 W2 i2c2_sda gpio_183 safe_mode W16 W4 i2c3_scl gpio_184 safe_mode W17 W5 i2c3_sda gpio_185 safe_mode B9 L25 hdq_sio sys_altclk i2c2_sccbe i2c3_sccbe gpio_170 safe_mode K22 AE14 mcspi1_clk mmc2_dat4 gpio_171 safe_mode K19 AD15 mcspi1_simo mmc2_dat5 gpio_172 safe_mode J18 AC15 mcspi1_somi mmc2_dat6 gpio_173 safe_mode K18 AB15 mcspi1_cs0 mmc2_dat7 gpio_174 safe_mode J20 AD14 mcspi1_cs1 mmc3_cmd gpio_175 safe_mode J19 AE15 mcspi1_cs2 mmc3_clk gpio_176 safe_mode J21 AE16 mcspi1_cs3 hsusb2_data2 gpio_177 mm_fsusb2_txdat safe_mode J22 AD16 mcspi2_clk hsusb2_data7 gpio_178 safe_mode H20 AC16 mcspi2_simo gpt9_pwm_evt hsusb2_data4 gpio_179 safe_mode H22 AB16 mcspi2_somi gpt10_pwm_evt hsusb2_data5 gpio_180 safe_mode H21 AA16 mcspi2_cs0 gpt11_pwm_evt hsusb2_data6 gpio_181 safe_mode H19 AE17 mcspi2_cs1 gpt8_pwm_evt hsusb2_data3 gpio_182 mm_fsusb2_txen safe_mode

AB18 Y1 sys_nirq gpio_0 safe_mode E10 M25 sys_clkout2 gpio_186 safe_mode G22 AD17 etk_clk mcbsp5_clkx mmc3_clk hsusb1_stp gpio_12 hw_dbg0 G21 AE18 etk_ctl mmc3_cmd hsusb1_clk gpio_13 mm_fsusb1_rxdp hw_dbg1 G20 AD18 etk_d0 mcspi3_simo mmc3_dat4 hsusb1_data0 gpio_14 mm_fsusb1_rxrcv hw_dbg2 F22 AC18 etk_d1 mcspi3_somi hsusb1_data1 gpio_15 mm_fsusb1_txse hw_dbg3

F20 AB18 etk_d2 mcspi3_cs0 hsusb1_data2 gpio_16 mm_fsusb1_txdat hw_dbg4 G19 AA18 etk_d3 mcspi3_clk mmc3_dat3 hsusb1_data7 gpio_17 hw_dbg5 E19 Y18 etk_d4 mcbsp5_dr mmc3_dat0 hsusb1_data4 gpio_18 hw_dbg6 F21 AE19 etk_d5 mcbsp5_fsx mmc3_dat1 hsusb1_data5 gpio_19 hw_dbg7 F19 AD19 etk_d6 mcbsp5_dx mmc3_dat2 hsusb1_data6 gpio_20 hw_dbg8 E21 AB19 etk_d7 mcspi3_cs1 mmc3_dat7 hsusb1_data3 gpio_21 mm_fsusb1_txen hw_dbg9

D22 AE20 etk_d8 mmc3_dat6 hsusb1_dir gpio_22 hw_dbg10 D21 AD20 etk_d9 mmc3_dat5 hsusb1_nxt gpio_23 mm_fsusb1_rxdm hw_dbg11 E22 AC20 etk_d10 uart1_rx hsusb2_clk gpio_24 hw_dbg12 E20 AB20 etk_d11 mcspi3_clk hsusb2_stp gpio_25 mm_fsusb2_rxdp hw_dbg13 E18 AE21 etk_d12 hsusb2_dir gpio_26 hw_dbg14 D20 AD21 etk_d13 hsusb2_nxt gpio_27 mm_fsusb2_rxdm hw_dbg15

(1)

uart3_rx_irrx

(1)

uart3_tx_irtx

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Table 2-3. Multiplexing Characteristics (continued)

ZER ZCN MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MODE 6 MODE 7

D19 AC21 etk_d14 hsusb2_data0 gpio_28 mm_fsusb2_rxrcv hw_dbg16 D18 AE22 etk_d15 hsusb2_data1 gpio_29 mm_fsusb2_txse hw_dbg17

A8 K24 sys_32k A10 K25 sys_xtalin A9 H25 sys_xtalout B8 M24 sys_clkreq gpio_1 AA18 Y2 sys_nrespwron Y18 Y3 sys_nreswarm gpio_30 AB19 Y4 sys_boot0 gpio_2 AB20 AA1 sys_boot1 gpio_3 W18 AA2 sys_boot2 gpio_4 AA19 AA3 sys_boot3 gpio_5 V18 AB1 sys_boot4 mmc2_dir_dat2 gpio_6 Y19 AB2 sys_boot5 mmc2_dir_dat3 gpio_7 W19 AC1 sys_boot6 gpio_8 AA20 AC2 sys_boot7 Y20 AC3 sys_boot8 E9 N25 sys_clkout1 gpio_10 safe_mode D13 U24 jtag_ntrst E14 U25 jtag_tck C12 T21 jtag_rtck A12 T22 jtag_tms_tmsc B12 T23 jtag_tdi D12 T24 jtag_tdo E13 T25 jtag_emu0 gpio_11 E12 R24 jtag_emu1 gpio_31 M2 B12 ddr_padref

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2.4 Signal Description

Many signals are available on multiple pins according to the software configuration of the pin multiplexing options.

1. SIGNAL NAME: The signal name

2. DESCRIPTION: Description of the signal

3. TYPE: Type = Ball type for this specific function: – I = Input

– O = Output – Z = High-impedance – D = Open Drain – DS = Differential – A = Analog

4. BALL: Associated ball location

5. SUBSYSTEM PIN MULTIPLEXING: Contains a list of the pin multiplexing options at the module/subsystem level. The pin function is selected at the module/system level.

Note: The Subsystem Multiplexing Signals are not described in Table 2-1 through Table 2-2.

2.4.1 External Memory Interfaces

Table 2-4. External Memory Interfaces - GPMC Signals Description

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SIGNAL NAME DESCRIPTION TYPE ZCN BALL ZER BALL SUBSYSTEM PIN

gpmc_a1 GPMC Address bit 1 O E3/G5 W5/AA7 gpmc_a17 gpmc_a2 GPMC Address bit 2 O E2/G4 Y5/Y7 gpmc_a18 gpmc_a3 GPMC Address bit 3 O E1/G3 AB4/W7 gpmc_a19 gpmc_a4 GPMC Address bit 4 O F7/G2 AA5/AA9 gpmc_a20 gpmc_a5 GPMC Address bit 5 O F6/G1 AB5/Y8 gpmc_a21 gpmc_a6 GPMC Address bit 6 O F4/H2 AB6/AA8 gpmc_a22 gpmc_a7 GPMC Address bit 7 O F3/H1 AA6/AB8 gpmc_a23 gpmc_a8 GPMC Address bit 8 O F2/J5 W6/W8 gpmc_a24 gpmc_a9 GPMC Address bit 9 O F1/J4 AB7/W10 gpmc_a25 gpmc_a10 GPMC Address bit 10 O G6/J3 Y6/AB9 gpmc_a26 gpmc_a11 GPMC Address bit 11 O J2 AB10

multiplexed on gpmc_d10

gpmc_a12 GPMC Address bit12 O J1 W9

multiplexed on gpmc_d11

gpmc_a13 GPMC Address bit13 O K4 AA10

multiplexed on gpmc_d12

gpmc_a14 GPMC Address bit O K3 Y9

14multiplexed on gpmc_d13

gpmc_a15 GPMC Address bit15 O K2 V10

multiplexed on gpmc_d14

gpmc_a16 GPMC Address bit16 O K1 V9

multiplexed on gpmc_d15

gpmc_a17 GPMC Address bit17 O E3 W5

multiplexed on gpmc_a1

MULTIPLEXING

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Table 2-4. External Memory Interfaces - GPMC Signals Description (continued)

SIGNAL NAME DESCRIPTION TYPE ZCN BALL ZER BALL SUBSYSTEM PIN

gpmc_a18 GPMC Address bit18 O E2 Y5

multiplexed on gpmc_a2

gpmc_a19 GPMC Address bit19 O E1 AB4

multiplexed on gpmc_a3

gpmc_a20 GPMC Address bit20 O F7 AA5

multiplexed on gpmc_a4

gpmc_a21 GPMC Address bit21 O F6 AB5

multiplexed on gpmc_a5

gpmc_a22 GPMC Address bit22 O F4 AB6

multiplexed on gpmc_a6

gpmc_a23 GPMC Address bit23 O F3 AA6

multiplexed on gpmc_a7

gpmc_a24 GPMC Address bit24 O F2 W6

multiplexed on gpmc_a8

gpmc_a25 GPMC Address bit25 O F1 AB7

multiplexed on gpmc_a9

gpmc_a26 GPMC Address bit26 O G6 Y6

multiplexed on

gpmc_a10 gpmc_d0 GPMC Data bit 0 IO G5 AA7 gpmc_a1/gpmc_d0 gpmc_d1 GPMC Data bit 1 IO G4 Y7 gpmc_a2/gpmc_d1 gpmc_d2 GPMC Data bit 2 IO G3 W7 gpmc_a3/gpmc_d2 gpmc_d3 GPMC Data bit 3 IO G2 AA9 gpmc_a4/gpmc_d3 gpmc_d4 GPMC Data bit 4 IO G1 Y8 gpmc_a5/gpmc_d4 gpmc_d5 GPMC Data bit 5 IO H2 AA8 gpmc_a6/gpmc_d5 gpmc_d6 GPMC Data bit 6 IO H1 AB8 gpmc_a7/gpmc_d6 gpmc_d7 GPMC Data bit 7 IO J5 W8 gpmc_a8/gpmc_d7 gpmc_d8 GPMC Data bit 8 IO J4 W10 gpmc_a9/gpmc_d8 gpmc_d9 GPMC Data bit 9 IO J3 AB9 gpmc_a10/gpmc_d9 gpmc_d10 GPMC Data bit 10 IO J2 AB10 gpmc_a11/gpmc_d10 gpmc_d11 GPMC Data bit 11 IO J1 W9 gpmc_a12/gpmc_d11 gpmc_d12 GPMC Data bit 12 IO K4 AA10 gpmc_a13/gpmc_d12 gpmc_d13 GPMC Data bit 13 IO K3 Y9 gpmc_a14/gpmc_d13 gpmc_d14 GPMC Data bit 14 IO K2 V10 gpmc_a15/gpmc_d14 gpmc_d15 GPMC Data bit 15 IO K1 V9 gpmc_a16/gpmc_d15 gpmc_ncs0 GPMC Chip Select 0 O L2 Y10 gpmc_ncs1 GPMC Chip Select 1 O L1 Y11 gpmc_ncs2 GPMC Chip Select 2 O M4 Y12 gpmc_ncs3 GPMC Chip Select 3 O M3 V12 gpmc_ncs4 GPMC Chip Select 4 O M2 AA11 gpmc_ncs5 GPMC Chip Select 5 O M1 W12 gpmc_ncs6 GPMC Chip Select 6 O N5 AA12 gpmc_ncs7 GPMC Chip Select 7 O N4 V11 gpmc_clk GPMC clock O N1 AB13

MULTIPLEXING

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Table 2-4. External Memory Interfaces - GPMC Signals Description (continued)

SIGNAL NAME DESCRIPTION TYPE ZCN BALL ZER BALL SUBSYSTEM PIN

gpmc_nadv_ale Address Valid or O R1 AA14

Address Latch

Enable gpmc_noe Output Enable O R2 AB14 gpmc_nwe Write Enable O R3 AA15 gpmc_nbe0_cle Lower Byte Enable. O R4 W11

Also used for

Command Latch

Enable gpmc_nbe1 Upper Byte Enable O T1 Y15 gpmc_nwp Flash Write Protect O T2 W14 gpmc_wait0 External indication of I T3 V13

wait gpmc_wait1 External indication of I T4 AA16

wait gpmc_wait2 External indication of I T5 Y14

wait gpmc_wait3 External indication of I U1 V14

wait

MULTIPLEXING

Table 2-5. EXTERNAL MEMORY INTERFACES - SDRC SIGNALS DESCRIPTION

SIGNAL NAME DESCRIPTION TYPE ZCN BALL ZER BALL

sdrc_d0 SDRAM data bit 0 IO B21 E3 sdrc_d1 SDRAM data bit 1 IO A21 D3 sdrc_d2 SDRAM data bit2 IO D20 C3 sdrc_d3 SDRAM data bit 3 IO C20 C2 sdrc_d4 SDRAM data bit 4 IO E19 F3 sdrc_d5 SDRAM data bit 5 IO D19 D2 sdrc_d6 SDRAM data bit 6 IO C19 C1 sdrc_d7 SDRAM data bit 7 IO B19 D1 sdrc_d8 SDRAM data bit 8 IO B18 G2 sdrc_d9 SDRAM data bit 9 IO D17 G3 sdrc_d10 SDRAM data bit 10 IO C17 H3 sdrc_d11 SDRAM data bit 11 IO D16 G4 sdrc_d12 SDRAM data bit 12 IO C16 H4 sdrc_d13 SDRAM data bit 13 IO B16 G1 sdrc_d14 SDRAM data bit 14 IO A16 J3 sdrc_d15 SDRAM data bit 15 IO A15 J1 sdrc_d16 SDRAM data bit 16 IO A7 T3 sdrc_d17 SDRAM data bit 17 IO B7 U3 sdrc_d18 SDRAM data bit 18 IO D7 U4 sdrc_d19 SDRAM data bit 19 IO E7 V4 sdrc_d20 SDRAM data bit 20 IO C6 V1 sdrc_d21 SDRAM data bit 21 IO D6 V2 sdrc_d22 SDRAM data bit 22 IO B5 V5 sdrc_d23 SDRAM data bit 23 IO C5 V3 sdrc_d24 SDRAM data bit 24 IO B4 W3 sdrc_d25 SDRAM data bit 25 IO A3 W4 sdrc_d26 SDRAM data bit 26 IO B3 Y3

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Table 2-5. EXTERNAL MEMORY INTERFACES - SDRC SIGNALS DESCRIPTION (continued)

SIGNAL NAME DESCRIPTION TYPE ZCN BALL ZER BALL

sdrc_d27 SDRAM data bit 27 IO C3 Y4 sdrc_d28 SDRAM data bit 28 IO C2 AA2 sdrc_d29 SDRAM data bit 29 IO D2 AA3 sdrc_d30 SDRAM data bit 30 IO B1 AA4 sdrc_d31 SDRAM data bit 31 IO C1 AB2 sdrc_ba0 SDRAM bank select 0 O A12 L4 sdrc_ba1 SDRAM bank select 1 O C13 K5 sdrc_ba2 SDRAM bank select 2 O D13 J5 sdrc_a0 SDRAM address bit 0 O A11 M3 sdrc_a1 SDRAM address bit 1 O B11 M4 sdrc_a2 SDRAM address bit 2 O C11 M5 sdrc_a3 SDRAM address bit 3 O D11 N3 sdrc_a4 SDRAM address bit 4 O E11 N2 sdrc_a5 SDRAM address bit 5 O A10 N4 sdrc_a6 SDRAM address bit 6 O B10 P3 sdrc_a7 SDRAM address bit 7 O C10 P2 sdrc_a8 SDRAM address bit 8 O D10 P1 sdrc_a9 SDRAM address bit 9 O E10 P4 sdrc_a10 SDRAM address bit 10 O A9 R1 sdrc_a11 SDRAM address bit 11 O B9 R2 sdrc_a12 SDRAM address bit 12 O A8 R3 sdrc_a13 SDRAM address bit 13 O B8 R4 sdrc_a14 SDRAM address bit 14 O D8 T2 sdrc_ncs0 Chip select 0 O E13 J4 sdrc_ncs1 Chip select 1 O A14 K4 sdrc_clk Clock O A13 L1 sdrc_nclk Clock Invert O B13 L2 sdrc_cke0 Clock Enable 0 O D14 K3 sdrc_nras SDRAM Row Access O C14 K1 sdrc_ncas SDRAM column address O E14 L3

sdrc_nwe SDRAM write enable O B14 K2 sdrc_dm0 Data Mask 0 O C21 F4 sdrc_dm1 Data Mask 1 O B15 J2 sdrc_dm2 Data Mask 2 O E8 T4 sdrc_dm3 Data Mask 3 O D1 AB3 sdrc_strben0 PCB layout trace loop 0 A A19 F2

sdrc_strben_dly0 PCB layout trace loop 0 A A18 F1

sdrc_strben1 PCB layout trace loop 1 A A5 W1

sdrc_strben_dly1 PCB layout trace loop 1 A A4 W2

sdrc_odt On-die termination output O C8 T1

sdrc_dqs0p Data Strobe 0 IO B20 E2 sdrc_dqs0n Data Strobe 0 IO A20 E1 sdrc_dqs1p Data Strobe 1 IO B17 H2

strobe

pin 0

pin 1

pin 0

pin 1

for sdrc_ncs0 only

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Table 2-5. EXTERNAL MEMORY INTERFACES - SDRC SIGNALS DESCRIPTION (continued)

SIGNAL NAME DESCRIPTION TYPE ZCN BALL ZER BALL

sdrc_dqs1n Data Strobe 1 IO A17 H1 sdrc_dqs2p Data Strobe 2 IO A6 U1 sdrc_dqs2n Data Strobe 2 IO B6 U2 sdrc_dqs3p Data Strobe 3 IO A2 Y1 sdrc_dqs3n Data Strobe 3 IO B2 Y2 ddr_padref Impedance control for A B12 M2

VREFSSTL 0.9-V DDR data PHY0 IO F14 L5

DDR2 output. This pin must be connected to ground via a 50-ohm (± 2%) resistor.

reference voltage input.

2.4.2 Video Interfaces

Table 2-6. VIDEO INTERFACES - CCDC SINGALS DESCRIPTION

SIGNAL NAME DESCRIPTION TYPE ZCN BALL ZER BALL SYSTEM MUX

ccdc_pclk CCDC pixel clock IO AD2 AB21 mode0 ccdc_field CCDC field ID signal IO AD1 AA21 mode0 ccdc_hd CCDC horizontal IO AE2 Y21 mode0

sync ccdc_vd CCDC vertical sync IO AD3 Y22 mode0 ccdc_wen CCDC write enable I AE3 W21 mode0 ccdc_data0 CCDC data bit 0 I AD4 W22 mode0 ccdc_data1 CCDC data bit 1 I AE4 W20 mode0 ccdc_data2 CCDC data bit 2 I AC5 V21 mode0 ccdc_data3 CCDC data bit 3 I AD5 V19 mode0 ccdc_data4 CCDC data bit 4 I AE5 V22 mode0 ccdc_data5 CCDC data bit 5 I Y6 U20 mode0 ccdc_data6 CCDC data bit 6 I AB6 V20 mode0 ccdc_data7 CCDC data bit 7 I AC6 U19 mode0 ccdc_data8 CCDC data bit 8 I AE6 U21 mode1 ccdc_data9 CCDC data bit 9 I AD6 U22 mode1 ccdc_data10 CCDC data bit 10 I Y7 T19 mode1 ccdc_data11 CCDC data bit 11 I AA7 T20 mode1 ccdc_data12 CCDC data bit 12 I AB7 T21 mode1 ccdc_data13 CCDC data bit 13 I AC7 R22 mode1 ccdc_data14 CCDC data bit 14 I AD7 T22 mode1 ccdc_data15 CCDC data bit 15 I AE7 R20 mode1

(1) See Multiplexing Characteristics table for more information.

MODE

(1)

Table 2-7. Video Interfaces - DSS Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

dss_pclk LCD Pixel Clock O AE23 B22 dss_hsync LCD Horizontal O AD22 B21

dss_vsync LCD Vertical O AD23 B20

Synchronization

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Table 2-7. Video Interfaces - DSS Signals Description (continued)

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

dss_acbias AC bias control (STN) or O AE24 B19

dss_data0 LCD Pixel Data bit 0 IO AD24 A20 dss_data1 LCD Pixel Data bit 1 IO AD25 A19 dss_data2 LCD Pixel Data bit 2 IO AC23 A18 dss_data3 LCD Pixel Data bit 3 IO AC24 B18 dss_data4 LCD Pixel Data bit 4 IO AC25 A17 dss_data5 LCD Pixel Data bit 5 IO AB24 C18 dss_data6 LCD Pixel Data bit 6 IO AB25 D17 dss_data7 LCD Pixel Data bit 7 IO AA23 B16 dss_data8 LCD Pixel Data bit 8 IO AA24 B17 dss_data9 LCD Pixel Data bit 9 IO AA25 C17 dss_data10 LCD Pixel Data bit 10 IO Y22 C16 dss_data11 LCD Pixel Data bit 11 IO Y23 D16 dss_data12 LCD Pixel Data bit 12 IO Y24 D14 dss_data13 LCD Pixel Data bit 13 IO Y25 A16 dss_data14 LCD Pixel Data bit 14 IO W21 D15 dss_data15 LCD Pixel Data bit 15 IO W22 B15 dss_data16 LCD Pixel Data bit 16 IO W23 A15 dss_data17 LCD Pixel Data bit 17 IO W24 A14 dss_data18 LCD Pixel Data bit 18 IO W25 C13 dss_data19 LCD Pixel Data bit 19 IO V24 C15 dss_data20 LCD Pixel Data bit 20 O V25 A13 dss_data21 LCD Pixel Data bit 21 O U21 B13 dss_data22 LCD Pixel Data bit 22 O U22 C14 dss_data23 LCD Pixel Data bit 23 O U23 B14

pixel data enable (TFT) output

Table 2-8. Video Interfaces – RFBI Signals Description

SIGNAL NAME [1] DESCRIPTION [2[ TYPE [3] ZCN BALL ZER BALL SUBSYSTEM PIN

rfbi_a0 RFBI command/data O AE24 B19 dss_acbias

control rfbi_cs0 1st LCD chip select O AD22 B21 dss_hsync rfbi_da0 RFBI data bus 0 IO AD24 A20 dss_data0 rfbi_da1 RFBI data bus 1 IO AD25 A19 dss_data1 rfbi_da2 RFBI data bus 2 IO AC23 A18 dss_data2 rfbi_da3 RFBI data bus 3 IO AC24 B18 dss_data3 rfbi_da4 RFBI data bus 4 IO AC25 A17 dss_data4 rfbi_da5 RFBI data bus 5 IO AB24 C18 dss_data5 rfbi_da6 RFBI data bus 6 IO AB25 D17 dss_data6 rfbi_da7 RFBI data bus 7 IO AA23 B16 dss_data7 rfbi_da8 RFBI data bus 8 IO AA24 B17 dss_data8 rfbi_da9 RFBI data bus 9 IO AA25 C17 dss_data9 rfbi_da10 RFBI data bus 10 IO Y22 C16 dss_data10 rfbi_da11 RFBI data bus 11 IO Y23 D16 dss_data11 rfbi_da12 RFBI data bus 12 IO Y24 D14 dss_data12 rfbi_da13 RFBI data bus 13 IO Y25 A16 dss_data13

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Table 2-8. Video Interfaces – RFBI Signals Description (continued)

SIGNAL NAME [1] DESCRIPTION [2[ TYPE [3] ZCN BALL ZER BALL SUBSYSTEM PIN

rfbi_da14 RFBI data bus 14 IO W21 D15 dss_data14 rfbi_da15 RFBI data bus 15 IO W22 B15 dss_data15 rfbi_rd Read enable for RFBI O AE23 B22 dss_pclk rfbi_wr Write Enable for O AD23 B20 dss_vsync

RFBI rfbi_te_vsync0 tearing effect removal I W23 A15 dss_data16

and Vsync input from

1st LCD rfbi_hsync0 Hsync for 1st LCD I W24 A14 dss_data17 rfbi_te_vsync1 tearing effect removal I W25 C13 dss_data18

and Vsync input from

2nd LCD rfbi_hsync1 Hsync for 2nd LCD I V24 C15 dss_data19 rfbi_cs1 2nd LCD chip select O V25 A13 dss_data20

MULTIPLEXING [5]

Table 2-9. Video Interfaces – TV Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

tv_out1 TV analog output O K21 NA

tv_out2 TV analog output O H24 NA

tv_vfb1 tv_vfb1: Feedback O K20 NA

tv_vfb2 tv_vfb2: Feedback O H23 NA

tv_vref External capacitor I H20 NA

Composite: tv_out1

S-VIDEO: tv_out2

through external resistor to composite

through external resistor to S-VIDEO

2.4.3 Serial Communication Interfaces

Table 2-10. HDQ Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

hdq_sio Bidirectional HDQ 1-Wire IO L25 NA

Table 2-11. Serial Communication Interfaces – I2C Signals Description (I2C1)

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

i2c1_scl I2C Master Serial clock. IOD V4 AA17

i2c1_sda I2C Serial Bidirectional IOD V5 AB17

Table 2-12. Serial Communication Interfaces - I2C Signals Description (I2C2)

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

i2c2_scl I2C Master Serial clock. IOD W1 Y17

i2c2_sda I2C Serial Bidirectional IOD W2 Y16

control and data Interface. Output is open drain.

Output is open drain.

Data. Output is open drain.

Output is open drain.

Data. Output is open drain.

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Table 2-13. Serial Communication Interfaces - I2C Signals Description (I2C3)

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

i2c3_scl I2C Master Serial clock. IOD W4 W16

i2c3_sda I2C Serial Bidirectional IOD W5 W17

Output is open drain.

Data. Output is open drain.

Table 2-14. Serial Communication Interfaces – McBSP LP Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 1)

mcbsp1_dr Received serial data I P23 C9 mcbsp1_clkr Receive Clock IO R25 B11 mcbsp1_fsr Receive frame IO P21 D11

mcbsp1_dx Transmitted serial data IO P22 C10 mcbsp1_clkx Transmit clock IO N24 C8 mcbsp1_fsx Transmit frame IO P24 C11

mcbsp_clks External clock input I P25 E11

MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 2)

mcbsp2_dr Received serial data I B25 C5 mcbsp2_dx Transmitted serial data IO D24 E4 mcbsp2_clkx Combined serial clock IO C25 D5 mcbsp2_fsx Combined frame IO D25 E5

synchronization

(shared by McBSP1, 2, 3, 4, and 5)

synchronization

MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 3)

mcbsp3_dr Received serial data I C24 B4 mcbsp3_dx Transmitted serial data IO B24 C4 mcbsp3_clkx Combined serial clock IO A24 D4 mcbsp3_fsx Combined frame IO C23 A4

MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 4)

mcbsp4_dr Received serial data I A23 B3 mcbsp4_dx Transmitted serial data IO B22 A2 mcbsp4_clkx Combined serial clock IO B23 A3 mcbsp4_fsx Combined frame IO A22 B2

MULTICHANNEL BUFFERED SERIAL PORT (McBSP LP 5)

mcbsp5_dr Received serial data I Y18 E19 mcbsp5_dx Transmitted serial data IO AD19 F19 mcbsp5_clkx Combined serial clock IO AD17 G22 mcbsp5_fsx Combined frame IO AE19 F21

synchronization

Table 2-15. Serial Communication Interfaces – McSPI Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL MULTICHANNEL SERIAL PORT INTERFACE (McSPI1)

mcspi1_clk SPI Clock IO AE14 K22

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Table 2-15. Serial Communication Interfaces – McSPI Signals Description (continued)

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

mcspi1_simo Slave data in, master data IO AD15 K19

mcspi1_somi Slave data out, master IO AC15 J18

mcspi1_cs0 SPI Enable 0, polarity IO AB15 K18

mcspi1_cs1 SPI Enable 1, polarity O AD14 J20

mcspi1_cs2 SPI Enable 2, polarity O AE15 J19

mcspi1_cs3 SPI Enable 3, polarity O AE16 J21

MULTICHANNEL SERIAL PORT INTERFACE (McSPI2)

mcspi2_clk SPI Clock IO AD16,AC9 J22 mcspi2_simo Slave data in, master data IO AC16,AD9 H20

mcspi2_somi Slave data out, master IO AB16,AE9 H22

mcspi2_cs0 SPI Enable 0, polarity IO AA16,AA10 H21

mcspi2_cs1 SPI Enable 1, polarity O AE17 H19

MULTICHANNEL SERIAL PORT INTERFACE (McSPI3)

mcspi3_clk SPI Clock IO W25,AD11,AA18 C13, M21, G19, E20 mcspi3_simo Slave data in, master data IO V24,AE11,AD18 C15, M20, G20

mcspi3_somi Slave data out, master IO V25, AB12, AC18 A13, K20, F22

mcspi3_cs0 SPI Enable 0, polarity IO U21,AE12,AB18 B13, K21, F20

mcspi3_cs1 SPI Enable 1, polarity O U22, AD12, AB19 C14, M18, E21

MULTICHANNEL SERIAL PORT INTERFACE (McSPI4)

mcspi4_clk SPI Clock IO W20, R25 C20, B11 mcspi4_simo Slave data in, master data IO P22 C10

mcspi4_somi Slave data out, master IO P23 C9

mcspi4_cs0 SPI Enable 0, polarity IO P24 C11

out

data in

configured by software

out

data in

configured by software

out

data in

configured by software

out

data in

configured by software

Table 2-16. Serial Communication Interfaces – HECC Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

hecc1_txd Transmit serial data pin O V2 AB15 hecc1_rxd Receive serial data pin I V3 AB16

Table 2-17. Serial Communication Interfaces – EMAC (RMII) Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

rmii_mdio_data Management data I/O IO AE6 U21 rmii_mdio_clk Management data clock O AD6 U22 rmii_rxd0 EMAC receive data pin 0 I Y7 T19 rmii_rxd1 EMAC receive data pin 1 I AA7 T20

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Table 2-17. Serial Communication Interfaces – EMAC (RMII) Signals Description (continued)

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

rmii_crs_dv EMAC carrier I AB7 T21

rmii_rxer EMAC receive error I AC7 R22 rmii_txd0 EMAC transmit data pin 0 O AD7 T22 rmii_txd1 EMAC transmit data pin 1 O AE7 R20 rmii_txen EMAC transmit enable O AD8 R19 rmii_50mhz_clk EMAC RMII 50 MHz clock I AE8 R21

sense/receive data valid

Table 2-18. Serial Communication Interfaces – UARTs Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART1)

uart1_cts UART1 Clear To Send I AD24,Y20,P25 C19 uart1_rts UART1 Request To Send O AD25,Y19 C21 uart1_rx UART1 Receive data I AA23,W20,AC20 C20 uart1_tx UART1 Transmit data O AB25,AA19 C22

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART2)

uart2_cts UART2 Clear To Send I B24,F20 A5 uart2_rts UART2 Request To Send O C24,F19 B5 uart2_rx UART2 Receive data I C23,E23 C6 uart2_tx UART2 Transmit data O A24,E24 D6

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART3) / IrDA

uart3_cts_rctx UART3 Clear To Send IO U1,N2 W15

uart3_rts_sd UART3 Request To Send O N3,V3 W13

uart3_rx_irrx UART3 Receive data , IR I AC25,P1,F25,V2 AA13

uart3_tx_irtx UART3 Transmit data , IR O AB24,P2,F24,E25 Y13

UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART4)

uart4_cts UART4 Clear To Send I AD3,AD11 Y22,M21 uart4_rts UART4 Request To Send O AE2,AE11 Y21,M20 uart4_rx UART4 Receive data I T5,AE3,AC12 Y14,W21,L19 uart4_tx UART4 Transmit data O T4,AD1,AB12 AA16,AA21,K20

(input), Remote TX (output)

, IR enable

and Remote RX

Table 2-19. Serial Communication Interfaces – USB Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL UNIVERSAL SERIAL BUS INTERFACE (USB0)

usb0_dp USB D+ (differential signal A F25 A6

usb0_dm USB D- (differential signal A F24 B6

usb0_drvvbus Digital output to control O E25 A7

usb0_id USB operating mode A G25 B7

pair)

external supply

identification pin

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Table 2-19. Serial Communication Interfaces – USB Signals Description (continued)

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

usb0_vbus For host or device mode A G24 C7

operation, tie the VBUS/USB power signal to the USB connector. When used in OTG mode operation, tie VBUS to the external charge pump and to the VBUS signal on the USB connector.

MM_FSUSB3

mm_fsusb3_rxdm Vminus receive data (not IO AE13 M19

used in 3- or 4-pin configurations)

mm_fsusb3_rxdp Vplus receive data (not IO AC13 L20

used in 3- or 4-pin configurations)

mm_fsusb3_rxrcv Differential receiver signal IO A23 B3

input (not used in 3-pin mode)

mm_fsusb3_txse0 Single-ended zero. Used IO B23 A3

as VM in 4-pin VP_VM mode.

mm_fsusb3_txdat USB data. Used as VP in IO B22 A2

4-pin VP_VM mode.

mm_fsusb3_txen_n Transmit enable IO A22 B2

MM_FSUSB2

mm_fsusb2_rxdm Vminus receive data (not IO AD21 D20

used in 3- or 4-pin configurations)

mm_fsusb2_rxdp Vplus receive data (not IO AB20 E20

used in 3- or 4-pin configurations)

mm_fsusb2_rxrcv Differential receiver signal IO AC21 D19

input (not used in 3-pin mode)

mm_fsusb2_txse0 Single-ended zero. Used IO AE22 D18

as VM in 4-pin VP_VM mode.

mm_fsusb2_txdat USB data. Used as VP in IO AE16 J21

4-pin VP_VM mode.

mm_fsusb2_txen_n Transmit enable IO AE17 H19

MM_FSUSB1

mm_fsusb1_rxdm Vminus receive data (not IO AD20 D21

used in 3- or 4-pin configurations)

mm_fsusb1_rxdp Vplus receive data (not IO AE18 G21

used in 3- or 4-pin configurations)

mm_fsusb1_rxrcv Differential receiver signal IO AD18 G20

input (not used in 3-pin mode)

mm_fsusb1_txse0 Single-ended zero. Used IO AC18 F22

as VM in 4-pin VP_VM mode.

mm_fsusb1_txdat USB data. Used as VP in IO AB18 F20

4-pin VP_VM mode.

mm_fsusb1_txen_n Transmit enable IO AB19 E21

HSUSB2

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Table 2-19. Serial Communication Interfaces – USB Signals Description (continued)

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

hsusb2_clk Dedicated for external O AC20 E22

hsusb2_stp Dedicated for external O AB20 E20

hsusb2_dir Dedicated for external I AE21 E18

hsusb2_nxt Dedicated for external I AD21 D20

hsusb2_data0 Dedicated for external IO AC21 D19

hsusb2_data1 Dedicated for external IO AE22 D18

hsusb2_data2 Dedicated for external IO AE16 J21

hsusb2_data3 Dedicated for external IO AE17 H19

hsusb2_data4 Dedicated for external IO AC16 H20

hsusb2_data5 Dedicated for external IO AB16 H22

hsusb2_data6 Dedicated for external IO AA16 H21

hsusb2_data7 Dedicated for external IO AD16 J22

HSUSB1

hsusb1_clk Dedicated for external O AE18 G21

hsusb1_stp Dedicated for external O AD17 G22

hsusb1_dir Dedicated for external I AE20 D22

hsusb1_nxt Dedicated for external I AD20 D21

hsusb1_data0 Dedicated for external IO AD18 G20

hsusb1_data1 Dedicated for external IO AC18 F22

hsusb1_data2 Dedicated for external IO AB18 F20

transceiver 60-MHz clock input from PHY

transceiver Stop signal

transceiver Data direction control from PHY

transceiver Next signal from PHY

transceiver Bidirectional data bus

transceiver Bidirectional data bus additional signals for 12-pin ULPI operation.

transceiver Bidirectional data bus

transceiver 60-MHz clock input from PHY

transceiver Stop signal

transceiver Data direction control from PHY

transceiver Next signal from PHY

transceiver Bidirectional data bus

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Table 2-19. Serial Communication Interfaces – USB Signals Description (continued)

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

hsusb1_data3 Dedicated for external IO AB19 E21

transceiver Bidirectional data bus

hsusb1_data4 Dedicated for external IO Y18 E19

transceiver Bidirectional data bus additional signals for 12-pin ULPI operation

hsusb1_data5 Dedicated for external IO AE19 F21

transceiver Bidirectional data bus additional signals for 12-pin ULPI operation

hsusb1_data6 Dedicated for external IO AD19 F19

transceiver Bidirectional data bus additional signals for 12-pin ULPI operation

hsusb1_data7 Dedicated for external IO AA18 G19

transceiver Bidirectional data bus additional signals for 12-pin ULPI operation

2.4.4 Removable Media Interfaces

Table 2-20. Removable Media Interfaces – MMC/SDIO Signals Description

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SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL MULTIMEDIA MEMORY CARD (MMC1) / SECURE DIGITAL IO (SDIO1)

mmc1_clk MMC/SD Output Clock O AA9 P22 mmc1_cmd MMC/SD command signal IO AB9 N21 mmc1_dat0 MMC/SD Card Data bit 0 / IO AC9 P21

mmc1_dat1 MMC/SD Card Data bit 1 IO AD9 N20 mmc1_dat2 MMC/SD Card Data bit 2 IO AE9 P19 mmc1_dat3 MMC/SD Card Data bit 3 IO AA10 P20 mmc1_dat4 MMC/SD Card Data bit 4 IO AB10 N22 mmc1_dat5 MMC/SD Card Data bit 5 IO AC10 N19 mmc1_dat6 MMC/SD Card Data bit 6 IO AD10 N18 mmc1_dat7 MMC/SD Card Data bit 7 IO AE10 P18

MULTIMEDIA MEMORY CARD (MMC2) / SECURE DIGITAL IO (SDIO2)

mmc2_clk MMC/SD Output Clock O AD11 M21 mmc2_dir_dat0 Direction control for DAT0 O AB13 L18

mmc2_dir_dat1 Direction control for DAT1 O AC13 L20

mmc2_dir_dat2 Direction control for DAT2 O AB1 V18

mmc2_dir_dat3 Direction control for DAT4, O AB2 Y19

mmc2_clkin MMC/SD input clock I AE13 NA mmc2_dat0 MMC/SD Card Data bit 0 IO AB12 K20 mmc2_dat1 MMC/SD Card Data bit 1 IO AC12 L19 mmc2_dat2 MMC/SD Card Data bit 2 IO AD12 M18

SPI Serial Input

signal case an external transceiver used

and DAT3 signals case an external transceiver used

signal case an external transceiver used

DAT5, DAT6, and DAT7 signals case an external transceiver used

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Table 2-20. Removable Media Interfaces – MMC/SDIO Signals Description (continued)

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

mmc2_dat3 MMC/SD Card Data bit 3 IO AE12 K21 mmc2_dat4 MMC/SD Card Data bit 4 IO AB13 L18 mmc2_dat5 MMC/SD Card Data bit 5 IO AC13 L20 mmc2_dat6 MMC/SD Card Data bit 6 IO AD13 L21 mmc2_dat7 MMC/SD Card Data bit 7 IO AE13 M19 mmc2_dir_cmd Direction control for CMD O AD13 NA

mmc2_cmd MMC/SD command signal IO AE11 M20

MULTIMEDIA MEMORY CARD (MMC3) / SECURE DIGITAL IO (SDIO3)

mmc3_clk MMC/SD Output Clock O AD15,AE17 J19 mmc3_cmd MMC/SD command signal IO AD14,AE18 J20 mmc3_dat0 MMC/SD Card Data bit 0 / IO AB13,Y18 E19

mmc3_dat1 MMC/SD Card Data bit 1 IO AC13,AE19 L20,F21 mmc3_dat2 MMC/SD Card Data bit 2 IO AD13,AD19 L21,F19 mmc3_dat3 MMC/SD Card Data bit 3 IO AE13,AA18 M19,G19 mmc3_dat4 MMC/SD Card Data bit 4 IO AD18 G20 mmc3_dat5 MMC/SD Card Data bit 5 IO AD20 D21 mmc3_dat6 MMC/SD Card Data bit 6 IO AE20 D22 mmc3_dat7 MMC/SD Card Data bit 7 IO AB19 E21

signal case an external transceiver is used

SPI Serial Input

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2.4.5 Test Interfaces

Table 2-21. Test Interfaces – ETK Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

etk_ctl ETK trace ctl O AE18 G21 etk_clk ETK trace clock O AD17 G22 etk_d0 ETK data 0 O AD18 G20 etk_d1 ETK data 1 O AC18 F22 etk_d2 ETK data 2 O AB18 F20 etk_d3 ETK data 3 O AA18 G19 etk_d4 ETK data 4 O Y18 E19 etk_d5 ETK data 5 O AE19 F21 etk_d6 ETK data 6 O AD19 F19 etk_d7 ETK data 7 O AB19 E21 etk_d8 ETK data 8 O AE20 D22 etk_d9 ETK data 9 O AD20 D21 etk_d10 ETK data 10 O AC20 E22 etk_d11 ETK data 11 O AB20 E20 etk_d12 ETK data 12 O AE21 E18 etk_d13 ETK data 13 O AD21 D20 etk_d14 ETK data 14 O AC21 D19 etk_d15 ETK data 15 O AE22 D18

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Table 2-22. Test Interfaces – JTAG Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

jtag_ntrst Test Reset I U24 D13 jtag_tck Test Clock I U25 E14 jtag_rtck ARM Clock Emulation O T21 C12 jtag_tms_tmsc Test Mode Select IO T22 A12 jtag_tdi Test Data Input I T23 B12 jtag_tdo Test Data Output O T24 D12 jtag_emu0 Test emulation 0 IO T25 E13 jtag_emu1 Test emulation 1 IO R24 E12

Table 2-23. Test Interfaces – HWDBG Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

hw_dbg0 Debug signal 0 O AD2,AD17 G22 hw_dbg1 Debug signal 1 O AD1,AE18 G21 hw_dbg2 Debug signal 2 O AD3,AD18 G20 hw_dbg3 Debug signal 3 O AE3,AC18 F22 hw_dbg4 Debug signal 4 O AC5,AC18 F20 hw_dbg5 Debug signal 5 O AD5,AA18 G19 hw_dbg6 Debug signal 6 O Y18,AE5 E19 hw_dbg7 Debug signal 7 O Y6,AE19 F21 hw_dbg8 Debug signal 8 O Y7,AD19 F19 hw_dbg9 Debug signal 9 O AA7,AB19 E21 hw_dbg10 Debug signal 10 O AC7,AE20 D22 hw_dbg11 Debug signal 11 O AD7,AD20 D21 hw_dbg12 Debug signal 12 O AE23,AC20 E22

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Table 2-23. Test Interfaces – HWDBG Signals Description (continued)

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

hw_dbg13 Debug signal 13 O AD22,AB20 E20 hw_dbg14 Debug signal 14 O AB25,AE21 E18 hw_dbg15 Debug signal 15 O AA23,AD21 D20 hw_dbg16 Debug signal 16 O AA24,AC21 D19 hw_dbg17 Debug signal 17 O AA25,AE22 D18

2.4.6 Miscellaneous

Table 2-24. Miscellaneous – GP Timer Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

gpt8_pwm_evt PWM or event for GP IO N4,E23,AE17 V11,C6,H19

gpt9_pwm_evt PWM or event for GP IO M4,M2,F20,AC16 Y12,AA11,A5,H20

gpt10_pwm_evt PWM or event for GP IO M3,M1,F19,AB16 V12,W12,B5,H22

gpt11_pwm_evt PWM or event for GP IO N5,E24,AA16,AA12 AA12,D6,H21

timer 8

timer 9

timer 10

timer 11

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2.4.7 General-Purpose IOs

Table 2-25. General-Purpose IOs Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

gpio_0 General-purpose IO 0 IO Y1 AB18 gpio_1 General-purpose IO 1 IO M24 B8 gpio_2 General-purpose IO 2 IO Y4 AB19 gpio_3 General-purpose IO 3 IO AA1 AB20 gpio_4 General-purpose IO 4 IO AA2 W18 gpio_5 General-purpose IO 5 IO AA3 AA19 gpio_6 General-purpose IO 6 IO AB1 V18 gpio_7 General-purpose IO 7 IO AB2 Y19 gpio_8 General-purpose IO 8 IO AC1 W19 gpio_10 General-purpose IO 10 IO N25 E9 gpio_11 General-purpose IO 11 IO T25 E13 gpio_12 General-purpose IO 12 IO AD17 G22 gpio_13 General-purpose IO 13 IO AE18 G21 gpio_14 General-purpose IO 14 IO AD18 G20 gpio_15 General-purpose IO 15 IO AC18 F22 gpio_16 General-purpose IO 16 IO AB18 F20 gpio_17 General-purpose IO 17 IO AA18 G19 gpio_18 General-purpose IO 18 IO Y18 E19 gpio_19 General-purpose IO 19 IO AE19 F21 gpio_20 General-purpose IO 20 IO AD19 F19 gpio_21 General-purpose IO 21 IO AB19 E21 gpio_22 General-purpose IO 22 IO AE20 D22 gpio_23 General-purpose IO 23 IO AD20 D21 gpio_24 General-purpose IO 24 IO AC20 E22 gpio_25 General-purpose IO 25 IO AB20 E20 gpio_26 General-purpose IO 26 IO AE21 E18 gpio_27 General-purpose IO 27 IO AD21 D20 gpio_28 General-purpose IO 28 IO AC21 D19 gpio_29 General-purpose IO 29 IO AE22 D18 gpio_30 General-purpose IO 30 IO Y3 Y18 gpio_31 General-purpose IO 31 IO R24 E12 gpio_34 General-purpose IO 34 IO E3 W5 gpio_35 General-purpose IO 35 IO E2 Y5 gpio_36 General-purpose IO 36 IO E1 AB4 gpio_37 General-purpose IO 37 IO F7 AA5 gpio_38 General-purpose IO 38 IO F6 AB5 gpio_39 General-purpose IO 39 IO F4 AB6 gpio_40 General-purpose IO 40 IO F3 AA6 gpio_41 General-purpose IO 41 IO F2 W6 gpio_42 General-purpose IO 42 IO F1 AB7 gpio_43 General-purpose IO 43 IO G6 Y6 gpio_44 General-purpose IO 44 IO J4 W10 gpio_45 General-purpose IO 45 IO J3 AB9 gpio_46 General-purpose IO 46 IO J2 AB10 gpio_47 General-purpose IO 47 IO J1 W9

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Table 2-25. General-Purpose IOs Signals Description (continued)

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

gpio_48 General-purpose IO 48 IO K4 AA10 gpio_49 General-purpose IO 49 IO K3 Y9 gpio_50 General-purpose IO 50 IO K2 V10 gpio_51 General-purpose IO 51 IO K1 V9 gpio_52 General-purpose IO 52 IO L1 Y11 gpio_53 General-purpose IO 53 IO M4 Y12 gpio_54 General-purpose IO 54 IO M3 V12 gpio_55 General-purpose IO 55 IO M2 AA11 gpio_56 General-purpose IO 56 IO M1 W12 gpio_57 General-purpose IO 57 IO N5 AA12 gpio_58 General-purpose IO 58 IO N4 V11 gpio_59 General-purpose IO 59 IO N1 AB13 gpio_60 General-purpose IO 60 IO R4 W11 gpio_61 General-purpose IO 61 IO T1 Y15 gpio_62 General-purpose IO 62 IO T2 W14 gpio_63 General-purpose IO 63 IO T4 AA16 gpio_64 General-purpose IO 64 IO T5 Y14 gpio_65 General-purpose IO 65 IO U1 V14 gpio_66 General-purpose IO 66 IO AE23 B22 gpio_67 General-purpose IO 67 IO AD22 B21 gpio_68 General-purpose IO 68 IO AD23 B20 gpio_69 General-purpose IO 69 IO AE24 B19 gpio_70 General-purpose IO 70 IO AD24 A20 gpio_71 General-purpose IO 71 IO AD25 A19 gpio_72 General-purpose IO 72 IO AC23 A18 gpio_73 General-purpose IO 73 IO AC24 B18 gpio_74 General-purpose IO 74 IO AC25 A17 gpio_75 General-purpose IO 75 IO AB24 C18 gpio_76 General-purpose IO 76 IO AB25 D17 gpio_77 General-purpose IO 77 IO AA23 B16 gpio_78 General-purpose IO 78 IO AA24 B17 gpio_79 General-purpose IO 79 IO AA25 C17 gpio_80 General-purpose IO 80 IO Y22 C16 gpio_81 General-purpose IO 81 IO Y23 D16 gpio_82 General-purpose IO 82 IO Y24 D14 gpio_83 General-purpose IO 83 IO Y25 A16 gpio_84 General-purpose IO 84 IO W21 D15 gpio_85 General-purpose IO 85 IO W22 B15 gpio_86 General-purpose IO 86 IO W23 A15 gpio_87 General-purpose IO 87 IO W24 A14 gpio_88 General-purpose IO 88 IO W25 C13 gpio_89 General-purpose IO 89 IO V24 C15 gpio_90 General-purpose IO 90 IO V25 A13 gpio_91 General-purpose IO 91 IO U21 B13 gpio_92 General-purpose IO 92 IO U22 C14 gpio_93 General-purpose IO 93 IO U23 B14 gpio_94 General-purpose IO 94 IO AD2 AB21

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Table 2-25. General-Purpose IOs Signals Description (continued)

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

gpio_95 General-purpose IO 95 IO AD1 AA21 gpio_96 General-purpose IO 96 IO AE2 Y21 gpio_97 General-purpose IO 97 IO AD3 Y22 gpio_98 General-purpose IO 98 IO AE3 W21 gpio_99 General-purpose IO 99 I AD4 W22 gpio_100 General-purpose IO 100 I AE4 W20 gpio_101 General-purpose IO 101 IO AC5 V21 gpio_102 General-purpose IO 102 IO AD5 V19 gpio_103 General-purpose IO 103 IO AE5 V22 gpio_104 General-purpose IO 104 IO Y6 U20 gpio_105 General-purpose IO 105 IO AB6 V20 gpio_106 General-purpose IO 106 IO AC6 U19 gpio_107 General-purpose IO 107 IO AE6 U21 gpio_108 General-purpose IO 108 IO AD6 U22 gpio_109 General-purpose IO 109 IO Y7 T19 gpio_110 General-purpose IO 110 IO AA7 T20 gpio_111 General-purpose IO 111 IO AB7 T21 gpio_112 General-purpose IO 112 I AE7 R20 gpio_113 General-purpose IO 113 I AD8 R19 gpio_114 General-purpose IO 114 I AE8 R21 gpio_116 General-purpose IO 116 IO D25 E5 gpio_117 General-purpose IO 117 IO C25 D5 gpio_118 General-purpose IO 118 IO B25 C5 gpio_119 General-purpose IO 119 IO D24 E4 gpio_120 General-purpose IO 120 IO AA9 P22 gpio_121 General-purpose IO 121 IO AB9 N21 gpio_122 General-purpose IO 122 IO AC9 P21 gpio_123 General-purpose IO 123 IO AD9 N20 gpio_124 General-purpose IO 124 IO AE9 P19 gpio_125 General-purpose IO 125 IO AA10 P20 gpio_126 General-purpose IO 126 IO AB10 N22 gpio_127 General-purpose IO 127 IO AC10 N19 gpio_128 General-purpose IO 128 IO AD10 N18 gpio_129 General-purpose IO 129 IO AE10 P18 gpio_130 General-purpose IO 130 IO AD11 M21 gpio_131 General-purpose IO 131 IO AE11 M20 gpio_132 General-purpose IO 132 IO AB12 K20 gpio_133 General-purpose IO 133 IO AC12 L19 gpio_134 General-purpose IO 134 IO AD12 M18 gpio_135 General-purpose IO 135 IO AE12 K21 gpio_136 General-purpose IO 136 IO AB13 L18 gpio_137 General-purpose IO 137 IO AC13 L20 gpio_138 General-purpose IO 138 IO AD13 L21 gpio_139 General-purpose IO 139 IO AE13 M19 gpio_140 General-purpose IO 140 IO B24 C4 gpio_141 General-purpose IO 141 IO C24 B4 gpio_142 General-purpose IO 142 IO A24 D4

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Table 2-25. General-Purpose IOs Signals Description (continued)

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

gpio_143 General-purpose IO 143 IO C23 A4 gpio_144 General-purpose IO 144 IO F20 A5 gpio_145 General-purpose IO 145 IO F19 B5 gpio_146 General-purpose IO 146 IO E24 D6 gpio_147 General-purpose IO 147 IO E23 C6 gpio_148 General-purpose IO 148 IO AA19 C22 gpio_149 General-purpose IO 149 IO Y19 C21 gpio_150 General-purpose IO 150 IO Y20 C19 gpio_151 General-purpose IO 151 IO W20 C20 gpio_152 General-purpose IO 152 IO B23 A3 gpio_153 General-purpose IO 153 IO A23 B3 gpio_154 General-purpose IO 154 IO B22 A2 gpio_155 General-purpose IO 155 IO A22 B2 gpio_156 General-purpose IO 156 IO R25 B11 gpio_157 General-purpose IO 157 IO P21 D11 gpio_158 General-purpose IO 158 IO P22 C10 gpio_159 General-purpose IO 159 IO P23 C9 gpio_160 General-purpose IO 160 IO P25 E11 gpio_161 General-purpose IO 161 IO P24 C11 gpio_162 General-purpose IO 162 IO N24 C8 gpio_163 General-purpose IO 163 IO N2 W15 gpio_164 General-purpose IO 164 IO N3 W13 gpio_165 General-purpose IO 165 IO P1 AA13 gpio_166 General-purpose IO 166 IO P2 Y13 gpio_167 General-purpose IO 167 IO AC7 R22 gpio_168 General-purpose IO 168 IO W1 Y17 gpio_170 General-purpose IO 170 IO L25 B9 gpio_171 General-purpose IO 171 IO AE14 K22 gpio_172 General-purpose IO 172 IO AD15 K19 gpio_173 General-purpose IO 173 IO AC15 J18 gpio_174 General-purpose IO 174 IO AB15 K18 gpio_175 General-purpose IO 175 IO AD14 J20 gpio_176 General-purpose IO 176 IO AE15 J19 gpio_177 General-purpose IO 177 IO AE16 J21 gpio_178 General-purpose IO 178 IO AD16 J22 gpio_179 General-purpose IO 179 IO AC16 H20 gpio_180 General-purpose IO 180 IO AB16 H22 gpio_181 General-purpose IO 181 IO AA16 H21 gpio_182 General-purpose IO 182 IO AE17 H19 gpio_183 General-purpose IO 183 IO W2 Y16 gpio_184 General-purpose IO 184 IO W4 W16 gpio_185 General-purpose IO 185 IO W5 W17 gpio_186 General-purpose IO 186 IO M25 E10

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2.4.8 System and Miscellaneous Terminals

Table 2-26. System and Miscellaneous Signals Description

SIGNAL NAME [1] DESCRIPTION [2] TYPE [3] ZCN BALL ZER BALL

sys_32k 32-kHz clock input I K24 A8 sys_xtalin Main input clock. Oscillator input I K25 A10 sys_xtalout Output of oscillator O H25 A9 sys_altclk Alternate clock source selectable for I L25 B9

GPTIMERs (maximum 54 MHz), USB (48 MHz) , or NTSC/PAL (54 MHz)

sys_clkreq Request from device for system clock (open IO M24 B8

source type) sys_clkout1 Configurable output clock1 O N25 E9 sys_clkout2 Configurable output clock2 O M25 E10 sys_boot0 Boot configuration mode bit 0 I Y4 AB19 sys_boot1 Boot configuration mode bit 1 I AA1 AB20 sys_boot2 Boot configuration mode bit 2 I AA2 W18 sys_boot3 Boot configuration mode bit 3 I AA3 AA19 sys_boot4 Boot configuration mode bit 4 I AB1 V18 sys_boot5 Boot configuration mode bit 5 I AB2 Y19 sys_boot6 Boot configuration mode bit 6 I AC1 W19 sys_boot7 Boot configuration mode bit 7 I AC2 AA20 sys_boot8 Boot configuration mode bit 8 I AC3 Y20 sys_nrespwron Power On Reset I Y2 AA18 sys_nreswarm Warm Boot Reset (open drain output) I Y3 Y18 sys_nirq External FIQ input I Y1 AB18 sys_ndmareq0 External DMA request 0 (system I M3 V12

expansion). Level (active low) or edge

(falling) selectable. sys_ndmareq1 External DMA request 1 (system I M2,U1 AA11

expansion). Level (active low) or edge

(falling) selectable. sys_ndmareq2 External DMA request 2 (system I F1,M1 W12

expansion). Level (active low) or edge

(falling) selectable. sys_ndmareq3 External DMA request 3 (system I G6,N5 AA12

expansion). Level (active low) or edge

(falling) selectable.

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2.4.9 Power Supplies

Table 2-27. Power Supplies Description

SIGNAL NAME[1] DESCRIPTION[2]

VDD_CORE 1.2-V core and oscillator macros power supply. R8, M18, L18, M11, M13, M15, N8, N10, N12, N14,

VSS Core and I/O common ground. N17, N14, N13,

VDDS_SRAM_MPU 1.8-V MPU SLDO analog power supply. AA13 L17 VDDS_SRAM_CORE_BG E17 J6

CAP_VDD_SRAM_MPU For proper device operation, connect to a 1mF AA12 M17

CAP_VDD_SRAM_CORE For proper device operation, connect to a 1mF E16 K6

VDDS_DPLL_MPU_USBH 1.8-V MPUSS DPLL and USBHOST DPLL analog OST power supply.

VDDS_DPLL_PER_CORE N20 F11 VDDA_DAC 1.8-V DAC analog power supply. H21 NA

VSSA_DAC DAC analog ground. H22 NA VDDA3P3V_USBPHY 3.3-V USB transceiver analog power supply. F23 F7 VDDA1P8V_USBPHY 1.8-V USB transceiver power supply. G22 D7

CAP_VDDA1P2LDO_USB PHY

1.8-V Core SLDO and VDDA of BandGap analog power supply.

1.2-V SRAMOUT for MPU SLDO. decoupling capacitor.

1.2-V SRAMOUT for Core SLDO. decoupling capacitor.

1.8-V DPLL and HSDIVIDER/ CORE and HSDIVIDER analog power supply.

Output of the 1.2-V internal LDO. For proper device operation, connect a 0.22uF F22 E7 capacitor between this pin and VSSA.

BALL BALL

(ZCN Pkg.) (ZER Pkg.)

V16, V15, V11, V10, U16, U15, U11, U10, T18, T17, T9, T8, J8,J10, J12, J14, J16, K9, K11, K13, R18, R17, R9, K15, L8, L10, L12, L14, M7, M9,

L9, L8, K18, P7, P9, P11, P13, P15, R8, R10, K17, K9, K8, R12, R14 J16, J15, J11, J10, H15, H11, H10

AE25, AE1, V18, V17, V14, V13, V12, V9, V8, U18, U17, U14, U13, U12, U9, U8, T14, T13, T12, R16, R15, R14, R13, R12, R11, R10, P18, P17, P16, P15, P14, P13, P12, P11, P10, P9, P8, N18,

N12, N9, N8, M17, M16, M15, M14, M13,M12, M11, M10, M9, M8, L17, L16, L15, L14, L13, L12, L11, L10, K14, K13, K12, J18, J17, J14, J13, J12, J9, J8, H14, H13, H12, H9, A25, A1, N23, G20, G21

AA15 K17

A1, A11,A22, E6, E16, F6, F13, F15, F17, G5, G7, G11, G14, G16, G18, H6, H7, H8, H9, H10, H11, H12, H13, H14, H15, H16, H17, J9, J11, J13, J15, K8, K10, K12, K14, K16, L7, L9, L11, L13, L15, M1, M6, M8, M10, M12, M14, M16, M22, N7, N9, N11, N13, N15, N17, P6, P8, P10, P12, P14, P16, R5, R7, R9, R11, R13, R15, R17, T6, T8, T10, T12, T14, T16, T18, U5, U7, U9, U11, U13, U15, U17, V6, AB1, AB12, AB22

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Table 2-27. Power Supplies Description (continued)

SIGNAL NAME[1] DESCRIPTION[2]

VDDSHV 1.8/3.3-V power supply. L22, N16, P17, R16, R18, T9, T11,

VDDS 1.8-V power supply. N1, N5, N6, P5, R6, T5, T7, T15, U6,

VDDSOSC 1.8-V oscillator power supply. L20 G9 VSSOSC Oscillator ground. J25 B10

BALL BALL

(ZCN Pkg.) (ZER Pkg.)

Y16, Y15, Y13, Y12, Y10, W16, W15, W13, W12,W10, W9, W6, V7, V6, U19, T20, T19, T7, T6, R7, R6, P20, P19, N19, N7, N6, M7, M6, M5, L19, K19, K7, K6, K5, J7, H18, H17

Y9, W18, U20, R5, H16, H8, G17, G16, G14, G13, G11, G10, G8, F16, F13, F11, F10, F8

A21, B1,E15, E17, F12, F14, F18, G10, G12, G13, G8, G17, H18, J17,

T13, T17, U8, U10, U12, U14, U16, U18, V7, V8, V17, AA22, AB11

F5, F16, G9, G15, H5, K7, L6, L16, AA1

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3 ELECTRICAL CHARACTERISTICS

3.1 Absolute Maximum Ratings

The following table specifies the absolute maximum ratings over the operating junction temperature range of commercial and extended temperature devices. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

Notes:

• Logic functions and parameter values are not assured out of the range specified in the recommended operating conditions.

• The AM3517/05 device adheres to EIA/JESD22−A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM).

Table 3-1. Absolute Maximum Ratings Over Operating Junction Temperature Range

PARAMETER MIN MAX UNIT

VDD_CORE Supply voltage range for core macros -0.5 1.6 V VDDS Second supply voltage range for 1.8-V I/O macros -0.5 2.25 V VDDSHV Supply voltage range for 1.8/3.3V I/O macros -0.5 3.8 V VDDS_SRAM_MPU Analog Supply voltage range for 1.8-V MPU SLDO -0.5 2.25 V VDDS_SRAM_CORE_BG Analog Supply voltage range for 1.8-V Core SLDO and -0.5 2.25 V

VDDS_DPLL_MPU_USB Analog power supply for 1.8-V MPUSS DPLL and -0.5 2.1 V HOST USBHOST DPLL

VDDS_DPLL_PER_COR Analog power supply for 1.8-V DPLL and HSDIVIDER/ -0.5 2.1 V E CORE and HSDIVIDER

VDDA_DAC Analog Power Supply for 1.8-V DAC -0.5 2.43 V VDDA3P3V_USBPHY Analog power supply for 3.3-V USB transceiver -0.5 3.6 V VDDA1P8V_USBPHY Power Supply for 1.8-V USB transceiver -0.5 2.0 V VDDSOSC Power Supply for 1.8-V oscillator -0.5 2.1 V V

PAD

ESD

IOI

clamp

stg

(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device. (2) ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 1000V HBM allows safe manufacturing with basic ESD control

methods. Actual performance of the device may exceed the value listed above.

(3) EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250V CDM allows safe manufacturing with basic ESD control

methods. Actual performance of the device may exceed the value listed above.

(4) Each device is tested with I/O pin injection of 200 mA with a stress voltage of 1.5 times maximum vdd at room temperature.

VDDA of BandGap

Voltage range at Oscillator input (sys_xtalin) -0.3 VDDSOSC + 0.3 V PAD

ESD stress HBM (human body model)

(1)

voltage

Current-pulse injection on each I/O pin Clamp current for an input or output -20 20 mA Storage temperature range -65 150 °C

VDDS 1.8-V I/O macros -0.3 VDDS + 0.3 Dual-voltage LVCMOS inputs, -0.3 VDDSHV + 0.3

VDDSHV = 1.8 V Dual-voltage LVCMOS inputs, -0.3 3.8

VDDSHV = 3.3 V USB VBUS pin (usb0_vbus) 5.5 USB 5V Tolerant IOs (usb0_dp, 5.25

usb0_dm, usb0_id)

(2)

CDM (charged device model)

(4)

(3)

1000 V

500 200 mA

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The supply voltages and power consumption estimates are detailed in Table 3-2.

Table 3-2. Estimated Power Consumption at Ball Level

SIGNAL NAME DESCRIPTION

VDD_CORE 1.2-V core and oscillator macros power supply 1500 mA VDDS_SRAM_MPU 1.8-V MPU SLDO analog power supply 40 mA VDDS_SRAM_CORE_BG 1.8-V Core SLDO and VDDA of BandGap analog power supply 40 mA VDDS_DPLL_MPU_USBHOST 1.8-V MPUSS DPLL and USBHOST DPLL analog power supply 25 mA VDDS_DPLL_PER_CORE 1.8-V DPLL and HSDIVIDER/ CORE and HSDIVIDER analog power supply 25 mA VDDA_DAC 1.8-V DAC analog power supply 65 mA VDDA3P3V_USBPHY 3.3-V USB transceiver analog power supply 10 mA VDDA1P8V_USBPHY 1.8-V USB transceiver power supply 50 mA VDDSHV 3.3-/1.8--V power supply 300 mA VDDS 1.8-V power supply 200 mA VDDSOSC 1.8-V oscillator power supply 20 mA

MAX CURRENT

(mA)

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3.2 Recommended Operating Conditions

All AM3517/05 modules are used under the operating conditions contained in Table 3-3. Note: Logic functions and parameter values are not assured if the device is operated out of the range

specified in the recommended operating conditions.

Table 3-3. Recommended Operating Conditions

PARAMETER DESCRIPTION MIN NOM MAX UNIT

VDD_CORE Core and oscillator macros power supply 1.152 1.20 1.248 V

Noise (peak-peak) 24.00 mVpp

VDDS_SRAM_ MPU SRAM LDO analog power supply 1.71 1.80 1.89 V MPU

VDDS_SRAM_ Core SRAM LDO and BandGap analog power 1.71 1.80 1.89 V CORE_BG supply

VDDS_DPLL_ MPU and USBHOST DPLL analog power supply 1.71 1.80 1.89 V MPU_ USBHOST

VDDS_DPLL_ Peripherals and Core DPLLs analog power supply 1.71 1.80 1.89 V PER_CORE

VDDA_DAC DAC analog power supply 1.71 1.80 1.89 V

VSSA_DAC DAC analog ground 0.00 V VDDA3P3V_ Analog power supply for 3.3-V USB transceiver 3.14 3.30 3.47 V

USBPHY VDDA1P8V_ Power Supply for 1.8-V USB transceiver 1.71 1.80 1.89 V

USBPHY VDDSHV 3.3-/1.8-V power supply 1.8 V Mode 1.71 1.80 1.89 V

VDDS 1.8-V power supply 1.71 1.80 1.89 V Tj Operating junction temperature Commercial 0 90 °C

Device 500 MHz ARM Clock Freq. < 90°C T Operating Life Power-On Hours (POH)

(1) The POH information is provided solely for your convenience and does not extend or modify the warranty provided under TI’s standard

terms and conditions for TI semiconductor products.

(2) Maximum lifetime will be 100k Power On Hours as long as no more than 50k is greater than 90°C.

Noise (peak-peak) 50.00 mVpp

Noise (peak-peak) 35.00 mVpp

Noise (peak-peak) 30.00 mVpp

Noise (peak-peak) 70.00 mVpp

Noise (peak-peak) 50.00 mVpp

3.3 V Mode 3.14 3.30 3.47 V

range Temperature

Extended -40 105 °C Temperature

100K hrs. 100K 100K

(2)

50K

(1)

600 MHz ARM Clock Freq. < 90°C T

90 - 105 °C T

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MPU

Core

Periph1

vdd_core domain

DPLL_MPU

LDO

in 1.8 V

out 1.2 V

Dual Video DAC

SRAM2 ARRAY

SRAM 2 LDO

0 V/1.0 V/1.2 V

SRAM1 ARRAY

SRAM 1 LDO

0 V/1.0 V/1.2 V

DPLL_CORE

LDO

in 1.8 V

out 1.2 V

DPLL4

LDO

in 1.8 V

out 1.2 V

LDO3

1.0 V/1.2 V

vdds

Periph2

DPLL5

LDO

in 1.8 V

out 1.2 V

BandGap

BCK MEM

vss

DLL/DCDL

HSDIVIDER

LDO

HSDIVIDER

LDO

cap_vdd_sram_core

tv_ref

(for capacitor)

vssa_dac

vdds_dpll_mpu_usbhost

vddshv

Device

vdd_core

vdds_dpll_per_core

vdda_dac

030-003

VDDSHV

VDDS

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The following diagram illustrates the power domains:

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Figure 3-1. AM3517/05 Voltage Domains

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3.3 DC Electrical Characteristics

summarizes the dc electrical characteristics.

Table 3-4. DC Electrical Characteristics

PARAMETER MIN NOM MAX UNIT

LVCMOS Pin Buffers

Capacitan Input capacitance 3 pF ce (dual-voltage LVCMOS I/Os)

(2)

(1) These IO specifications apply to the dual-voltage IOs only and do not apply to the DDR2/mDDR interfaces. DDR2/mDDR IOs are 1.8V (2) These parameters must adhere to the requirements defined in section 7.1.7.2 of Universal Serial Bus Specifications revision 2.0.

High-level input voltage 0.65 x V

VDDSHV = 1.8 V

VDDSHV = 3.3 V

(1)

VDDSHV. 2

sys_xtalin 0.8 x VDDOSC

Low-level input voltage 0.35 x V

VDDSHV = 1.8 V

VDDSHV = 3.3 V

(1)

sys_xtalin 0.2 x VDDOSC

High-level output voltage VDDSHV - V

VDDSHV = 1.8 V

VDDSHV = 3.3 V

Low-level output voltage 0.45 V

VDDSHV = 1.8 V VDDSHV = 3.3 V

Input transition time (rise time, tR or fall VDDSHV = 1.8 Normal mode 10 ns time, tF evaluated between 10% and 90% at PAD)

(1)

V VDDSHV = 3.3 Normal mode 10

(1)

0.45

(1)

2.4

High-speed mode 3

Output capacitance 3 pF (dual-voltage LVCMOS I/Os)

Complex IO Dedicated to USB : USB0_DM and USB0_DP

High-level input voltage Low/Full speed 2.0 V

High speed

Low-level input voltage Low/Full speed 0.8 V

High speed

High-level output voltage Low/Full speed 2.8 VDDA3P3V_ V

High speed 360 440 mV

Low-level output voltage Low/Full speed 0.0 0.3 V

High speed -10 10 mV

IOs and adhere to the JESD79-2A standard.

VDDSHV

0.8

0.4

(2)

USBPHY

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3.4 Core Voltage Decoupling

For module performance, decoupling capacitors are required to suppress the switching noise generated by high frequency and to stabilize the supply voltage. A decoupling capacitor is most effective when it is close to the device because this minimizes the inductance of the circuit board wiring and interconnects.

Table 3-5 summarizes the power supplies decoupling characteristics.

Table 3-5. Core Voltage Decoupling Characteristics

PARAMETER MIN TYP MAX UNIT

Cvdd_core Ccap_vdd_sram_core 100 nF Cvdds_dpll_mpu_usbhost 100 nF Cvdds_dpll_per_core 100 nF Cvdda_dac 100 nF Cvdd_sram_core 100 nF Cvdd_sram_core_bg 100 nF Cvdds_sram_mpu 100 nF Cvddshv 100 nF Cvdda3p3v_usbphy 100 nF Cvdda1p8v_usbphy 100 nF

(1) 1 capacitor per 2 to 4 balls

(1)

50 100 120 nF

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SRAM_LDO1

SRAM_LDO2

WKUP_LDO

DPLL_MPU

DPLL_CORE

vdds_dpll_mpu _usbhost

vdds_sram_mpu

DPLL5

DPLL4

vdds_dpll_per_core

Video DAC

vdda_dac

Device

VSS

vssa_dac

Cvdds_sram_mpu

vdds_sram_core_bg

Ccap_vdd_sram_core

Cvdds_dpll_mpu_usbhost

Cvdds_dpll_per_core

Cvdda_dac

vdda_dac

vdds_dpll_per_core

vdds_dpll_mpu_usbhost

Core

vdd_core

Cvdd_core

Vdd_core

030-004

MPU

Cvdds_sram_core_bg

Cvdd_sram_core

cap_vdd_sram_mpu

Ccap_vdd_sram_mpu

vdd_sram_core

cap_vdd_sram _core

vdds_sram_mpu

vdd_sram_core

vdds_sram_core_bg

AM3517, AM3505

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The following illustrates an example of power supply decoupling.

SPRS550B–OCTOBER 2009–REVISED JULY 2010

(1) Decoupling capacitors must be placed as closed as possible to the power ball. Choose the ground located closest to the power pin

for each decoupling capacitor. Place the decoupling capacitor Ci in a group of 1, 2, or 3 balls; the total must be equal to the decoupling requirement. In case you interconnect powers, first insert the decoupling capacitor and then interconnect the powers.

(2) The decoupling capacitor value depends on the board characteristics.

Figure 3-2. Power Supply Decoupling

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3.5 Power-up and Power-down

This section provides the timing requirements for the AM3517/05 hardware signals.

3.5.1 Power-up Sequence

The following steps give an example of power-up sequence supported by the AM3517/05 .

1. IO 1.8V supply (VDDS), Band-gap and LDO supplies (VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU) and oscillator supply (VDDSOSC) should come up first to a stable state.

2. IO 3.3V (VDDSHV) supply should be ramped up next to a stable state.

3. Core (VDD_CORE) supply follows next to a stable state.

4. All the PLL supplies (VDDS_DPLL_PER_CORE, VDDS_DPLL_MPU_USBHOST) and 1.8 V complex IO supplies (VDDA_DAC, VDDA1P8V_USBPHY) should be ramped up next to a stable state.

5. Finally, 3.3 V complex IO (VDDA_3P3V_USBPHY) should be ramped up.

6. sys_nrespwron must be held low at the time the power supplies are ramped up till the time the sys_32k and sys_xtalin clocks are stable.

Note: In VDDSHV 1.8 V operation mode, VDDSHV can be grouped and powered up together with VDDS, VDDS_SRAM_CORE_BG, VDDS_SRAM_MPU and VDDSOSC.

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VDDS, VDDS_SRAM_CORE_BG

VDDS_SRAM_MPU

VDDSOSC

1.8V

VDDSHV

3.3V

1.2V

VDD_CORE

VDDS_DPLL_PER_CORE

VDDS_DPLL_MPU_USBHOST,

VDDA_DAC,

VDDA1P8V_USBPHY

1.8V

VDDA3P3V_USBPHY

3.3V

sys_nrespwron

sys_32k

sys_xtalin

AM3517, AM3505

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Figure 3-3 shows the power-up sequence.

SPRS550B–OCTOBER 2009–REVISED JULY 2010

Figure 3-3. Power-up Sequence

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3.5.2 Power-down Sequence

The AM3517/05 device proceeds with the power-down sequence shown below.

The following steps give an example of the power-down sequence supported by the AM3517/05 device.

1. Reset AM3517/05 device.

2. Stop all signals driven to AM3517/05 .

3. Option 1: Power down all domains simutaneously.

4. Option 2: If all domains cannot be powered down simultaneously, follow the below sequence: (a) Power off all complex I/O domains

(b) Power off core domain (VDD_CORE) (c) Power off all PLL domains (VDDS_DPLL_MPU_USBHOST and VDDS_DPLL_PER_CORE) (d) Power off all SRAM LDOs (e) Power off all standard I/O domains (VDDS and VDDSHV)

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AM35x

Power IC

sys_32k

sys_altclk

sys_clkout1

Alternate Clock Source Selectable (54, 48 MHz or other [up to 59 MHz])

To Quartz (Oscillator output) or Unconnected

From Quartz (Oscillator input), Square Clock, or Crystal

Clock Request. To Square Clock Source or from Peripherals

Oscillator

is Used

Oscillator

is Bypassed

Unconnected

Square

Clock

Source

To Peripherals (From OSC_CLK: 26 MHz, core_clk [DPLL, up to 166 MHz], DPLL-96 MHZ or DPLL-54 MHz outputs with a divider of 1, 2, 4, 8, or 16)

GPin

To Peripherals (From OSC_CLK: 26 MHz)

sys_clkout2

sys_xtalout

sys_xtalin

sys_clkreq

sys_xtalout

sys_xtalin

sys_clkreq

sys_xtalout

sys_xtalin

sys_clkreq

030-007

Ethernet input 50-MHz clock

rmii_50mhz_clk

AM3517, AM3505

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4 CLOCK SPECIFICATIONS

The AM3517/05 device has three external input clocks, a low frequency (sys_32k), a high frequency (sys_xtalin), and an optional (sys_altclk). The AM3517/05 device has two configurable output clocks, sys_clkout1 and sys_clkout2.

Figure 4-1 shows the interface to the external clock sources and clock outputs.

SPRS550B–OCTOBER 2009–REVISED JULY 2010

Figure 4-1. Clock Interface

The AM3517/05 device operation requires the following three input clocks:

• The 32-kHz clock can be generated using one of the following options and can be selected via the sys_boot7 pin. See Figure 4-2.

– External: Supplied by an oscillator on the sys_32k pin. – Internal: 32-kHz clock generation using a fixed divider on the HS system clock (26MHz).

• The system alternative clock can be used (through the sys_altclk pin) to provide alternative 48 or 54 MHz or other clock source (up to 54 MHz).

• The system clock input (26 MHz) is used to generate the main source clock of the AM3517/05 device. It supplies the DPLLs as well as several AM3517/05 modules. The system clock input can be connected to either:

– A crystal oscillator clock managed by sys_xtalin and sys_xtalout. In this case, the sys_clkreq is

used as an input (GPIN).

– A CMOS digital clock through the sys_xtalin pin. In this case, the sys_clkreq is used as an output to

request the external system clock.

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Sys_32k_in

32.5 kHz

Fixed

Divider

/800

Latch

Sys_clk=

26 MHz

JTAG Overrides

for DFT

Sys_clk

PowerOn Reset

Sys_32k

Sys_xtalin

Sys_xtalout

Sys_boot7

AM3517, AM3505

SPRS550B–OCTOBER 2009–REVISED JULY 2010

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Figure 4-2. 32-kHz Clock Generation

The AM3517/05 outputs externally two clocks:

• sys_clkout1 can output the oscillator clock (26 MHz) at any time.

• sys_clkout2 can output the oscillator clock, core_clk, 96 MHz or 54 MHz. It can be divided by 2, 4, 8, or 16 and its off state polarity is programmable.

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C1 C2

sys_xtalin

sys_xtalout VSSOSC

Crystal 26 MHz

AM3517, AM3505

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4.1 Oscillator

The sys_xtalin (26 MHz) oscillator provides the primary reference clock for the AM3517 device. The on-chip oscillator requires an external crystal connected across the sys_xtalin and sys_xtalout pins, along with two load capacitors, as shown in Figure 4-3. The external crystal load capacitors must be connected only to the oscillator ground pin (VSSOSC). Do not connect to board ground (VSS).

Note: If an external oscillator is to be used, the external oscillator clock signal should be connected to the sys_xtalin pin with a 1.8V amplitude. The sys_xtalout should be left unconnected and the VSSOSC signal should be connected to board ground (VSS).

SPRS550B–OCTOBER 2009–REVISED JULY 2010

Figure 4-3. AM3517/05 Oscillator Connections

The load capacitors, C1 and C2, should be chosen such that the equation is satisfied (typical values are C1 = C2 = 10 pF). CL in the equation is the load specified by the crystal manufacturer. All discrete components used to implement the oscillator circuit should be placed as close as possible to the associated oscillator pins (sys_xtalin and sys_xtalout) and to the VSS pin.

CL= C1C2/ (C1+ C2) (1)

Table 4-1. Crystal Electrical Characteristics

PARAMETER MIN TYP MAX UNIT

Oscillation frequency 26 MHz Crystal ESR 50 Ω Frequency stability +/- 50 ppm Parallel Load Capacitance 20 pF

(C1 and C2) Shunt Capacitance 5 pF

4.2 Input Clock Specifications

The clock system accepts three input clock sources:

• 32-kHz digital CMOS clock

• Crystal oscillator clock or CMOS digital clock (26 MHz)

• Alternate clock (48 or 54 MHz, or other up to 54 MHz)

PARAMETER DESCRIPTION MIN TYP MAX UNIT

f(xtalin) Frequency, sys_xtalin 26 MHz tw(xtalin) Duty Cycle, 45 55 %

tj(xtalin) Jitter, sys_xtalin -1 1 %

Table 4-2. 26Mhz sys_clk Input Clock Timing Requirements

sys_xtalin

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Table 4-2. 26Mhz sys_clk Input Clock Timing Requirements (continued)

PARAMETER DESCRIPTION MIN TYP MAX UNIT

tt(xtalin) Transition time, 5 ns

sys_xtalin

Table 4-3. 32-kHz Input Clock Source Electrical Characteristics

PARAMET DESCRIPTION MIN TYP MAX UNIT

f Frequency, sys_32k 32.768 kHz C

Input capacitance 0.45 pF Input resistance 0.25 10

GΩ

Table 4-4 details the input requirements of the 32-kHz input clock.

Table 4-4. 32-kHz Input Clock Source Timing Requirements

PARAMETE DESCRIPTION MIN TYP MAX UNIT

1 / t

c(32k)

R(32k)

F(32k)

J(32k)

(1) See Electrical Characteristics for Standard LVCMOS IOs part for sys_32k VIH/VILparameters.

Frequency, sys_32k 32 kHz Rise transition time, sys_32k 20 ns Fall transition time, sys_32k 20 ns Frequency stability, sys_32k +/-200 ppm

(1)

Table 4-5. 48-MHz, 54-MHz, or up to 59-MHz Input Clock Source Electrical Characteristics

NAME DESCRIPTION MIN MAX UNIT

f Frequency , sys_altclk 48, 54, or up to 59 MHz C

Input capacitance 0.74 pF Input resistance 0.25 10

GΩ

Table 4-6 details the input requirements of the 48- or 54-MHz input clock.

Table 4-6. 48-MHz, 54-MHz, or up to 59-MHz Input Clock Source Timing Requirements

PARAMETER DESCRIPTION MIN MAX UNIT

1 / t

c(sys_altclk)

w(sys_altclk)

j(sys_altclk)

r(sys_altclk)

f(sys_altclk)

t(sys_altclk)

(1) Peak-to-peak jitter is defined as the difference between the maximum and the minimum output periods on a statistical population of 300

period samples. The sinusoidal noise is added on top of the vdds supply voltage.

(2) See , Electrical Characteristics, for sys_altclk VIH/VILparameters.

Frequency, sys_altclk 48, 54, or up to 59 MHz Duty cycle 45 60 % Jitter -1 1 % Rise transition time 10 ns Fall transition time 10 ns Frequency tolerance -50 50 ppm

(1) (2)

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sys_clkout1

CO0 CO1 CO1

030-014

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4.3 Output Clock Specifications

Two output clocks (pin sys_clkout1 and pin sys_clkout2) are available:

• sys_clkout1 can output the oscillator clock (26 MHz) at any time. It can be controlled by software or externally using sys_clkreq control. When the device is in the off state, the sys_clkreq can be asserted to enable the oscillator and activate the sys_clkout1 without waking up the device. The off state polarity of sys_clkout1 is programmable.

• sys_clkout2 can output sys_clk (26 MHz), core_clk (core DPLL output), APLL-96 MHz, or APLL-54 MHz. It can be divided by 2, 4, 8, or 16 and its off state polarity is programmable. This output is active only when the core domain is active.

Table 4-7 summarizes the sys_clkout1 output clock electrical characteristics.

Table 4-7. sys_clkout1 Output Clock Electrical Characteristics

NAME DESCRIPTION MIN TYP MAX UNIT

f Frequency 26 MHz C

(1) The load capacitance is adapted to a frequency.

Load capacitance

Table 4-8 details the sys_clkout1 output clock timing characteristics.

(1)

f(max) = 38.4 MHz 70 pF f(max) = 26 MHz 125

Table 4-8. sys_clkout1 Output Clock Switching Characteristics

NAME DESCRIPTION MIN TYP MAX UNIT

f 1 / CO0 Frequency 26 MHz CO1 t

CO2 t CO3 t

(1) With a load capacitance of 25 pF.

w(CLKOUT1)

R(CLKOUT1) F(CLKOUT1)

Pulse duration, sys_clkout1 low or high 0.40 * 0.60 * ns

Rise time, sys_clkout1 Fall time, sys_clkout1

(1)

c(CLKOUT1)

3.31 ns

Figure 4-4. sys_clkout1 System Output Clock

Table 4-9 summarizes the sys_clkout2 output clock electrical characteristics.

Table 4-9. sys_clkout2 Output Clock Electrical Characteristics

NAME DESCRIPTION MIN TYP MAX UNIT

f Frequency, sys_clkout2 C

(1) The maximum frequency supported is core_clk/2 MHz. (2) The load capacitance is adapted to a frequency.

Load capacitance

(1)

(2)

f(max) = 166 MHz 2 8 12 pF

166 MHz

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sys_clkout2

CO0 CO1 CO1

030-015

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Table 4-10 details the sys_clkout2 output clock timing characteristics.

Table 4-10. sys_clkout2 Output Clock Switching Characteristics

NAME DESCRIPTION MIN TYP MAX UNIT

f 1 / CO0 Frequency 166 MHz CO1 t CO2 t CO3 t

w(CLKOUT2) R(CLKOUT2) F(CLKOUT2)

Pulse duration, sys_clkout2 low or high 0.40 * tc(CLKOUT2) 0.60 * tc(CLKOUT2) ns Rise time, sys_clkout2 Fall time, sys_clkout2

(1)

3.7 ns

4.3 ns

(1) With a load capacitance of 25 pF.

Figure 4-5. sys_clkout2 System Output Clock

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Device

VDDS_DPLL_MPU_USBHOST

Power Rail

DPLL4

DPLL1

DPLL3

VDDS_DPLL_PER_CORE

DPLL5

030-016

AM3517, AM3505

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4.4 DPLL Specifications

The AM3517/05 integrates four DPLLs. The PRM and CM drive them. The four main DPLLs are:

• DPLL1 (MPU)

• DPLL3 (Core)

• DPLL4 (Peripherals)

• DPLL5 (Second Peripherals DPLL)

Figure 4-6 illustrates the DPLL implementation.

SPRS550B–OCTOBER 2009–REVISED JULY 2010

4.4.1 Digital Phase-Locked Loop (DPLL)

The DPLL provides all interface clocks and some functional clocks (such as the processor clocks) of the AM3517/05 device.

DPLL1 gets an always-on clock used to produce the synthesized clock. They get a high-speed bypass clock used to switch the DPLL output clock on this high-speed clock during bypass mode.

The high-speed bypass clock is an L3 divided clock (programmable by 1 or 2) that saves DPLL processor power consumption when the processor does not need to run faster than the L3 clock speed, or optimizes performance during frequency scaling.

Each DPLL synthesized frequency is set by programming M (multiplier) and N (divider) factors. In addition, all DPLL outputs can be controlled by an independent divider (M2 to M6).

The clock generating DPLLs of the AM3517/05 device have following features:

• Independent power domain per DPLL

• Controlled by clock-manager (CM)

• Fed with always-on system clock with independent gating control per DPLL

• Analog part supplied through dedicated power supply (1.8 V) and an embedded LDO to get rid of 1-MHz noise

• Up to four independent output dividers for simultaneous generation of multiple clock frequencies

Figure 4-6. DPLL Implementation

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4.4.1.1 DPLL1 (MPU)

DPLL1 is located in the MPU subsystem and supplies all clocks of the subsystem. All MPU subsystem clocks are internally generated in the subsystem. When the core domain is on, it can use the DPLL3 (CORE DPLL) output as a high-frequency bypass input clock.

4.4.1.2 DPLL3 (CORE)

DPLL3 supplies all interface clocks and also a few module functional clocks. It can be also source of the emulation trace clock. It is located in the core domain area. All interface clocks and a few module functional clocks are generated in the CM. When the core domain is on, it can be used as a bypass input to DPLL1.

4.4.1.3 DPLL4 (Peripherals)

DPLL4 generates clocks for the peripherals. It supplies five clock sources: 96-MHz functional clocks to subsystems and peripherals , 54 MHz to TV DAC, display functional clock, camera sensor clock, and emulation trace clock. It is located in the core domain area. All interface clocks and few module functional clocks are generated in the CM. Its outputs to the DSS, PER, and EMU domains are propagated with always-on clock trees.

4.4.1.4 DPLL5 (Second peripherals DPLL)

DPLL5 supplies the 120-MHz functional clock to the CM.

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DPLL_MPU

DPLL_CORE

DLL

DPLL5

DPLL4

VDDS_DPLL_MPU_USBHOST

VDDS_DPLL_PER_CORE

Noise Filter

030-017

AM3517, AM3505

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4.4.2 DPLL Noise Isolation

The DPLL requires dedicated power supply pins to isolate the core analog circuit from the switching noise generated by the core logic that can cause jitter on the clock output signal. Guard rings are added to the cell to isolate it from substrate noise injection.

The vdd supplies are the most sensitive to noise; decoupling capacitance is recommended below the supply rails. The maximum input noise level allowed is 30 mVPPfor frequencies below 1 MHz.

Figure 4-7 illustrates an example of a noise filter.

SPRS550B–OCTOBER 2009–REVISED JULY 2010

Figure 4-7. DPLL Noise Filter

Table 4-11 specifies the noise filter requirements.

Table 4-11. DPLL Noise Filter Requirements

NAME MIN TYP MAX UNIT

Filtering capacitor 100 nF (1) The capacitors must be inserted between power and ground as close as possible. (2) This circuit is provided only as an example. (3) The filter must be located as close as possible to the device. (4) No filtering required if noise is below 10 mVPP.

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Device

DSS

tv_vref

DIN1[9:0]

vssa_dacvdda_dac

Video DAC 1

TV DCT

Video DAC 2

TVOUT

BUFFER

DIN2[9:0]

TVOUT

BUFFER

TVOUT

BUFFER

tv_vfb1

tv_out1

CBG

tv_out2

tv_vfb2

V_ref

030-018

OUT1

OUT2

AM3517, AM3505

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5 VIDEO DAC SPECIFICATIONS

A dual-display interface equips the AM3517/05 processor. This display subsystem provides the necessary control signals to interface the memory frame buffer directly to the external displays (TV-set). Two (one per channel) 10-bit current steering DACs are inserted between the DSS and the TV set to generate the video analog signal. One of the video DACs also includes TV detection and power-down mode. Figure 5-1 illustrates the AM3517/05 DAC architecture.

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Figure 5-1. Video DAC Architecture

The following paragraphs detail the 10-bit DAC interface pinout, static and dynamic specifications, and noise requirements. The operating conditions and absolute maximum ratings are detailed in Table 5-2 and

Table 5-4.

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Texas instruments AM3517, AM3505 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 AM3517/05 ARM Microprocessor

1.1 Features

1.2 Description

1.3 Functional Block Diagram

1.4 ZCN and ZER Package Differences

Revision History

2 TERMINAL DESCRIPTION

2.1 Pin Assignments

2.1.1 Pin Map (Top View)

2.2 Ball Characteristics

2.3 Multiplexing Characteristics

2.4 Signal Description

2.4.1 External Memory Interfaces

2.4.2 Video Interfaces

2.4.3 Serial Communication Interfaces

2.4.4 Removable Media Interfaces

2.4.5 Test Interfaces

2.4.6 Miscellaneous

2.4.7 General-Purpose IOs

2.4.8 System and Miscellaneous Terminals

2.4.9 Power Supplies

3 ELECTRICAL CHARACTERISTICS

3.1 Absolute Maximum Ratings

3.2 Recommended Operating Conditions

3.3 DC Electrical Characteristics

3.4 Core Voltage Decoupling

3.5 Power-up and Power-down

3.5.1 Power-up Sequence

3.5.2 Power-down Sequence

4 CLOCK SPECIFICATIONS

4.1 Oscillator

4.2 Input Clock Specifications

4.3 Output Clock Specifications

4.4 DPLL Specifications

4.4.1 Digital Phase-Locked Loop (DPLL)

4.4.1.1 DPLL1 (MPU)

4.4.1.2 DPLL3 (CORE)

4.4.1.3 DPLL4 (Peripherals)

4.4.1.4 DPLL5 (Second peripherals DPLL)

4.4.2 DPLL Noise Isolation

5 VIDEO DAC SPECIFICATIONS