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AM1806 ARM®Microprocessor

1 AM1806 ARM Microprocessor

1.1 Features

1

• 375- and 456-MHz ARM926EJ-S™ RISC MPU

• Enhanced Direct Memory Access Controller 3 (EDMA3):

– 2 Channel Controllers – 3 Transfer Controllers – 64 Independent DMA Channels – 16 Quick DMA Channels – Programmable Transfer Burst Size

• 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces)

• Two External Memory Interfaces: – EMIFA

• NOR (8- or 16-Bit-Wide Data)

• NAND (8- or 16-Bit-Wide Data)

• 16-Bit SDRAM with 128-MB Address Space

– DDR2/Mobile DDR Memory Controller with one

of the following:

• 16-Bit DDR2 SDRAM with 256-MB Address Space

• 16-Bit mDDR SDRAM with 256-MB Address Space

• Three Configurable 16550-Type UART Modules: – With Modem Control Signals – 16-Byte FIFO – 16x or 13x Oversampling Option

• LCD Controller

• Two Serial Peripheral Interfaces (SPIs) Each with Multiple Chip Selects

• Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces with Secure Data I/O (SDIO) Interfaces

• Two Master and Slave Inter-Integrated Circuits ( I2C Bus™)

• One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address and Data Bus For High Bandwidth

• Programmable Real-Time Unit Subsystem (PRUSS)

– Two Independent Programmable Real-Time Unit

(PRU) Cores

• 32-Bit Load-Store RISC Architecture

• 4KB of Instruction RAM per Core

• 512 Bytes of Data RAM per Core

• PRUSS can be Disabled via Software to Save Power

• Register 30 of Each PRU is Exported from

1

the Subsystem in Addition to the Normal R31

AM1806

SPRS658F –FEBRUARY 2010–REVISED MARCH 2014

Output of the PRU Cores.

– Standard Power-Management Mechanism

• Clock Gating

• Entire Subsystem Under a Single PSC Clock Gating Domain

– Dedicated Interrupt Controller – Dedicated Switched Central Resource

• USB 2.0 OTG Port with Integrated PHY (USB0) – USB 2.0 High- and Full-Speed Client – USB 2.0 High-, Full-, and Low-Speed Host – End Point 0 (Control) – End Points 1,2,3,4 (Control, Bulk, Interrupt or

ISOC) RX and TX

• One Multichannel Audio Serial Port (McASP): – Transmit and Receive Clocks – Two Clock Zones and 16 Serial Data Pins – Supports TDM, I2S, and Similar Formats – DIT-Capable – FIFO Buffers for Transmit and Receive

• Two Multichannel Buffered Serial Ports (McBSPs): – Transmit and Receive Clocks – Supports TDM, I2S, and Similar Formats – AC97 Audio Codec Interface – Telecom Interfaces (ST-Bus, H100) – 128-Channel TDM – FIFO Buffers for Transmit and Receive

• Video Port Interface (VPIF): – Two 8-Bit SD (BT.656), Single 16-Bit or Single

Raw (8-, 10-, and 12-Bit) Video Capture Channels

– Two 8-Bit SD (BT.656), Single 16-Bit Video

Display Channels

• Universal Parallel Port (uPP): – High-Speed Parallel Interface to FPGAs and

Data Converters

– Data Width on Both Channels is 8- to 16-Bit

Inclusive – Single-Data Rate or Dual-Data Rate Transfers – Supports Multiple Interfaces with START,

ENABLE, and WAIT Controls

• Real-Time Clock (RTC) with 32-kHz Oscillator and Separate Power Rail

• Three 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)

• One 64-Bit General-Purpose or Watchdog Timer (Configurable as Two 32-Bit General-Purpose

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Timers) • Three 32-Bit Enhanced Capture (eCAP) Modules:

• Two Enhanced High-Resolution Pulse Width – Configurable as 3 Capture Inputs or 3 Auxiliary Modulators (eHRPWMs): Pulse Width Modulator (APWM) Outputs

– Dedicated 16-Bit Time-Base Counter with – Single-Shot Capture of up to Four Event Time-

Period and Frequency Control Stamps

– 6 Single-Edge Outputs, 6 Dual-Edge Symmetric • 361-Ball Pb-Free Plastic Ball Grid Array (PBGA)

Outputs, or 3 Dual-Edge Asymmetric Outputs [ZCE Suffix], 0.65-mm Ball Pitch – Dead-Band Generation • 361-Ball Pb-Free PBGA [ZWT Suffix], 0.80-mm – PWM Chopping by High-Frequency Carrier – Trip Zone Input

Ball Pitch

• Commercial or Extended Temperature

1.2 Applications

• Gaming • Data Concentrators

• Medical, Healthcare, Fitness • Building Automation

• Printers • Set Top Box

• ePOS • Industrial Automation

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1.3 Description

The AM1806 ARM Microprocessor is a low-power applications processor based on ARM926EJ-S. The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs)

to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core has a coprocessor 15 (CP15), protection module, and data and program memory management units (MMUs) with table look-aside buffers. The ARM core processor has separate 16-KB instruction and 16-KB data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has 8KB of RAM (Vector Table) and 64KB of ROM.

The peripheral set includes: one USB2.0 OTG interface; two inter-integrated circuit (I2C Bus) interfaces; one multichannel audio serial port (McASP) with 16 serializers and FIFO buffers; two multichannel buffered serial ports (McBSPs) with FIFO buffers; two serial peripheral interfaces (SPIs) with multiple chip selects; four 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI); up to 9 banks of general-purpose input/output (GPIO) pins, with each bank containing 16 pins with programmable interrupt and event generation modes, multiplexed with other peripherals; three UART interfaces (each with RTS and CTS); two enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two external memory interfaces; an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals; and a higher speed DDR2/Mobile DDR controller.

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SPRS658F –FEBRUARY 2010–REVISED MARCH 2014

The universal parallel port (uPP) provides a high-speed interface to many types of data converters, FPGAs or other parallel devices. The uPP supports programmable data widths between 8- to 16-bits on both channels. Single-data rate and double-data rate transfers are supported as well as START, ENABLE, and WAIT signals to provide control for a variety of data converters.

A video port interface (VPIF) is included providing a flexible video I/O port. The rich peripheral set provides the ability to control external peripheral devices and communicate with

external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides.

The device has a complete set of development tools for the ARM processor. These tools include C compilers, and scheduling, and a Windows®debugger interface for visibility into source code execution.

Device Information

PART NUMBER PACKAGE BODY SIZE

AM1806ZCE NFBGA (361) 13,00 mm x 13,00 mm AM1806ZWT NFBGA (361) 16,00 mm x 16,00 mm

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Switched Central Resource (SCR)

16KB

I-Cache

16KB

D-Cache

4KB ETB

ARM926EJ-S CPU

With MMU

ARM Subsystem

JTAG Interface

System Control

Input

Clock(s)

64KB ROM

8KB RAM

(Vector Table)

Power/Sleep

Controller

Multiplexing

PLL/Clock Generator

w/OSC

GeneralPurpose

Timer (x3)

Serial Interfaces

Audio Ports

McASP w/FIFO

DMA

Peripherals

Display Internal Memory

LCD

Ctlr

128KB

RAM

External Memory InterfacesConnectivity

EDMA3

(x2)

Control Timers

ePWM

(x2)

eCAP

(x3)

EMIFA(8b/16B)

NAND/Flash 16b SDRAM

DDR2/MDDR

Controller

RTC/

32-kHz

OSC

I C

(x2)

2

SPI (x2)

UART

(x3)

McBSP

(x2)

Video

VPIF

Parallel Port

uPP

USB2.0

OTG Ctlr

PHY

HPI

MMC/SD

(8b) (x2)

Customizable Interface

PRU Subsystem

Memory

Protection

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SPRS658F –FEBRUARY 2010–REVISED MARCH 2014

1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the device.

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(1) Note: Not all peripherals are available at the same time due to multiplexing.

Figure 1-1. Functional Block Diagram

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2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This data manual revision history highlights the changes made to the SPRS658E device-specific data manual to make it an SPRS658F revision.

SEE ADDITIONS/MODIFICATIONS/DELETIONS

• Moved Trademarks information from first page to within Section 7, Device and Documentation

Global

Section 1.3

Description

Section 3.7

Terminal Functions

Section 3.7.17

Universal Serial Bus Modules (USB0)

Section 3.8

Unused Pin Configurations

Section 5

Specifications

Section 5.4

Notes on Recommended Power-On Hours

Section 6.10.5 • Added vertical lines to show difference between Setup, Strobe, and Hold

EMIFA Electrical/Timing Figure 6-13, Asynchronous Memory Write Timing for EMIFA:

Section 7.1.2

Device and DevelopmentSupport Tool Nomenclature

Section 7.6

Glossary

Support.

• Moved ESDS Warning to within Section 7, Device and Documentation Support.

• Updated Features, Applications, and Description for consistency and translation. Added NEW Device Information Table.

Table 3-3 thru Table 3-25:

• Updated/Changed footnote beginning with "IPD = Internal Pulldown resistor..."; added sentence "For more detailed information on pullup/pulldown..."

Table 3-19, Universal Serial Bus (USB) Terminal Functions

• Updated/Changed the capacitor value in USB0_VDDA12 pin DESCRIPTION from "1 μF" to "0.22-μF"

Table 3-28, Unused USB0 Signal Configurations:

• Updated/Changed USB0_VDDA12 row text from "No Connect" to "...to an external 0.22-μF filter capacitor"

Updated/Changed title from "Device Operating Conditions" to "Specifications"

Section 5.2, Handling Ratings:

• Split handling, ratings, and certifications from the Abs Max table and placed in NEW Handling Ratings table.

Table 5-1, Recommended Power-On Hours:

• Updated/Changed all applicable Silicon Revisions from "B" to "B/E"

Figure 6-12, Asynchronous Memory Read Timing for EMIFA:

• Added vertical lines to show difference between Setup, Strobe, and Hold

Figure 7-1, Device Nomenclature:

• Added "E = Silicon Revision 2.3" under SILICON REVISION

Added NEW section.

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Revision History

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3 Device Overview

3.1 Device Characteristics

Table 3-1 provides an overview of the device. The table shows significant features of the device, including

the capacity of on-chip RAM, peripherals, and the package type with pin count.

Table 3-1. Characteristics of the Device

HARDWARE FEATURES AM1806

DDR2/mDDR Controller

EMIFA Flash Card Interface MMC and SD cards supported EDMA3

Timers

Peripherals Not all peripherals pins

are available at the same time (for more detail, see the Device Configurations section).

On-Chip Memory

JTAG BSDL_ID DEVIDR0 Register 0x0B7D_102F CPU Frequency MHz ARM926 375 MHz (1.2V) or 456 MHz (1.3V)

Voltage

Packages

Product Status

(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(1)

UART 3 (each with RTS and CTS flow control) SPI 2 (Each with one hardware chip select) I2C 2 (both Master/Slave) Multichannel Audio Serial Port [McASP] 1 (each with transmit/receive, FIFO buffer, 16 serializers) Multichannel Buffered Serial Port [McBSP] 2 (each with transmit/receive, FIFO buffer, 16)

eHRPWM USB 2.0 (USB0) High-Speed OTG Controller with on-chip OTG PHY

General-Purpose Input/Output Port 9 banks of 16-bit LCD Controller 1 Universal Parallel Port (uPP) 1 Video Port Interface (VPIF) 1 (video in and video out) PRU Subsystem (PRUSS) 2 Programmable PRU Cores Size (Bytes) 168KB RAM

Organization 8KB RAM (Vector Table)

Core (V) I/O (V) 1.8V or 3.3 V

Product Preview (PP), Advance Information (AI), or Production Data (PD)

4 64-Bit General Purpose (each configurable as 2 separate

DDR2, 16-bit bus width, up to 156 MHz

Mobile DDR, 16-bit bus width, up to 150 MHz

Asynchronous (8/16-bit bus width) RAM, Flash,

16-bit SDRAM, NOR, NAND

64 independent channels, 16 QDMA channels,

2 channel controllers, 3 transfer controllers

32-bit timers, one configurable as Watch Dog)

4 Single Edge, 4 Dual Edge Symmetric, or

2 Dual Edge Asymmetric Outputs

ARM

16KB I-Cache

16KB D-Cache

64KB ROM

ADDITIONAL MEMORY

128KB RAM

1.2 V nominal for 375 MHz version

1.3 V nominal for 456 MHz version

13 mm x 13 mm, 361-Ball 0.65 mm pitch, PBGA (ZCE) 16 mm x 16 mm, 361-Ball 0.80 mm pitch, PBGA (ZWT)

375 MHz versions - PD 456 MHz versions - PD

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3.2 Device Compatibility

The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.

3.3 ARM Subsystem

The ARM Subsystem includes the following features:

• ARM926EJ-S RISC processor

• ARMv5TEJ (32/16-bit) instruction set

• Little endian

• System Control Co-Processor 15 (CP15)

• MMU

• 16KB Instruction cache

• 16KB Data cache

• Write Buffer

• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)

• ARM Interrupt controller

3.3.1 ARM926EJ-S RISC CPU

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The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications where full memory management, high performance, low die size, and low power are all important. The ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. Specifically, the ARM926EJ-S processor supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes, providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code overhead.

The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a complete high performance subsystem, including:

• ARM926EJ -S integer core

• CP15 system control coprocessor

• Memory Management Unit (MMU)

• Separate instruction and data caches

• Write buffer

• Separate instruction and data (internal RAM) interfaces

• Separate instruction and data AHB bus interfaces

• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB) For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available

at http://www.arm.com

3.3.2 CP15

The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and data caches, Memory Management Unit (MMU), and other ARM subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions, when the ARM in a privileged mode such as supervisor or system mode.

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3.3.3 MMU

A single set of two level page tables stored in main memory is used to control the address translation, permission checks and memory region attributes for both data and instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the information held in the page tables. The MMU features are:

• Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.

• Mapping sizes are: – 1MB (sections) – 64KB (large pages) – 4KB (small pages) – 1KB (tiny pages)

• Access permissions for large pages and small pages can be specified separately for each quarter of the page (subpage permissions)

• Hardware page table walks

• Invalidate entire TLB, using CP15 register 8

• Invalidate TLB entry, selected by MVA, using CP15 register 8

• Lockdown of TLB entries, using CP15 register 10

3.3.4 Caches and Write Buffer

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The size of the Instruction cache is 16KB, Data cache is 16KB. Additionally, the caches have the following features:

• Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)

• Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with two dirty bits in the Dcache

• Dcache supports write-through and write-back (or copy back) cache operation, selected by memory region using the C and B bits in the MMU translation tables

• Critical-word first cache refilling

• Cache lockdown registers enable control over which cache ways are used for allocation on a line fill, providing a mechanism for both lockdown, and controlling cache corruption

• Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the possibility of TLB misses related to the write-back address.

• Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of the Dcache or Icache, and regions of virtual memory.

The write buffer is used for all writes to a noncachable bufferable region, write-through region and write misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a four-address buffer. The Dcache write-back has eight data word entries and a single address entry.

3.3.5 Advanced High-Performance Bus (AHB)

The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the Config bus and the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the Config Bus and the external memories bus.

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3.3.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in the device also includes the Embedded Trace Buffer (ETB). The ETM consists of two parts:

• Trace Port provides real-time trace capability for the ARM9.

• Triggering facilities provide trigger resources, which include address and data comparators, counter, and sequencers.

The device trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace data.

3.3.7 ARM Memory Mapping

By default the ARM has access to most on and off chip memory areas, including EMIFA, DDR2, and the additional 128K byte on chip SRAM. Likewise almost all of the on chip peripherals are accessible to the ARM by default.

To improve security and/or robustness, the device has extensive memory and peripheral protection units which can be configured to limit access rights to the various on/off chip resources to specific hosts; including the ARM as well as other master peripherals. This allows the system tasks to be partitioned between the ARM and DSP as best suites the particular application; while enhancing the overall robustness of the solution.

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See Table 3-2 for a detailed top level device memory map that includes the ARM memory space.

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3.4 Memory Map Summary

Note: Read/Write accesses to illegal or reserved addresses in the memory map may cause undefined

behavior.

Table 3-2. Device Top Level Memory Map

Start Address End Address Size ARM Mem Map EDMA Mem Map PRUSS Mem Master LCDC Mem

0x0000 0000 0x0000 0FFF 4K PRUSS Local

0x0000 1000 0x01BB FFFF

0x01BC 0000 0x01BC 0FFF 4K ARM ETB

memory 0x01BC 1000 0x01BC 17FF 2K ARM ETB reg 0x01BC 1800 0x01BC 18FF 256 ARM Ice Crusher 0x01BC 1900 0x01BF FFFF 0x01C0 0000 0x01C0 7FFF 32K EDMA3 CC 0x01C0 8000 0x01C0 83FF 1K EDMA3 TC0 0x01C0 8400 0x01C0 87FF 1K EDMA3 TC1 0x01C0 8800 0x01C0 FFFF 0x01C1 0000 0x01C1 0FFF 4K PSC 0 0x01C1 1000 0x01C1 1FFF 4K PLL Controller 0 0x01C1 2000 0x01C1 3FFF 0x01C1 4000 0x01C1 4FFF 4K SYSCFG0 0x01C1 5000 0x01C1 FFFF 0x01C2 0000 0x01C2 0FFF 4K Timer0 0x01C2 1000 0x01C2 1FFF 4K Timer1 0x01C2 2000 0x01C2 2FFF 4K I2C 0 0x01C2 3000 0x01C2 3FFF 4K RTC 0x01C2 4000 0x01C3 FFFF 0x01C4 0000 0x01C4 0FFF 4K MMC/SD 0 0x01C4 1000 0x01C4 1FFF 4K SPI 0 0x01C4 2000 0x01C4 2FFF 4K UART 0 0x01C4 3000 0x01CF FFFF 0x01D0 0000 0x01D0 0FFF 4K McASP 0 Control 0x01D0 1000 0x01D0 1FFF 4K McASP 0 AFIFO Ctrl 0x01D0 2000 0x01D0 2FFF 4K McASP 0 Data 0x01D0 3000 0x01D0 BFFF 0x01D0 C000 0x01D0 CFFF 4K UART 1 0x01D0 D000 0x01D0 DFFF 4K UART 2 0x01D0 E000 0x01D0 FFFF 0x01D1 0000 0x01D1 07FF 2K McBSP0 0x01D1 0800 0x01D1 0FFF 2K McBSP0 FIFO Ctrl 0x01D1 1000 0x01D1 17FF 2K McBSP1 0x01D1 1800 0x01D1 1FFF 2K McBSP1 FIFO Ctrl 0x01D1 2000 0x01DF FFFF 0x01E0 0000 0x01E0 FFFF 64K USB0 0x01E1 0000 0x01E1 0FFF 4K UHPI 0x01E1 1000 0x01E1 2FFF 0x01E1 3000 0x01E1 3FFF 4K LCD Controller 0x01E1 4000 0x01E1 4FFF 4K Memory Protection Unit 1 (MPU 1)

Map Peripheral Mem Map

Map

Address Space

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Table 3-2. Device Top Level Memory Map (continued)

Start Address End Address Size ARM Mem Map EDMA Mem Map PRUSS Mem Master LCDC Mem

0x01E1 5000 0x01E1 5FFF 4K Memory Protection Unit 2 (MPU 2) 0x01E1 6000 0x01E1 6FFF 4K UPP 0x01E1 7000 0x01E1 7FFF 4K VPIF 0x01E1 8000 0x01E1 9FFF 0x01E1 A000 0x01E1 AFFF 4K PLL Controller 1 0x01E1 B000 0x01E1 BFFF 4K MMCSD1 0x01E1 C000 0x01E2 5FFF 0x01E2 6000 0x01E2 6FFF 4K GPIO 0x01E2 7000 0x01E2 7FFF 4K PSC 1 0x01E2 8000 0x01E2 8FFF 4K I2C 1 0x01E2 9000 0x01E2 BFFF 0x01E2 C000 0x01E2 CFFF 4K SYSCFG1 0x01E2 D000 0x01E2 FFFF 0x01E3 0000 0x01E3 7FFF 32K EDMA3 CC1 0x01E3 8000 0x01E3 83FF 1K EDMA3 TC2 0x01E3 8400 0x01EF FFFF

0x01F0 0000 0x01F0 0FFF 4K eHRPWM 0 0x01F0 1000 0x01F0 1FFF 4K HRPWM 0 0x01F0 2000 0x01F0 2FFF 4K eHRPWM 1 0x01F0 3000 0x01F0 3FFF 4K HRPWM 1 0x01F0 4000 0x01F0 5FFF 0x01F0 6000 0x01F0 6FFF 4K ECAP 0 0x01F0 7000 0x01F0 7FFF 4K ECAP 1 0x01F0 8000 0x01F0 8FFF 4K ECAP 2

0x01F0 9000 0x01F0 BFFF 0x01F0 C000 0x01F0 CFFF 4K Timer2 0x01F0 D000 0x01F0 DFFF 4K Timer3 0x01F0 E000 0x01F0 EFFF 4K SPI1 0x01F0 F000 0x01F0 FFFF

0x01F1 0000 0x01F1 0FFF 4K McBSP0 FIFO Data

0x01F1 1000 0x01F1 1FFF 4K McBSP1 FIFO Data

0x01F1 2000 0x3FFF FFFF

0x4000 0000 0x5FFF FFFF 512M EMIFA SDRAM data (CS0)

0x6000 0000 0x61FF FFFF 32M EMIFA async data (CS2)

0x6200 0000 0x63FF FFFF 32M EMIFA async data (CS3)

0x6400 0000 0x65FF FFFF 32M EMIFA async data (CS4)

0x6600 0000 0x67FF FFFF 32M EMIFA async data (CS5)

0x6800 0000 0x6800 7FFF 32K EMIFA Control Regs

0x6800 8000 0x7FFF FFFF

0x8000 0000 0x8001 FFFF 128K On-Chip RAM

0x8002 0000 0xAFFF FFFF 0xB000 0000 0xB000 7FFF 32K DDR2/mDDR Control Regs 0xB000 8000 0xBFFF FFFF 0xC000 0000 0xCFFF FFFF 256M DDR2/mDDR Data 0xD000 0000 0xE000 0000 0xFFFD 0000 0xFFFD FFFF 64K ARM local ROM

Map Peripheral Mem Map

Map

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Table 3-2. Device Top Level Memory Map (continued)

Start Address End Address Size ARM Mem Map EDMA Mem Map PRUSS Mem Master LCDC Mem

0xFFFE 0000 0xFFFE DFFF 0xFFFE E000 0xFFFE FFFF 8K ARM Interrupt

Controller

0xFFFF 0000 0xFFFF 1FFF 8K ARM local RAM ARM Local RAM

0xFFFF 2000 0xFFFF FFFF

Map Peripheral Mem Map

Map

(PRU0 only)

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W

V

U

T

R

P

N

M

L

K

10987654321

DVDD3318_C

VP_CLKOUT3/ PRU1_R30[0]/

GP6[1]/

PRU1_R31[1]

V

SS

NC

VP_CLKOUT2/

MMCSD1_DAT[2]/

PRU1_R30[2]/

GP6[3]/

PRU1_R31[3]

NC

NC NCNC NC

NC NCNC

DVDD3318_C

DDR_A[11]

VP_DOUT[15]/

LCD_D[15]/ UPP_XD[7]/

GP7[7]/

BOOT[7]

DV

DD3318_C

DV

DD18

DDR_DVDD18 DDR_DVDD18

DDR_D[15]

DDR_RAS

DDR_CLKP

DDR_CLKN

DDR_A[2]DDR_A[10]

V

SS

LCD_AC_ENB_CS/

GP6[0]/

PRU1_R31[28]

DDR_A[13]

DDR_CAS

DDR_A[5]

DDR_CKE

DDR_BA[0]

V

SS

CV

DD

RV

DD

DDR_A[9] DDR_A[1]

DDR_WE

DDR_D[10]

DDR_A[7]

DDR_A[0] DDR_D[12]

DDR_A[12] DDR_A[3]

DDR_CS

DDR_A[6]

DDR_DQM[1]

V

SS

CV

DD

V

SS

DDR_DVDD18

VP_DOUT[12]/

LCD_D[12]/ UPP_XD[4]/

GP7[4]/

BOOT[4]

DDR_VREF

DDR_BA[1]

DDR_A[8]

DDR_A[4]

DDR_BA[2]

V

SS

W

V

U

T

R

P

N

M

L

K

DDR_D[13]

V

SS

V

SS

V

SS

V

SS

DV

DD18

V

SS

V

SS

V

SS

V

SS

NC

V

SS

V

SS

V

SS

V

SS

CV

DD

CV

DD

V

SS

DDR_DVDD18DDR_DVDD18DDR_DVDD18DDR_DVDD18

DVDD3318_C

VP_DOUT[13]/

LCD_D[13]/ UPP_XD[5]/

GP7[5]/

BOOT[5]

VP_DOUT[14]/

LCD_D[14]/

UPP_XD[6]/

GP7[6]/

BOOT[6]

DDR_DVDD18 DDR_DVDD18 DDR_DVDD18

VP_DOUT[9]/

LCD_D[9]/

UPP_XD[1]/

GP7[1]/

BOOT[1]

VP_DOUT[10]/

LCD_D[10]/ UPP_XD[2]/

GP7[2]/

BOOT[2]

VP_DOUT[11]/

LCD_D[11]/

UPP_XD[3]/

GP7[3]/

BOOT[3]

VP_DOUT[6]/

LCD_D[6]/

UPP_XD[14]/

GP7[14]/

PRU1_R31[14]

VP_DOUT[7]/

LCD_D[7]/

UPP_XD[15]/

GP7[15]/

PRU1_R31[15]

VP_DOUT[8]/

LCD_D[8]/

UPP_XD[0]/

GP7[0]/

BOOT[0]

VP_DOUT[3]/

LCD_D[3]/

UPP_XD[11]/

GP7[11]/

PRU1_R31[11]

VP_DOUT[4]/

LCD_D[4]/

UPP_XD[12]/

GP7[12]/

PRU1_R31[12]

VP_DOUT[5]/

LCD_D[5]/

UPP_XD[13]/

GP7[13]/

PRU1_R31[13]

VP_DOUT[0]/

LCD_D[0]/

UPP_XD[8]/

GP7[8]/

PRU1_R31[8]

VP_DOUT[1]/

LCD_D[1]/

UPP_XD[9]/

GP7[9]/

PRU1_R31[9]

VP_DOUT[2]/

LCD_D[2]/

UPP_XD[10]/

GP7[10]/

PRU1_R31[10]

A B

CD

AM1806

SPRS658F –FEBRUARY 2010–REVISED MARCH 2014

3.5 Pin Assignments

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings.

3.5.1 Pin Map (Bottom View)

The following graphics show the bottom view of the ZCE and ZWT packages pin assignments in four quadrants (A, B, C, and D). The pin assignments for both packages are identical.

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Figure 3-1. Pin Map (Quad A)

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W

V

U

T

R

P

N

M

L

K

191817161514131211

NC

DVDD3318_C

CV

DD

USB_CVDD

DVDD3318_C

DDR_DQGATE0

DVDD18

DDR_DQGATE1

DDR_D[9] DDR_D[8]DDR_D[11]

DVDD18

RTC_CVDD

RESET

USB0_DM USB0_DP

VP_DIN[11]/ UHPI_HD[3]/

UPP_D[3]/

PRU0_R30[11]/

PRU0_R31[11]

USB0_VDDA33 USB0_VBUS

NC

VP_DIN[0]/

UHPI_HD[8]/

UPP_D[8]/

PRU1_R31[29]

VP_DIN[1]/

UHPI_HD[9]/

UPP_D[9]/

PRU0_R31[23]

VP_DIN[2]/

UHPI_HD[10]/

UPP_D[10]/

PRU0_R31[24]

VP_DIN[4]/

UHPI_HD[12]/

UPP_D[12]/

PRU0_R31[26]

PRU0_R30[28]/ UHPI_HCNTL1/

UPP_CHA_START/

GP6[10]

NC

PLL0_VDDA

PRU0_R30[30]/

/

PRU1_R30[11]/

GP6[12]

UHPI_HINT

USB0_VDDA18

VP_DIN[5]/

UHPI_HD[13]/

UPP_D[13]/

PRU0_R31[27]

DDR_D[1]

VP_DIN[7]/

UHPI_HD[15]/

UPP_D[15]/

PRU0_R31[29]

OSCVSS

DDR_D[2]

VP_DIN[6]/

UHPI_HD[14]/

UPP_D[14]/

PRU0_R31[28]

VP_DIN[3]/

UHPI_HD[11]/

UPP_D[11]/

PRU0_R31[25]

VP_DIN[14]_

HSYNC/

UHPI_HD[6]/

UPP_D[6]/

PRU0_R30[14]/

PRU0_R31[14]

EMU1

VP_DIN[8]/

UHPI_HD[0]/

UPP_D[0]/

GP6[5]/

PRU1_R31[0]

USB0_VDDA12

TDI

NC

PRU0_R30[26]/

UHPI_HR /

UPP_CHA_WAIT/

GP6[8]/

PRU1_R31[17]

W

VP_DIN[12]/ UHPI_HD[4]/

UPP_D[4]/

PRU0_R30[12]/

PRU0_R31[12]

RESETOUT

UHPI_HAS//

PRU1_R30[14]/

GP6[15]

RSV2

RTCK/

GP8[0]

OSCOUT

DDR_D[0]

PRU0_R30[27]/

UHPI_HHWIL/

UPP_CHA_ENABLE/

GP6[9]

VP_DIN[13]_

FIELD/

UHPI_HD[5]/

UPP_D[5]/

PRU0_R30[13]/

PRU0_R31[13]

TRST

OSCIN

VP_CLKIN1/

/

PRU1_R30[9]/

GP6[6]/

PRU1_R31[16]

UHPI_HDS1

VP_DIN[15]_

VSYNC/

UHPI_HD[7]/

UPP_D[7]/ PRU0_R30[15]/ PRU0_R31[15]

VP_CLKIN0/

/

PRU1_R30[10]/

GP6[7]/

UPP_2xTXCLK

UHPI_HCS

VP_DIN[10]/

UHPI_HD[2]/

UPP_D[2]/

PRU0_R30[10]/

PRU0_R31[10]

V

SS

DVDD3318_B

PLL0_VSSA

TMS

PRU0_R30[31]/

/

PRU1_R30[12]

GP6[13]

UHPI_HRDY

NC

PLL1_VSSA

PLL1_VDDA

NC

USB0_ID

VP_DIN[9]/

UHPI_HD[1]/

UPP_D[1]/

PRU0_R30[9]/

PRU0_R31[9]

CLKOUT/

/

PRU1_R30[13]/

GP6[14]

UHPI_HDS2

USB0_DRVVBUS

DDR_DQS[0]

PRU0_R30[29]/ UHPI_HCNTL0/

UPP_CHA_CLOCK/

GP6[11]

W

V

U

T

R

P

N

M

L

K

DDR_DQM[0]

DDR_D[3]

DDR_D[4]

DDR_D[6]

DDR_ZP

DDR_D[5]

DDR_D[7]

DDR_D[14]

DDR_DQS[1]

V

SS

V

SS

V

SS

V

SS

V

SS

CV

DD

DVDD3318_C

A B

CD

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AM1806

SPRS658F –FEBRUARY 2010–REVISED MARCH 2014

Figure 3-2. Pin Map (Quad B)

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H

G

F

E

D

C

B

A

191817161514131211

CV

DD

EMA_A[8]/

PRU1_R30[16]/

GP5[8]

EMA_A[14]/

MMCSD0_DAT[7]/

PRU1_R30[22]/

GP5[14]/

PRU1_R31[22]

EMA_A[15]/

MMCSD0_DAT[6]/

PRU1_R30[23]/

GP5[15]/

PRU1_R31[23]

EMA_A[10]/

PRU1_R30[18]/

GP5[10]/

PRU1_R31[18]

EMA_A[9]/

PRU1_R30[17]/

GP5[9]

EMA_A[13]/ PRU0_R30[21]/ PRU1_R30[21]

GP5[13]/

PRU1_R31[21]

EMA_A[12]/

PRU1_R30[20]/

GP5[12]/

PRU1_R31[20]

EMA_A[16]/

MMCSD0_DAT[5]/

PRU1_R30[24]/

GP4[0]

EMA_A[18]/

MMCSD0_DAT[3]/

PRU1_R30[26]/

GP4[2]

DV

DD3318_B

DV

DD18

EMA_A[6]/

GP5[6]

EMA_A[5]/

GP5[5]

EMA_A[2]/

GP5[2]

EMA_A[7]/

PRU1_R30[15]/

GP5[7]

EMA_A[4]/

GP5[4]

SPI0_SIMO/

EPWMSYNCO/

GP8[5]

SPI0_SCS[5]/ UART0_RXD/

GP8[4]

SPI1_SCS[1]/

EPWM1A/

PRU0_R30[8]/

GP2[15]/

TM64P2_IN12

SPI0_SCS[4]/ UART0_TXD/

GP8[3]

SPI0_CLK/

EPWM0A/

GP1[8]

SPI1_SCS[3]/ UART1_RXD/

GP1[1]

SPI1_SCS[0]/

EPWM1B/

PRU0_R30[7]/

GP2[14]/

TM64P3_IN12

EMA_OE/

GP3[10]

SPI1_SCS[4]/

UART2_TXD/

I2C1_SDA/

GP1[2]

EMA_A[3]/

GP5[3]

DV

DD18

RTC_VSS

EMA_WAIT[0]/ PRU0_R30[0]/

GP3[8]/

PRU0_R31[0]

EMA_RAS/

PRU0_R30[3]/

GP2[5]/

PRU0_R31[3]

SPI0_SCS[3] UART0_CTS//

GP8[2]

SPI0_SCS[0]/

TM64P1_OUT12/

GP1[6]/

TM64P1_IN12

SPI0_SOMI/

EPWMSYNCI/

GP8[6]

SPI0_SCS[2]

UART0_RTS//

GP8[1]

SPI1_SCS[7]/

I2C0_SCL/

TM64P2_OUT12/

GP1[5]

SPI1_SIMO/

GP2[10]

SPI1_CLK/

GP2[13]

EMA_CS[3]/

GP3[14]

V

SS

V

SS

SPI1_ENA/

GP2[12]

RTC_XO

EMA_CS[2]/

GP3[15]

EMA_WAIT[1]/ PRU0_R30[1]/

GP2[1]/

PRU0_R31[1]

EMA_A[20]/

MMCSD0_DAT[1]/

PRU1_R30[28]/

GP4[4]

EMA_BA[1]/

GP2[9]

SPI0_ENA/

EPWM0B/

PRU0_R30[6]

EMA_CS[5]/

GP3[12]

SPI1_SCS[5]/ UART2_RXD/

I2C1_SCL/

GP1[3]

EMA_A[0]/

GP5[0]

EMA_BA[0]/

GP2[8]

EMA_A[1]/

GP5[1]

DV

DD3318_B

SPI0_SCS[1]/

TM64P0_OUT12/

GP1[7]/

TM64P0_IN12

DV

DD3318_A

SPI1_SCS[6]/

I2C0_SDA/

TM64P3_OUT12/

GP1[4]

EMA_CS[0]/

GP2[0]

CV

DD

SPI1_SOMI/

GP2[11]

H

G

F

E

D

C

B

A

J

TDO

TCK

EMU0

RTC_XI

RSVDN

J

SPI1_SCS[2]/

UART1_TXD/

GP1[0]

EMA_A[11]/

PRU1_R30[19]/

GP5[11]/

PRU1_R31[19]

EMA_A[17]/

MMCSD0_DAT[4]/

PRU1_R30[25]

GP4[1]

DV

DD3318_B

DV

DD3318_B

DV

DD18

CV

DD

DV

DD3318_A

DV

DD3318_A

RV

DD

CV

DD

CV

DD

V

SS

CV

DD

DV

DD18

DV

DD3318_B

A B

CD

AM1806

SPRS658F –FEBRUARY 2010–REVISED MARCH 2014

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Figure 3-3. Pin Map (Quad C)

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J

H

G

F

E

D

C

B

A

10987654321

EMA_D[15]/

GP3[7]

AXR15/

EPWM0TZ[0]/

ECAP2_APWM2/

GP0[7]

ACLKR/

PRU0_R30[20]/

GP0[15]/

PRU0_R31[22]

ACLKX/

PRU0_R30[19]/

GP0[14]/

PRU0_R31[21]

AHCLKX/

USB_REFCLKIN/

/

GP0[10]/

PRU0_R31[17]

UART1_CTS

AFSX/

GP0[12]/

PRU0_R31[19]

AFSR/

GP0[13]/

PRU0_R31[20]

AXR9/

DX1/

GP0[1]

AXR4/ FSR0/

GP1[12]

AXR5/ CLKX0/ GP1[13]

AXR7/

EPWM1TZ[0]/

PRU0_R30[17]

GP1[15]/

PRU0_R31[7]

AXR10/

DR1/

GP0[2]

AXR1/

DX0/

GP1[9]

AXR3/

FSX0/

GP1[11]

AXR2/

DR0/

GP1[10]

MMCSD1_DAT[6]/

LCD_MCLK/

PRU1_R30[6]/

GP8[10]/

PRU1_R31[7]

RTC_ALARM/

/

GP0[8]/

UART2_CTS

DEEPSLEEP

AXR0/

ECAP0_APWM0/

GP8[7]/

CLKS0

PRU0_R30[24]/ MMCSD1_CLK/

UPP_CHB_START/

GP8[14]/

PRU1_R31[26]

MMCSD1_DAT[4]/

LCD_VSYNC/

PRU1_R30[4]/

GP8[8]/

PRU1_R31[5]

V

SS

PRU0_R30[22]/

PRU1_R30[8]/

UPP_CHB_WAIT/

GP8[12]/

PRU1_R31[24]

AXR8/

CLKS1/

ECAP1_APWM1/

GP0[0]/

PRU0_R31[8]

AXR12/

FSR1/ GP0[4]

EMA_D[4]/

GP4[12]

AXR14/ CLKR1/

GP0[6]

EMA_WEN_DQM[1]/

GP2[2]

EMA_D[0]/

GP4[8]

EMA_A[19]/

MMCSD0_DAT[2]/

PRU1_R30[27]/

GP4[3]

EMA_D[9]/

GP3[1]

EMA_A_R /

GP3[9]

W

MMCSD0_CLK/ PRU1_R30[31]/

GP4[7]

EMA_D[8]/

GP3[0]

EMA_D[13]/

GP3[5]

VP_CLKIN2/

MMCSD1_DAT[3]/

PRU1_R30[3]/

GP6[4]/

PRU1_R31[4]

VP_CLKIN3/

MMCSD1_DAT[1]/

PRU1_R30[1]/

GP6[2]/

PRU1_R31[2]

AMUTE/

GP0[9]/

PRU0_R31[16]

PRU0_R30[16]/

UART2_RTS/

DV

DD3318_A

DV

DD3318_A

EMA_WE/

GP3[11]

EMA_D[10]/

GP3[2]

EMA_D[3]/

GP4[11]

EMA_SDCKE/ PRU0_R30[4]/

GP2[6]/

PRU0_R31[4]

EMA_D[14]/

GP3[6]

EMA_D[7]/

GP4[15]

EMA_D[1]/

GP4[9]

EMA_A[22]/

MMCSD0_CMD/

PRU1_R30[30]/

GP4[6]

EMA_D[2]/

GP4[10]

EMA_A[21]/

MMCSD0_DAT[0]/

PRU1_R30[29]/

GP4[5]

PRU0_R30[23]/

MMCSD1_CMD/

UPP_CHB_ENABLE/

GP8[13]/

PRU1_R31[25]

AHCLKR/

/

GP0[11]/

PRU0_R31[18]

PRU0_R30[18]/

UART1_RTS

EMA_D[12]/

GP3[4]

EMA_WEN_DQM[0]/

GP2[3]

EMA_CLK/

PRU0_R30[5]/

GP2[7]/

PRU0_R31[5]

AXR6/

CLKR0/

GP1[14]/

PRU0_R31[6]

AXR11/

FSX1/

GP0[3]

EMA_D[6]/

GP4[14]

EMA_D[11]/

GP3[3]

RV

DD

EMA_D[5]/

GP4[13]

MMCSD1_DAT[7]/

LCD_PCLK/

PRU1_R30[7]/

GP8[11]

MMCSD1_DAT[5]/

LCD_HSYNC/

PRU1_R30[5]/

GP8[9]/

PRU1_R31[6]

PRU0_R30[25]/

MMCSD1_DAT[0]/

UPP_CHB_CLOCK/

GP8[15]/

PRU1_R31[27]

AXR13/ CLKX1/

GP0[5]

J

H

G

F

E

D

C

B

A

EMA_CS[4]/

GP3[13]

EMA_CAS/

PRU0_R30[2]/

GP2[4]/

PRU0_R31[2]

DV

DD3318_B

DV

DD3318_B

DV

DD3318_B

DV

DD3318_B

DV

DD18

CV

DD

CV

DD

DV

DD3318_B

DV

DD18

V

SS

DV

DD3318_A

V

SS

V

SS

CV

DD

CV

DD

V

SS

V

SS

CV

DD

NC NC

DV

DD3318_C

CV

DD

V

SS

V

SS

A B

CD

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AM1806

SPRS658F –FEBRUARY 2010–REVISED MARCH 2014

3.6 Pin Multiplexing Control

Device level pin multiplexing is controlled by registers PINMUX0 - PINMUX19 in the SYSCFG module. For the device family, pin multiplexing can be controlled on a pin-by-pin basis. Each pin that is multiplexed

with several different functions has a corresponding 4-bit field in one of the PINMUX registers. Pin multiplexing selects which of several peripheral pin functions controls the pin's IO buffer output data

and output enable values only. The default pin multiplexing control for almost every pin is to select 'none' of the peripheral functions in which case the pin's IO buffer is held tri-stated.

Note that the input from each pin is always routed to all of the peripherals that share the pin; the PINMUX registers have no effect on input from a pin.

Figure 3-4. Pin Map (Quad D)

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SPRS658F –FEBRUARY 2010–REVISED MARCH 2014

3.7 Terminal Functions

Table 3-3 to Table 3-27 identify the external signal names, the associated pin/ball numbers along with the

mechanical package designator, the pin type (I, O, IO, OZ, or PWR), whether the pin/ball has any internal pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO mode, and a functional pin description.

3.7.1 Device Reset and JTAG

Table 3-3. Reset and JTAG Terminal Functions

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SIGNAL

NAME NO.

RESET K14 I IPU B Device reset input RESETOUT / UHPI_HAS / PRU1_R30[14] /

GP6[15]

TMS L16 I IPU B JTAG test mode select TDI M16 I IPU B JTAG test data input TDO J18 O IPU B JTAG test data output TCK J15 I IPU B JTAG test clock TRST L17 I IPD B JTAG test reset EMU0 J16 I/O IPU B Emulation pin EMU1 K16 I/O IPU B Emulation pin RTCK/ GP8[0]

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for that particular peripheral.

(2) IPD = Internal Pulldown resistor, IPU = Internal Pullup resistor. CP[n] = configurable pull-up/pull-down (where n is the pin group) using

the PUPDENA and PUPDSEL registers in the System Module. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see the Device Configuration section. For electrical specifications on pullup and internal pulldown circuits, see the Device Operating Conditions section.

(3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can

be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power

supply DVDD3318_C. (4) Open drain mode for RESETOUT function. (5) GP8[0] is initially configured as a reserved function after reset and will not be in a predictable state. This signal will only be stable after

the GPIO configuration for this pin has been completed. Users should carefully consider the system implications of this pin being in an

unknown state after reset.

(5)

T17 O

K17 I/O IPD B JTAG Test Clock Return Clock Output

TYPE

(1)

PULL

RESET

(4)

CP[21] C Reset output

JTAG

POWER

(2)

GROUP

(3)

DESCRIPTION

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3.7.2 High-Frequency Oscillator and PLL

Table 3-4. High-Frequency Oscillator and PLL Terminal Functions

AM1806

SPRS658F –FEBRUARY 2010–REVISED MARCH 2014

SIGNAL

NAME NO.

CLKOUT / UHPI_HDS2 /

PRU1_R30[13] / GP6[14]

(1)

TYPE

PULL

T18 O CP[22] C PLL Observation Clock

POWER

(2)

GROUP

(3)

DESCRIPTION

1.2-V OSCILLATOR

OSCIN L19 I — — Oscillator input OSCOUT K19 O — — Oscillator output OSCVSS L18 GND — — Oscillator ground

1.2-V PLL0

PLL0_VDDA L15 PWR — — PLL analog VDD(1.2-V filtered supply) PLL0_VSSA M17 GND — — PLL analog VSS(for filter)

1.2-V PLL1

PLL1_VDDA N15 PWR — — PLL analog VDD(1.2-V filtered supply) PLL1_VSSA M15 GND — — PLL analog VSS(for filter)

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for

that particular peripheral. (2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using

the PUPDENA and PUPDSEL registers in the System Module. For more detailed information on pullup/pulldown resistors and situations

where external pullup/pulldown resistors are required, see the Device Configuration section. For electrical specifications on pullup and

internal pulldown circuits, see the Device Operating Conditions section. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can

be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of

power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power

supply DVDD3318_C.

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AM1806

SPRS658F –FEBRUARY 2010–REVISED MARCH 2014

3.7.3 Real-Time Clock and 32-kHz Oscillator

Table 3-5. Real-Time Clock (RTC) and 1.2-V, 32-kHz Oscillator Terminal Functions

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SIGNAL

NAME NO.

TYPE

(1)

PULL

POWER

(2)

GROUP

(3)

DESCRIPTION

RTC_XI J19 I — — RTC 32-kHz oscillator input RTC_XO H19 O — — RTC 32-kHz oscillator output RTC_ALARM / UART2_CTS / GP0[8] / DEEPSLEEP F4 O CP[0] A RTC Alarm

RTC_CVDD L14 PWR — — RTC_V

ss

H18 GND — — Oscillator ground

RTC module core power (isolated from chip CVDD)

(1) I = Input, O = Output, I/O = Bidirectional, Z = High impedance, PWR = Supply voltage, GND = Ground, A = Analog signal.

Note: For multiplexed pins where functions have different types (ie., input versus output), the table reflects the pin function direction for

that particular peripheral. (2) IPD = Internal Pulldown resistor; IPU = Internal Pullup resistor; CP[n] = configurable pull-up/pull-down (where n is the pin group) using

the PUPDENA and PUPDSEL registers in the System Module. The pull-up and pull-down control of these pins is not active until the

device is out of reset. During reset, all of the pins associated with these registers are pulled down. If the application requires a pull-up,

an external pull-up can be used. For more detailed information on pullup/pulldown resistors and situations where external

pullup/pulldown resistors are required, see the Device Configuration section. For electrical specifications on pullup and internal pulldown

circuits, see the Device Operating Conditions section. (3) This signal is part of a dual-voltage IO group (A, B or C). These groups can be operated at 3.3V or 1.8V nominal. The three groups can

be operated at independent voltages but all pins withina group will operate at the same voltage. Group A operates at the voltage of

power supply DVDD3318_A. Group B operates at the voltage of power supply DVDD3318_B. Group C operates at the voltage of power

supply DVDD3318_C.

3.7.4 DEEPSLEEP Power Control

Table 3-6. DEEPSLEEP Power Control Terminal Functions

SIGNAL

NAME NO.

TYPE

(1)

PULL

RTC_ALARM / UART2_CTS / GP0[8] / DEEPSLEEP F4 I CP[0] A DEEPSLEEP power control output