TEXAS INSTRUMENTS AJC111 Technical data

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

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FEATURES

D Single Channel Codec D Noise Shaped Delta Sigma ADC and DAC

Technology

D Low Supply Voltage and Current:

− 1.3-V Typical Power Supply

− 350-µA Typical Supply Current Drain

D Power Supply Up Monitor and Low Battery

Monitor That Also Automatically Shuts Off H-Bridge Output When Battery Decays Below

1.05 V in a Nontransient Manner

D Typical 2.4-µVrms Input Referred Noise With

0.01% Total Harmonic Distortion for Front End and 108-dB Dynamic Range

D ADC Has 87-dB Dynamic Range With 73-dB

Total Harmonic Distortion 100 Hz−10 kHz, 40-kHz Sampling Rate

D Typical 55-dB PSRR 100 Hz to 10 kHz for

Analog Front End

D Low Noise Programmable Gain

Amplifier/Compressor Front End With Programmable Fast and Slow Attack and Decay Rates With Dual or Single Attack and Decay Rate Option

D Typical Output Noise of 12 µVrms With 0.05%

Total Harmonic Distortion for Delta Sigma DAC and H-Bridge Output Driver

D Low Jitter Oscillator That Generates all

Internal Clocks and Generates 5-MHz Output DSP/µC Clock

D Regulated Bandgap Voltage Reference D Programmable Functionality via Digital Serial

Interface

− McBSP Interface, DSP Protocol

− TI TMS320VC54x, TMS320VC55x DSPs

− SPI Interface, Microcontroller Protocol

− TI MSP430xx

D External Chip Power Down and Reset

D Available in:

− 32-Pin QFN 5×5-mm Plastic Package

− 32-Pad Bumped Die in Waffle Pack (wafer scale packaging), or Tape and Reel, (Preview, Available 3rd Quarter 2003)

APPLICATIONS

D Hearing Instruments D Personal Medical Devices D Hearing Protection D Aural Processing D Low-Power Headsets

DESCRIPTION

The AIC111 IC design specification serves to provide product development teams with a guideline for how the AIC1 11 IC is specified and programmable options that are available. The document outlines a top-level block description of the IC along with system specifications and functions. Individual block descriptions and target specifications are also outlined.

The Texas Instruments AIC111 is a TI µPower DSP compatible, or microcontroller compatible audio codec product, or analog interface circuit. The AIC111 is part of a comprehensive family of DSP/µC based highperformance analog interface solutions. The AIC111 is targeted primarily at personal medical devices, such as hearing instruments, aural preprocessing applications, and low-power headset applications. The AIC111 is used in any design requiring a programmable time constant PGA/compressor interface, high dynamic range analog-to-digital converter, an external DSP/µC handling signal processing, or a low distortion digital-to-analog converter with a balanced H-Bridge speaker driver. It supports a CMOS digital interface tailored for TI DSPs with the McBSP protocol such as TMS320VC54x DSP family and SPI-based controllers such as TI MSP430x family of microcontrollers. The AIC111 also has an external microphone or sensor supply and bias and power supply up low-battery monitor indicator.

semiconductor products and disclaimers thereto appears at the end of this data sheet.

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H-bridge amplifier output

DAC full scale output differential

SLAS382 − JUNE 2003

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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The AIC1 11 comes in a 32-pin QFN 5×5-mm package. A 32-pad solder ball bumped flip chip die that comes in waffle packs or tape and reel is in preview and will be available 3rd quarter 2003.

AVAILABLE OPTIONS

PART NUMBER PACKAGE

AIC111RHB 32-pin QFN (5 mm x 5 mm), in tube.

AIC111RHBR 32-pin QFN (5 mm x 5 mm), tape and reel

AIC111YE

AIC111YER

32-pad waffle scale chip package, bumped die in waffle pack (contact the factory for availability) − Preview,

available 3rd quarter 2003

32-pad (WSCP) bumped die in tape and reel (contact the factory for availability) − Preview, available 3rd

quarter 2003

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

Input voltage AI or DI pins −0.3 V to 4 V Power supply VDD, power pins −0.3 V to 4.5 V Latch-up tolerance JEDEC latch-up (EIA/JEDS78) 100 mA Operating free-air temperature range, T Functional temperature range −15°C to 85°C Reflow temperature range (flip chip) 220°C to 230°C Storage temperature range, T Storage humidity 65% R.H.

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only , a n d functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

Specifications are assured operating at maximum device limits for QFN package only, unless otherwise specified.

stg

(1)(2)

UNIT

0°C to 70°C

−40°C to 125°C

ELECTRICAL CHARACTERISTICS

INPUT/OUTPUT, OPERATING TEMPERATURE AT 2 5 °C

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Digital interface (see Notes 1 and 2) BUF_DVDD (see Note 1) 3.6 V VIH High-level input voltage BUF_DVDD−0.2 V VIL Low-level input voltage BUF_DVSS+0.2 V VOH High-level output voltage BUF_DVDD V VOL Low-level output voltage BUF_DVSS V Maximum allowed input voltage (AVIN) Differential 450 mVpk Input impedance (AVIN) (see Note 3) Nominal gain = 50x 20 kΩ Input capacitance (AVIN) 5 pF Microphone bias voltage (MIC_VSUP) 20-µA maximum 0.87 0.94 0.99 V Microphone bias resistor (MIC_BIAS) 27 29.1 31 kΩ

Fixed Q 3/4 HB_VDD Adaptive Q HB_VDD

Output resistance Differential, HB − VDD = 1.3 V 20 or 40 Ω

(1)

DVDD, VDD_OSC, and AVDD should be within 50 mV, preferably connected together. AVSS1, 2, DVSS, and VSS_OSC should be within 50 mV, preferably connected together.

(2)

Maximum (0.9 V , DVDD −0.5 V) ≤ BUF_DVDD ≤3.6 V

(3)

Driving single-ended: Rin = R × [(1+A)/(2+A)], A = PGAC Gain (linear), R = 20.4 kΩ for A ≥ 4 or 20.4 kΩ × (4/A) for A<4. Rin(min) = 1 7 k Ω (A=4), Rin(max) = 59.89 kΩ (A = 0.89), Rin(nom) = 20 kΩ (A = 50).

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TERMINAL ASSIGNMENTS

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AVSS1 AVSS2

AVINP

AVINM

VMID_FILT

MIC_BIAS

VREF

MIC_VSUP

Alignment

Marker

(0,0)

MIC_VSUP

VREF

MIC_BIAS

VMID_FILT

AVINM

AVINP AVSS2 AVSS1

AVSS_REF

1 2 3 4 5 6 7

91011121314

SUB_VSS

91011121314

8 7

6 5 4 3 2 1

AVSS_REF

VRFILT

AVDD

3132

AIC111

Bumped Side

VDD_OSC

VSS_OSC

Back Side

AIC111

3132

VRFILT

AVDD

EXT_RST/PWDN

RST/LBM

2930

VOUT_P

VSS_OSC

HB_VSS_P

HB_VDD

VOUT_P

2930

DVSS2

RST/LBM

EXT_RST/PWDN

DVSS2

HB_VDD

VOUT_M

HB_VSS_M

VOUT_M

SCLK

FRAME

SDIN SDOUT

BUF_DVSS

BUF_DVDD

DVDD DVSS1

19 18

MCLK

IMODE

Bumped View

HB_VSS_M

For exact bump

location see Spec.

IMODE

MCLK

DVSS1

DVDD

BUF_DVDD

BUF_DVSS

SDOUT

SDIN

FRAME

PCB View

Section 2.2

Figure 1. AIC111YE Bumped View and PCB Flipped Pin Placements

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SLAS382 − JUNE 2003

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AVSS1

AVSS2

AVINP

AVINM

VMID_FILT

MIC_BIAS

VREF_BG

MIC_VSUP

AVSS_REF

9 10111213141516

VRFILT

AVDD

DVSS

29303132

RST/LBM

DVSS

SCLK

AIC111RHB

FRAME

252627

SDIN

SDOUT

BUF_DVSS

BUF_DVDD

DVDD

DVSS

MCLK

IMODE

SUB_VSS

VDD_OSC

VSS_OSC

HB_VSS_P

VOUT_P

HB_VDD

Figure 2. AIC111RHB 32-Pin QFN Pinout

VOUT_M

HB_VSS_M

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TYPE

DESCRIPTION

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Terminal Functions

TERMINAL

NO. NAME

1 AVSS1 GND Ground return for ADC analog circuits 2 AVSS2 GND Ground return for PGAC and MIC power analog circuits 3 AVINP AI Noninverting differential analog input coupled through an external 1-µF capacitor to external microphone

output 4 AVINM AI Inverting d i fferential analog signal input coupled through an external 1-µF capacitor to ground 5 VMID_FILT AO Midsupply ac ground reference filter pin bypassed by a 1-µF capacitor connected to ground 6 MIC_BIAS AO Source connection of external microphone source follower preamp. (Provides 29.1 kΩ to AVSS2) 7 VREF AO Bandgap reference output bypassed by external 1-µF VREF filter capacitor 8 MIC_VSUP AO Supply voltage for external microphone source follower preamp bypassed with an external 0.1-µF capacitor 9 SUB_VSS GND Isolated substrate VSS for analog circuits

10 VDD_OSC VDD Power pin for internal oscillator 11 VSS_OSC GND Ground return for internal oscillator 12 HB_VSS_P GND Ground return for noninverting stack of H-bridge amplifier 13 VOUT_P AO Noninverting H-bridge output voltage 14 HB_VDD VDD Power pin for H-bridge amplifier 15 VOUT_M AO Inverting H-bridge output voltage 16 HB_VSS_M GND Ground return for inverting stack of H-bridge amplifier 17 IMODE DI Digital interface format selection pin 18 MCLK DO 5-MHz output clock for external DSP/µC 19 DVSS1 GND Ground return for digital circuits 20 DVDD VDD Power pin for digital circuits 21 BUF_DVDD VDD Power pin for interface digital I/O circuits 22 BUF_DVSS GND Ground return for interface digital I/O circuits 23 SDOUT DO Digital interface serial data output pin 24 SDIN DI Digital interface serial data input pin 25 FRAME DO Digital interface serial data framer 26 SCLK DO Digital interface serial shift clock 27 DVSS2 GND Ground return for digital circuits 28 RST/LBM DO Provides external reset and low battery monitor 29 EXT_RST/PWDN DI Powers down all analog blocks and holds digital outputs low until internal system is up 30 AVDD VDD VDD power pin for analog circuits 31 VRFILT AO Positive ADC reference pin bypassed with 1-µF capacitor to AVSS_REF 32 AVSS_REF GND Ground for ADC voltage reference

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FUNCTIONAL BLOCK DIAGRAM

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AVINP

AVINM

VREF

VMID_FILT

PGA/Compressor

SUB_VSS

MIC/Sensor

Power and

Bias

Bandgap

Reference

AVDD

VRFILT

AVSS_REF

RC Flt

Biases

Generator

Delta

Sigma

ADC

AVSS

Dec.

Filter

HPF

Output Buffers

IMODE

EXT_RST/PWDN

Digital

Interface

SCLK

SDOUT

FRAME

Delta

Sigma

DAC

DVDDMIC_VSUP DVSSMIC_BIAS

BUF_DVDD BUF_DVSS

SDIN

HB_VDD

HB_VSS_P

H−Bridge

Speaker

Driver

POR

Oscillator

HB_VSS_M

VOUT_P VOUT_M

RST/LBM

VDD_OSC VSS_OSC

MCLK

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OPERATION

The power source may be a zinc-air battery operating at a typical voltage of 1.3 V. A single external de-coupling capacitor of 1 µF is recommended on the main power supply.

VOLTAGE and CURRENT, OPERATING TEMPERATURE AT 25°C

PARAMETER TEST CONDITION MIN TYP MAX UNIT

AVDD, DVDD (All pins of type AVDD, DVDD in pin-out table)

IS (supply current)

Steady-state battery supply

S Unloaded: H-Bridge output open S Microphone resistor model connected (see Figure 6) S Power supplies = 1.3 V S No receiver attached

1.1 1.3 1.5 V

350 µA

FUNCTIONAL INPUT CHANNEL PERFORMANCE REQUIREMENTS

The front end is defined as the differential signal path from the PGA/compressor inputs, AVINP, and A VINM through the delta-sigma ADC and decimation filter.

Typical Conditions; deviations are noted in table.

D Operating Temperature Range: 0°C to 70°C. All specification are at 25°C and 1.3 V unless otherwise noted. D AVDD, DVDD range: 1.1 V to 1.5 V D AVINP, AVINM inputs: AC coupled, Frequency ranging from 100 Hz–10 kHz D Measurement Bandwidth: 100 Hz–10 kHz A-weighted. D Idle channel definition: AVINP and AVINM are both ac-coupled to AVSS. D Typical PGAC gain range is −1 dB to 40 dB. D Maximum input voltage: 450 mVpk.

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Broad-band noise Input referred idle channel 2.4 µV RMS THD (low level) AVIN≤ PGAC threshold (see Note 1) 0.01 0.2% DC Offset Idle channel −5 0 5 mV Droop at 10 kHz Referenced to amplitude at 1 kHz 1.2 dB

(1)

PGAC threshold = PGAC threshold voltage/maximum gain of PGAC.

−10

−20

−30

−40

−50

Gain − dB

−60

−70

−80

−90

−100 0 102030405060708090100

f − Frequency − kHz

−2

−4

−6

−8

−10

Gain − dB

−12

−14

−16

−18

−20 0 2 4 6 8 101214161820

f − Frequency − kHz

Figure 3. Input Channel Frequency Response With HPF Bypassed

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Analog-to-Digital Converter Filtered Input Voltage Reference

Function – Filters analog supply AVDD for DS-ADC reference. With a recommended 0.1-µF external capacitor

between pins VRFILT and AVSS_REF, the pole is set at approximately 72 Hz, with 1 µF, the pole is set at approximately 7 Hz.

Programmable Gain Amplifier and Compressor

Function: The programmable gain amplifier and compressor (PGAC) amplifies the microphone or sensor output

signal, provides an appropriate impedance to the microphone buffer or sensor , and provides input gain compression limiting depending on the input signal level if one is not using the fixed gain mode, where the PGAC gain is set by selected register bits. Input compression limiting is discrete automatic gain correction (AGC) based on detecting the peak input signal level using a peak detector circuit that has programmable time responses to provide AGC control, and is intended to prevent a steady state input level up to the defined PGAC limit from being clipped. The attack/release times of the PGAC are programmable by internal clock selection inside the PGAC digital level circuitry that affects the rate of gain changes.

The PGAC has four modes of operation: automatic dual-rate (default), automatic single-rate, fixed single-rate, and fixed immediate. Mode selection is controlled by bits 3 and 2 of the PDCREG register.

Automatic dual-rate mode (00, default):

In this mode of operation, the PGAC has two attack (gain decrease) rates and two release (gain increase) rates, which may be selected by programming the FASTARREG and FORMAT4 registers. Internally, two counters are used to control the compressor gain. The fast rate counter responds at the fast attack and release rates, and it counts down at the attack rate to decrease the PGAC gain if the output of the PGAC is instantaneously larger than a preset threshold (PGAC_THRES = 400-mV peak), or it counts up to increase the gain, up to the maximum allowed gain as set by the PGACREG register, if the output of the PGAC falls below a second threshold, which is 3 dB lower (283-mV peak), which provides hysteresis. Before the gain is allowed to increase, the signal at the output of the PGAC must be below the lower threshold for a period of time which is controlled by bit 4 of PDCREG, and can be 50 ms (0, default) or 25 ms (1). The slow-rate counter responds at the slow attack and release rates, and it attempts to track the state of the fast rate counter. The PGAC gain is determined by whichever counter is smaller. In this way, the PGAC can respond and recover rapidly to short signal bursts while responding more slowly to the signal average.

Automatic single-rate mode (01):

In this mode of operation, the PGAC has one attack rate and one release rate, which may be selected by programming the FASTARREG register. The operation of the PGAC is similar to the dual-rate mode, except that the slow-rate counter is disabled and the PGAC gain is solely determined by the fast-rate counter.

Fixed single-rate mode (10):

In this mode of operation, the PGAC gain tracks the value specified in the PGACREG register regardless of the signal amplitude, and changes in PGACREG cause the gain to decrease or increase at the corresponding fast attack or release rate specified in the FASTARREG register.

Fixed immediate mode (11):

In this mode of operation, the PGAC gain tracks the value specified in the PGACREG register regardless of the signal amplitude, and changes in PGACREG cause the gain to change immediately to the desired gain without stepping through the intermediate gain states.

Bit 7 of the PGACREG register controls the PGAC gain read mode. While this bit is low (default), reading PGACREG returns the contents of PGACREG. However, if this bit is set high, then any subsequent read(s) of PGACREG returns the actual, instantaneous PGAC gain. This information may be useful, for example, for dynamic range expansion, effectively undoing the compression effect in the automatic modes of operation.

Characteristics: Compression limits the PCAG output. PGACREG is a programmable register.

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Specifications at 25°C, AVDD = 1.3 V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input Signal Parameters

Maximum signal swing Gain = −1 dB 900 mV

Block Parameters

Gain size step 0.3 0.5 0.7 dB

(1)

Based on a system clock of 1.280 MHz.

(2)

For fixed gain mode the rate is 80 KdB/s to new programmed value of gain. All intermediate 0.5 dB gain steps are passed through to reach new gain.

Delta Sigma A/D Converter/Anti-alias Filter Function: Converts the PGAC differential output to a digital word with an equivalent dynamic range of approximately

14 bits. Characteristics: The delta sigma ADC has a 64 oversampling ratio, a 1.28-MHz master clock, and a 40-kHz output

data rate. Digital coding is 2s complement. Tones are at least 12 dB below broadband noise level. Full-scale signal range corresponds to +215 –1, −2

Specifications at 25°C, AVDD = 1.3 V

PARAMETER

Block parameters Dynamic range −3 dB rel. to reference 87 dB Input sample rate 1.28 MHz Output sample rate 40 kHz THD BW: 100 Hz−10 kHz 85 dB

TEST CONDITIONS MIN TYP MAX UNIT

Digital High-Pass Filter Function: Provide a high-pass filter in ADC signal path. The high-pass filter (HPF first order) removes dc offsets

introduced into the channel. FORMAT1 register selections for a 50 Hz, 100 Hz, or bypass are available. Characteristics: Programmable selections for a 50 Hz, 100 Hz, or bypass are available. The default HPF pole is

50 Hz.

Specifications

PARAMETER

HPF corner frequency −3 dB nom mode 50 Hz

TEST CONDITIONS MIN TYP MAX UNIT

Delta Sigma DAC Function: Generates an over-sampled bit string to drive the H-bridge output amplifier such that when filtered

reproduces the desired analog waveform.

Characteristics: A 32 times over-sampled modulator multi-bit design. Specifications

(input_data)

clk

PARAMETER

Signal; BW = 10 kHz 40 kHz

TEST CONDITIONS MIN TYP MAX UNIT

640 kHz

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H-Bridge Load Switching

AVSS

Idle channel, measured at output of channel,

Broadband noise

Idle channel, measured at output of channel,

Vrms

Maximum output swing

SLAS382 − JUNE 2003

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H-bridge Output Driver Function: An H-bridge output driver efficiently converts the delta sigma DAC modulator output signals. The external

load provides the low-pass filtering that recovers the differential analog signal from the H-bridge. Characteristics: Standard H-bridge configuration with transistors sized to differentially drive the load impedance.

The load impedance is complex and a function of frequency.

Inverting Phase

VDD ( vbat)

OUTMM

OUTP OUTM

Receiver

Load

AVSS

OUTPP

NOTE:

Noninverting Phase

VDD (vbat)

OUTPM

OUTP OUTM

OUTMP

VDD does not necessarily have to be connected to the same potential as AVDD, it could be connected to a higher potential than A VDD, equal to A V DD, but not less than AVDD.

Receiver

Load

OUTMM

OUTPP

OUTPM

OUTMP

Figure 4. Definition of Phase and Output Switching Current Polarity

Specifications at 25°C, HB_VDD = 1.3 V

PARAMETER

Block Parameters

DC offset Idle channel; Differential across VOUT_P and VOUT_M −5 0 5 mV

BW = 100 Hz−10 kHz, HB_VDD = 1.3 V , A-weighted THD BW = 100 Hz−10 kHz 0.03% Switching frequency 640 kHz

TEST CONDITIONS MIN TYP MAX UNIT

Fixed Q 33 Adaptive Q 12

Fixed Q 3/4 HB_VDD Adaptive Q HB_VDD

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