Texas Instruments 74AC11139PWR, 74AC11139PWLE, 74AC11139N, 74AC11139DR, 74AC11139D Datasheet
74AC11139
DUAL 2-LINE DECODER/DEMULTIPLEXER
SCAS070B – JULY 1989 – REVISED APRIL 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
D
Incorporates Two Enable Inputs to Simplify
Cascading and/or Data Reception
D
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
500-mA Typical Latch-Up Immunity at
125°C
D
Package Options Include Plastic
Small-Outline (D) and Thin Shrink
Small-Outline (PW) Packages, and
Standard Plastic 300-mil DIPs (N)
description
The 74AC11139 circuit is designed to be used in high-performance memory-decoding or data-routing
applications requiring very short propagation delay times. In high-performance memory systems, this decoder
can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing
a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than
the typical access time of the memory . This means that the effective system delay introduced by the decoder
is negligible.
The 74AC11139 is composed of two individual 2-line to 4-line decoders in a single package. The active-low
enable input can be used as a data line in demultiplexing applications. This decoder/demultiplexer features fully
buffered inputs, each of which represents only one normalized load to its driving circuit.
The 74AC11139 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
ENABLE
INPUT
SELECT
INPUTS
OUTPUTS
G
A B Y0 Y1 Y2 Y3
H X X H H H H
L L LLHHH
L H LHLHH
L L HHHLH
L H H H H H L
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1Y1
1Y2
1Y3
GND
2Y0
2Y1
2Y2
2Y3
1Y0
1A
1B
1G
V
CC
2G
2A
2B
D, N, OR PW PACKAGE
(TOP VIEW)
74AC11139
DUAL 2-LINE DECODER/DEMULTIPLEXER
SCAS070B – JULY 1989 – REVISED APRIL 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbols (alternatives)
†
X/Y
1
15
1A
2
14
1B
EN
13
10
2B
9
11
2A
1Y0
16
0
1Y1
1
1
1Y2
2
2
1Y3
3
3
2Y0
5
2Y1
6
2Y2
7
2Y3
8
DMUX
0
15
1A
1
14
1B
13
9
2B
11
10
2A
1Y0
16
0
1Y1
1
1
1Y2
2
2
1Y3
3
3
2Y0
5
2Y1
6
2Y2
7
2Y3
8
G
3
0
1G
1G
2G
2G
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1A
1Y3
1Y2
1Y1
1Y0
Data
Outputs
Select
Inputs
15
16
1
2
3
1B
14
Enable 1G
13
2A
2Y3
2Y2
2Y1
2Y0
Select
10
6
7
8
2B
9
Enable 2G
11
5
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