Texas Instruments 74AC11008PWR, 74AC11008PWLE, 74AC11008N, 74AC11008DR, 74AC11008D Datasheet

74AC11008

QUADRUPLE 2-INPUT POSITIVE-AND GATE

SCAS014C – AUGUST 1987 – REVISED APRIL 1996

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Flow-Through Architecture Optimizes
PCB Layout

D

Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise

D

EPIC

 (Enhanced-Performance Implanted

CMOS) 1-µm Process

D

500-mA Typical Latch-Up Immunity at
125°C

D

Package Options Include Plastic
Small-Outline (D) and Thin Shrink
Small-Outline (PW) Packages, and
Standard Plastic 300-mil DIPs (N)

description

This device contains four independent 2-input AND gates. It performs the Boolean function

Y+A • BorY

+A)

B

in positive logic.

The 74AC11008 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A B

Y

H H H
L XL
X L L

logic symbol

†

1

1A

16

1B

1Y

2

15

2A

14

2B

2Y

3

11

3A

10

3B

3Y

6

9

4A

8

4B

4Y

7

&

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Copyright  1996, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC is a trademark of Texas Instruments Incorporated.

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

1A
1Y

2Y
GND
GND

3Y

4Y

4B

1B
2A
2B
V

CC

V

CC

3A
3B
4A

D, N, OR PW PACKAGE

(TOP VIEW)

74AC11008
QUADRUPLE 2-INPUT POSITIVE-AND GATE

SCAS014C – AUGUST 1987 – REVISED APRIL 1996

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1Y

1A
1B

1
16

2

2Y

2A
2B

15
14

3

3Y

3A
3B

11
10

6

4Y

4A
4B

9
8

7

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through V

CC

or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum power dissipation at TA = 55°C (in still air) (see Note 2):D package 1.3 W. . . . . . . . . . . . . . . . . . . .

N package 1.1 W. . . . . . . . . . . . . . . . . . . .

PW package 0.5 W. . . . . . . . . . . . . . . . . . .

Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The maximum package power dissipation is calculated using a junction temperature of 150_C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.

74AC11008

QUADRUPLE 2-INPUT POSITIVE-AND GATE

SCAS014C – AUGUST 1987 – REVISED APRIL 1996

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

MIN NOM MAX UNIT

V

CC

Supply voltage 3 5 5.5 V

VCC = 3 V 2.1

V

IH

High-level input voltage

VCC = 4.5 V

3.15

V
VCC = 5.5 V 3.85
VCC = 3 V 0.9

V

IL

Low-level input voltage

VCC = 4.5 V

1.35

V
VCC = 5.5 V 1.65

V

I

Input voltage 0 V

CC

V

V

O

Output voltage 0 V

CC

V
VCC = 3 V –4

I

OH

High-level output current

VCC = 4.5 V

–24

mA
VCC = 5.5 V –24
VCC = 3 V 12

I

OL

Low-level output current

VCC = 4.5 V

24

mA
VCC = 5.5 V 24

∆t/∆v Input transition rise or fall rate 0 10 ns/V
T

A

Operating free-air temperature –40 85 °C

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

TA = 25°C

PARAMETER

TEST CONDITIONS

V

CC

MIN TYP MAX

MIN

MAX

UNIT

3 V 2.9 2.9

IOH = –50 µA

4.5 V 4.4 4.4

5.5 V 5.4 5.4

V

OH

IOH = –4 mA 3 V 2.58 2.48

V

4.5 V 3.94 3.8

IOH = –24 mA

5.5 V 4.94 4.8

IOH = –75 mA

†

5.5 V 3.85
3 V 0.1 0.1

IOL = 50 µA

4.5 V 0.1 0.1

5.5 V 0.1 0.1

V

OL

IOL = 12 mA 3 V 0.36 0.44

V

4.5 V 0.36 0.44

I

OL

= 24

mA

5.5 V 0.36 0.44

IOL = 75 mA

†

5.5 V 1.65

I

I

VI = VCC or GND 5.5 V ±0.1 ±1 µA

I

CC

VI = VCC or GND, IO = 0 5.5 V 4 40 µA

C

i

VI = VCC or GND 5 V 3.5 pF

†

Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.

74AC11008
QUADRUPLE 2-INPUT POSITIVE-AND GATE

SCAS014C – AUGUST 1987 – REVISED APRIL 1996

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended operating free-air temperature range,
V

CC

= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)

FROM TO

TA = 25°C

PARAMETER

(INPUT) (OUTPUT)

MIN TYP MAX

MIN

MAX

UNIT

t

PLH

1.5 6.3 9 1.5 10.2

t

PHL

A or B

Y

1.5 5.6 7.8 1.5 8.6

ns

switching characteristics over recommended operating free-air temperature range,
V

CC

= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)

FROM TO

TA = 25°C

PARAMETER

(INPUT) (OUTPUT)

MIN TYP MAX

MIN

MAX

UNIT

t

PLH

1.5 4.3 6.2 1.5 6.9

t

PHL

A or B

Y

1.5 5.6 5.9 1.5 6.5

ns

operating characteristics, VCC = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS TYP UNIT

C

pd

Power dissipation capacitance per gate CL = 50 pF, f = 1 MHz 29 pF

PARAMETER MEASUREMENT INFORMATION

LOAD CIRCUIT

From Output

Under Test

CL = 50 pF

(see Note A)

500 Ω

t

PLH

t

PHL

50% V

CC

50% V

CC

V

CC

0 V

50% V

CC

50% V

CC

V

OH

V

OL

Input

(see Note B)

Output

VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.

Figure 1. Load Circuit and Voltage Waveforms

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1998, Texas Instruments Incorporated