3.3V V
CC
1,8,19,26,33,42,49
56,70,75,86,93,100
107,116,128,136,138,
145,157,165,172
I 3.3-V power input
5V V
CC
12,40,60,63
84,109,135,162
I 5-V tolerant power input. When interfacing with a 3.3-V parts, these termi-
nals should be connected to 3.3-V power.
autoboot 159 I Autoboot to select autoboot mode
aux_adr15–0 98,99,101,103–106
108,1 10–113,1 15
1 17–119
O Auxiliary port address lines
aux_clk 64 O Auxiliary port clock out (output at frequency of PCI clock)
aux_csz 69 O Auxiliary port chip select
aux_data15–0 76–78,80–83,85,87
88,90–92,94,96,97
I/O Auxiliary port bidirectional data bus to external logic
aux_intz 61 I Auxiliary port interrupt
aux_oez 74 O Auxiliary port output enable
aux_rdy 62 I Auxiliary port ready indication (from external logic)
aux_rstz 66 O Auxiliary port reset out
aux_wez1–0 71,73 O Auxiliary port write strobes (to external logic)
GND 6,14,21,28,35,45
51,65,72,79,89,95
102,114,121,130,141
150,155,158,160,168
175
I Ground
gpio_data3–0 122–125 I/O Auxiliary port general purpose programmable I/O signals
link_cyclein 137 I Optional external 8-kHz clock
link_cycleout 139 O Cycle timer 8-kHz cycle clock out
N/C 2,29,46,120 Not connected
pci_ad31–0 169–171,173,174,176
3,4,9–11,13,15–18
36–39,41,43,44,47,50
52–55,57–59
I/O PCI multiplexed address/data bus signals
pci_cbez3–0 5,20,34,48 I/O PCI multiplexed command/byte enable signals
pci_clk 161 I PCI system clock
pci_devselz 25 I/O PCI device select
pci_framez 22 I/O PCI frame signal