Texas Instruments 5962-8759501KA Datasheet

5 6 7 8 9 10 11

25 24 23 22 21 20 19

432128

12 13 14 15 16

OE B1 B2 NC B3 B4 B5

A1 A2 A3

NC

A4 A5 A6

DIR

SAB

CLKAB

B8

B7

A8

GND

NC

CLKBA

SBA

V

A7

B6

17 18

27 26

NC – No internal connection

CC

CLKAB

SAB

DIR

A1 A2 A3 A4 A5 A6 A7 A8

GND

V

CC

CLKBA SBA OE B1 B2 B3 B4 B5 B6 B7 B8

1 2 3 4 5 6 7 8 9 10 11 12

24 23 22 21 20 19 18 17 16 15 14 13

SN54ALS646, SN54ALS648, SN54AS646 . . . JT PACKAGE

SN74ALS646A, SN74ALS648A, SN74AS646,

SN74AS648 . . . DW OR NT PACKAGE

(TOP VIEW)

SN54ALS646, SN54ALS648, SN54AS646 . . . FK PACKAGE

(TOP VIEW)

SN54ALS646, SN54ALS648, SN54AS646

SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648

OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STA TE OUTPUTS

SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995

Copyright  1995, Texas Instruments Incorporated

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

• Independent Registers for A and B Buses

• Multiplexed Real-Time and Stored Data

• Choice of True or Inverting Data Paths

• Choice of 3-State or Open-Collector

Outputs

• Package Options Include Plastic

Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs

DEVICE OUTPUT LOGIC

SN54ALS646, SN74ALS646A, ′AS646 3 state True SN54ALS648, SN74ALS648A, SN74AS648 3 state Inverting

description

These devices consist of bus-transceiver circuits with 3-state or open-collector outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the octal bus transceivers and registers.

Output-enable (OE

) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the highimpedance port may be stored in either or both registers.

The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. DIR determines which bus receives data when OE

is low. In

the isolation mode (OE

high), A data may be stored in one register and/or B data may be stored in the other

register. When an output function is disabled, the input function is still enabled and can be used to store and transmit

data. Only one of the two buses, A or B, may be driven at a time. The -1 version of the SN74ALS646A is identical to the standard version, except that the recommended

maximum I

OL

in the -1 version is increased to 48 mA. There are no -1 versions of the SN54ALS646,

SN54ALS648, or SN74ALS648A. The SN54ALS646, SN54ALS648, and SN54AS646 are characterized for operation over the full military

temperature range of –55°C to 125°C. The SN74ALS646A, SN74ALS648A, SN74AS646, and SN74AS648 are characterized for operation from 0°C to 70°C.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

SN54ALS646, SN54ALS648, SN54AS646 SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STA TE OUTPUTS

SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

21

L

3

DIR

L

1

CLKAB

X

23

CLKBA

X

2

SAB

X

22

SBA

L

REAL-TIME TRANSFER

BUS B TO BUS A

21

L

3

DIR

H

1

CLKAB

X

23

CLKBA

X

2

SAB

L

22

SBA

X

REAL-TIME TRANSFER

BUS A TO BUS B

21

X

3

DIR

X

1

CLKAB23CLKBA

X

2

SAB

X

22

SBA

X

STORAGE FROM A, B, OR A AND B

21

L

3

DIR

L

1

CLKAB

X

23

CLKBA

H or L

2

SAB

X

22

SBA

H

TRANSFER STORED DATA

TO A AND/OR B

X H

X X

XX

X

X X

L H H or L X H X

↑

↑ ↑↑

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

OE OE

OEOE

Figure 1. Bus-Management Functions

Pin numbers shown are for the DW, JT, and NT packages.

SN54ALS646, SN54ALS648, SN54AS646

SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648

OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STA TE OUTPUTS

SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Function Tables

SN54ALS646, SN54AS646, SN74ALS646A, SN74AS646

INPUTS

DATA I/O

OE

DIR CLKAB CLKBA SAB SBA A1–A8 B1–B8

OPERATION OR FUNCTION

X X ↑ X X X Input Unspecified

†

Store A, B unspecified

†

X XX ↑X X Unspecified

†

Input Store B, A unspecified

†

H X ↑ ↑ X X Input Input Store A and B data H X H or L H or L X X Input disabled Input disabled Isolation, hold storage L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus L H X X L X Input Output Real-time A data to B bus L H H or L X H X Input Output Stored A data to B bus

†

The data output functions can be enabled or disabled by various signals at OE and DIR. Data input functions are always enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

SN54ALS648, SN74ALS648A, SN74AS648

INPUTS

DATA I/O

OE

DIR CLKAB CLKBA SAB SBA A1–A8 B1–B8

OPERATION OR FUNCTION

X X ↑ X X X Input Unspecified

†

Store A, B unspecified

†

X XX ↑X X Unspecified

†

Input Store B, A unspecified

†

H X ↑ ↑ X X Input Input Store A and B data H X H or L H or L X X Input disabled Input disabled Isolation, hold storage L L X X X L Output Input Real-time B data to A bus L L X H or L X H Output Input Stored B data to A bus L H X X L X Input Output Real-time A data to B bus L H H or L X H X Input Output Stored A data to B bus

†

The data output functions can be enabled or disabled by various signals at OE and DIR. Data input functions are always enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

SN54ALS646, SN54ALS648, SN54AS646 SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STA TE OUTPUTS

SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbols

†

A1

4

B1

20

4D

5

7

5

1

6D ≥1

≥1

1

2

A2

5

B2

19

A3

6

B3

18

A4

7

B4

17

A5

8

B5

16

A6

9

B6

15

A7

10

B7

14

A8

11

B8

13

SN54ALS646, SN54AS646,

SN74ALS646A, SN74AS646

OE

G3

21

3 EN2 [AB]

G5

22

SBA

3 EN1 [BA]

3

DIR

23

CLKBA

1

CLKAB

G7

2

SAB

C6

C4

A1

4

B1

20

4D

5

7

5

1

6D ≥1

≥1

1

2

A2

5

B2

19

A3

6

B3

18

A4

7

B4

17

A5

8

B5

16

A6

9

B6

15

A7

10

B7

14

A8

11

B8

13

SN54ALS648,

SN74ALS648A, SN74AS648

OE

G3

21

3 EN2 [AB]

G5

22

SBA

3 EN1 [BA]

3

DIR

23

CLKBA

1

CLKAB

G7

2

SAB

C6

C4

†

These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

Pin numbers shown are for the DW, JT, and NT packages.

SN54ALS646, SN54ALS648, SN54AS646

SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648

OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STA TE OUTPUTS

SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagrams (positive logic)

A1

B1

1D

C1

1D

C1

One of Eight Channels

20

4

2

1

22

23

21

3

SAB

CLKAB

SBA

CLKBA

DIR

OE

To Seven Other Channels

SN54ALS646, SN54AS646, SN74ALS646A, SN74AS646

A1

B1

1D

C1

1D

C1

One of Eight Channels

20

4

2

1

22

23

21

3

SAB

CLKAB

SBA

CLKBA

DIR

OE

To Seven Other Channels

SN54ALS648,

SN74ALS648A, SN74AS648

Pin numbers shown are for the DW, JT, and NT packages.

SN54ALS646, SN54ALS648, SN54AS646 SN74ALS646A, SN74ALS648A, SN74AS646, SN74AS648 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STA TE OUTPUTS

SDAS039F – DECEMBER 1983 – REVISED JANUARY 1995

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage, V

CC

7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage, V

I

: Control inputs 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O ports 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

: SN54ALS646 –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74ALS646A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

SN54ALS646 SN74ALS646A

MIN NOM MAX MIN NOM MAX

UNIT

V

CC

Supply voltage 4.5 5 5.5 4.5 5 5.5 V

V

IH

High-level input voltage 2 2 V

V

IL

Low-level input voltage 0.7 0.8 V

I

OH

High-level output current –12 –15 mA

12 24

IOLL

ow-level output curren

t

48

‡

m

A

f

clock

Clock frequency 0 35 0 40 MHz

t

w

Pulse duration, CLKBA or CLKAB high or low 14.5 12.5 ns

t

su

Setup time, A before CLKAB↑ or B before CLKBA↑ 15 10 ns

t

h

Hold time, A after CLKAB↑ or B after CLKBA↑ 0 0 ns

T

A

Operating free-air temperature –55 125 0 70 °C

‡

Applies only to the -1 version and only if VCC is maintained between 4.75 V and 5.25