TEXAS INSTRUMENTS UC1525A, 27A, UC2525A, UC3525A Technical data

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Regulating Pulse Width Modulators

UC1525A/27A
UC2525A/27A
UC3525A/27A

FEATURES

8 to 35V Operation

•

5.1V Reference Trimmed to±1%

•

100Hz to 500kHz Oscillator Range

•

Separate Oscillator Sync Terminal

•

Adjustable Deadtime Control

•

Internal Soft-Start

•

Pulse-by-Pulse Shutdown

•

Input Undervoltage Lockout with

•

Hysteresis
Latching PWM to Prevent Multiple

•

Pulses
Dual Source/Sink Output Drivers

•

BLOCK DIAGRAM

DESCRIPTION

The UC1525A/1527A series of pulse width modulator integrated circuits are de
signed to offer improved performance and lowered external parts count when
used in designing all types of switching power supplies. The on-chip +5.1V ref
erence is trimmed to±1% and the input common-mode range of the error ampli
fier includes the reference voltage, eliminating external resistors. A sync input to
the oscillator allows multiple units to be slaved or a single unit to be synchro
nized to an external system clock. A single resistor between the C
charge terminals provides a wide range of dead-time adjustment. These
devices also feature built-in soft-start circuitry with only an external timing ca
pacitor required. A shutdown terminal controls both the soft-start circuitry and
the output stages, providing instantaneous turn off through the PWM latch with
pulsed shutdown, as well as soft-start recycle with longer shutdown commands.
These functions are also controlled by an undervoltage lockout which keeps the
outputs off and the soft-start capacitor discharged for sub-normal input volt
ages. This lockout circuitry includes approximately 500mV of hysteresis for jit
ter-free operation. Another feature of these PWM circuits is a latch following the
comparator. Once a PWM pulse has been terminated for any reason, the out­puts will remain off for the duration of the period. The latch is reset with each
clock pulse. The output stages are totem-pole designs capable of sourcing or
sinking in excess of 200mA. The UC1525A output stage features NOR logic,
giving a LOW output for an OFF state. The UC1527A utilizes OR logic which
results in a HIGH output level when OFF.

and the dis

T

-

-

-

-

-

-

-

-

OSC

VR EF

OUT

16

4

13

NOR

11

NOR

14

UC1525AO utput S tage

13

OR

11

OR

14

UC1527AO utput S tage

5kΩ

UVLO

Lockout

COMP

V

REF

50 µA

F lip

Flop

R

S

PWM
La tch

S

3kΩ

Reference

Regulator

Error
Amp

OSC

To inte rna l

circuitry

15

+VIN

SYNC

NI INP UT

RT

CT

12

3

6

5

7

9

1

2

8

10

GROUND

DISCHARG E

COMPENSATION

INV INPUT

SOFTSTART

SHUTDO WN OUTPUT B

VC

OUTPUT A

OUTPUT B

VC

OUTPUT A

SLUS191B - February 1997 - Revised June 2005

UC1525A/27A
UC2525A/27A
UC3525A/27A

ABSOLUTE MAXIMUM RATINGS(Note 1)

Supply Voltage, (+VIN)............................+40V

Collector Supply Voltage (V

)......................+40V

C

Logic Inputs ............................–0.3V to +5.5V

Analog Inputs............................–0.3V to +V

IN

Output Current, Source or Sink ...................500mA

Reference Output Current ........................50mA

Oscillator Charging Current ........................5mA

Power Dissipation at T
Power Dissipation at T

= +25°C (Note 2)..........1000mW

A

= +25°C (Note 2) .........2000mW

C

Operating Junction Temperature ..........–55°C to +150°C

Storage Temperature Range .............–65°C to +150°C

Lead Temperature (Soldering, 10 seconds) .........+300°C

Note 1: Values beyond which damage may occur.
Note 2: Consult packaging Section of Databook for thermal

limitations and considerations of package.

CONNECTION DIAGRAMS

DIL-16 (TOP VIEW)
J or N Package

RECOMMENDED OPERATING CONDITIONS

(Note 3)

Input Voltage (+VIN) .......................+8Vto+35V

Collector Supply Voltage (V

Sink/Source Load Current (steady state) ........0to100mA

Sink/Source Load Current (peak) ..............0to400mA

Reference Load Current ......................0to20mA

Oscillator Frequency Range..............100Hz to 400kHz

Oscillator Timing Resistor ..................2kΩ to 150kΩ

Oscillator Timing Capacitor ................001µFto.01µF

Dead Time Resistor Range ....................0to500Ω

Operating Ambient Temperature Range

UC1525A, UC1527A..................–55°C to +125°C

UC2525A, UC2527A...................–25°C to +85°C

UC3525A, UC3527A.....................0°Cto+70°C

Note 3: Range over which the device is functional and parame

ter limits are guaranteed.

PLCC-20, LCC-20 (TOP VIEW)
Q, L Package

)...............+4.5V to +35V

C

PACKAGE PIN FUNCTION

FUNCTION PIN

N/C 1
Inv. Input 2
N.I. Input 3
SYNC 4
OSC. output 5
N/C 6
C

T

R

T

7

8
Discharge 9
Softstart 10
N/C 11
Compensation 12
Shutdown 13
Output A 14
Ground 15
N/C 16
V

C

17
Output B 18
+V
V

IN

REF

19

20

-

2

ELECTRICAL CHARACTERISTICS:+V

UC1525A/27A
UC2525A/27A
UC3525A/27A

= 20V, and over operating temperature, unless otherwise specified, TA=T

IN

.

J

PARAMETER TEST CONDITIONS

UC1525A/UC2525A
UC1527A/UC2527A

UC3525A
UC3527A

MIN TYP MAX MIN TYP MAX

Reference Section

Output Voltage T
Line Regulation V
Load Regulation I

= 25°C 5.05 5.10 5.15 5.00 5.10 5.20 V

J

= 8 to 35V 10 20 10 20 mV

IN

= 0 to 20mA 20 50 20 50 mV

L

Temperature Stability (Note 5) Over Operating Range 20 50 20 50
Total Output Variation (Note 5) Line, Load, and Temperature 5.00 5.20 4.95 5.25 V
Shorter Circuit Current V
Output Noise Voltage (Note 5)
Long Term Stability (Note 5) T

=0,TJ= 25°C 80 100 80 100 mA

REF

≤°

10Hz 10kHz, T = 25 C

= 125°C 20 50 20 50 mV

J

J

40 200 40 200

Oscillator Section(Note 6)

Initial Accuracy (Notes5&6) T
Voltage Stability (Notes5&6) V
Temperature Stability (Note 5) Over Operating Range
Minimum Frequency R
Maximum Frequency R
Current Mirror I

= 25°C

J

=8to35V

IN

± 2 ± 6 ± 2 ± 6

± 0.3 ± 1 ± 1 ± 2

± 3 ± 6 ± 3 ± 6

= 200kΩ,CT= 0.1µF 120 120 Hz

T

=2kΩ,CT= 470pF 400 400 kHz

T

= 2mA 1.7 2.0 2.2 1.7 2.0 2.2 mA

RT

Clock Amplitude (Notes5&6) 3.0 3.5 3.0 3.5 V
Clock Width (Notes5&6) T

= 25°C 0.3 0.5 1.0 0.3 0.5 1.0

J

Sync Threshold 1.2 2.0 2.8 1.2 2.0 2.8 V
Sync Input Current Sync Voltage = 3.5V 1.0 2.5 1.0 2.5 mA

Error Amplifier Section(V

CM

= 5.1V)
Input Offset Voltage 0.5 5 2 10 mV
Input Bias Current 1 10 1 10
Input Offset Current 1 1
DC Open Loop Gain R
Gain-Bandwidth Product

≥ 10MΩ 60 75 60 75 dB

L

= 0dB, TJ= 25°C 1 2 1 2 MHz

A

V

(Note 5)

DC Transconductance

=25°C, 30kΩ≤RL≤ 1MΩ 1.1 1.5 1.1 1.5 mS

T

J

(Notes5&7)
Output Low Level 0.2 0.5 0.2 0.5 V
Output High Level 3.8 5.6 3.8 5.6 V
Common Mode Rejection V
Supply Voltage Rejection V

= 1.5 to 5.2V 60 75 60 75 dB

CM

= 8 to 35V 50 60 50 60 dB

IN

Note 5: These parameters, although ensured over the recommended operating conditions, are not 100% tested in production.
Note 6: Tested at f

f

=

CR

TTD

Note 7: DC transconductance (g

= 40kHz (RT= 3.6kW,CT= 0.01mF, RD=0W). Approximate oscillator frequency is defined by:

OSC

1

+

0.7 3R()

) relates to DC open-loop voltage gain (AV) according to the following equation: AV=gMR

M

where RLis the resistance from pin 9 to ground. The minimum gMspecification is used to calculate minimum AVwhen the
error amplifier output is loaded.

UNITS

µVrm s

%
%
%

µs

µA

µA

L

3