Tektronix TLA5000B DATASHEET

Logic Analyzers

TLA5000B Series Data Sheet

Applications

Features & Beneﬁts

500 ps (2 G Hz)/32 Mb timing record length to c apt ure intermittent events over a wi

125 ps resolution MagniVu™ acquisition simultaneous with timing or state acquisition to ﬁnd elusive timing problems quickly, without double probing

Glitch and setup/hold violation triggering and display to ﬁnd and display elusive hardware problems

235 MHz digital circuits

iView™ time-correlated digital-analog view to clearly see how analog anomalies are affecting your digital signals

34/68/102/136 channel conﬁ gurations offer ﬂexible solutions to ﬁt any budget

Micros interface with network connectivity

Remotely control and monitor the TLA over the network using either hosted mode or the built-in Windows XP remote desktop

de time window

state acquisition provides analysis of high-speed synchronous

oft Windows XP Professional PC controller provides familiar user

Digital hard

Monitoring and measurement of digital hardware performance

Single microprocessor or bus debug

TLA5000B Se debug power

The affordable TLA5000B Series logic analyzers make high-speed timing resolution triggering available to any digital designer who needs to identify initialization failures, operation crashes, and intermittent operation. For ﬁrst-time as well as experienced logic analyzer users, the TLA5000B Series is ideal for single-bus timing and state analysis. An intuitive user interface, familiar Windows-based desktop, and OpenChoice features ma your design environment.

500 ps timi MagniVu timing resolution within each acquisition means you can measure digital signal timing on increasingly faster signals with conﬁdence. With MagniVu timing resolution, ﬁnd difﬁcult problems such as digital logic errors, glitches, setup/hold violations, and crosstalk quickly. Use setup/hold violation triggering and display to validate setup/hold performance of digital devices.

Today, most designs can have both digital and analog anomalies. With iView™ tim anomalies are affecting your digital signals—right on your logic analyzer display.

ware veriﬁcation and debug

ries logic analyzers combine with simplicity and affordability

, fast state acquisition, long record length, and sophisticated

networking and analysis

ke the TLA5000B Series logic analyzers easy to network into

ng resolution and 32 Mb record length with simultaneous 125 ps

e-correlated digital-analog view, you’ll clearly see how analog

Data Sheet

Characteristics

General

Number of Channels – (all channels are acquired including clocks).

TLA5201B: 34 channels (2 are clock channels). TLA5202B: 68 channels (4 are clock channels). TLA5203B: 102 channels (4 are clock and 2 are qualiﬁer channels). TLA5204B: 136 channels (4 are clock and 4 are qualiﬁer channels).

Time Stamp – 51 bits at 125 ps resolution (3.25 days duration).

Clocking/Acquisition Modes – Asynchronous and Synchronous. 125 ps (8 GHz)

MagniVu™ high-speed timing is available simultaneous with all modes.

Input C haracteristics (with P64xx probes)

Capacitive Loading –

<0.7 pF typical data/clock (P6419, P6450). 2 pF typical data/clock (P6410, P6434).

Threshold Selection Range – From -2.0 V to +4.5 V in 5 mV increments.

Threshold presets include TTL (1.5 V), CMOS (1.65 V), ECL (–1.3 V), PECL (3.7 V), LVPECL (2.0 V), LVCMOS 1.5 V (0.75 V), LVCMOS 1.8 V (0.9 V), LVCMOS 2.5 V (1.25 V), LVCMOS 3.3 V (1.65 V), LVDS (0 V), and user deﬁned.

Threshold Selection Channel Granularity – Separate selection for each of the

clock/qualiﬁer channels and one per group of 16 data channels.

Threshold Accuracy (including probe) – ±(100 mV).

Input Voltage Range –

Operating: -2.5 V to 5.0 V. Nondestructive: ±15 V.

Minimum Input Signal Swing –

±250 mV (P6410, P6419, P6450). ±300 mV (P6434).

Input Signal Minimum Slew Rate – 200 mV/ns typical.

State Acquisition Characteristics

Maximum State Clock Rate – 235 MHz.

Maximum State Data Rate – 470 Mb/s.

State Record Length with Time Stamps (half/full channels) – 4/2 Mb , 16/8 Mb,

64/32 Mb.

Setup-and-Hold Time Selection Range – 16 ns range that may be shifted towards the

setup region by 0 ns [+8, -8] ns, 4 ns [+12, -4] ns, or 8 ns [+16, 0] ns.

Setup-and-Hold Window –

All Channels: 1.5 ns typical.

Minimum Clock Pulse Width –

1.5 ns (P6434).

1.25 ns (P6410, P6419, P6450).

ux Channel Selection –

Dem

through user interface with 8-channel granularity.

Channels can be demultiplexed to other channels

Timing Acquisition Characteristics

MagniVu™ Timing Resolution – 125 ps (8 GHz).

Storage rate adjustable to 250 ps, 500 ps, 1 ns, a nd 2 ns.

MagniVu Timing Record Length – 16 Kb per channel, with adjustable trigger position. Timing Resolution (quarter/half/full channels) – 500ps/1ns/2nsto50ms. Timing Record Length (quarter/half/full channels with time stamps and with or without trans Timing Recor

length.

Channel-to-channel Skew – 1 ns (900 ps typical). Minimum Recognizable Pulse/Glitch Width (single channel) – 1 ns (P6410, P6419,

P6450) 1.25 ns (P6434).

Minimum Detectable Setup/Hold Violation – 250 ps. Minimum Recognizable Multichannel Trigger Event – Sample period +

channel-to

Trigger Cha

Independe Maximum In Maximum Nu Maximum Nu Maximum Nu

resources).

Number of Word Recognizers – 16. Number of Transition Recognizers – 16. Number of Range Recognizers – 4. Number of Counter/Timers – 2. Trigger Event Types – Word, group, channel, transition, range, anything, counter

value, timer value, signal, glitch, setup-and-hold violation, snapshot.

Trigger Action Types – Trigger main, trigger MagniVu™, store, don’t store, start

store, s stop timer, reset timer, snapshot current sample, goto state, set/clear signal, do nothing.

Trigger Sequence Rate – DC to 500 MHz (2 ns). Counter/Timer Range – 51 bits each (>50 days at 2 ns). Counter Rate – DC to 500 MHz (2 ns). Timer Clock Rate – 500 MHz (2 ns). Counter/Timer Latency – 2ns. Range Recognizers – Double bounded (can be as wide as any group, must be

groupe

Setup

7.5 ns after clock edge in 125 ps increments.

Setup-and-Hold Violation Recognizer Hold Time Range – From 7.5 ns before to 8 ns

after clock edge in 125 ps increments.

Trigger Position – Any data sample. MagniVu™ Trigger Position – MagniVu position can be set from 0% to 60% centered

arou

Stor

block, by trigger action, or transitional. Force main preﬁll selection available.

itional storage) –

dLengthwithGlitchStorageEnabled–

8/4/2 Mb, 32/16/8 Mb, 128/64/32 Mb per channel.

Half of default main record

-channel skew.

racteristics

nt Trigger States –

dependent If/Then Clauses per State –

mber of Events per If/Then Clause – mber of Actions per If/Then Clause – mber of Trigger Events –

top store, increment counter, decrement counter, reset counter, start timer,

daccordingtospeciﬁed order of signiﬁcance).

-and-Hold Violation Recognizer Setup Time Range –

nd the MagniVu trigger.

age Control (data qualiﬁcation) –

16.

18 (2 counter/timers plus any 16 other

From 8 ns before to

Global (conditional), by state (start/stop),

2 www.tektronix.com

Logic Analyzers — TLA5000B Series

iView™ (Integrated View) Capability

Number of Oscilloscopes that can be Connected to a TLA System – 1. External Oscilloscopes Supported – For a complete list of currently

supported oscilloscopes that are supported, please visit our website http://www.t

TLA Con nectio Oscilloscope

ektronix.com/iview.

ns –

USB, Trigger In, Trigger Out, Clock Out.

Connections –

GPIB, Trigger In, Trigger Out, Clock In (when available)

for the GPIB iView cable (Opt 1C).

Setup – iView external oscilloscope wizard automates setup. Data Correlation – After oscilloscope acquisition is complete, data is automatically

transferred to the TLA and time correlated with the TLA acquisition data.

Deskew – Oscilloscope and TLA data is automatically deskewed and time correlated

when using th

iView Exter

PC Characte

Operating S

e iView external oscilloscope cable.

nal Oscilloscope Cable Length –

2m.

ristics

ystem –

Microsoft Windows XP Professional with Multilingual User

Interface Pack.

Processor – Intel Celeron 2.0 GHz. Chipset – Intel 865G. DRAM – 512 MB SDRAM. Sound – 16 bit I/O and Mic In port. Hard Drive – ≥80 GB. Optical Drive – Internal 24/10/24 CD-RW.

Integral Controls

Front-panel Display –

Size: 10.4 in. (26.4 cm) diagonal.

ive-matrix color TFT LCD with backlight.

Type: Act Resolution: 1024×768. Colors: 256 K.

Simultaneous Display Capability – The front-panel and secondary displays can be

d simultaneously using the same resolution. The secondary external display

operate can be used simultaneously using an independent resolution.

Front-panel Controls – Special function knobs for instrument control and

mini-QWERTY keypad.

External Peripheral Interfaces

External Display Port Type – TwofemaleDB15SVGA.

External Display Resolution – Up to 1600×1200 noninterlaced at 16.8 M colors.

LAN Port Type – 10/100Base-T, RJ-45.

External Keyboard Port Type – PS2 mini-DIN.

External Mouse Port Type – PS2 mini-DIN.

Parallel Interface Port Type – Female DB25.

Parallel Interface Modes – Centronics mode, EPP (Extended Parallel Port), ECP

(Microsoft high-speed mode).

Serial Interface Port Type – Male DB9.

Audio Out Port Type – Stereo minijack.

MicInPortType–Minijack.

USB Port – Four USB 2.0.

Symbolic Support

Number of Symbols/Ranges – Unlimited (limited only by amount of virtual memory

availableonTLA).

Object File Formats Supported – IEEE695, OMF 51, OMF 86, OMF 166, OMF 286,

OMF 386, COFF, Elf/Dwarf 1 and 2, Elf/Stabs, TSF (TSF is a generic ASCII ﬁle format documented in the TLA user manual). If a format is not listed, please contact your local Tektronix representative.

External Instrumentation Interfaces

System Trigger Output – Asserted whenever a system trigger occurs

(TTL-compatible output, back-terminated into 50 Ω). BNC type connector.

System Trigger Input – Forces a system trigger (triggers all modules) when asserted

(TTL-compatible, edge-sensitive, falling-edge latched). BNC type connector.

External Signal Output – Canbeusedtodriveexternalcircuitryfromamodule’s

trigger mechanism (TTL-compatible output, back-terminated into 50 Ω). BNC type connector.

External Signal Input – Can be used to provide an external signal to arm or trigger

any or all modules (TTL-compatible, level-sensitive). BNC type connector.

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