The information in this User’s Manual has been carefully reviewed and is believed to be accurate.
The vendor assumes no responsibility for any inaccuracies that may be contained in this document,
makes no commitment to update or to keep current the information in this manual, or to notify any
person or organization of the updates. Please Note: For the most up-to-date version of this
manual, please see our web site at www.supermicro.com.
Super Micro Computer, Inc. ("Supermicro") reserves the right to make changes to the product
described in this manual at any time and without notice. This product, including software and documentation, is the property of Supermicro and/or its licensors, and is supplied only under a license.
Any use or reproduction of this product is not allowed, except as expressly permitted by the terms
of said license.
IN NO EVENT WILL SUPER MICRO COMPUTER, INC. BE LIABLE FOR DIRECT, INDIRECT,
SPECIAL, INCIDENTAL, SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE
USE OR INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, SUPER MICRO COMPUTER, INC.
SHALL NOT HAVE LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED
WITH THE PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, INTEGRATING,
INSTALLING OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA.
Any disputes arising between manufacturer and customer shall be governed by the laws of Santa
Clara County in the State of California, USA. The State of California, County of Santa Clara shall
be the exclusive venue for the resolution of any such disputes. Supermicro's total liability for all
claims will not exceed the price paid for the hardware product.
FCC Statement: This equipment has been tested and found to comply with the limits for a Class B
digital device pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates,
uses, and can radiate radio frequency energy and, if not installed and used in accordance with the
manufacturer’s instruction manual, may cause interference with radio communications. However,
there is no guarantee that interference will not occur in a particular installation. If this equipment
does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, you are encouraged to try to correct the interference by one or more
of the following measures:
•Reorient or relocate the receiving antenna.
•Increase the separation between the equipment and the receiver.
•Connect the equipment into an outlet on a circuit different from that to which the
receiver is connected.
•Consult the dealer or an experienced radio/television technician for help.
California Best Management Practices Regulations for Perchlorate Materials: This Perchlorate warning applies only to products containing CR (Manganese Dioxide) Lithium coin cells. “Perchlorate
Material-special handling may apply. See www.dtsc.ca.gov/hazardouswaste/perchlorate”.
WARNING: Handling of lead solder materials used in this product
may expose you to lead, a chemical known to the State of California
to cause birth defects and other reproductive harm.
Manual Revision 1.0a
Release Date: May 12, 2012
Unless you request and receive written permission from Super Micro Computer, Inc., you may not
copy any part of this document. Information in this document is subject to change without notice.
Other products and companies referred to herein are trademarks or registered trademarks of their
respective companies or mark holders.
Note: Up to 256GB of memory are supported using ECC QR (Quad
Rank or 4-Rank) registered DIMM technology at 1600/1333/1066/800
MHz. Up to 64GB of memory are supported using non-ECC
UDIMMs.
2-10
Page 37
Chapter 2: Installation
2-4 Motherboard Installation
All motherboards have standard mounting holes to t different types of chassis.
Make sure that the locations of all the mounting holes for both motherboard and
chassis match. Although a chassis may have both plastic and metal mounting fas-
teners, metal ones are highly recommended because they ground the motherboard
to the chassis. Make sure that the metal standoffs click in or are screwed in tightly.
Then use a screwdriver to secure the motherboard onto the motherboard tray.
Tools Needed
Philips Screwdriver
SXB2A
J13
USB/0/1
J17
LAN1
JLAN1
LAN2
JLAN2
JCOM1
1
JTPM1
1920
2
JTPM1: TPM/PORT80
J28
JPL1
1
1
JPL2
1
3
3
JPMB
JIPMB1
COM1
BD1
AC
A
C
LED2
JVGA1
VGA
1
LE2
CA
2-3:DISABLE
2-3:DISABLE
1-2:ENABLE
JPL2:LAN2
1-2:ENABLE
JPL1:LAN1
JUIDB1
2
UID
SXB1A
2
2-3:NIMI
1-2:RST
JWD:
JWP1:
WRITE PROTECT
USB
JOH1:OVER HEAT LED
J26
7
1
JOH1
JWD
A
JPG1
1
3
JI2C2/JI2C3
1-2:Enable
2-3:Disable
JPCIE3
SLOT3 PCIE 3.0X8
1-2:NORMAL
2-3:BIOS RECOVERY
JPR1:
USB
J23
2
2-3:DISABLE
1-2:ENABLE
JPB1: BMC
1-2:NORMAL
2-3:ME RECOVERY
JPME1:
JD1:
4-7:SPEAKER
1-2:PWR_LED
1
7
SP1
+
JD1
7
1
JPB1
3
3
JPME1
MH5
JPG1: VGA
2-3:Disable
1-2:Enable
BT1
2-3:NMI
1-2:RST(DEFAULT)
JWD:WATCH DOG TIMER
1
JI2C3
3
3
1
JI2C2
JPCIE1
SXB1B
I-SATA5
SATA6
SATA5
1
7
Location of Mounting Holes
Caution: 1) To prevent damage to the motherboard and its components,
please do not use a force greater than 8 lb/inch on each mounting screw
during motherboard installation. 2) Some components are very close to the
mounting holes. Please take precautionary measures to avoid damaging
these components when installing the motherboard to the chassis.
Philips Screws
SXB2B
LE1
C
A
JBT1
JBT1:CMOS CLEAR
1
7
7
1
7
SAS1
SAS2
I-SATA2
I-SATA3
I-SATA4
SATA4
SATA3
1
7
7
1
1
7
Standoffs
FANC
FAND
JPW2
JPW3
8
8
5
5
1
FAN1 1
1
4
JPCIE2
1
4
DIMMA1
CPU
REV: 1.00
DESIGNED IN USA
X9SRG
1
1
7
SAS3
SAS4
JSD1:
PWRSDOM
JSTBY1:STAND BY POWER FOR DOM
1
3
JSD1
3
DIMMC1
1
JSTBY1
2
8
I-SATA1
I-SATA0
SATA2
SATA1
8
8
12
7
4
7
1
7
4
1
1
1
FANB
FANA
127
1
11
JL1
20
19
:CHASSIS INTRUSIONJL1
4
1
1
J1
J2
C509
2
1
J3
JF1
J4
PWRHDDXNMI
LEDLED
1
NIC
2
NIC
LED
UID
FAIL
RSTPS
PWR
ON
JF1
FAN2
4
1
4
1
FAN3
J7
J5 J12
J6
4
1
FAN4
10
JI2C1
JPW1
OFF:Disable
JI2C1
ON:Enable
20
1
2-11
Page 38
X9SRG-F Motherboard User’s Manual
Installing the Motherboard
1. Install the I/O shield into the chassis.
2. Locate the mounting holes on the motherboard.
3. Locate the matching mounting holes on the chassis. Align the mounting holes
on the motherboard against the mounting holes on the chassis.
4. Install standoffs in the chassis as needed.
5. Install the motherboard into the chassis carefully to avoid damaging mother-
board components.
6. Using the Philips screwdriver, insert a Pan head #6 screw into a mounting
hole on the motherboard and its matching mounting hole on the chassis.
7. Repeat Step 5 to insert #6 screws into all mounting holes.
8. Make sure that the motherboard is securely placed in the chassis.
Note: Images displayed are is for illustration only. Your chassis or compo-
nents might look different from those shown in this manual.
2-12
Page 39
Chapter 2: Installation
1
11
JPW2
5
8
4
1
JPW3
8
4
FAND
1
FANC
4
1
1
FANA
4
1
DIMMA1
DIMMC1
2-5 Connectors/IO Ports
The I/O ports are color coded in conformance with the PC 99 specication. See the
gure below for the colors and locations of the various I/O ports.
Motherboard I/O Backpanel
SXB2A
USB/0/1
JCOM1
1
COM1
JVGA1
VGA
LE2
CA
UID
J13
2
USB
J23
2
2-3:NIMI
1-2:RST
JWD:
JWP1:
WRITE PROTECT
USB
JOH1:OVER HEAT LED
J26
J17
LAN1
JLAN1
LAN2
JLAN2
1
JTPM1
1920
2
JTPM1: TPM/PORT80
J28
JPL1
1
1
JPL2
3
3
JPMB
JIPMB1
BD1
AC
A
C
LED2
1
2-3:DISABLE
2-3:DISABLE
1-2:ENABLE
JPL2:LAN2
1-2:ENABLE
JPL1:LAN1
JUIDB1
2
SXB1A
1
JOH1
JWD
A
JPG1
1
3
JPCIE3
JD1:
4-7:SPEAKER
1-2:PWR_LED
1
7
7
SP1
JD1
1
JPB1
3
3
JPME1
MH5
BT1
2-3:NMI
1-2:RST(DEFAULT)
JWD:WATCH DOG TIMER
1
JI2C3
3
JI2C2/JI2C3
1-2:Enable
2-3:Disable
3
1
JI2C2
SLOT3 PCIE 3.0X8
SXB2B
1-2:NORMAL
2-3:BIOS RECOVERY
JPR1:
LE1
C
A
2-3:DISABLE
1-2:ENABLE
JPB1: BMC
1-2:NORMAL
2-3:ME RECOVERY
JPME1:
+
7
JPG1: VGA
2-3:Disable
1-2:Enable
JBT1
JBT1:CMOS CLEAR
7
SAS1
JPCIE1
SXB1B
I-SATA5
I-SATA4
SATA6
7
SATA4
SATA5
1
1
7
JPCIE2
CPU
REV:1.00
DESIGNED IN USA
X9SRG
1
7
1
1
1
7
7
SAS3
SAS2
I-SATA3
SATA3
1
7
SAS4
JSD1:
PWRSDOM
JSTBY1:STAND BY POWER FOR DOM
1
3
JSD1
3
1
JSTBY1
2
I-SATA1
I-SATA2
SATA2
7
1
1
7
8
I-SATA0
SATA1
7
8
8
12
7
4
1
FANB
127
1
4
5
6
7
2
3
8
Motherboard I/O Backpanel
1. IPMI LAN5. LAN2
2. USB 2.0 Port 06. COM1
3. USB 2.0 Port 17. VGA
4. LAN18. Unit ID
2-13
Page 40
X9SRG-F Motherboard User’s Manual
Universal Serial Bus (USB)
Two (2) Universal Serial Bus 2.0 ports
are located on the I/O back panel.
There are also four (4) USB 2.0 ports
on two headers on the motherboard
that may be used to provide front
chassis access using USB cables (not
included). See the tables below for pin
denitions.
1. Back Panel USB 2.0 (USB #0)
2. Back Panel USB 2.0 (USB #1)
3. Front Panel USB 2.0 (USB #2/3)
4. Front Panel USB 2.0 (USB #4/5)
1
2
Back Panel USB (2.0)
Pin Denitions
Pin# Denition Pin# Denition
1+5V5+5V
2USB_PN16USB_PN0
3USB_PP17USB_PP0
4Ground8Ground
Front Panel USB (2.0)
Header Pin Denitions
Pin # DenitionPin # Denition
1+5V2+5V
3USB_PN24USB_PN3
5USB_PP26USB_PP3
7Ground8Ground
9Key10Ground
4
3
FANC
FAND
JPW2
JPW3
8
8
5
5
1
FAN1 1
1
4
JPCIE2
SXB2A
J13
USB/0/1
J17
LAN1
JLAN1
LAN2
JLAN2
JCOM1
1
JTPM1
1920
2
JTPM1: TPM/PORT80
J28
JPL1
1
1
JPL2
1
3
3
A
JPMB
JIPMB1
COM1
BD1
AC
A
C
LED2
JVGA1
VGA
1
LE2
CA
2-3:DISABLE
2-3:DISABLE
1-2:ENABLE
JPL2:LAN2
1-2:ENABLE
JPL1:LAN1
JUIDB1
2
UID
SXB1A
USB
2
J23
2
2-3:NIMI
1-2:RST
JWD:
JWP1:
WRITE PROTECT
USB
JOH1:OVER HEAT LED
J26
1
7
7
1
JD1
JOH1
JWD
JPB1
3
JPG1
1
3
BT1
2-3:NMI
1-2:RST(DEFAULT)
JWD:WATCH DOG TIMER
1
JI2C3
3
JI2C2/JI2C3
1-2:Enable
2-3:Disable
3
1
JI2C2
JPCIE3
SLOT3 PCIE 3.0X8
SXB2B
1-2:NORMAL
2-3:BIOS RECOVERY
JPR1:
LE1
C
A
2-3:DISABLE
1-2:ENABLE
JPB1: BMC
1-2:NORMAL
2-3:ME RECOVERY
JPME1:
JD1:
4-7:SPEAKER
1-2:PWR_LED
SP1
+
7
1
3
JPME1
MH5
JPG1: VGA
2-3:Disable
1-2:Enable
JBT1
JBT1:CMOS CLEAR
1
7
7
1
1
7
7
SAS3
SAS1
JPCIE1
SXB1B
I-SATA3
I-SATA5
I-SATA4
SATA6
SATA4
SATA5
1
7
7
1
7
SAS4
SAS2
I-SATA1
I-SATA2
I-SATA0
SATA2
SATA1
SATA3
1
7
1
1
7
CPU
REV: 1.00
DESIGNED IN USA
X9SRG
1
JSD1:
PWRSDOM
JSTBY1:STAND BY POWER FOR DOM
1
3
JSD1
3
DIMMC1
1
JSTBY1
2
8
8
8
12
7
4
7
4
1
1
1
FANB
FANA
127
1
4
DIMMA1
1
11
JL1
20
19
:CHASSIS INTRUSIONJL1
4
1
1
J1
J2
C509
2
1
J3
JF1
J4
PWRHDDXNMI
LEDLED
1
NIC
2
NIC
LED
UID
FAIL
RSTPS
PWR
ON
JF1
FAN2
4
1
4
1
FAN3
J7
J5 J12
J6
4
1
FAN4
10
JI2C1
JPW1
OFF:Disable
JI2C1
ON:Enable
20
1
2-14
Page 41
Chapter 2: Installation
Ethernet Ports (LAN1/LAN2)
Two Ethernet ports (LAN1/LAN2) are
located next to the USB ports on the
I/O backpanel. These ports provide
networking connectivity with speeds
up to 1Gb/s. Please see the table on
the left for the pin denitions.
IPMI Port (IPMI)
In addition to the two Ethernet ports
(LAN1/LAN2) this motherboard also
features an IPMI port. This provides
remote system management ac-
cess through a standard IP protocol
network.
Serial Ports
One COM port (COM1) is provided on
the motherboard, located on the I/O
backpanel. See the table on the right
for pin denitions.
LAN Ports
Pin Denition
Pin# Denition
1TD0-10SGND
2TD0+11P3V3SB
3TD1-12Act LED
4TD1+13Link 100 LED
5TD2-14Link 1000 LED
6TD2+15Ground
7TD3-16Ground
8TD3+17Ground
9P2V5SB18Ground
(NC: No Connection)
Serial Ports-COM1
Pin Denitions
Pin # DenitionPin # Denition
1DCD6DSR
2RXD7RTS
3TXD8CTS
4DTR9RI
5Ground10N/A
(Green, +3V3SB)
(Yellow, +3V3SB)
1. IPMI Port
2. LAN1
3. LAN2
4. Serial Port
1
23
4
2-15
Page 42
X9SRG-F Motherboard User’s Manual
VGA Connector (VGA)
A Video (VGA/CRT) connector is
located next to COM Port1 on the I/O
backpanel. This connector is used to
provide video and CRT display.
Unit Identier Switch (UID)
The Unit ID Switch is located on
the I/O backpanel. When the Unit ID
Switch is turned on, both the blue rear
Unit ID LED and front panel Unit LED
on JF1 (if attached to the front Unit ID
LED on the chassis, see page 2-19)
will activate. Push the Unit ID Switch
again to turn off both Indicators.
These Unit ID LED Indicators provide
easy identication of the system unit,
when installed in a server cabinet for
instance. See also Unit ID LED on
page 2-19.
VGA Pin
Denitions
Pin# Denition Pin# Denition
1Red10Ground
2Green11NC
3Blue12MS1: SDA (DDC Data)
4NC13HSYNC
5Ground14VSYSNC
6Ground15MS3: SCL (DDC CLK)
7Ground16Case
8Ground17Case
95V
NC= No Connection
1. VGA
2. Unit ID Switch
3, Rear Unit ID LED
(see page 2-35)
2-16
1
2
3
Page 43
Chapter 2: Installation
Front Control Panel
JF1 contains header pins for various buttons and indicators that are normally lo-
cated on a control panel at the front of the chassis. These connectors are designed
specically for use with Supermicro server chassis. See the gure below for the
descriptions of the various control panel buttons and LED indicators. Refer to the
following section for descriptions and pin denitions.
1920
Ground
X
Power LED
NMI
X
Vcc
Pin 19Pin 20
Unit ID LED
Power Fail LED
SXB2A
J13
USB/0/1
J17
LAN1
JLAN1
LAN2
JLAN2
JCOM1
1
JTPM1
1920
2
JTPM1: TPM/PORT80
J28
JPL1
1
1
JPL2
1
3
3
JPMB
JIPMB1
COM1
A
C
LED2
JVGA1
VGA
1
LE2
CA
2-3:DISABLE
2-3:DISABLE
1-2:ENABLE
JPL2:LAN2
1-2:ENABLE
JPL1:LAN1
JUIDB1
2
UID
SXB1A
HDD LED
NIC1 LED
NIC2 LED
Ground
Ground
JWP1:
WRITE PROTECT
JOH1:OVER HEAT LED
JOH1
A
JPG1
1
3
BD1
AC
Vcc
Vcc
Vcc
Vcc
Pin 2
Pin 1
Vcc
#3~4
Reset Button
Power Button
#1~2
2
1
JF1 Header Pins
FANC
FAND
JPW2
JPW3
8
8
5
5
1
FAN1 1
1
4
JPCIE2
SXB2B
1-2:NORMAL
2-3:BIOS RECOVERY
JPR1:
LE1
C
USB
2
J23
2
2-3:NIMI
1-2:RST
JWD:
USB
J26
1
7
1
JWD
2-3:NMI
1-2:RST(DEFAULT)
JWD:WATCH DOG TIMER
1
JI2C3
JI2C2/JI2C3
1-2:Enable
2-3:Disable
1
JI2C2
JPCIE3
SLOT3 PCIE 3.0X8
A
2-3:DISABLE
1-2:ENABLE
JPB1: BMC
1-2:NORMAL
2-3:ME RECOVERY
JPME1:
JD1:
4-7:SPEAKER
1-2:PWR_LED
7
SP1
+
JD1
7
1
JPB1
3
3
JPME1
MH5
JPG1: VGA
2-3:Disable
1-2:Enable
BT1
JBT1
3
3
JBT1:CMOS CLEAR
1
7
7
1
1
7
7
SAS3
SAS1
JPCIE1
SXB1B
I-SATA3
I-SATA5
I-SATA4
SATA6
SATA4
SATA5
1
7
7
1
7
SAS4
SAS2
I-SATA1
I-SATA2
I-SATA0
SATA2
SATA3
1
7
1
1
7
CPU
REV: 1.00
DESIGNED IN USA
X9SRG
1
JSD1:
PWRSDOM
JSTBY1:STAND BY POWER FOR DOM
1
3
JSD1
3
DIMMC1
1
JSTBY1
2
8
SATA1
8
8
12
7
4
7
4
1
1
1
FANB
FANA
127
1
4
DIMMA1
1
11
JL1
20
19
:CHASSIS INTRUSIONJL1
4
1
1
J1
J2
C509
2
1
J3
JF1
J4
PWRHDDXNMI
LEDLED
1
NIC
2
NIC
LED
UID
FAIL
RSTPS
PWR
ON
JF1
FAN2
4
1
4
1
FAN3
J7
J5 J12
J6
4
1
FAN4
10
JI2C1
JPW1
OFF:Disable
JI2C1
ON:Enable
20
1
2-17
Page 44
X9SRG-F Motherboard User’s Manual
Front Control Panel Pin Denitions
Power LED
The Power LED connection is located
on pins 15 and 16 of JF1. Refer to the
table on the right for pin denitions.
HDD LED
The HDD LED connection is located
on pins 13 and 14 of JF1. Attach a
cable here to indicate the status of
HDD-related activities, including IDE,
SATA activities. See the table on the
right for pin denitions.
Power Fail LED
The Power Fail LED connection is
located on pins 5 and 6 of JF1. Refer
to the table on the right for pin deni-
tions.
A. PWR LED
B. HDD LED
C. PWR Fail LED
Ground
X
Power LED
Pin Denitions (JF1)
Pin# Denition
15+5V
16Ground
HDD LED
Pin Denitions (JF1)
Pin# Denition
13+5V
14HD Active
PWR Fail LED
Pin Denitions (JF1)
Pin# Denition
5Vcc
6Ground
1920
NMI
X
Power LED
Status
State Denition
OffSystem Off
OnSystem Running
HDD LED
Status
State Denition
OffNo Activity
Blinking HDD Busy
Power Fail LED
Status
State Denition
OffNormal
OnPower Failure
A
Power LED
B
Unit ID LED
Power Fail LED
C
HDD LED
NIC1 LED
NIC2 LED
Ground
Ground
2
2-18
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
#3~4
Reset Button
Power Button
#1~2
1
Page 45
Chapter 2: Installation
NIC1/NIC2 (LAN1/LAN2)
The NIC (Network Interface Control-
ler) LED connection for LAN port 1
is located on pins 11 and 12 of JF1,
and the LED connection for LAN Port
2 is on Pins 9 and 10. NIC1 LED and
NIC2 LED are 2-pin NIC LED head-
ers. Attach NIC LED cables to NIC1
and NIC2 LED indicators to display
network activity. Refer to the table on
the right for pin denitions.
Unit ID LED (Front Panel)
Connect a cable to the Unit ID connec-
tion on pins 7 and 8 of JF1 to connect
to the Unit ID LED on the chassis. The
Unit ID LED is used together with the
Unit ID (UID) Switch (see 2-16).
Ground
X
LAN1/LAN2 LED
Pin Denitions (JF1)
Pin# Denition
9/11Vcc
10/12 Ground
Unit ID LED
Pin Denitions (JF1)
Pin# Denition
7Vcc
8UID LED
1920
NMI
X
NIC LED
Status
State Denition
OffNo Activity
Blinking NIC Busy
Unit ID LED
Status
State Denition
OffUID Off
OnUID On
A. NIC1 LED
B. NIC2 LED
C. UID LED
Power LED
HDD LED
A
NIC1 LED
B
NIC2 LED
Unit ID LED
C
Power Fail LED
Ground
Ground
2
2-19
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
#3~4
Reset Button
Power Button
#1~2
1
Page 46
X9SRG-F Motherboard User’s Manual
NMI Button
The non-maskable interrupt button
header is located on pins 19 and 20
of JF1. Refer to the table on the right
for pin denitions.
Reset Button
The Reset Button connection is lo-
cated on pins 3 and 4 of JF1. Momen-
tarily contacting both pins will hard re-
set the system. Attach it to a hardware
reset switch on the computer case to
reset the system. Refer to the table on
the right for pin denitions.
Power Button
The Power Button connection is locat-
ed on pins1 and 2 of JF1. Momentarily
contacting both pins will power on/off
the system. This button can also be
congured to function as a suspend
button (with a setting in the BIOS - see
Chapter 4). To turn off the power in the
suspend mode, press the button for at
least 4 seconds. Refer to the table on
the right for pin denitions.
Ground
X
NMI Button
Pin Denitions (JF1)
Pin# Denition
19Control
20Ground
Reset Button
Pin Denitions (JF1)
Pin# Denition
3Reset
4Ground
Power Button
Pin Denitions (JF1)
Pin# Denition
1Signal
2+3V Standby
A. NMI Button
B. Reset Button
C. PWR Button
1920
NMI
A
X
Power LED
HDD LED
NIC1 LED
NIC2 LED
Unit ID LED
Power Fail LED
Ground
Ground
2
2-20
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
#3~4
Reset Button
Power Button
#1~2
1
B
C
Page 47
Chapter 2: Installation
2-6 Connecting Cables & Optional Devices
This section provides brief descriptions and pin-out denitions for onboard headers
and connectors. Be sure to use the correct cable for each header or connector.
20-pin Power Connector
Main PWR (JPW1) & GPU PWR
Connectors (JPW2, JPW3)
The 20-pin proprietary main power
connector (JPW1) is used to provide
power to the motherboard. The 8-pin
GPU PWR connector JPW2 is also
required for the graphics processor.
JPW3 is used if additional power to
the GPU is needed for performance
boost. These power connectors meet
the SSI EPS 12V specication. See
the table on the right for pin deni-
tions.
12V 8-pin Power Connec-
tor Pin Denitions
Pins Denition
1 through 4Ground
5 through 8+12V
(Required)
Pin Denitions (JPW1)
Pin# Denition Pin # Denition
11PS_ON_N1GND1
125V STBY2GND2
13GND63GND3
14GND74GND4
15GND85GND5
16NC26NC1
1712V_5712V_1
1812V_6812V_2
1912V_7912V_3
2012V_81012V_4
A. 20-Pin ATX Main PWR
B. 8-Pin GPU PWR (JPW2)
C. 8-Pin GPU PWR (JPW3)
C
B
FANC
FAND
JPW2
JPW3
8
8
5
5
1
FAN1 1
1
4
JPCIE2
SXB2A
J13
USB/0/1
J17
LAN1
JLAN1
LAN2
JLAN2
JCOM1
1
JTPM1
1920
2
JTPM1: TPM/PORT80
J28
JPL1
1
1
JPL2
1
3
3
JPMB
JIPMB1
COM1
BD1
AC
A
C
LED2
JVGA1
VGA
1
LE2
CA
2-3:DISABLE
2-3:DISABLE
1-2:ENABLE
JPL2:LAN2
1-2:ENABLE
JPL1:LAN1
JUIDB1
2
UID
SXB1A
USB
2
J23
2
2-3:NIMI
1-2:RST
JWD:
JWP1:
WRITE PROTECT
USB
JOH1:OVER HEAT LED
J26
1
7
7
1
JD1
JOH1
JWD
JPB1
3
A
JPG1
1
BT1
3
2-3:NMI
1-2:RST(DEFAULT)
JWD:WATCH DOG TIMER
1
JI2C3
3
JI2C2/JI2C3
1-2:Enable
2-3:Disable
3
1
JI2C2
JPCIE3
SLOT3 PCIE 3.0X8
SXB2B
1-2:NORMAL
2-3:BIOS RECOVERY
JPR1:
LE1
C
A
2-3:DISABLE
1-2:ENABLE
JPB1: BMC
1-2:NORMAL
2-3:ME RECOVERY
JPME1:
JD1:
4-7:SPEAKER
1-2:PWR_LED
SP1
+
7
1
3
JPME1
MH5
JPG1: VGA
2-3:Disable
1-2:Enable
JBT1
JBT1:CMOS CLEAR
1
7
7
1
1
7
7
SAS3
SAS1
JPCIE1
SXB1B
I-SATA3
I-SATA5
I-SATA4
SATA6
SATA4
SATA5
1
7
7
1
7
SAS4
SAS2
I-SATA1
I-SATA2
I-SATA0
SATA2
SATA3
1
7
1
1
7
CPU
REV: 1.00
DESIGNED IN USA
X9SRG
1
JSD1:
PWRSDOM
JSTBY1:STAND BY POWER FOR DOM
1
3
JSD1
3
DIMMC1
1
JSTBY1
2
8
SATA1
8
8
12
7
4
7
4
1
1
1
FANB
FANA
127
1
4
DIMMA1
1
11
A
JL1
20
19
:CHASSIS INTRUSIONJL1
4
1
1
J1
J2
C509
2
1
J3
JF1
J4
PWRHDDXNMI
LEDLED
1
NIC
2
NIC
LED
UID
FAIL
RSTPS
PWR
ON
JF1
FAN2
4
1
4
1
FAN3
J7
J5 J12
J6
4
1
FAN4
10
JI2C1
JPW1
OFF:Disable
JI2C1
ON:Enable
20
1
2-21
Page 48
X9SRG-F Motherboard User’s Manual
Fan Headers (FAN1~4, FANA~D)
The X9SRG-F series has eight (8) fan
headers (Fan 1~Fan 4 and Fan A~Fan
D). These fans are 4-pin fan headers.
Though Pins 1-3 of the fan headers
are backward compatible with tradi-
tional 3-pin fans, it is recommended
that 4-pin fans are used to allow the
fan speed control setting in the BIOS
Hardware Monitoring section (if set)
to automatically adjust fan speeds
based on the system temperature.
Refer to the table on the right for pin
denitions.
Chassis Intrusion (JL1)
A Chassis Intrusion header is located
at JL1 on the motherboard. Attach the
appropriate cable from the chassis to
inform you of a chassis intrusion when
the chassis is opened.
Fan Header
Pin Denitions
Pin# Denition
1Ground (Black)
2+12V (Red)
3Tachometer
4PWM_Control
Fan Header
Recommended Usage
Fan# Denition
1~4CPU/System
A~DI/O & Addon Cards
Chassis Intrusion
Pin Denitions (JL1)
Pin# Denition
1Intrusion Input
2Ground
1. Fan 1
2. Fan 2
3. Fan 3
4. Fan 4
A. Fan A
B. Fan B
C. Fan C
D. Fan D
E. Chassis Intrusion
C
D
FANC
FAND
JPW2
8
1
4
JPCIE2
SXB2A
J13
USB/0/1
J17
LAN1
JLAN1
LAN2
JLAN2
JCOM1
1
JTPM1
1920
2
JTPM1: TPM/PORT80
J28
JPL1
1
1
JPL2
1
3
3
JPMB
JIPMB1
COM1
BD1
AC
A
C
LED2
JVGA1
VGA
1
LE2
CA
2-3:DISABLE
2-3:DISABLE
1-2:ENABLE
JPL2:LAN2
1-2:ENABLE
JPL1:LAN1
JUIDB1
2
UID
SXB1A
USB
2
J23
2
2-3:NIMI
1-2:RST
JWD:
JWP1:
WRITE PROTECT
USB
JOH1:OVER HEAT LED
J26
1
7
7
1
JD1
JOH1
JWD
JPB1
A
JPG1
1
3
2-3:NMI
1-2:RST(DEFAULT)
JWD:WATCH DOG TIMER
1
JI2C3
3
JI2C2/JI2C3
1-2:Enable
2-3:Disable
3
1
JI2C2
JPCIE3
SLOT3 PCIE 3.0X8
SXB2B
1-2:NORMAL
2-3:BIOS RECOVERY
JPR1:
LE1
C
A
2-3:DISABLE
1-2:ENABLE
JPB1: BMC
1-2:NORMAL
2-3:ME RECOVERY
JPME1:
JD1:
4-7:SPEAKER
1-2:PWR_LED
SP1
+
7
1
3
3
JPME1
MH5
JPG1: VGA
2-3:Disable
1-2:Enable
BT1
JBT1
JBT1:CMOS CLEAR
1
7
7
1
1
7
7
SAS3
SAS1
JPCIE1
SXB1B
I-SATA3
I-SATA5
I-SATA4
SATA6
SATA4
SATA5
1
7
7
1
7
SAS4
SAS2
I-SATA1
I-SATA2
I-SATA0
SATA2
SATA1
SATA3
1
7
1
1
7
CPU
REV: 1.00
DESIGNED IN USA
X9SRG
1
JSD1:
PWRSDOM
JSTBY1:STAND BY POWER FOR DOM
1
3
JSD1
3
DIMMC1
1
JSTBY1
2
8
8
8
12
7
4
7
4
1
1
1
FANB
FANA
127
A
B
1
4
DIMMA1
1
11
E
1
JPW3
8
5
5
1
FAN11
JL1
20
19
:CHASSIS INTRUSIONJL1
4
1
1
J1
J2
C509
2
1
J3
JF1
J4
PWRHDDXNMI
LEDLED
1
NIC
2
NIC
LED
UID
FAIL
RSTPS
PWR
ON
JF1
FAN2
2
4
1
3
4
1
FAN3
J7
J5 J12
J6
4
1
FAN4
10
JI2C1
JPW1
OFF:Disable
JI2C1
ON:Enable
20
1
4
2-22
Page 49
Chapter 2: Installation
Legacy Wake-On-LAN Header
(JSTBY1)
The onboard LA Ns (LAN1 and LAN2)
do not need WOL header to support
its Wake-On-LAN function. We
preserved the legacy WOL header
to provide convenience for some
embedded customers who need in-
ternal power source from the board.
See the table on the right for pin
denitions.
System Management Bus
(JIPMB1)
A System Management Bus header
for the IPMI slot is located at JIPMB1.
Connect the appropriate cable here
to use the IPMB I2C connection on
your system.
Wake-On-LAN
(JSTBY1)
Pin Denitions
Pin# Denition
1+5V Standby
2Ground
3Wake-up
System Management
Bus (JIPMB1)
Pin# Denition
1Data
2Ground
3Clock
4No Connection
A. Wake On LAN
B. System Management Bus
FANC
FAND
JPW2
JPW3
8
8
5
5
1
FAN1 1
1
4
JPCIE2
SXB2A
J13
USB/0/1
J17
LAN1
JLAN1
LAN2
JLAN2
JCOM1
1
JTPM1
1920
2
JTPM1: TPM/PORT80
J28
JPL1
1
1
JPL2
1
3
3
JPMB
JIPMB1
COM1
B
BD1
AC
A
C
LED2
JVGA1
VGA
1
LE2
CA
2-3:DISABLE
2-3:DISABLE
1-2:ENABLE
JPL2:LAN2
1-2:ENABLE
JPL1:LAN1
JUIDB1
2
UID
SXB1A
USB
2
J23
2
2-3:NIMI
1-2:RST
JWD:
JWP1:
WRITE PROTECT
USB
JOH1:OVER HEAT LED
J26
1
7
7
1
JD1
JOH1
JWD
JPB1
3
A
JPG1
1
BT1
3
2-3:NMI
1-2:RST(DEFAULT)
JWD:WATCH DOG TIMER
1
JI2C3
3
JI2C2/JI2C3
1-2:Enable
2-3:Disable
3
1
JI2C2
JPCIE3
SLOT3 PCIE 3.0X8
SXB2B
1-2:NORMAL
2-3:BIOS RECOVERY
JPR1:
LE1
C
A
2-3:DISABLE
1-2:ENABLE
JPB1: BMC
1-2:NORMAL
2-3:ME RECOVERY
JPME1:
JD1:
4-7:SPEAKER
1-2:PWR_LED
SP1
+
7
1
3
JPME1
MH5
JPG1: VGA
2-3:Disable
1-2:Enable
JBT1
JBT1:CMOS CLEAR
1
7
7
1
1
7
7
SAS3
SAS1
JPCIE1
SXB1B
I-SATA3
I-SATA5
I-SATA4
SATA6
SATA4
SATA5
1
7
7
1
7
SAS4
SAS2
I-SATA1
I-SATA2
I-SATA0
SATA2
SATA3
1
7
1
1
7
CPU
REV: 1.00
DESIGNED IN USA
X9SRG
1
JSD1:
PWRSDOM
JSTBY1:STAND BY POWER FOR DOM
1
3
JSD1
3
DIMMC1
1
JSTBY1
2
8
SATA1
8
8
12
7
4
7
4
1
1
1
FANB
FANA
127
1
4
DIMMA1
1
11
JL1
20
19
:CHASSIS INTRUSIONJL1
4
1
1
J1
J2
C509
2
1
J3
JF1
J4
PWRHDDXNMI
LEDLED
1
NIC
2
NIC
LED
UID
FAIL
RSTPS
PWR
ON
JF1
FAN2
4
1
4
1
FAN3
J7
J5 J12
J6
4
1
FAN4
10
JI2C1
JPW1
OFF:Disable
JI2C1
ON:Enable
20
1
A
2-23
Page 50
X9SRG-F Motherboard User’s Manual
Power Supply I2C (JI2C1)
The Power Supply I2C Connector,
located at JI2C1, monitors the status
of the power supply, fan and system
temperature. See the table on the right
for pin denitions.
DOM PWR Connector (JSD1)
The Disk-On-Module (DOM) power
connector, located at JSD1, provides
5V (Gen1/Gen) power to a solid-state
DOM storage device connected to one
of the SATA ports. See the table on the
right for pin denitions.
PWR Supply (I2C)
Pin Denitions
Pin# Denition
1Clock
2Data
3PWR Fail
4 Ground
53.3V
DOM PWR (JSD1)
Pin Denitions
Pin# Denition
15V
2Ground
3Ground
A. Power Supply I2C
B. DOM Power
FANC
FAND
JPW2
JPW3
8
8
5
5
1
FAN1 1
1
4
JPCIE2
SXB2A
J13
USB/0/1
J17
LAN1
JLAN1
LAN2
JLAN2
JCOM1
1
JTPM1
1920
2
JTPM1: TPM/PORT80
J28
JPL1
1
1
JPL2
1
3
3
JPMB
JIPMB1
COM1
BD1
AC
A
C
LED2
JVGA1
VGA
1
LE2
CA
2-3:DISABLE
2-3:DISABLE
1-2:ENABLE
JPL2:LAN2
1-2:ENABLE
JPL1:LAN1
JUIDB1
2
UID
SXB1A
USB
2
J23
2
2-3:NIMI
1-2:RST
JWD:
JWP1:
WRITE PROTECT
USB
JOH1:OVER HEAT LED
J26
1
7
7
1
JD1
JOH1
JWD
JPB1
A
JPG1
1
3
2-3:NMI
1-2:RST(DEFAULT)
JWD:WATCH DOG TIMER
1
JI2C3
3
JI2C2/JI2C3
1-2:Enable
2-3:Disable
3
1
JI2C2
JPCIE3
SLOT3 PCIE 3.0X8
SXB2B
1-2:NORMAL
2-3:BIOS RECOVERY
JPR1:
LE1
C
A
2-3:DISABLE
1-2:ENABLE
JPB1: BMC
1-2:NORMAL
2-3:ME RECOVERY
JPME1:
JD1:
4-7:SPEAKER
1-2:PWR_LED
SP1
+
7
1
3
3
JPME1
MH5
JPG1: VGA
2-3:Disable
1-2:Enable
BT1
JBT1
JBT1:CMOS CLEAR
1
7
7
1
1
7
7
SAS3
SAS1
JPCIE1
SXB1B
I-SATA3
I-SATA5
I-SATA4
SATA6
SATA4
SATA5
1
7
7
1
7
SAS4
SAS2
I-SATA1
I-SATA2
I-SATA0
SATA2
SATA1
SATA3
1
7
1
1
7
CPU
REV: 1.00
DESIGNED IN USA
X9SRG
1
B
JSD1:
PWRSDOM
JSTBY1:STAND BY POWER FOR DOM
1
3
JSD1
3
DIMMC1
1
JSTBY1
2
8
8
8
12
7
4
7
4
1
1
1
FANB
FANA
127
1
4
DIMMA1
1
11
JL1
20
19
:CHASSIS INTRUSIONJL1
4
1
1
J1
J2
C509
2
1
J3
JF1
J4
PWRHDDXNMI
LEDLED
1
NIC
2
NIC
LED
UID
FAIL
RSTPS
PWR
ON
JF1
FAN2
4
1
4
1
FAN3
J7
J5 J12
J6
4
1
FAN4
10
JI2C1
JPW1
OFF:Disable
JI2C1
ON:Enable
20
1
A
2-24
Page 51
Chapter 2: Installation
T-SGPIO1/2/-S Headers (T-SGPIO)
Four T-SGPIO (Serial-Link General
Purpose Input/Output) headers are
located next to the I-SATA Ports on
the motherboard. These headers are
used to communicate with the enclo-
sure management chip in the system.
See the table on the right for pin
denitions. Refer to the board layout
below for the locations of the headers.
TPM Header (JTPM1)
This header is used to connect a
Trusted Platform Module (TPM),
which is available from a third-party
vendor. A TPM is a security device
that supports encryption and authen-
tication in hard drives. It enables the
motherboard to deny access if the
TPM associated with the hard drive
is not installed in the system. See the
table on the right for pin denitions.
Serial Link General-Purpose Headers
(SGPIO)
Pin Denitions
Pin# Denition Pin Denition
1NC2NC
3Ground4DATA Out
5Load6Ground
7Clock8NC
Trusted Platform Module Header (JTPM1)
Pin Denitions
Pin # DenitionPin # Denition
1LCLK2GND
3LFRAME#4No Pin
5LRESET#6+5V (X)
7LAD38LAD2
93.3V10LAD1
11LAD012GND
13SMB_CLK4 14SMB_DAT4
15+3V_DUAL16SERIRQ
17GND18CLKRUN# (X)
19LPCPD#20LDRQ# (X)
A. T-SGPIO1
B. T-SGPIO2
C. T-SGPIO-S
D. TPM Header
FANC
FAND
JPW2
JPW3
8
8
5
5
1
FAN1 1
1
4
JPCIE2
SXB2A
J13
USB/0/1
J17
LAN1
JLAN1
LAN2
JLAN2
JCOM1
1
JTPM1
1920
D
2
JTPM1: TPM/PORT80
J28
JPL1
1
1
JPL2
1
3
3
JPMB
JIPMB1
COM1
BD1
AC
A
C
LED2
JVGA1
VGA
1
LE2
CA
2-3:DISABLE
2-3:DISABLE
1-2:ENABLE
JPL2:LAN2
1-2:ENABLE
JPL1:LAN1
JUIDB1
2
UID
SXB1A
USB
2
J23
2
2-3:NIMI
1-2:RST
JWD:
JWP1:
WRITE PROTECT
USB
JOH1:OVER HEAT LED
J26
1
7
7
1
JD1
JOH1
JWD
JPB1
3
A
JPG1
1
BT1
3
2-3:NMI
1-2:RST(DEFAULT)
JWD:WATCH DOG TIMER
1
JI2C3
3
JI2C2/JI2C3
1-2:Enable
2-3:Disable
3
1
JI2C2
JPCIE3
SLOT3 PCIE 3.0X8
SXB2B
1-2:NORMAL
2-3:BIOS RECOVERY
JPR1:
LE1
C
A
2-3:DISABLE
1-2:ENABLE
JPB1: BMC
1-2:NORMAL
2-3:ME RECOVERY
JPME1:
JD1:
4-7:SPEAKER
1-2:PWR_LED
SP1
+
7
1
3
JPME1
MH5
JPG1: VGA
2-3:Disable
1-2:Enable
JBT1
JBT1:CMOS CLEAR
1
7
7
1
1
7
7
SAS3
SAS1
JPCIE1
SXB1B
I-SATA3
I-SATA5
I-SATA4
SATA6
SATA4
SATA5
1
7
7
1
7
SAS4
SAS2
I-SATA1
I-SATA2
I-SATA0
SATA2
SATA3
1
7
1
1
7
CPU
REV: 1.00
DESIGNED IN USA
X9SRG
1
JSD1:
PWRSDOM
JSTBY1:STAND BY POWER FOR DOM
B
1
3
JSD1
3
DIMMC1
1
JSTBY1
2
8
SATA1
8
8
12
7
4
7
4
1
A
1
1
FANB
FANA
127
C
1
4
DIMMA1
1
11
JL1
20
19
:CHASSIS INTRUSIONJL1
4
1
1
J1
J2
C509
2
1
J3
JF1
J4
PWRHDDXNMI
LEDLED
1
NIC
2
NIC
LED
UID
FAIL
RSTPS
PWR
ON
JF1
FAN2
4
1
4
1
FAN3
J7
J5 J12
J6
4
1
FAN4
10
JI2C1
JPW1
OFF:Disable
JI2C1
ON:Enable
20
1
2-25
Page 52
X9SRG-F Motherboard User’s Manual
Overheat/Fan Fail LED (JOH1)
The JOH1 header is used to connect
an LED to provide warnings of chas-
sis overheat. This LED will also blink
to indicate a fan failure. Refer to the
table on right for pin denitions.
SXB2A
J13
USB/0/1
J17
LAN1
JLAN1
LAN2
JLAN2
JCOM1
1
JTPM1
1920
2
JTPM1: TPM/PORT80
J28
JPL1
1
1
JPL2
1
3
3
JPMB
JIPMB1
COM1
BD1
AC
A
C
LED2
JVGA1
VGA
1
LE2
CA
2-3:DISABLE
2-3:DISABLE
1-2:ENABLE
JPL2:LAN2
1-2:ENABLE
JPL1:LAN1
JUIDB1
2
UID
SXB1A
USB
2
J23
2
2-3:NIMI
1-2:RST
JWD:
JWP1:
WRITE PROTECT
USB
JOH1:OVER HEAT LED
J26
1
7
7
1
JD1
JOH1
JWD
JPB1
A
A
JPG1
1
BT1
3
2-3:NMI
1-2:RST(DEFAULT)
JWD:WATCH DOG TIMER
1
JI2C3
3
JI2C2/JI2C3
1-2:Enable
2-3:Disable
3
1
JI2C2
JPCIE3
SLOT3 PCIE 3.0X8
SXB2B
1-2:NORMAL
2-3:BIOS RECOVERY
JPR1:
LE1
C
A
2-3:DISABLE
1-2:ENABLE
JPB1: BMC
1-2:NORMAL
2-3:ME RECOVERY
JPME1:
JD1:
4-7:SPEAKER
1-2:PWR_LED
SP1
+
7
1
3
3
JPME1
MH5
JPG1: VGA
2-3:Disable
1-2:Enable
JBT1
JBT1:CMOS CLEAR
1
7
7
SAS1
JPCIE1
SXB1B
I-SATA3
I-SATA5
I-SATA4
SATA6
SATA4
SATA5
1
1
7
7
1
7
OH/Fan Fail LED (JOH1)
Pin Denitions
Pin# Denition
15vDC
2OH Active
OH/Fan Fail LED
(JOH1)
Pin Denitions
State Message
SolidOverheat
Blinking Fan Fail
A. Overheat/Fan Fail LED
FANC
FAND
JPW2
JPW3
8
8
5
5
1
FAN1 1
1
4
JPCIE2
1
4
DIMMA1
CPU
REV: 1.00
DESIGNED IN USA
X9SRG
1
1
1
7
7
SAS3
SAS4
SAS2
I-SATA2
SATA3
7
1
JSD1:
PWRSDOM
JSTBY1:STAND BY POWER FOR DOM
1
3
JSD1
3
DIMMC1
1
JSTBY1
2
8
I-SATA1
I-SATA0
SATA2
SATA1
8
8
12
7
4
7
1
7
4
1
1
1
FANB
FANA
127
1
11
JL1
20
19
:CHASSIS INTRUSIONJL1
4
1
1
J1
J2
C509
2
1
J3
JF1
J4
PWRHDDXNMI
LEDLED
1
NIC
2
NIC
LED
UID
FAIL
RSTPS
PWR
ON
JF1
FAN2
4
1
4
1
FAN3
J7
J5 J12
J6
4
1
FAN4
10
JI2C1
JPW1
OFF:Disable
JI2C1
ON:Enable
20
1
2-26
Page 53
2-7 Jumper Settings
Explanation of Jumpers
To modify the operation of the mother-
board, jumpers can be used to choose
between optional settings. Jumpers
create shorts between two pins to
change the function of the connector.
Pin 1 is identied with a square solder
pad on the printed circuit board.
Note: On two pin jumpers,
"Closed" means the jumper
is on, and "Open" means the
jumper is off the pins.
LAN Port Enable/Disable (JPL1/
JPL2)
Jumpers JPL1 and JPL2 enables or
disables LAN Por t 1 and LAN Port 2
on the motherboard. See the table
on the right for jumper settings. The
default setting is enabled.
Chapter 2: Installation
LAN Enable
Jumper Settings
Setting Denition
Pins 1-2Enabled (Default)
Pins 2-3Disabled
A. LAN Port 1 Enable
B. LAN Port 2 Enable
FANC
FAND
JPW2
JPW3
8
8
5
5
1
FAN1 1
1
4
JPCIE2
SXB2A
J13
USB/0/1
J17
LAN1
JLAN1
LAN2
JLAN2
JCOM1
1
JTPM1
1920
J28
1
COM1
A
C
LED2
JVGA1
VGA
1
LE2
CA
JUIDB1
2
UID
SXB1A
B
2
JTPM1: TPM/PORT80
JPL1
1
1
JPL2
3
3
JPMB
JIPMB1
BD1
AC
A
2-3:DISABLE
2-3:DISABLE
1-2:ENABLE
JPL2:LAN2
1-2:ENABLE
JPL1:LAN1
USB
2
J23
2
2-3:NIMI
1-2:RST
JWD:
JWP1:
WRITE PROTECT
USB
JOH1:OVER HEAT LED
J26
1
7
7
1
JD1
JOH1
JWD
JPB1
A
JPG1
1
BT1
3
2-3:NMI
1-2:RST(DEFAULT)
JWD:WATCH DOG TIMER
1
JI2C3
3
JI2C2/JI2C3
1-2:Enable
2-3:Disable
3
1
JI2C2
JPCIE3
SLOT3 PCIE 3.0X8
SXB2B
1-2:NORMAL
2-3:BIOS RECOVERY
JPR1:
LE1
C
A
2-3:DISABLE
1-2:ENABLE
JPB1: BMC
1-2:NORMAL
2-3:ME RECOVERY
JPME1:
JD1:
4-7:SPEAKER
1-2:PWR_LED
SP1
+
7
1
3
3
JPME1
MH5
JPG1: VGA
2-3:Disable
1-2:Enable
JBT1
JBT1:CMOS CLEAR
1
7
7
1
1
7
7
SAS3
SAS1
JPCIE1
SXB1B
I-SATA3
I-SATA5
I-SATA4
SATA6
SATA4
SATA5
1
7
7
1
7
SAS4
SAS2
I-SATA1
I-SATA2
I-SATA0
SATA2
SATA3
1
7
1
1
7
CPU
REV: 1.00
DESIGNED IN USA
X9SRG
1
JSD1:
PWRSDOM
JSTBY1:STAND BY POWER FOR DOM
1
3
JSD1
3
DIMMC1
1
JSTBY1
2
8
SATA1
8
8
12
7
4
7
4
1
1
1
FANB
FANA
127
1
4
DIMMA1
1
11
JL1
20
19
:CHASSIS INTRUSIONJL1
4
1
1
J1
J2
C509
2
1
J3
JF1
J4
PWRHDDXNMI
LEDLED
1
NIC
2
NIC
LED
UID
FAIL
RSTPS
PWR
ON
JF1
FAN2
4
1
4
1
FAN3
J7
J5 J12
J6
4
1
FAN4
10
JI2C1
JPW1
OFF:Disable
JI2C1
ON:Enable
20
1
2-27
Page 54
X9SRG-F Motherboard User’s Manual
Clear CMOS (JBT1)
JBT1 is used to clear CMOS. Instead of pins, this "jumper" consists of contact pads
to prevent accidental clearing of CMOS. To clear CMOS, use a metal object such
as a small screwdriver to touch both pads at the same time to short the connection.
Always remove the AC power cord from the system before clearing CMOS.
Important: For an ATX power supply, you must completely shut down the
system, remove the AC power cord and then short JBT1 to clear CMOS.
PCI Slot SMB Enable (JI2C2/
JI2C3)
Use Jumpers JI2C2/JI2C3 to enable
PCI SMB (System Management Bus)
support to improve system manage-
ment for the PCI slots. See the table
on the right for jumper settings.
SXB2A
J13
USB/0/1
J17
LAN1
JLAN1
LAN2
JLAN2
JCOM1
1
JTPM1
1920
2
JTPM1: TPM/PORT80
J28
JPL1
1
1
JPL2
1
3
3
JPMB
JIPMB1
COM1
BD1
AC
A
C
LED2
JVGA1
VGA
1
LE2
CA
2-3:DISABLE
2-3:DISABLE
1-2:ENABLE
JPL2:LAN2
1-2:ENABLE
JPL1:LAN1
JUIDB1
2
UID
SXB1A
USB
2
J23
2
2-3:NIMI
1-2:RST
JWD:
JWP1:
WRITE PROTECT
USB
JOH1:OVER HEAT LED
J26
1
7
7
1
JD1
JOH1
JWD
JPB1
C
A
JPG1
1
BT1
3
2-3:NMI
1-2:RST(DEFAULT)
JWD:WATCH DOG TIMER
1
JI2C3
3
JI2C2/JI2C3
1-2:Enable
2-3:Disable
3
1
JI2C2
JPCIE3
SLOT3 PCIE 3.0X8
SXB2B
1-2:NORMAL
2-3:BIOS RECOVERY
JPR1:
LE1
C
A
2-3:DISABLE
1-2:ENABLE
JPB1: BMC
1-2:NORMAL
2-3:ME RECOVERY
JPME1:
JD1:
4-7:SPEAKER
1-2:PWR_LED
SP1
+
7
1
3
3
JPME1
MH5
JPG1: VGA
2-3:Disable
1-2:Enable
JBT1
JBT1:CMOS CLEAR
1
7
7
1
SAS1
SAS2
JPCIE1
SXB1B
I-SATA3
I-SATA5
I-SATA4
SATA6
SATA4
SATA3
SATA5
1
1
7
7
1
7
PCI Slot SMB Enable (JI2C)
Jumper Settings
Setting Denition
Short Enabled (Default)
Open Disabled
A. Clear CMOS
B. JI2C2
C. JI2C3
FANC
FAND
JPW2
JPW3
8
8
5
5
1
FAN1 1
1
4
JPCIE2
1
4
DIMMA1
CPU
REV: 1.00
DESIGNED IN USA
X9SRG
1
1
7
7
SAS3
SAS4
JSD1:
PWRSDOM
JSTBY1:STAND BY POWER FOR DOM
1
3
JSD1
3
DIMMC1
1
JSTBY1
2
8
I-SATA1
I-SATA2
I-SATA0
SATA2
SATA1
8
8
12
7
4
7
7
1
1
7
4
1
1
1
FANB
FANA
127
1
11
JL1
20
19
:CHASSIS INTRUSIONJL1
4
1
1
J1
J2
C509
2
1
J3
JF1
J4
PWRHDDXNMI
LEDLED
1
NIC
2
NIC
LED
UID
FAIL
RSTPS
PWR
ON
JF1
FAN2
4
1
4
1
FAN3
J7
J5 J12
J6
4
1
FAN4
10
JI2C1
JPW1
OFF:Disable
JI2C1
ON:Enable
20
1
B
A
2-28
Page 55
Chapter 2: Installation
Watch Dog Reset (JWD1)
Watch Dog (JWD1) is a system moni-
tor that can reboot the system when
a sof tware application hangs. Close
Pins 1-2 to reset the system if an ap-
plication hangs. Close Pins 2-3 to
generate a non-maskable interrupt
signal for the application that hangs.
See the table on the right for jumper
settings. Watch Dog must also be en-
abled in the BIOS.
VGA Enable (JPG1)
JPG1 allows you to enable or disable
the onboard VGA port. The default
position is on pins 1 and 2 to enable
VGA. See the table on the right for
jumper settings.
Watch Dog (JWD1)
Jumper Settings
Setting Denition
Pins 1-2Reset (Default)
Pins 2-3NMI
OpenDisabled
VGA Enable/Disable (JPG1)
Jumper Settings
Setting Denition
Pins 1-2Enabled (Default)
Pins 2-3Disabled
A. Watch Dog Reset
B. VGA Enable
FANC
FAND
JPW2
JPW3
8
8
5
5
1
FAN1 1
1
4
JPCIE2
SXB2A
J13
USB/0/1
J17
LAN1
JLAN1
LAN2
JLAN2
JCOM1
1
JTPM1
1920
2
JTPM1: TPM/PORT80
J28
JPL1
1
1
JPL2
1
3
3
JPMB
JIPMB1
COM1
BD1
AC
A
C
LED2
JVGA1
VGA
1
LE2
CA
2-3:DISABLE
2-3:DISABLE
1-2:ENABLE
JPL2:LAN2
1-2:ENABLE
JPL1:LAN1
JUIDB1
2
UID
SXB1A
USB
2
J23
2
2-3:NIMI
1-2:RST
JWD:
JWP1:
WRITE PROTECT
USB
JOH1:OVER HEAT LED
J26
1
7
7
1
JD1
JOH1
JWD
JPB1
A
A
JPG1
1
3
2-3:NMI
1-2:RST(DEFAULT)
JWD:WATCH DOG TIMER
1
JI2C3
3
JI2C2/JI2C3
1-2:Enable
2-3:Disable
3
1
JI2C2
B
JPCIE3
SLOT3 PCIE 3.0X8
SXB2B
1-2:NORMAL
2-3:BIOS RECOVERY
JPR1:
LE1
C
A
2-3:DISABLE
1-2:ENABLE
JPB1: BMC
1-2:NORMAL
2-3:ME RECOVERY
JPME1:
JD1:
4-7:SPEAKER
1-2:PWR_LED
SP1
+
7
1
3
3
JPME1
MH5
JPG1: VGA
2-3:Disable
1-2:Enable
BT1
JBT1
JBT1:CMOS CLEAR
1
7
7
1
1
7
7
SAS3
SAS1
JPCIE1
SXB1B
I-SATA3
I-SATA5
I-SATA4
SATA6
SATA4
SATA5
1
7
7
1
7
SAS4
SAS2
I-SATA1
I-SATA2
I-SATA0
SATA2
SATA3
1
7
1
1
7
CPU
REV: 1.00
DESIGNED IN USA
X9SRG
1
JSD1:
PWRSDOM
JSTBY1:STAND BY POWER FOR DOM
1
3
JSD1
3
DIMMC1
1
JSTBY1
2
8
SATA1
8
8
12
7
4
7
4
1
1
1
FANB
FANA
127
1
4
DIMMA1
1
11
JL1
20
19
:CHASSIS INTRUSIONJL1
4
1
1
J1
J2
C509
2
1
J3
JF1
J4
PWRHDDXNMI
LEDLED
1
NIC
2
NIC
LED
UID
FAIL
RSTPS
PWR
ON
JF1
FAN2
4
1
4
1
FAN3
J7
J5 J12
J6
4
1
FAN4
10
JI2C1
JPW1
OFF:Disable
JI2C1
ON:Enable
20
1
2-29
Page 56
X9SRG-F Motherboard User’s Manual
BMC Enable/Disable (JPB1)
JPB1 is used to enable or disable
the BMC (Baseboard Management
Control) chip and the onboard IPMI
port. This jumper is used together with
the IPMI settings in the BIOS. See the
table on the right for jumper settings.
ME Recovery (JPME1)
ME Recovery (JPME1) is used to en-
able or disable the ME Recovery fea-
ture of the motherboard. This jumper
will reset Intel ME values back to their
default settings.
SXB2A
J13
USB/0/1
J17
LAN1
JLAN1
LAN2
JLAN2
JCOM1
1
JTPM1
1920
2
JTPM1: TPM/PORT80
J28
JPL1
1
1
JPL2
1
3
3
JPMB
JIPMB1
COM1
BD1
AC
A
C
LED2
JVGA1
VGA
1
LE2
CA
2-3:DISABLE
2-3:DISABLE
1-2:ENABLE
JPL2:LAN2
1-2:ENABLE
JPL1:LAN1
JUIDB1
2
UID
SXB1A
USB
2
J23
2
2-3:NIMI
1-2:RST
JWD:
JWP1:
WRITE PROTECT
USB
JOH1:OVER HEAT LED
J26
1
7
7
1
JD1
JOH1
JWD
JPB1
A
A
JPG1
1
BT1
3
2-3:NMI
1-2:RST(DEFAULT)
JWD:WATCH DOG TIMER
1
JI2C3
3
JI2C2/JI2C3
1-2:Enable
2-3:Disable
3
1
JI2C2
JPCIE3
SLOT3 PCIE 3.0X8
SXB2B
1-2:NORMAL
2-3:BIOS RECOVERY
JPR1:
LE1
C
A
2-3:DISABLE
1-2:ENABLE
JPB1: BMC
1-2:NORMAL
2-3:ME RECOVERY
JPME1:
JD1:
4-7:SPEAKER
1-2:PWR_LED
SP1
+
7
1
3
JPME1
B
3
MH5
JPG1: VGA
2-3:Disable
1-2:Enable
JBT1
JBT1:CMOS CLEAR
1
7
7
SAS1
SAS2
JPCIE1
SXB1B
I-SATA3
I-SATA5
I-SATA4
SATA6
SATA4
SATA5
1
1
7
7
1
7
BMC IPMI Enable/Disable
(JPB1) Jumper Settings
Setting Denition
Pins 1-2Enabled (Default)
Pins 2-3Disabled
ME Recovery (JPME1)
Jumper Settings
Setting Denition
Pins 1-2Normal (Default)
Pins 2-3Force Update
A. BMC Enable/Disable
B. ME Recovery
FANC
FAND
JPW2
JPW3
8
8
5
5
1
FAN1 1
1
4
JPCIE2
1
4
DIMMA1
CPU
REV: 1.00
DESIGNED IN USA
X9SRG
1
1
1
7
7
SAS3
SAS4
JSD1:
PWRSDOM
JSTBY1:STAND BY POWER FOR DOM
1
3
JSD1
3
DIMMC1
1
JSTBY1
2
8
I-SATA1
I-SATA2
I-SATA0
SATA2
SATA1
SATA3
7
1
7
8
8
12
7
4
7
1
4
1
1
1
FANB
FANA
127
1
11
JL1
20
19
:CHASSIS INTRUSIONJL1
4
1
1
J1
J2
C509
2
1
J3
JF1
J4
PWRHDDXNMI
LEDLED
1
NIC
2
NIC
LED
UID
FAIL
RSTPS
PWR
ON
JF1
FAN2
4
1
4
1
FAN3
J7
J5 J12
J6
4
1
FAN4
10
JI2C1
JPW1
OFF:Disable
JI2C1
ON:Enable
20
1
2-30
Page 57
2-8 Onboard Indicators
LAN 1/LAN 2
LAN Port LEDs
The LAN ports are located on the I/O
backpanel of the motherboard. Each
Ethernet LAN port has two LEDs.
The yellow LED indicates activity,
while the Link LED may be green,
amber, or off to indicate the speed of
the connections. On the IPMI port,
the yellow LED on the right indicates
activity, while the green LED on the
left indicates the speed of the con-
nection. See the table at right for
more information. See the tables at
right for more information.
Chapter 2: Installation
Link LEDs (Green/Amber/Off)
LED Color Denition
OffNo Connection or 10 Mbps
Green100 Mbps
Amber1 Gbps
LAN
LAN
Link LED
IPMI LAN
Link LED
Activity LED
Activity LED
Standby Power (LED2)
The Standby Power LED is located
at LED2 on the motherboard. When
LED2 is on, it means that the AC
power cable is connected and the
power supply hard switch is on, indi-
cating that power is owing through
the power supply and into the moth-
erboard. The system may or may not
be running.
USB/0/1
JCOM1
1920
J28
1
COM1
C
JVGA1
VGA
1
LE2
CA
2
UID
Standby PWR LED (LED2)
LED Status
Status Denition
OffSystem unplugged or
power supply is switched
off
OnStandby Power On
A. Standby Power LED
FANC
FAND
JPW2
JPW3
8
8
5
5
1
FAN1 1
1
4
JPCIE2
SXB2A
J13
J17
LAN1
JLAN1
LAN2
JLAN2
1
JTPM1
2
JTPM1: TPM/PORT80
JPL1
1
1
JPL2
3
3
JPMB
JIPMB1
BD1
AC
A
A
LED2
2-3:DISABLE
2-3:DISABLE
1-2:ENABLE
JPL2:LAN2
1-2:ENABLE
JPL1:LAN1
JUIDB1
SXB1A
USB
2
J23
2
2-3:NIMI
1-2:RST
JWD:
JWP1:
WRITE PROTECT
USB
JOH1:OVER HEAT LED
J26
1
7
7
1
JD1
JOH1
JWD
JPB1
3
A
JPG1
1
BT1
3
2-3:NMI
1-2:RST(DEFAULT)
JWD:WATCH DOG TIMER
1
JI2C3
3
JI2C2/JI2C3
1-2:Enable
2-3:Disable
3
1
JI2C2
JPCIE3
SLOT3 PCIE 3.0X8
SXB2B
1-2:NORMAL
2-3:BIOS RECOVERY
JPR1:
LE1
C
A
2-3:DISABLE
1-2:ENABLE
JPB1: BMC
1-2:NORMAL
2-3:ME RECOVERY
JPME1:
JD1:
4-7:SPEAKER
1-2:PWR_LED
SP1
+
7
1
3
JPME1
MH5
JPG1: VGA
2-3:Disable
1-2:Enable
JBT1
JBT1:CMOS CLEAR
1
7
7
1
1
7
7
SAS3
SAS1
JPCIE1
SXB1B
I-SATA3
I-SATA5
I-SATA4
SATA6
SATA4
SATA5
1
7
7
1
7
SAS4
SAS2
I-SATA1
I-SATA2
I-SATA0
SATA2
SATA3
1
7
1
1
7
CPU
REV: 1.00
DESIGNED IN USA
X9SRG
1
JSD1:
PWRSDOM
JSTBY1:STAND BY POWER FOR DOM
1
3
JSD1
3
DIMMC1
1
JSTBY1
2
8
SATA1
8
8
12
7
4
7
4
1
1
1
FANB
FANA
127
1
4
DIMMA1
1
11
JL1
20
19
:CHASSIS INTRUSIONJL1
4
1
1
J1
J2
C509
2
1
J3
JF1
J4
PWRHDDXNMI
LEDLED
1
NIC
2
NIC
LED
UID
FAIL
RSTPS
PWR
ON
JF1
FAN2
4
1
4
1
FAN3
J7
J5 J12
J6
4
1
FAN4
10
JI2C1
JPW1
OFF:Disable
JI2C1
ON:Enable
20
1
2-31
Page 58
X9SRG-F Motherboard User’s Manual
1
11
JPW2
5
8
4
1
JPW3
8
4
FAND
1
FANC
4
1
1
FANA
4
1
DIMMA1
DIMMC1
Power On (LE1)
The Power On LED is located at LE1
on the motherboard. When LE1 is
on, it means that the AC power cable
is connected, the power supply hard
switch and soft switch are on, and the
system is running.
IPMI Heartbeat LED (BD1)
An IPMI Heartbeat LED is located
at BD1. When BD1 blinks, it means
that IPMI is enabled and functioning
properly.
Unit ID LED (LE2)
The Unit ID LED is used to indicate
that the Unit ID switch has been ac-
tivated. Please see pages 2-16 and
2-19 for details.
Power On LED (LE1)
LED Status
Status Denition
OffSystem Off or Standby Power
OnSystem is On/Running
IPMI Heartbeat LED (BD1)
LED Settings
Green: BlinkingIPMI is ready for use
OffIPMI Disabled
Unit ID LED (LE2)
LED Settings
Blue: SteadyUnit ID Switch is On
OffUnit ID Switch is Off
A. Onboard Power LED
B. IPMI Heartbeat LED
C. Unit ID LED
SXB2A
USB/0/1
JCOM1
1
COM1
JVGA1
C
VGA
LE2
CA
UID
J13
2
USB
J23
2
2-3:NIMI
1-2:RST
JWD:
JWP1:
WRITE PROTECT
USB
JOH1:OVER HEAT LED
J26
J17
LAN1
JLAN1
LAN2
JLAN2
1
JTPM1
1920
2
JTPM1: TPM/PORT80
J28
JPL1
1
1
JPL2
3
3
JPMB
JIPMB1
BD1
AC
A
C
LED2
1
2-3:DISABLE
2-3:DISABLE
1-2:ENABLE
JPL2:LAN2
1-2:ENABLE
JPL1:LAN1
JUIDB1
2
SXB1A
1
JOH1
JWD
A
JPG1
1
3
B
JPCIE3
JD1:
4-7:SPEAKER
1-2:PWR_LED
1
7
7
SP1
JD1
1
JPB1
3
3
JPME1
MH5
BT1
2-3:NMI
1-2:RST(DEFAULT)
JWD:WATCH DOG TIMER
1
JI2C3
3
JI2C2/JI2C3
1-2:Enable
2-3:Disable
3
1
JI2C2
SLOT3 PCIE 3.0X8
2-32
SXB2B
1-2:NORMAL
2-3:BIOS RECOVERY
JPR1:
LE1
C
A
2-3:DISABLE
1-2:ENABLE
JPB1: BMC
1-2:NORMAL
2-3:ME RECOVERY
JPME1:
+
7
JPG1: VGA
2-3:Disable
1-2:Enable
JBT1
JBT1:CMOS CLEAR
7
SAS1
JPCIE1
SXB1B
I-SATA5
I-SATA4
SATA6
7
SATA4
SATA5
1
1
7
JPCIE2
A
REV:1.00
DESIGNED IN USA
X9SRG
1
7
1
1
1
7
7
SAS3
SAS2
I-SATA3
SATA3
1
7
SAS4
JSD1:
PWRSDOM
JSTBY1:STAND BY POWER FOR DOM
1
3
JSD1
3
1
JSTBY1
2
I-SATA1
I-SATA2
SATA2
7
1
7
8
I-SATA0
SATA1
8
12
7
7
1
1
127
CPU
8
4
FANB
Page 59
2-9 SATA Connections
Chapter 2: Installation
SATA Connections (I-SATA & SCU)
Six Serial ATA (SATA) connectors
(I-SATA 0~5) are located on the moth-
erboard. I-SATA 0/1 supports data
transfer rates of up to 6Gb/s (SATA
3.0), while I-SATA 2~5 supports data
transfer rates of up to 3Gb/s (SATA
2.0). Please see the pin denitions
on the right table.
In addition to these six SATA ports,
four additional SATA connections
(3Gb/s, via SCU) are also located on
the X9SRG-F series (SCU 1~4).
SXB2A
J13
USB/0/1
J17
LAN1
JLAN1
LAN2
JLAN2
JCOM1
1
JTPM1
1920
2
JTPM1: TPM/PORT80
J28
JPL1
1
1
JPL2
1
3
3
JPMB
JIPMB1
COM1
BD1
AC
A
C
LED2
JVGA1
VGA
1
LE2
CA
2-3:DISABLE
2-3:DISABLE
1-2:ENABLE
JPL2:LAN2
1-2:ENABLE
JPL1:LAN1
JUIDB1
2
UID
SXB1A
USB
2
J23
2
2-3:NIMI
1-2:RST
JWD:
JWP1:
WRITE PROTECT
USB
JOH1:OVER HEAT LED
J26
1
7
7
1
JD1
JOH1
JWD
JPB1
A
JPG1
1
3
2-3:NMI
1-2:RST(DEFAULT)
JWD:WATCH DOG TIMER
1
JI2C3
3
JI2C2/JI2C3
1-2:Enable
2-3:Disable
3
1
JI2C2
JPCIE3
SLOT3 PCIE 3.0X8
SXB2B
1-2:NORMAL
2-3:BIOS RECOVERY
JPR1:
LE1
C
A
2-3:DISABLE
1-2:ENABLE
JPB1: BMC
1-2:NORMAL
2-3:ME RECOVERY
JPME1:
JD1:
4-7:SPEAKER
1-2:PWR_LED
SP1
+
2
1
7
1
3
3
JPME1
MH5
JPG1: VGA
2-3:Disable
1-2:Enable
BT1
JBT1
JBT1:CMOS CLEAR
1
7
7
SAS1
SAS2
JPCIE1
SXB1B
I-SATA3
I-SATA5
I-SATA4
SATA6
SATA4
SATA3
SATA5
1
1
7
7
1
7
SATA/SAS Connectors
Pin Denitions
Pin# Signal
1Ground
2SATA_TXP
3SATA_TXN
4Ground
5SATA_RXN
6SATA_RXP
7Ground
A. I-SATA 0 (3.0)
B. I-SATA 1 (3.0)
C. I-SATA 2 (2.0)
D. I-SATA 3 (2.0)
1. SCU 1
2. SCU 2
3. SCU 3
4. SCU 4
E. I-SATA 4 (2.0)
F. I-SATA 5 (2.0)
FANC
FAND
JPW2
JPW3
8
8
5
5
1
FAN1 1
1
4
JPCIE2
3
4
CPU
REV: 1.00
DESIGNED IN USA
X9SRG
1
1
1
7
7
SAS3
SAS4
JSD1:
PWRSDOM
JSTBY1:STAND BY POWER FOR DOM
1
3
JSD1
3
DIMMC1
1
JSTBY1
2
8
I-SATA1
I-SATA2
I-SATA0
SATA2
SATA1
8
8
12
7
4
7
7
1
1
7
4
1
1
1
FANB
FANA
127
1
4
DIMMA1
1
11
JL1
20
19
:CHASSIS INTRUSIONJL1
4
1
1
J1
J2
C509
2
1
J3
JF1
J4
PWRHDDXNMI
LEDLED
1
NIC
2
NIC
LED
UID
FAIL
RSTPS
PWR
ON
JF1
FAN2
4
1
4
1
FAN3
J7
J5 J12
J6
4
1
FAN4
10
JI2C1
JPW1
OFF:Disable
JI2C1
ON:Enable
20
1
F
E
D
A
B
C
2-33
Page 60
X9SRG-F Motherboard User’s Manual
Notes
2-34
Page 61
Chapter 3: Troubleshooting
Chapter 3
Troubleshooting
3-1 Troubleshooting Procedures
Use the following procedures to troubleshoot your system. If you have followed all
of the procedures below and still need assistance, refer to the ‘Technical Support
Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter.
Always disconnect the AC power cord before adding, changing or installing any
hardware components.
Before Power On
1. Make sure that the Standby is not on. (Note: If it is on, the onboard power
is on. Be sure to unplug the power cable before installing or removing the
components.)
2. Make sure that there are no short circuits between the motherboard and
chassis.
3. Disconnect all ribbon/wire cables from the motherboard, including those for
the keyboard and mouse. Also, be sure to remove all add-on cards.
4. Install a CPU and heatsink (-be sure that it is fully seated) and then connect
the chassis speaker and the power LED to the motherboard. Check all jumper
settings as well.
No Power
1. Make sure that there are no short circuits between the motherboard and
chassis.
2. Make sure that all jumpers are set to their default positions.
3. Check if the 115V/230V switch on the power supply is properly set.
4. Turn the power switch on and off to test the system.
5. The battery on your motherboard may be old. Check to make sure that it still
supplies ~3VDC. If it does not, replace it with a new one.
3-1
Page 62
X9SRG-F Motherboard User’s Manual
No Video
1. If the power is on, but you have no video--in this case, you will need to re-
move all the add-on cards and cables rst.
2. Use the speaker to determine if any beep codes exist. (Refer to Appendix A
for details on beep codes.)
3. Remove all memory modules and turn on the system. (If the alarm is on,
check the specs of memory modules, reset the memory or try a different one.)
Memory Errors
1. Make sure that the DIMM modules are properly installed and fully seated in
the slots.
2. You should be using memory recommended by Supermicro (see Section 2-3).
Also, it is recommended that you use the memory modules of the same type
and speed for all DIMMs in the system. Do not use memory modules of differ-
ent sizes, different speeds and different types on the same motherboard.
3. Check for bad DIMM modules or slots by swapping modules between slots to
see if you can locate the faulty ones.
4. Check the switch of 115V/230V power supply.
When You Lose the System’s Setup Conguration
1. Please be sure to use a high quality power supply. A poor quality power sup-
ply may cause the system to lose CMOS setup information. Refer to Section
1-5 for details on recommended power supplies.
2. The battery on your motherboard may be old. Check to verify that it still sup-
plies ~3VDC. If it does not, replace it with a new one.
3. If the above steps do not x the Setup Conguration problem, contact your
vendor for repairs.
3-2
Page 63
Chapter 3: Troubleshooting
3-2 Technical Support Procedures
Before contacting Technical Support, please make sure that you have followed all
the steps listed below. Also, Note that as a motherboard manufacturer, Supermicro
does not sell directly to end users, so it is best to rst check with your distributor or
reseller for troubleshooting services. They should know of any possible problem(s)
with the specic system conguration that was sold to you.
1. Please go through the ‘Troubleshooting Procedures’ and 'Frequently Asked
Question' (FAQ) sections in this chapter or see the FAQs on our website
(http://www.supermicro.com/support/faqs/) before contacting Technical Sup-
port.
2. BIOS upgrades can be downloaded from our website at (http://www.supermi-
cro.com/support/bios/).
Note: Not all BIOS can be ashed. Some cannot be ashed; it depends
on the boot block code of the BIOS.
3. If you've followed the instructions above to troubleshoot your system, and still
cannot resolve the problem, then contact Supermicro's technical support and
provide them with the following information:
• Motherboard model and PCB revision number
• BIOS release date/version (this can be seen on the initial display when your
system rst boots up)
•System conguration
•An example of a Technical Support form is on our website at (http://www.su-
permicro.com/support/contact.cfm).
4. Distributors: For immediate assistance, please have your account number
ready when placing a call to our technical support department. We can be
reached by e-mail at support@supermicro.com, by phone at: (408) 503-
8000, option 2, or by fax at (408)503-8019.
3-3
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X9SRG-F Motherboard User’s Manual
3-3 Frequently Asked Questions
Question: What type of memory does my motherboard support?
Answer: Please see Section 2-3 for a comprehensive answer.
Question: How do I update my BIOS?
Answer: It is recommended that you do not upgrade your BIOS if you are not
experiencing any problems with your system. Updated BIOS les are located on
our website at http://www.supermicro.com/support/bios/. Please check our BIOS
warning message and the information on how to update your BIOS on our web
site. Select your motherboard model and download the BIOS ROM le to your
computer. Also, check the current BIOS revision to make sure that it is newer than
your BIOS before downloading. Please unzip the BIOS le onto a bootable device
or a USB pen/thumb drive. To ash the BIOS, run the batch le named "ami.bat"
with the new BIOS ROM le from your bootable device or USB pen/thumb drive.
Use the following format:
F:\> ami.bat BIOS-ROM-lename.xxx <Enter>
Note: Always use the le named “ami.bat ” to update the BIOS, and inser t
a space between "ami.bat" and the lename. The BIOS -ROM -lename
will bear the motherboard name (i.e., X9SRG) and build version as the
extension. For example, "X9SRG1.218". When completed, your system
will automatically reboot.
When the BIOS ashing screen is completed, the system will reboot and
will show “Press F1 or F2”. At this point, you will need to load the BIOS
defaults. Press <F1> to go to the BIOS setup screen, and press <F3> to
load the default settings. Next, press <F4> to save and exit. The system
will then reboot.
Warning: Do not shut down or reset the system while updating the BIOS
to prevent possible system boot failure!
Note: The SPI BIOS chip installed on this motherboard is not removable.
To repair or replace a damaged BIOS chip, please send your motherboard
to RMA at Supermicro for service.
Question: I think my BIOS is corrupted. How can I recover my BIOS?
Answer: Please see Appendix C-BIOS Recovery for detailed instructions.
Question: What's on the CD that came with my motherboard?
Answer: The supplied compact disc has quite a few drivers and programs that will
greatly enhance your system. We recommend that you review the CD and install the
applications you need. Applications on the CD include chipset drivers for Windows,
security programs, and audio drivers.
3-4
Page 65
Chapter 3: Troubleshooting
Question: Why do I get an error message “IASTOR.SYS read error” and "press F6
to install Intel RAID driver" when installing Windows on my motherboard?
Answer: To solve this issue, disable the IPMI jumper (if your motherboard has this
feature). Another solution is to use a USB oppy drive instead of the onboard oppy
drive. For the IPMI jumper location, please check Chapter 1.
Question: What is the heatsink part number for my X9SRG-F Series motherboard?
Answer: For the 1U passive heatsink, ask for SNK-P0047P. For the 3U active
heatsink, use SNK-P0050AP4.
Question: Why can't I recover the BIOS even when I’ve followed the instructions
in the user’s manual for the motherboard?
Answer: Please disable the IPMI jumper and try it again. For the jumper location,
please check Chapter 1.
3-5
Page 66
X9SRG-F Motherboard User’s Manual
3-4 Battery Removal and Installation
Battery Removal
To remove the onboard battery, follow the steps below:
1. Power off your system and unplug your power
cable.
2. Locate the onboard battery as shown below.
3. Using a tool such as a pen or a small screwdriver,
push the battery lock outwards to unlock it. Once
unlocked, the battery will pop out from the holder.
4. Remove the battery.
Proper Battery Disposal
Warning! Please handle used batteries
carefully. Do not damage the battery in any
way; a damaged battery may release hazard-
ous materials into the environment. Do not
discard a used battery in the garbage or a
public landll. Please comply with the regula-
tions set up by your local hazardous waste
management agency to dispose of your used
battery properly.
Battery
Lock
Battery
Battery Holder
This side up
Battery Installation
1. To install an onboard battery, follow the steps 1&
2 above and continue below:
2. Identify the battery's polarity. The positive (+) side
should be facing up.
3. Insert the battery into the battery holder and push
it down until you hear a click to ensure that the
battery is securely locked.
Warning: When replacing a battery, be sure
to only replace it with the same type.
3-6
1
Press down until
you hear a click.
2
Page 67
Chapter 3: Troubleshooting
3-5 Returning Merchandise for Service
A receipt or copy of your invoice marked with the date of purchase is required
before any warranty service will be rendered. You can obtain service by calling
your vendor for a Returned Merchandise Authorization (RMA) number. For faster
service, you may also obtain RMA authorizations online (http://www.supermicro.
com/support/rma/). When you return the motherboard to the manufacturer, the
RMA number should be prominently displayed on the outside of the shipping
carton, and mailed prepaid or hand-carried. Shipping and handling charges will
be applied for all orders that must be mailed when service is complete.
This warranty only covers normal consumer use and does not cover damages
incurred in shipping or from failure due to the alteration, misuse, abuse or improper
maintenance of products.
During the warranty period, contact your distributor rst for any product prob-
lems.
3-7
Page 68
X9SRG-F Motherboard User’s Manual
Notes
3-8
Page 69
Chapter 4: AMI BIOS
Chapter 4
BIOS
4-1 Introduction
This chapter describes the AMI BIOS Setup Utility for the X9SRG-F Motherboard.
The AMI ROM BIOS is stored in a Flash EEPROM and can be easily updated. This
chapter describes the basic navigation of the AMI BIOS Setup Utility setup screens.
Note: For instructions on BIOS recovery, please refer to the instruction
guide posted at http://www.supermicro.com/support/manuals/.
Starting BIOS Setup Utility
To enter the AMI BIOS Setup Utility screens, press the <Delete> key while the
system is booting up.
Note: In most cases, the <Delete> key is used to invoke the AMI BIOS
setup screen. There are a few cases when other keys are used, such as
<F1>, <F2>, etc.
Each main BIOS menu option is described in this manual. The Main BIOS setup
menu screen has two main frames. The left frame displays all the options that can
be congured. Grayed-out options cannot be congured. Options in blue can be
congured by the user. The right frame displays the key legend. Above the key
legend is an area reserved for a text message. When an option is selected in the
left frame, it is highlighted in white. Often informational text will accompany it. (Note:
the AMI BIOS has default informational text built in. Supermicro retains the option
to include, omit, or change any of these informational messages.)
The AMI BIOS Setup Utility uses a key-based navigation system called "hot keys".
Most of the AMI BIOS setup utility "hot keys" can be used at any time during the
setup navigation process. These keys include <F1>, <F10>, <Enter>, <ESC>, ar-
row keys, etc.
Note: Options printed in Bold are default settings.
How To Change the Conguration Data
The conguration data that determines the system parameters may be changed by
entering the AMI BIOS Setup utility. This Setup utility can be accessed by pressing
<Del> at the appropriate time during system boot.
4-1
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X9SRG-F Motherboard User’s Manual
How to Start the Setup Utility
Normally, the only visible Power-On Self-Test (POST) routine is the memory test.
As the memory is being tested, press the <Delete> key to enter the main menu of
the AMI BIOS Setup Utility. From the main menu, you can access the other setup
screens. An AMI BIOS identication string is displayed at the left bottom corner of
the screen, below the copyright message.
Warning! Do not upgrade the BIOS unless your system has a BIOS-related
issue. Flashing the wrong BIOS can cause irreparable damage to the
system. In no event shall Supermicro be liable for direct, indirect, special,
incidental, or consequential damages arising from a BIOS update. If you
have to update the BIOS, do not shut down or reset the system while the
BIOS is updating. This is to avoid possible boot failure.
4-2 Main Setup
When you rst enter the AMI BIOS Setup Utility, you will enter the Main setup screen.
You can always return to the Main setup screen by selecting the Main tab on the
top of the screen. The Main BIOS Setup screen is shown below.
4-2
Page 71
Chapter 4: AMI BIOS
System Overview: The following BIOS information will be displayed:
System Time/System Date
Use this option to change the system time and date. Highlight System Time or Sys-
tem Date using the arrow keys. Enter new values through the keyboard. Press the
<Tab> key or the arrow keys to move between elds. The date must be entered in
Day MM/DD/YY format. The time is entered in HH:MM:SS format. (Note: The time
is in the 24-hour format. For example, 5:30 P.M. appears as 17:30:00.)
Supermicro X9SRG-F
Version: This item displays the version of the BIOS used in the system.
Build Date: This item displays the day this version of BIOS was built.
Memory Information
Total Memory
This displays the size of memory available in the system:
4-3
Page 72
X9SRG-F Motherboard User’s Manual
4-3 Advanced Setup Congurations
Use the arrow keys to select Boot Setup and hit <Enter> to access the submenu
items:
BOOT Feature
Quiet Boot
This option allows the bootup screen options to be modied between POST mes-
sages or the OEM logo. Select Disabled to display the POST messages. Select
Enabled to display the OEM logo instead of the normal POST messages. The op-
tions are Enabled and Disabled.
AddOn ROM Display Mode
This sets the display mode for Option ROM. The options are Force BIOS and
Keep Current.
Bootup Num-Lock
This feature selects the Power-on state for Numlock key. The options are Off
and On.
Wait For 'F1' If Error
This forces the system to wait until the 'F1' key is pressed if an error occurs. The
options are Disabled and Enabled.
4-4
Page 73
Chapter 4: AMI BIOS
Interrupt 19 Capture
Interrupt 19 is the software interrupt that handles the boot disk function. When this
item is set to Enabled, the ROM BIOS of the host adaptors will "capture" Interrupt
19 at boot and allow the drives that are attached to these host adaptors to function
as bootable disks. If this item is set to Disabled, the ROM BIOS of the host adap-
tors will not capture Interrupt 19, and the drives attached to these adaptors will not
function as bootable devices. The options are Enabled and Disabled.
Watch Dog Function
If enabled, the Watch Dog timer will allow the system to automatically reboot when
a non-recoverable error occurs that lasts for more than ve minutes. The options
are Enabled and Disabled.
Power Button Function
This feature controls how the system shuts down when the power button is pressed.
Select 4-Seconds Override to force the user to press and hold the Power Button for
4 seconds before the system turns off. Select Instant Off if you want the system to
instantly power off when the Power Button is pressed. The options are 4 Seconds
Override and Instant Off.
Restore on AC Power Loss
Use this feature to set the power state after a power outage. Select Power-Off for
the system power to remain off after a power loss. Select Power-On for the system
power to be turned on after a power loss. Select Last State to allow the system
to resume its last state before a power loss. The options are Power On, Stay Off
and Last State.
CPU Conguration
Warning: Take Caution when changing the Advanced settings. An incorrect
value, a very high DRAM frequency or incorrect DRAM timing may cause
system to become unstable. When this occurs, revert to the default setting.
Socket 1 CPU Information
This item is for informational purposes only and displays CPU information
including type, speed, number of cores, etc.
Clock Spread Spectrum
Select Enable to use the feature of Clock Spectrum, which will allow the BIOS to
monitor and attempt to reduce the level of Electromagnetic Interference caused by
the components whenever needed. Select Disabled to enhance system stability.
The options are Disabled and Enabled.
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Hyper Threading
Set to Enabled to use the processor's Hyper Threading Technology feature. The
options are Enabled and Disabled.
Active Processor Cores
Set to Enabled to use a processor's Second Core and beyond. (Please refer to
Intel's web site for more information.) The options are All, 1, 2, 4.
Limit CPUID Maximum
This feature allows the user to set the maximum CPU ID value. Enable this function
to boot the legacy operating systems that cannot support processors with extended
CPUID functions. The options are Enabled and Disabled (for the Windows OS.).
Execute-Disable Bit Capability (Available when supported by the OS and
the CPU)
Set to Enabled to enable the Execute Disable Bit which will allow the processor
to designate areas in the system memory where an application code can execute
and where it cannot, thus preventing a worm or a virus from ooding illegal codes
to overwhelm the processor or damage the system during an attack. The default is
Enabled. (Refer to Intel and Microsoft Web Sites for more information.)
Intel® AES-NI
Set to Enabled to use the processor's Advanced Encryption Standard (AES) feature.
The options are Enabled and Disabled.
Hardware Prefetcher (Available when supported by the CPU)
If set to Enabled, the hardware pre fetcher will pre fetch streams of data and instruc-
tions from the main memory to the L2 cache in the forward or backward manner to
improve CPU performance. The options are Disabled and Enabled.
Adjacent Cache Line Prefetch (Available when supported by the CPU)
The CPU fetches the cache line for 64 bytes if this option is set to Disabled. The
CPU fetches both cache lines for 128 bytes as comprised if Enabled.
MLC Streamer Prefetcher (Available when supported by the CPU)
If set to Enabled, the MLC (mid-level cache) streamer prefetcher will prefetch
streams of data and instructions from the main memory to the L2 cache to improve
CPU performance. The options are Disabled and Enabled.
MLC Spatial Prefetcher (Available when supported by the CPU)
If this feature is set to Disabled, The CPU prefetches the cache line for 64 bytes.
If this feature is set to Enabled the CPU fetches both cache lines for 128 bytes as
comprised. The options are Disabled and Enabled.
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DCU Streamer Prefetcher
This feature enables prefetch of the next L1 data line based on multiple loads in
the same cache line. The options are Enabled and Disabled.
DCU IP Prefetcher
Set this feature to Enabled to activate the L1 Data Prefetcher based on sequential
load history. The options are Enabled and Disabled.
Intel® Virtualization Technology (Available when supported by the CPU)
Select Enabled to use the feature of Virtualization Technology to allow one platform
to run multiple operating systems and applications in independent partitions, creat-
ing multiple "virtual" systems in one physical computer. The options are Enabled
and Disabled. Note: If there is any change to this setting, you will need to power
off and restart the system for the change to take effect. Please refer to Intel’s web
site for detailed information.
CPU Power Management Conguration
Power Technology
This feature determines what power-saving scheme the motherboard uses. The
options are Disabled, Energy Efcient and Custom. If Custom is selected, the
following options become available:
EIST
EIST (Enhanced Intel SpeedStep Technology) allows the system to automati-
cally adjust processor voltage and core frequency in an effort to reduce
power consumption and heat dissipation. Please refer to Intel’s web site
for detailed information. The options are Disabled and Enabled.
Turbo Mode
This feature allows processor cores to run faster than marked frequency in
specic conditions. The options are Disabled and Enabled.
CPU C3 Report
Select Enabled to allow the BIOS to report the CPU C3 State (ACPI C2) to
the operating system. During the CPU C3 State, the CPU clock generator
is turned off. The options are Enabled and Disabled.
CPU C6 Report
Select Enabled to allow the BIOS to report the CPU C6 State (ACPI C3) to
the operating system. During the CPU C6 State, the power to all cache is
turned off. The options are Enabled and Disabled.
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CPU C7 Report
Select Enabled to allow the BIOS to report the CPU C7 State (ACPI C3) to
the operating system. CPU C7 State is a processor-specic low C-State.
The options are Enabled and Disabled.
Package C State Limit
If set to Auto, the AMI BIOS will automatically set the limit on the C-State
package register. The options are C0, C2, C6, and No Limit.
Long duration power limit - this is the processor power consumption limit (in
Watts) during a long duration time window.
Long duration maintained - this is the time in milliseconds where the Long Dura-
tion Power Limit is maintained.
Short duration power limit - During Turbo Mode, the system may exceed the
processor's default power setting and exceed the Short Duration Power limit. By
increasing this value, the processor can provide better performance for a short
duration.
Chipset Conguration
WARNING: Setting the wrong values in the following sections may cause
the system to malfunction.
North Bridge Conguration
This item displays the current IO chipset Revision.
Integrated IO Conguration
Intel® VT-d
Select Enabled to enable Intel's Virtualization Technology support for Direct I/O
VT-d by reporting the I/O device assignments to VMM through the DMAR ACPI
Tables. This feature offers fully-protected I/O resource-sharing across the Intel
platforms, providing the user with greater reliability, security and availability in
networking and data-sharing. The settings are Enabled and Disabled.
Intel® I/OAT
The Intel I/OAT (I/O Acceleration Technology) signicantly reduces CPU over-
head by leveraging CPU architectural improvements, freeing resources for more
other tasks. The options are Disabled and Enabled.
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Data Direct I/O
Select Enabled to enable Intel I/OAT (I/O Acceleration Technology), which sig-
nicantly reduces CPU overhead by leveraging CPU architectural improvements
and freeing the system resource for other tasks. The options are Disabled and
Enabled.
DCA Support
This feature accelerates the performance of I/O devices using Direct Cache
Access. The default is Enabled and can not be changed.
IOU1-PCIe Port
This feature allows the user to set the PCI-Exp bus speed between IOU1 and
PCI-e port. The options are x4x4 and x8.
CPU Slot3 PCI-E 3.0 x8 Link Speed
This feature enables the user to select the target link speed for this slot. The
options are GEN1 , GEN2, and GEN3.
IOU2 - PCIe Port
This feature allows the user to set the PCI-Exp bus speed between IOU2 and
PCIe port. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, and x16, and Auto.
SXB1 Slot1 PCI-E 3.0 x8/16 Link Speed
This feature enables the user to select the target link speed for this slot. The
options are GEN1 , GEN2, and GEN3.
SXB1 Slot2 PCI-E 3.0 x8 Link Speed
This feature enables the user to select the target link speed for this slot. The
options are GEN1 , GEN2, and GEN3.
IOU3 - PCIe Port
This feature allows the user to set the PCI-Exp bus speed between IOU3 and
PCIe port. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, and x16, and Auto.
SXB2 Slot1 PCI-E 3.0 x8/16 Link Speed
This feature enables the user to select the target link speed for this slot. The
options are GEN1 , GEN2, and GEN3.
SXB2 Slot2 PCI-E 3.0 x8 Link Speed
This feature enables the user to select the target link speed for this slot. The
options are GEN1 , GEN2, and GEN3.
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DIMM Conguration
Memory Conguration
This section displays memory status such as Current Memory Mode, Memory
Speed, Mirroring and Sparing information.
DIMM Information
This feature displays information regarding the installed memory.
Memory Mode
The only option is Independent, a feature that allows for all DIMMs to be avail-
able to the operating system.
DRAM RAPL Mode
RAPL which stands for Running Average Power Limit is a feature that provides
mechanisms to enforce power consumption limits on supported processors The
options are DRAM RAPL MODE0 , DRAM RAPL MODE1, and Disabled.
DDR Speed
Use this option to force the system memory to run at a different frequency than
the default frequency. The available options are Auto, Force DDR-800, Force
DDR-1066, Force DDR-1333, Force DDR3-1600 and Force SPD.
Channel Interleaving
This feature selects from the different channel memory interleaving methods.
The options are Auto, 1 Way, 2 Way, 3 Way and 4 Way.
Rank Interleaving
This feature selects from the different rank memory interleaving methods. The
options are Auto, 1 Way, 2 Way, 4 Way and 8 Way.
Patrol Scrub
Patrol Scrubbing is a process that allows the CPU to correct correctable memory
errors detected on a memory module and send the correction to the requestor
(the original source). When this item is set to Enabled, the North Bridge will read
and write back one cache line every 16K cycles, if there is no delay caused by
internal processing. By using this method, roughly 64 GB of memory behind the
North Bridge will be scrubbed every day. The options are Enabled and Disabled.
Demand Scrub
Demand Scrubbing is a process that allows the CPU to correct correctable
memory errors found on a memory module. When the CPU or I/O issues a
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demand-read command, and the read data from memory turns out to be a
correctable error, the error is corrected and sent to the requestor (the original
source). Memory is updated as well. Select Enabled to use Demand Scrubbing
for ECC memory correction. The options are Enabled and Disabled.
Data Scrambling
This feature enables Data Scrambling. The options are Enabled and Disabled.
Device Tagging
This feature enables Device Tagging. The options are Enabled and Disabled.
Thermal Throttling
This feature selects from the different throttling methods. The options are Dis-
abled and CLTT (Closed Loop Thermal Throttling).
South Bridge Conguration
This item displays the current South Bridge Revision.
All USB Devices
This feature enables all USB ports/devices. The options are Enabled and Dis-
abled. When set to enabled, EHCI Controller 1 and 2 (below) become available.
EHCI Controller 1 / EHCI Controller 2
This feature enables the Enhanced Host Controller Interface (EHCI). The options
are Enabled and Disabled.
Legacy USB Support
This feature enables support for legacy USB devices. Select Auto to disable
legacy support if USB devices are not present. Select Disable to have USB
devices available only for EFI applications. The options are Enabled, Disabled
and Auto.
Port 60/64 Emulation
This feature enables I/O port 60h/64h emulation support. This should be enabled
for complete USB keyboard legacy support for non-USB aware Operating Sys-
tems. The options are Enabled, and Disabled.
EHCI Hand-Off
This item is for Operating Systems that does not support Enhanced Host Con-
troller Interface (EHCI) hand-off. When enabled, EHCI ownership change will be
claimed by the EHCI driver. The settings are Enabled and Disabled.
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SATA Conguration
When this submenu is selected, the AMI BIOS automatically detects the presence
of the SATA Devices and displays the following items:
SATA Port0~Port5
This item displays the information detected on the installed SATA drives on the
particular SATA port.
SATA Mode
This item selects the mode for the installed drives. The options are Disabled, IDE
Mode, AHCI Mode and RAID Mode. The following are displayed depending on
your selection:
IDE Mode
The following items are displayed when IDE Mode is selected:
Serial-ATA Controller 0~1
This feature is used to activate/deactivate the SATA controller, and sets
the compatibility mode. The options are Disabled, Enhanced, and Compat-
ible. The default of Serial-ATA Controller 0 is Compatible. The default of
Serial-ATA Controller 1 is Enhanced.
AHCI Mode
The following items are displayed when AHCI Mode is selected:
Aggressive Link Power Management
This feature Enables or Disables Aggressive Link Power Management
support for Cougar Point B0 stepping and later. The options are Enabled
and Disabled.
Port 0~5 Hot Plug
Set this item to Enabled to enable hot-plugging for the particular port.
The options are Enabled and Disabled.
Staggered Spin Up
Set this item to Enabled to enable Staggered Spin-up support. The
options are Enabled and Disabled.
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RAID Mode
The following items are displayed when RAID Mode is selected:
Port 0~5 Hot Plug
Set this item to Enabled to enable hot-plugging for the particular port.
The options are Enabled and Disabled.
SCU Conguration
When this submenu is selected, the AMI BIOS automatically detects the presence
of the SAS SCU devices and displays the following items:
Storage Controller Unit (SCU)
Set this item to Enabled to activate the chipset's SCU devices. The options are
Enabled and Disabled.
OnChip SCU Option ROM
Set this item to Enabled to activate the onboard SAS option ROM. The options are
Enabled and Disabled.
PCIe/PCI/PnP Conguration
This feature allows the user to set the PCI/PnP congurations for the following items:
PCI ROM Priority
In case of multiple Option ROMs (Legacy and EFI-compatible), this feature speci-
es what ROM to launch. The options are Legacy ROM and EFI Compatible ROM.
PCI Latency Timer
This feature sets the latency Timer of each PCI device installed on a PCI bus. Se-
lect 64 to set the PCI latency to 64 PCI clock cycles. The options are 32 PCI Bus
Clocks, 64 PCI Bus Clocks, 96 PCI Bus Clocks, 128 PCI Bus Clocks, 160 PCI
Bus Clocks, 192 PCI Bus Clocks, 224 PCI Bus Clocks and 248 PCI Bus Clocks.
Above 4G Decoding
Set this item to Enabled to activate 64-bit capable devices to be decoded above
the 4G address space. This works only if the system supports 64-bit PCI decoding.
The options are Enabled and Disabled.
PERR# Generation
Set this item to Enabled to allow PCI devices to generate PERR# error codes. The
options are Enabled and Disabled.
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SERR# Generation
Set this item to Enabled to allow PCI devices to generate SERR# error codes. The
options are Enabled and Disabled.
Maximum Payload
This feature selects the setting for the PCIE maximum payload size. The options
are Auto, 128 Bytes, and 256 Bytes.
Maximum Read Request
This feature selects the setting for the PCIE maximum Read Request size. The
options are Auto, 128 Bytes, 256 Bytes, 512 Bytes, 1024 Bytes, 2048 Bytes, and
4096 Bytes.
ASPM Support
Set this item to the desired ASPM (Active State Power Management) level. The