Supermicro X8OBN-F, X8OBN-CPU, X8OBN-BR1 User Manual

X8OBN-F Platform

with

X8OBN-F Baseboard

X8OBN-CPU CPU Board

X8OBN-BR1 Bridge Card

USER’S MANUAL

Revision 1.1a

The information in this User’s Manual has been carefully reviewed and is believed to be accurate.
The vendor assumes no responsibility for any inaccuracies that may be contained in this document,
and makes no commitment to update or to keep current the information in this manual, or to notify
any person or organization of the updates. Please Note: For the most up-to-date version of this

manual, please see our Website at www.supermicro.com.

Super Micro Computer, Inc. ("Supermicro") reserves the right to make changes to the product
described in this manual at any time and without notice. This product, including software and docu­mentation, is the property of Supermicro and/or its licensors, and is supplied only under a license.
Any use or reproduction of this product is not allowed, except as expressly permitted by the terms
of said license.

IN NO EVENT WILL SUPER MICRO COMPUTER, INC. BE LIABLE FOR DIRECT, INDIRECT,
SPECIAL, INCIDENTAL, SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE
USE OR INABILITY TO USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF
THE POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, SUPER MICRO COMPUTER, INC.
SHALL NOT HAVE LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED OR USED
WITH THE PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, INTEGRATING,
INSTALLING OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA.

Any disputes arising between the manufacturer and the customer shall be governed by the laws of
Santa Clara County in the State of California, USA. The State of California, County of Santa Clara
shall be the exclusive venue for the resolution of any such disputes. Supermicro's total liability for
all claims will not exceed the price paid for the hardware product.

FCC Statement: This equipment has been tested and found to comply with the limits for a Class
A digital device pursuant to Part 15 of the FCC Rules. These limits are designed to provide
reasonable protection against harmful interference when the equipment is operated in a commercial
environment. This equipment generates, uses, and can radiate radio frequency energy and, if not
installed and used in accordance with the manufacturer’s instruction manual, may cause harmful
interference with radio communications. Operation of this equipment in a residential area is likely
to cause harmful interference, in which case you will be required to correct the interference at your
own expense.

California Best Management Practices Regulations for Perchlorate Materials: This Perchlorate
warning applies only to products containing CR (Manganese Dioxide) Lithium coin cells. “Perchlorate
Material-special handling may apply. See www.dtsc.ca.gov/hazardouswaste/perchlorate”.

WARNING: Handling of lead solder materials used in this
product may expose you to lead, a chemical known to
the State of California to cause birth defects and other
reproductive harm.

Manual Revision 1.1a
Release Date: Dec. 9, 2011
Unless you request and receive written permission from Super Micro Computer, Inc., you may not

copy any part of this document.
Information in this document is subject to change without notice. Other products and companies

referred to herein are trademarks or registered trademarks of their respective companies or mark
holders.

Copyright © 2011 by Super Micro Computer, Inc.
All rights reserved.

Printed in the United States of America

Preface

This manual is written for system integrators, PC technicians and
knowledgeable PC users. It provides information for the installation and use of the
X8OBN-F platform, which consists of the X8OBN Baseboard, the X8OBN-CPU
Board, and the X8OBN-BR1 Bridge Card.

Note: CPU card and CPU board, Bridge card and Bridge board are used
interchangeably in this manual.

About the X8OBN-F Platform

The X8OBN-F platform consists of the X8OBN Baseboard, the X8OBN-CPU CPU
Board, and the X8OBN-BR1 Bridge Card. Each X8OBN-CPU Board supports up
to two Intel 7500 series processors and 16 DDR3 1066MHz memory modules. The
Intel 7500 series processors offer Intel QuickPath Interconnect (QPI) Technology,
providing point-to-point system interface that replaces Front Side Bus technology.
The X8OBN-BR Bridge card provides connections between a pair of the CPU boards
installed on the X8OBN Baseboard. With support of Intel Turbo Boost Technology
and up to 80 CPU cores, the X8OBN-F platform offers substantial enhancement in
system performance for 4-way and 8-way servers. Please refer to our Website at
http://www.supermicro.com for processor and memory support updates. This prod­uct is intended to be installed and serviced by professional technicians.

Preface

Manual Organization

Chapter 1 provides quick installation instructions.
Chapter 2 describes the features, specifi cations and performance of the X8OBN-F

baseboard, and provides detailed information on the 7500 chipset.
Chapter 3 provides hardware installation instructions. Read this chapter when in-

stalling the processor, memory modules and other hardware components into the
system. If you encounter any problems, see Chapter 4, which describes trouble­shooting procedures for video, memory and system setup stored in CMOS.

Chapter 5 includes an introduction to BIOS and provides detailed information on
running the CMOS Setup Utility.

Appendix A provides BIOS Error Beep Codes.
Appendix B lists software installation instructions.

iii

X8OBN-F Platform User’s Manual

Conventions Used in this Manual

Pay special attention to the following symbols for proper baseboard installation and
to prevent damage to the system or injury to yourself:

Danger/Caution: Instructions to be strictly followed to prevent catastrophic
system failure or to avoid bodily injury,

Warning: Important information given to ensure proper system installation
or to prevent damage to the components,

Note: Additional information given to differentiate between various models
or to provide information for correct system setup.

iv

Contacting Supermicro

Headquarters

Address: Super Micro Computer, Inc.

980 Rock Ave.
San Jose, CA 95131 U.S.A.

Tel: [phone]
Fax: [phone]
Email: [e-mail] (General Information)

[e-mail] (Technical Support)

Website: www.supermicro.com

Europe

Address: Super Micro Computer B.V.

Preface

Het Sterrenbeeld 28, 5215 ML
's-Hertogenbosch, The Netherlands

Tel: [phone]
Fax: [phone]
Email: [e-mail] (General Information)

[e-mail] (Technical Support)
[e-mail] (Customer Support)

Asia-Pacifi c

Address: Super Micro Computer, Inc.

4F, No. 232-1, Liancheng Rd.
Chung-Ho 235, Taipei County
Taiwan, R.O.C.

Tel: [phone]
Fax: [phone]
Website: www.supermicro.com.tw
Email: [e-mail] (Technical Support)
Tel: [phone] (Technical Support)

v

X8OBN-F Platform User’s Manual

Table of Contents

Preface
Chapter 1 Quick Installation Guide

1-1 Preparation for Proper System Installation ..................................................... 1-1

1-2 Installing the CPU on the CPU Board ............................................................ 1-2

1-3 Installing the Memory Module on the CPU Board ..........................................1-2

1-4 Installing the CPU Heatsink on the CPU Board .............................................1-3

1-5 Attaching the Air Shroud on the CPU Module ................................................ 1-3

1-6 Installing the Baseboard into the Chassis ...................................................... 1-4

1-7 Installing the CPU Module on the Baseboard ................................................ 1-5

1-8 Installing the Bridge Board between the CPU Boards ................................... 1-6

1-9 Installing Internal Peripherals ..........................................................................1-7

1-10 Installing External Peripherals ........................................................................1-8

Chapter 2 Overview

2-1 Overview ......................................................................................................... 2-1

2-2 Chipset Overview ..........................................................................................2-13

2-3 Special Features ...........................................................................................2-14

2-4 PC Health Monitoring .................................................................................... 2-14

2-5 ACPI Features ...............................................................................................2-15

2-6 Power Supply ................................................................................................2-15

2-7 Super I/O ....................................................................................................... 2-16

2-8 Overview of the Nuvoton WPCM450R Controller .......................................2-16

Chapter 3 Installation

3-1 Static-Sensitive Devices ..................................................................................3-1

Precautions .....................................................................................................3-1

Unpacking .......................................................................................................3-1

3-2 Populating the CPU Board ..............................................................................3-2

Installing a CPU on the CPU Board ............................................................... 3-2

Installing the CPU Heatsink on the CPU Board .............................................3-3

Installing Memory Modules on the CPU Board .............................................. 3-4

Removing Memory Modules ........................................................................... 3-4

3-3 Installing the Baseboard into the Chassis ...................................................... 3-5

Tools Needed .................................................................................................. 3-5

3-4 Installing the Populated CPU Board on the Baseboard ................................. 3-6

3-5 Installing the Bridge Card between the CPU Boards .....................................3-7

3-6 Memory Support for the X8OBN-F Platform ................................................... 3-8

3-7 Control Panel Connectors/I/O Ports..............................................................3-10

Back Panel Connectors/I/O Ports .................................................................3-10

vi

Table of Contents

Back Panel I/O Port Locations and Defi nitions ...........................................3-10

ATX PS/2 Keyboard and PS/2 Mouse Ports .............................................3-11

Universal Serial Bus (USB) ...................................................................... 3-12

Serial Ports ............................................................................................... 3-13

Video Connection .....................................................................................3-13

Ethernet Ports .......................................................................................... 3-14

Unit Identifi er Switch ................................................................................3-15

Front Control Panel ....................................................................................... 3-16

Front Control Panel Pin Defi nitions............................................................... 3-17

NMI Button ............................................................................................... 3-17

Power LED ..............................................................................................3-17

HDD LED .................................................................................................. 3-18

NIC1/NIC2 LED Indicators ....................................................................... 3-18

Overheat (OH)/Fan Fail/PWR Fail/UID LED ............................................ 3-19

Power Fail LED ........................................................................................ 3-19

Reset Button ........................................................................................... 3-20

Power Button ........................................................................................... 3-20

3-8 Connecting Cables ........................................................................................ 3-21

Power Connectors ...................................................................................3-21

DOM Power Connector ............................................................................ 3-21

Fan Headers ............................................................................................. 3-22

Chassis Intrusion .....................................................................................3-22

Internal Buzzer ......................................................................................... 3-23

Power LED/Speaker ................................................................................. 3-23

TPM Header/Port 80 ................................................................................ 3-24

Overheat LED/Fan Fail ............................................................................3-24

T-SGPIO 1/2 Headers .............................................................................. 3-25

3-9 Jumper Settings ............................................................................................3-26

Explanation of Jumpers ................................................................................3-26

GLAN Enable/Disable ..............................................................................3-26

CMOS Clear ............................................................................................. 3-27

Watch Dog Enable/Disable ...................................................................... 3-27

VGA Enable .............................................................................................. 3-28

TPM Support Enable ................................................................................ 3-28

BMC Enable ............................................................................................ 3-29

ME Recovery ...........................................................................................3-29

Manufacturer Mode Select ....................................................................... 3-30

JUID_OW1 (UID_Overwriting)..................................................................3-30

BMC Reset .............................................................................................. 3-31

vii

X8OBN-F Platform User’s Manual

3-10 Onboard LED Indicators ...............................................................................3-32

GLAN LEDs .............................................................................................. 3-32

IPMI Dedicated LAN LEDs .......................................................................3-32

Rear UID LED ......................................................................................... 3-33

BMC Heartbeat LED ................................................................................3-33

3-11 Serial ATA Connections ................................................................................. 3-34

Serial ATA Ports........................................................................................ 3-34

Chapter 4 Troubleshooting

4-1 Troubleshooting Procedures ...........................................................................4-1

Before Power On ............................................................................................ 4-1

No Power ........................................................................................................ 4-1

No Video ......................................................................................................... 4-2

System Boot Failure ..................................................................................... 4-2

Losing the System’s Setup Confi guration ....................................................... 4-2

Memory Errors ...............................................................................................4-3

When the System Becomes Unstable ............................................................ 4-3

4-2 Technical Support Procedures ........................................................................4-4

4-3 Frequently Asked Questions ...........................................................................4-5

4-4 Returning Merchandise for Service.................................................................4-6

Chapter 5 BIOS

5-1 Introduction ...................................................................................................... 5-1

Starting BIOS Setup Utility ..............................................................................5-1

How To Change the Confi guration Data ......................................................... 5-1

Starting the Setup Utility ................................................................................. 5-2

5-2 Main Setup ......................................................................................................5-2

5-3 Advanced Setup Confi guration .......................................................................5-4

5-4 Chipset .......................................................................................................... 5-19

5-5 Server Management ......................................................................................5-27

5-6 iSCSI ............................................................................................................. 5-29

5-7 Boot Confi guration ........................................................................................ 5-29

5-8 Security ......................................................................................................... 5-31

5-9 Save & Exit ................................................................................................... 5-32

Appendix A BIOS Error Beep Codes

A-1 BIOS Error Beep Codes ................................................................................. A-1

Appendix B Software Installation Instructions

B-1 Installing Software Programs ..........................................................................B-1

B-2 Confi guring SuperDoctor III ............................................................................ B-2

viii

Chapter 1: Quick Installation Guide

Chapter 1

Quick Installation Guide

If you purchase a bare bone system from Supermicro, the X8OBN-F Baseboard, the
X8OBN-CPU CPU Module, which includes the CPU board and its accessory, and
the X8OBN-BR1 Bridge Module, which includes a bridge board and its accessory,
are enclosed in the chassis. To prepare your system for proper installation, follow
the instructions below.

1-1 Preparation for Proper System Installation

Removing the Bridge Module from the Chassis

Loosen the screws on the Bridge board bracket.1.

Using even pressure pull the Bridge module out of the CPU module.2.

Removing the CPU Module from the Chassis

Locate the red latches on the handles of the CPU module1.

Press both red latches outwards (towards the ends of the chassis) to release 2.
the CPU module handle from its locking position.

Hold both handles of the CPU board upwards to gently pull the CPU board 3.
out from the chassis.

A

B

Press the red latches outwards to

unlock the CPU Board

Note 1. All graphics and images are for illustration only. They may be dif-

ferent from what you have in your system.
Note 2. CPU card and CPU board, Bridge card and Bridge board are used

interchangeably in this manual.

Pull the handles upwards to remove

the CPU Board from the chassis.

1-1

X8OBN-F Platform User's Manual

1-2 Installing the CPU on the CPU Board

2

A B

1

A. Press the socket clip down to unlock
it. Gently lift the socket clip to open the
load plate.

C

CPU Pin 1

C. Align CPU Pin 1 against Socket Pin

1. Once they are aligned, lower the CPU
down to the socket.

CPU Key

B. Align the CPU key with the socket
key.

D

D. Once the CPU is fully seated on

the socket, press the socket clip down
to lock it.

To avoid damaging the CPU, do not rub the CPU pins against the
socket.

1-3 Installing the Memory Module on the CPU Board

A B C

A. Align the key on the DIMM module

against the key of the DIMM socket.
B. Insert the DIMM module straight

down to the DIMM socket by pressing
both ends of the DIMM module at the
same time.

C. Press the notches on the ends of
the DIMM module inwards to lock it.

1-2

Chapter 1: Quick Installation Guide

1-4 Installing the CPU Heatsink on the CPU Board

A B

A. If needed, apply the proper amount

of thermal grease (with thickness of
up to 0.13 mm) to the heatsink.

Note: The proper amount of
thermal grease has been ap­plied to our heatsinks. If you
use a heatsink purchased
from SMC, skip this step.

B. Place the heatsink on top of the
CPU so that the two mounting holes
on the heatsink are aligned with those
on the retention mechanism.

C. Insert t wo push- pins on the sid es
of the heatsink through the mount­ing holes on the motherboard, and
turn the push-pins clockwise to lock
them.

1-5 Attaching the Air Shroud on the CPU Module

Attach the air shroud on the CPU module before you install the CPU module on
the X8OBN baseboard, making sure that all four hooks of the air shroud are fully
engaged.

Populated CPU Board (w/Air Shroud)

Populated CPU Board (w/Air Shroud) (Side View)

Populated CPU Board (w/Air Shroud) (Side View)

1-3

X8OBN-F Platform User's Manual

1-6 Installing the Baseboard into the Chassis

Follow the steps below to install the baseboard into the chassis. Be sure to install
the IO shield on the rear side of the chassis before you install the baseboard.

A. Locate the release latch on the
handle of the power distributor.
Press the release latch to release
the power distributor from locking
position.

B. Push the handle of the power
distributor forwards to make room
for the main board to be installed.

C. Locate the mounting holes (23)
on the baseboard.

D. Install standoffs in the chassis as
needed and secure the baseboard
to the standoffs with screws.

E. Place the baseboard in the chas­sis making sure that the mounting
holes on the baseboard match the
corresponding standoffs on the
chassis. Please note that there
are three locating standoffs in the
chassis as shown in the draw­ing. Be sure that the main board
is fully seated on these locating
standoffs.

C

USB 0/1

COM1

VGA

LAN1

LAN2

LED6

LED4

B

KB/Mouse

IPMI LAN

Fan12

J30
J29

Fan 11

Fan 10

J25

UID

J32

Fan 9

JPT1
JUID_OW1

LAN CTRL

JPL1

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

BMC CTRL

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

JPB1

JPRST1

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

D

E

Image will be placed

when available

LS

X8OBN-F Baseboard

Rev. 1.01

LED15

LED13

LED16

LED17

LED14

LED18

LED19

LED12

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 2

Battery

BT1

JBT1

JPME1

ICH10R

JPME2

JWF1

JIPMB1

JTPM1

USB8

USB2/3

USB4/5

I-SATA4

Locating Standoff

Image will be placed

when available

LS

JWD1

JOH1

Fan8

I/O Hub 1

Buzzer

I-SATA5

I-SATA3

I-SATA1

COM2

I-SATA2

I-SATA0

JPWR3

Fan7

J26

Fan2

JPWR1

Fan1

LS

JF1

FP CRTL

Fan6

Fan5

JP18

Fan4

JP19

JP17

Fan3

JP16

JPWR4

JP3

PWR 1

JP22

JPWR2

JD1

PWR 2

T-SGPIO2

JL1

JP21

T-SGPIO1

Note: Mounting Holes
marked with are for
locating standoffs.

F. Pull the handle of the power
distributor backward to connect it
to the base board.

G. Connect the HDD Power Con­nector cables to the power supply
through an opening on the middle
fan plate.

H. Connect the intrusion cable and
the Front Panel Control cable.

LS

1-4

G

H

when available

Image will be placed

when available

X8OBN BaseBoard in the Chassis

Image will be placed

Chapter 1: Quick Installation Guide

1-7 Installing the CPU Module on the Baseboard

After populating the CPU board with needed components, and installing the base­board in the chassis, you can install the CPU module on the baseboard.

A. Using two hands, hold both handles of the CPU module.
B. Locate the CPU board slots on the X8OBN baseboard. Insert a CPU module into

a CPU board slot by following the steps below, starting from Slot1.

Align the guiding edges of the CPU bracket against the guiding rails on the 1.
middle fan bracket and on the rear window of the chassis.

Insert the CPU module into the baseboard until the bottom of the CPU board 2.
contacts the top of the CPU slot.

Press both handles of the CPU board inwardly to close them. Then, gently 3.
push the CPU board into the CPU board slot until the CPU board is fully
seated in the CPU slot.

Press the red latches on the handles of the CPU bracket to lock the CPU 4.
module onto the baseboard.

A

X8OBN-F Baseboard

Rev. 1.01

X8OBN Baseboard

D

CPU Board Slot4
CPU Board Slot3

CPU Board Slot2

CPU Board Slot1

B

Populated CPU Board (w/Air Shroud)

CPU Board

CPU Board Slot

BaseBoard

1-5

X8OBN-F Platform User's Manual

1-8 Installing the Bridge Board between the CPU
Boards

Once you've installed the CPU modules on the baseboard, you can install the
X8OBN-BRI Bridge board on the CPU boards.

Note: A Bridge board is needed to connect the pair(s) of the CPU boards
installed on Slot1 & Slot2, and/or Slot3 & Slot4. There is no Bridge board
needed between Slot2 and Slot3. Refer to the table below for details.

CPU Board

on Slot1

Yes Yes No No One card needed

Yes Yes Yes Yes One card needed

CPU Board

on Slot2

CPU Board

on Slot3

CPU Board

on Slot4

X8OBN-BRI Bridge Board

to be Installed

between Slot1 & Slot2

between Slot1 & Slot2;

Another card needed

between Slot3 & Slot4

Memory
Support

16/32

DIMMs

32/64

DIMMs

To install the Bridge board between the CPU boards, follow the steps below:

A. Place the Bridge module on top of the CPU boards, making sure that the slot on
the Bridge board matches the golden fi nger of the CPU boards.

B. Press the module evenly to ensure that the gold fi ngers of the CPU boards are
fully seated on the Bridge board slots. Double check to make sure that all Bridge
modules are aligned horizontally after installation.

Bridge Card

X8OBN-BR1 Bridge Card

Populated CPU Board with Air Shroud

Four CPU Boards

1-6

To Connect to the CPU Board

Two Bridge Cards

1-9 Installing Internal Peripherals

A

SATA Drives

B

Add-on Cards

Chapter 1: Quick Installation Guide

Remove screws from the assembly.1.

Pull the AC plug cage out of the chassis.2.

Remove the L bracket.3.

Install add-on cards.4.

Install screws and lock add-on cards.5.

Insert the add-on card assembly properly into the chassis.6.

Secure it to the chassis with screws.7.

1-7

X8OBN-F Platform User's Manual

1-10 Installing External Peripherals

Mouse

Keyboard

All graphics and images are for illustration only. They may be different from 1.
what you have in your system.

For more details on power cable connection, please refer to Section 3-8 in 2.
Chapter. Also refer to Chapter 3 for more information on system installation.

IPMI LAN

USB 0/1

Notes:

COM1 VGA

LAN1 LAN 2

UID

Switch

1-8

Chapter 2: Overview

Chapter 2

Overview

2-1 Overview

Checklist

Congratulations on purchasing your computer system from an acknowledged leader
in the industry. Supermicro systems are designed with the utmost attention to detail
to provide you with the highest standards in quality and performance.

For more information regarding this product, please visit our website at www.
supermicro.com.

2-1

X8OBN-F Platform User’s Manual

X8OBN-F Baseboard Image

Note: All graphics shown in this manual were based upon the latest PCB

Revision available at the time of publishing of the manual. The board
you've received may or may not look exactly the same as the graphics
shown in this manual.

2-2

X8OBN-F Baseboard Layout

Chapter 2: Overview

COM1

VGA

USB 0/1

LAN1

LAN2

LED6

UID

JPL1

LED4

Fan12

J30

J29

Fan 11

J25
J32

LAN CTRL

BMC CTRL

JPB1

KB/Mouse

IPMI LAN

Fan 10
Fan 9

JPRST1

JPT1
JUID_OW1

LED13

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

X8OBN-F Baseboard

Rev. 1.01

LED15

LED16

LED14

LED17

LED19

LED18

PLX
PCI Bridge

USB10

USB8

JPME1

JIPMB1

I/O Hub 2

JBT1

ICH10R

USB4/5

JTPM1

USB2/3

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

Battery

BT1

JWF1

I-SATA4

JPME2

I-SATA5

I/O Hub 1

I-SATA3

I-SATA2

Fan8

Buzzer

I-SATA1

I-SATA0

JOH1

JWD1

COM2

JPWR3

Fan7

Fan2

JPWR1

J26

Fan1

JP3

JPWR2

FP CRTL

JPWR4

JD1

T-SGPIO2

JL1

T-SGPIO1

JP22

JP21

JF1

Fan6

Fan5

JP18

Fan4

JP19

JP17

Fan3

JP16

PWR 1

PWR 2

Notes:

See Chapter 3 for detailed information on jumpers, I/O ports and JF1 front

•

panel connections.

" " indicates the location of "Pin 1".

•

Jumpers not indicated are for testing only. •

LED Indicators that are not documented are for testing only.•

Please refer to the quick installation guide in Chapter 1 and installation instruc-•
tions listed in Chapter 3 for installation instructions.

2-3

X8OBN-F Platform User’s Manual

X8OBN-CPU Board Image

MB3
(for CPU2)

MB1
(for CPU2)

X8OBN-CPU

Rev.1.01

P2-DIMM6A

P2-DIMM5A

P2-DIMM7A

P2-DIMM8A

P2-DIMM2A

P2-DIMM1A

P2-DIMM3A

P2-DIMM4A

X8OBN-CPU Board Layout

J48J47

MB4
(for CPU2)

MB2
(for CPU2)

J35

J43

J44

CPU2

CPU1

J45J46

MB2
(for CPU1)

MB4
(for CPU1)

P1-DIMM4A

P1-DIMM3A

MB1
(for CPU1)

P1-DIMM1A

P1-DIMM2A

P1-DIMM8A

P1-DIMM7A

MB3
(for CPU1)

P1-DIMM5A

P1-DIMM6A

J36

2-4

X8OBN-BR1 Bridge Card Image

Chapter 2: Overview

2-5

X8OBN-F Platform User’s Manual

COM1

VGA

USB 0/1

LAN1

LAN2

LED6

UID

JPL1

LED4

Fan12

J30

J29

Fan 11

J25
J32

LAN CTRL

BMC CTRL

JPB1

KB/Mouse

IPMI LAN

Fan 10
Fan 9

JPRST1

JPT1
JUID_OW1

LED13

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

X8OBN-F Baseboard Layout

X8OBN-F Baseboard

Rev. 1.01

LED15

LED16

LED14

LED17

LED19

LED18

PLX
PCI Bridge

USB10

USB8

JPME1

JIPMB1

I/O Hub 2

JBT1

ICH10R

USB4/5

JTPM1

USB2/3

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

Battery

BT1

JWF1

I-SATA4

JPME2

I-SATA5

I/O Hub 1

I-SATA3

I-SATA2

Fan8

Buzzer

I-SATA1

I-SATA0

JOH1

JWD1

COM2

JPWR3

Fan7

Fan2

JPWR1

J26

Fan1

JP3

JPWR2

FP CRTL

JPWR4

JD1

T-SGPIO2

JL1

T-SGPIO1

JP22

JP21

JF1

Fan6

Fan5

JP18

Fan4

JP19

JP17

Fan3

JP16

PWR 1

PWR 2

Note: Due to PCI-E auto-switching, please follow the instructions below.

For PCI-E 2.0 Slot 10 and Slot 9• : Install Slot 10 fi rst. However, Slot 10

will be down-graded to support a PCI-E 2.0 x8 device when Slot 9 is
populated with a PCI-E 2.0x8 device.

For PCI-E 2.0 Slot 8 and Slot 7• : Install Slot 8 fi rst. However, Slot 8
will be down-graded to support a PCI-E 2.0 x8 device when Slot 7 is
populated with a PCI-E 2.0x8 device.

For PCI-E 2.0 Slot 6 and Slot 5• : Install Slot 6 fi rst. However, Slot 6
will be down-graded to support a PCI-E 2.0 x8 device when Slot 5 is
populated with a PCI-E 2.0x8 device.

For PCI-E 2.0 Slot 4 and Slot 3• : Install Slot 4 fi rst. However, Slot 4
will be down-graded to support a PCI-E 2.0 x8 device when Slot 3 is
populated with a PCI-E 2.0x8 device.

2-6

Chapter 2: Overview

X8OBN-F Baseboard Quick Reference

X8OBN-F Jumpers

Jumper

JBT1
JPB1

Description Default Setting

Clear CMOS See Chapter 3

BMC Enabled Pins 1-2 (Enabled)
JPG1 VGA Enabled Pins 1-2 (Enabled)
JPME1 ME Mode Recovery Off (Normal)
JPME2 ME Mode Select Off (Normal)
JPL1 GLAN1/GLAN2 Enable Pins 1-2 (Enabled)
JPRST1 BMC Reset Off (Normal)
JPT1 TPM Enabled Pins 1-2 (Enabled)
JUID_OW1 UID Overwrite Off (Normal)
JWD1 Watch Dog Pins 1-2 (Reset)

X8OBN-F Baseboard Connectors

Connectors Description

3-pin Fans (Two) 3-pin Fan Headers for IOH1 (Fan7) & IOH2 (Fan8)
4-pin Fans (Six) 4-pin System/Cooling Fan Headers (Fan1/Fan2,

Fan9~Fan 12)

(Four) 4-pin CPU_Board Fan Headers (Fan3~Fan6)
BT1 Onboard Battery (See Chpt. 4 for Used Battery Disposal)
Buzzer Internal Buzzer
CPU Board Slots

CPU Board Slots 1~4 (for CPU boards)
1~4

COM1/COM2 COM/Serial Connections
I-SATA 0~5 Intel SB SATA Connectors 0~5
JD1 Speaker/Power LED Indicator
JF1 Front Panel Control Header
JIPMB1 4-pin External BMC I

2

C Header (for an IPMI Card)
JL1 Chassis Intrusion
JOH1 Overheat/Fan Fail LED
JP16~JP19 HDD Power Connectors (See Warning on Pg. 2-8)
JP21/JP22 Main Power supply Connectors (JP22: PWR1/JP21: PWR2)

JPWR1~JPWR4 8-Pin GPU Power Connectors (Warning on Pg. 2-8.)
JTPM1 TPM (Trusted Platform Module)/Port 80 Header
JWF1 SATA DOM (Device_On-Module) Power Connector (See

KB/MOUSE Keyboard/Mouse Connections

(See Warning on Pg. 2-8)

Warning on Pg. 2-8)

2-7

X8OBN-F Platform User’s Manual

LAN1/LAN2 G-bit Ethernet Ports 1/2
(IPMI) LAN IPMI_Dedicated LAN
PCI-E 2.0 x8 PCI-Express 2.0 x8 Slots (Slot3/Slot5/Slot7/Slot9)(See Note

on P. 2-6)

PCI-E 2.0 x8 in x16 PCI-Express 2.0 x8 in x16 Slots (Slot1/Slot2) (See Note on

P. 2-6)

PCI-E 2.0 x16 PCI-Express 2.0 x16 Slots (Slot4/Slot6/Slot8/Slot10) (See

Note on P. 2-6)

T-SGPIO 1/2 Serial_Link General Purpose I/O Headers
USB 0/1 Back Panel USB 0/1
USB 2/3, USB 4/5,

USB 8, USB 10
UID Switch UID (Unit Identifi er) Switch
VGA Backpanel VGA Port

LED Description State Status

LED4 BMC Heartbeat LED Green: Blinking Normal

LED 6 UID LED

LED12~LED19 Port 80 LEDs

Note: For PCI-E slots to work properly, follow the instructions listed on
Page 2-6.

Warning! To avoid damaging the power supply or the system, and to
provide adequate power to the components, be sure to connect the main
power connectors (JP22, JP21) and the following power connectors to the
power supply. Failure to do so will void the manufacturer warranty.

Front Panel Accessible USB Connections

X8OBN-F LED Indicators

Blue: On (Windows OS),
Blinking (Linux)

8-bit binary POST Code
LEDs

UID LED

(for future
debug)

Main Power Connectors (JP22, JP21).

•

HDD Power Connectors (reserved for HDD used only) (JP16~JP19)•

GPU 8-pin Power Connectors (reserved for graphics card use only) (JPWR1/•
JPWR2/JPWR3/JPWR4)

SATA DOM Power Connector used for SATA devices (JWF1)

•

2-8

Baseboard Features

Chapter 2: Overview

Baseboard

CPU (per
CPU Board)

Memory (per
CPU Board)

Modular design with a baseboard with four CPU_board
slots that support up to four CPU boards;

The baseboard includes two 7500 IO hubs, one 1.
PLX PEX8648 PCI-E software controller and ten
PCI-E slots;

Each CPU board includes the following:2.
Two Intel•

cessors; each processor supports four full-width Intel
QuickPath Interconnect (QPI) links (with support of
up to 25.6 GT/s per QPI link and with Data Transfer
Rate of up to 6.4 GT/s per direction)

16 DDR3R RDIMMs running at speeds of 1066/978/800 •
MHz (via an onboard buffer)

Support for up to 256 GB of Registered ECC DDR3

•

memory per CPU board
RDIMM

• 1GB, 2GB, 4GB, 8GB, and 16GB

®

7500 Series (Socket LS-LGA 1567) pro-

Chipset

Expansion
Slots (See

Page 2-6)
Graphics
Network

I/O Devices

Two Intel® 7500 IO Hubs•
One ICH10R•
Four (4) PCI E 2.0 x8 • (Slot3/Slot5/Slot7/Slot9)
Two (2) PCI E 2.0 x8 in x16

• (Slot1/Slot2)

Four (4) PCI E 2.0 x16

• (Slot4/Slot6/Slot8/Slot10)

Winbond BMC Video Controller (Matrox G200eW)•
One Intel 82576 Gigabit (10/100/1000 Mb/s) Ethernet •

Dual-Channel Controller for LAN 1/LAN 2 ports.
One IPMI LAN 2.0 port supported by the BMC

•

SATA Connections

SATA Ports

• Six (6)

RAID (Win-

•

dows)

Integrated IPMI 2.0

IPMI 2.0 supported by the WPCM450R BMC

•

Serial (COM) Port

RAID 0, 1, 5, 10

Two (2) Fast UART 16550 Connections: a Backplane

•

Serial Port and a Front Accessible Serial Header

2-9

X8OBN-F Platform User’s Manual

Super I/O

Winbond Super I/O 83527

•

Peripheral
Devices

BIOS

Power

USB Devices

Two (2) USB ports on the rear I/O panel (USB 0/1)

•

Two (2) USB connectors (4 ports) for front access •
(USB 2/3, USB 4/5)

Two (2) Type A internal connector (USB 8/10)

•

64 Mb SPI AMI BIOS•
APM 1.2, PCI 2.3, ACPI 1.0/2.0/3.0, USB Keyboard,

•

Plug & Play (PnP) and SMBIOS 2.5
Two (2) Main Power Supply Connectors (PWR1/•

PWR2)
Four (4) 8-pin GPU Power Connectors

•

(JPWR1~JPWR4),
Four (4) HDD Power Connectors (JP16/JP17/JP18/3.

JP19)

One (1) SATA DOM Power Connection (JWF1)

•

Note: All these power connections are required
for adequate power supply to the components
and the system.

®

SM Flash BIOS

Confi g.

PC Health
Monitoring

ACPI/ACPM Power Management

•

Main switch override mechanism•
Power-on mode for AC power recovery•

CPU Monitoring

Onboard voltage monitors for CPU Vcore (up to 8
CPUs), IOH1 Vcore, IOH2 Vcore, 3.3VDD, 3.3VSB,
P3V3, P3V3_AUX, 12V, 5V, Memory Voltage, and Bat­tery Voltage.

CPU 7-Phase switching voltage regulator

•

CPU/System overheat LED and control•
CPU Thermal Trip support•
Thermal Monitor 2 (TM2) support•

2-10

Chapter 2: Overview

Fan Control

Twelve (12) 4-pin system cooling fans with Fan status

•

monitoring with fi rmware (Pulse Width Modulation)
fan speed control and Low noise fan speed control

Two (2) 3-pin IOH fans (JP3: IOH1 Fan/JP2: IOH2

•

Fan)

System Man­agement

Dimensions

Notes:

1. For IPMI Confi guration Instructions, please refer to the Embedded IPMI
Confi guration User's Guide available @ http://www.supermicro.com/support/
manuals/.

2. For PCI-E expansion slots to work properly, please refer to the instruc­tions listed on Page 2-6.

PECI (Platform Environment Confi guration Interface) •

2.0 support
System resource alert via SuperDoctor III

•

SuperDoctor III, Watch Dog, NMI•
Chassis Intrusion Header and Detection•

16.8" (L) x 16.4" (W) (426.72mm x 416.56 mm) •
(X8OBN-F Baseboard)

2-11

X8OBN-F Platform User’s Manual

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 Ch.D

DDR3 Ch.E

DDR3 Ch.C

MB1

SMI 6.4GT/s

QPI 6.4GT/s

CPU0 CPU1

DDR3 800/1066 * 1

DDR3 Ch.F

MB2

SMI 6.4GT/s

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 Ch.A

DDR3 Ch.B

DDR3 Ch.D

DDR3 Ch.C

DDR3 Ch.E

MB0

MB1

SMI 6.4GT/s

SMI 6.4GT/s

CPU3

QPI 6.4GT/s

CPU2

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 Ch.F

DDR3 Ch.H

DDR3 Ch.G

MB2

MB3

SMI 6.4GT/s

SMI 6.4GT/s

QPI 6.4GT/s

QPI 6.4GT/s

DDR3 Ch.B

DDR3 Ch.A

MB0

SMI 6.4GT/s

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 Ch.G

DDR3 Ch.H

MB3

SMI 6.4GT/s

BOXBORO

x8

Stack 2 Ports

USB Connector

Internal Headers

2 * USB 2 Ports

2 * USB Type A

Internal Connectors

SPI BIOS

SPI

SM BUS

12 * FAN

HWM

W83795ADG

6 * SATA Connectors

SATA

USB 2.0 x4

USB 2.0 x2

USB 2.0 x2

IOH1

ESI (x4)

x8

x16

ESI (x4)

USB 2.0 X2

ICH10R

PCI 32/33

LPC

DDR3 Ch.A

DDR3 800/1066 * 1

QPI 6.4GT/s

DDR3 800/1066 * 1

DDR3 Ch.A

SMI 6.4GT/s

SMI 6.4GT/s

SMI 6.4GT/s

SMI 6.4GT/s

MB0

MB1

DDR3 Ch.B

DDR3 Ch.D

DDR3 Ch.C

DDR3 Ch.E

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 Ch.B

DDR3 Ch.D

DDR3 Ch.C

DDR3 Ch.E

MB0

MB1

SMI 6.4GT/s

CPU7

QPI 6.4GT/s

CPU6

SMI 6.4GT/s

MB0

MB1

SMI 6.4GT/s

SMI 6.4GT/s

MB2

MB3

DDR3 Ch.F

DDR3 Ch.H

DDR3 Ch.G

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 Ch.F

DDR3 Ch.H

DDR3 Ch.G

MB2

MB3

SMI 6.4GT/s

SMI 6.4GT/s

SMI 6.4GT/s

SMI 6.4GT/s

MB2

MB3

QPI 6.4GT/s

QPI 6.4GT/s

QPI 6.4GT/s

QPI 6.4GT/s

SMI 6.4GT/s

SMI 6.4GT/s

MB1

MB0

DDR3 Ch.E

DDR3 Ch.B

DDR3 Ch.D

DDR3 Ch.C

DDR3 Ch.A

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 Ch.E

DDR3 Ch.B

DDR3 Ch.A

DDR3 Ch.D

DDR3 Ch.C

MB1

MB0

SMI 6.4GT/s

SMI 6.4GT/s

CPU5

QPI 6.4GT/s

CPU4

SMI 6.4GT/s

SMI 6.4GT/s

MB0

MB1

SMI 6.4GT/s

SMI 6.4GT/s

MB3

MB2

DDR3 Ch.H

DDR3 Ch.G

DDR3 Ch.F

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 Ch.F

DDR3 Ch.H

DDR3 Ch.G

MB2

MB3

SMI 6.4GT/s

SMI 6.4GT/s

SMI 6.4GT/s

SMI 6.4GT/s

MB2

MB3

QPI 6.4GT/s

MUX

PCI-e x16 (x16)

PCI-e x8 (x8)

Slot6

Slot5

BOXBORO

QPI 6.4GT/s QPI 6.4GT/s

x8

PEX8648

PCI-E

BRIDGE

x8

x8

MUX

PCI-e x16 (x16)

PCI-e x8 (x8)

Slot4

Slot3

IOH2

x8

x8

MUX

x8

x8

PCI-e x16 (x8)

PCI-e x16 (x8)

Slot1

Slot2

x4

x8

MUX

WPCM450

BMC

10/100 PHY

VGA Connector

10/100 RJ45

SIO

KB/MS Connector

COM1 Connector

COM2 Header

W83527HG

TPM

SLB9635

TPM

Internal

Hheader

DDR3 Ch.F

DDR3 Ch.E

DDR3 Ch.H

DDR3 Ch.B

DDR3 Ch.A

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 Ch.G

DDR3 Ch.D

DDR3 Ch.C

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

Note: This is a general block diagram and may not exactly represent the
features on your baseboard. See the Baseboard Features pages for the
actual specifi cations of each baseboard.

DDR3 Ch.E

DDR3 Ch.A

DDR3 Ch.B

DDR3 Ch.D

DDR3 Ch.C

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 Ch.F

DDR3 Ch.H

DDR3 Ch.G

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

DDR3 800/1066 * 1

PCI-e x16 (X16)

Slot0

System Block Diagram

2-12

PCI-e x16 (X16)

PCI-e x8 (X8)

Slot8

Slot9

KAWELA

PCI-e x8 (X8)
Slot7

GLAN RJ45 CONN

GLAN RJ45 CONN

Chapter 2: Overview

2-2 Chipset Overview

Built upon the functionality and the capability of the Intel 7500 platform, the
X8OBN-F basebo ard provi des the p er forma nce and s uppor t for e ight- proc essor­based HPC/Cluster/Database servers. The 7500 platform consists of the 7500
Serie s S oc ket- L S (LGA 1567) pr oc e ss or, the 750 0 (I O H), and t he I CH10R (Sout h
Bridge).

With the Intel QuickPath interconnect (QPI) controller built in, the 7500 Series
processor offer s point-to- point system interconnect interface, greatly enhancing
system performance by utilizing serial link interconnections, allowing for increased
bandwidth and scalability.

The IO H provide s the inter fac e betwe en QPI -base d proc essor a nd PCI -E xpres s
comp onents . Each pr oce ssor s uppor ts f our ful l-w idth, b idirec tio nal interc onne cts
at the speed of 4.8 GT/s, 5.86 GT/s or 6.4 GT/s. Each QPI link consists of 20 pairs
of unidirectional different ial lanes for data transmis si on in addition to a dif ferent ial
forwarding clock. The x16 PCI Express Gen 2 connections can also be confi gured
as x8, x4, x2, x1 links to comply with the PCI-E Base Specifi cation, Re v . 2. 0. The se
PCI- E G en 2 la nes su ppo r t pee r-to -p eer r ead an d wr ite tr ansa cti ons . In addi tio n,
the leg ac y I O H p rov i d es a x4 ES I (Ente rpris e S o ut h B r i d g e Inte rfac e) link sup p o rt
for the l egacy br idg e.

The 7500 chipset also offers a wide range of ESI, Intel® I/OAT Gen 3, Intel
VT-d an d RAS (Reliabi lity, Availabili ty and Ser viceabilit y) suppor t. The feature s
suppor ted includ e memory inte rface ECC, x4/ x8 Single Devic e Data Cor rection
(SDDC), Flow-through C RC (Cyclic Redundancy Check), parity protection, out-of­band regi ster ac cess v ia SM Bus, and m emor y mir ror ing for da ta integr it y.

Main Features of the 7500 Platform

Fully-connectivity (with four Intel® QuickPath Interconnects and up to ten cores •
in each socket with 24MB of shared last level (L3) cache supported)

CPU-Integrated memory controller with support of DDR-3 1066 MHz RDIMMS

•

running at 800/978/1066 MHz via a memory buffer

Virtualization Technology

•

44 bits physical address and 48 bits virtual address supported•

2-13

X8OBN-F Platform User’s Manual

2-3 Special Features

Recovery from AC Power Loss

Basic I/O System (BIOS) provides a setting for you to determine how the system
will respond when AC power is lost and then restored to the system. You can
choose for the system to remain powered off (in which case you must press the
power switch to turn it back on), or for it to automatically return to a power-on state.
See the Advanced BIOS Setup section to change this setting. The default setting
is Last State.

2-4 PC Health Monitoring

This section describes the PC health monitoring features of the board. This platform
has fi ve onboard System Hardware Monitor chips that provide PC health monitoring.
An onboard voltage monitor will scan these onboard voltages continuously: CPU
Vcore (up to 8 CPUs), IOH1 Vcore, IOH2 Vcore, 3.3VDD, 3.3VSB, P3V3, P3V3_
AUX, 12V, 5V, Memory Voltage, and Battery Voltage. Once a voltage becomes
unstable, a warning is given or an error message is sent to the screen. The user
can adjust the voltage thresholds to defi ne the sensitivity of the voltage monitor.

Fan Status Monitor with Firmware Control

PC health monitoring in the BIOS can check the RPM status of the cooling fans. The
onboard CPU and chassis fans are controlled by Thermal Management via BIOS
(under the Hardware Monitoring section in the Advanced Setting).

Environmental Temperature Control

The thermal control sensor monitors the CPU temperature in real time and will turn
on the thermal control fan whenever the CPU temperature exceeds a user-defi ned
threshold. The overheat circuitry runs independently from the CPU. Once the ther­mal sensor detects that the CPU temperature is too high, it will automatically turn
on the thermal fans to prevent the CPU from overheating. The onboard chassis
thermal circuitry can monitor the overall system temperature and alert the user when
the chassis temperature is too high.

Note: To avoid possible system overheating, please be sure to provide
adequate airfl ow to your system.

System Resource Alert

This feature is available when the system is used with SuperDoctor III in the

2-14

Chapter 2: Overview

Windows OS environment or used with SuperDoctor II in Linux. SuperDoctor
is used to notify the user of cer tain system events. For example, you can also
confi gure SuperDoctor to provide you with warnings when the system temperature,
CPU tempe ratures, vo ltage s and fan sp eeds go b eyond pred efi ned thresholds.

2-5 ACPI Features

ACPI stands for Advanced Confi guration and Power Interface. The ACPI specifi ca-
tion defi nes a fl exible and abstract hardware interface that provides a standard
way to integrate power management features throughout a PC system, including
its hardware, operating system and application software. This enables the system
to automatically turn on and off peripherals such as CD-ROMs, network cards, hard
disk drives and printers.

In addition to enabling operating system-directed power management, ACPI also
provides a generic system event mechanism for Plug and Play, and an operating
system-independent interface for confi guration control. ACPI leverages the Plug and
Play BIOS data structures, while providing a processor architecture-independent
implementation that is compatible with Windows XP, Windows Vista and Windows
2008 Operating Systems.

Slow Blinking LED for Suspend-State Indicator

When the CPU goes into a suspend state, the chassis power LED will start blinking
to indicate that the CPU is in suspend mode. When the user presses any key, the
CPU will "wake up" and the LED will automatically stop blinking and remain on.

2-6 Power Supply

As with all computer products, a stable power source is necessary for proper and
reliable operation. It is even more important for processors that have high CPU
clock rates.

The X8OBN-F baseboard includes two main system power connectors (JP21/22),
four HDD power connectors (JP16~JP19), four GPU Power connectors (JPWR1~4),
and a SA T A DOM power connector (JWF1). Please connect these power connectors
to the power supply to provide adequate power to the components and the system.
Also your power supply must supply 1.5A for the Ethernet ports.

Warning! To avoid damaging the power supply or the system, be sure
to connect the Main Power connectors and other power connectors as
required to the power supply. Failure to do so will void the manufacturer
warranty on your power supply and the board.

2-15

X8OBN-F Platform User’s Manual

It is strongly recommended that you use a high quality power supply that meets the
ATX power supply Specifi cation 2.02 or above. It must also be SSI compliant. (For
more information, please refer to the website at http://www.ssiforum.org/). Addition­ally , in areas where noisy power transmission is present, you may choose to install a
line fi lter to shield the computer from noise. It is recommended that you also install
a power surge protector to help avoid problems caused by power surges.

2-7 Super I/O

The Super I/O provides functions that comply with ACPI (Advanced Confi guration
and Power Interface), which includes support of legacy and ACPI power manage­ment through an SMI or SCI function pin. It also features auto power management
to reduce power consumption.

2-8 Overview of the Nuvoton WPCM450R Controller

The Nuvoton WPCM450R Controller is a Baseboard Management Controller (BMC)
that supports 2D/VGA-compatible Graphics cores, Virtual Media, and Keyboard/
Video/Mouse Redirection (KVMR) modules. With blade-oriented Super I/O capability
built-in, the WPCM450R Controller is ideal for legacy-reduced server platforms.

The WPCM450R interfaces with a host system via PCI interface to communicate
with the Graphics core. It supports USB 2.0 and 1.1 for remote keyboard/mouse/
virtual media emulation. It also provides LPC interface to control Super IO func­tions. The WPCM450R is connected to the network via an external Ethernet PHY
module.

The BMC also supports two high-speed, 16550 compatible serial communication
ports (UARTs). Each UART includes a 16-byte send/receive FIFO, a programmable
baud rate generator, complete modem control capability and a processor interrupt
system. Both UARTs provide legacy speed with baud rate of up to 115.2 Kbps
as well as an advanced speed with baud rates of 250 K, 500 K, or 1 Mb/s, which
support higher speed modems.

The WPCM450R communicates with onboard components via six SMBus inter­faces, fan control, and Platform Environment Control Interface (PECI) buses.

Note: For more information on IPMI confi guration, please refer to the
Embedded IPMI User's Guide posted on our Website @ http://www.su­permicro.com/support/manuals/.

2-16

Chapter 3: Installation

Chapter 3

Installation

3-1 Static-Sensitive Devices

Electrostatic Discharge (ESD) can damage electronic com ponents. To avoid dam­aging your system board, it is important to handle it very carefully. The following
measures are generally suffi cient to protect your equipment from ESD.

Precautions

Use a grounded wrist strap designed to prevent static discharge.•

Touch a grounded metal object before removing the board from the antistatic •
bag.

Handle the board by its edges only; do not touch its components, peripheral

•

chips, memory modules or gold contacts.

When handling chips or modules, avoid touching their pins.

•

Put the baseboard and peripherals back into their antistatic bags when not in •
use.

For grounding purpose, make sure that your system chassis provides excellent

•

conductivity between the power supply, the case, the mounting fasteners and
the baseboard.

Use only the correct type of onboard CMOS battery as specifi ed by the

•

manufacturer. Do not install the onboard battery upside down to avoid possible
explosion.

Unpacking

The base board is shipp ed in antistat ic packaging t o avoid static dam age. When
unpacking the board, make sure the person handling it is static protected.

Note: Please refer to the quick installation guide listed in Chapter 1 for
more information on system installation.

3-1

X8OBN-F Platform User's Manual

!

3-2 Populating the CPU Board

Warning! When handling the processor, avoid placing direct pressure on

the CPU pins, CPU socket, and the label area of the heatsink and the fan
to avoid damaging the components and the system. Be sure to attach the
CPU board to the CPU board plate before you install a component on the
CPU board.

Always connect the power cord last, and always remove it before adding, 1.
removing or changing any hardware components. Make sure that you install
the processor into the CPU socket before you install the CPU heatsink.

When purchasing a board without a 7500 Series processor pre-installed, 2.
make sure that the CPU socket plastic cap is in place, and none of the CPU
socket pins are bent; otherwise, contact the retailer immediately.

Refer to our website at www.supermicro.com for CPU/Memory support up-3.
dates.

Installing a CPU on the CPU Board

Follow the instructions given in Chapter 1 to install the CPU board to the CPU 1.
board plate.

Press the socket clip to release the load plate, which covers the CPU socket, 2.
from its locking position.

Gently lift the socket clip to open the load plate.3.

Warning: Shipment wit hout the pl astic cap p roperl y installe d will caus e
damage to the socket pins.

3-2

Chapter 3: Installation

Installing the CPU Heatsink on the CPU Board

If needed, apply the proper amount of thermal grease (with thickness of up to 1.

0.13 mm) to the heatsink. (If you are using a heatsink purchased from SMC,
please skip this step because the needed amount of the thermal grease has
been applied to the heatsink.)

Place the heatsink on top of the CPU so that the two mounting holes on the 2.
heatsink are aligned with those on the retention mechanism.

3. In ser t tw o push -pin s on the si des of t he heats ink thr ough th e mounti ng hole s
on the mot herb oard, an d turn t he push -p ins clo ck wise to l ock t hem. .

Note: Reverse the steps indicated above to remove the heatsink from
the CPU Board.

3-3

X8OBN-F Platform User's Manual

Installing Memory Modules on the CPU Board

Notes: 1. Be sure to install the CPU board to the CPU board plate before

installing any components to the CPU board. (See Chapter 1). 2. Check
Supermicro's website for recommended memory modules.

CAUTION

Exercise extreme care when installing or removing DIMM

module s to prevent a ny possi ble dam age.

X8OBN-CPU

MB3
(for CPU2)

MB1
(for CPU2)

P2-DIMM6A

P2-DIMM5A

P2-DIMM7A

P2-DIMM8A

P2-DIMM2A

P2-DIMM1A

P2-DIMM3A

P2-DIMM4A

Rev.1.01

MB4
(for CPU2)

MB2
(for CPU2)

J43

J35

J44

J48J47

CPU2

CPU1

J45J46

MB2
(for CPU1)

MB4
(for CPU1)

P1-DIMM4A

P1-DIMM3A

MB1
(for CPU1)

P1-DIMM1A

P1-DIMM2A

P1-DIMM8A

P1-DIMM7A

MB3
(for CPU1)

P1-DIMM5A

P1-DIMM6A

J36

Insert the desired number of DIMMs into the memory slots, starting with P1-1.
DIMM #1A. (For best performance, please use the memory modules of the
same type and the same speed in the same bank.)

Push the release tabs outwards on both ends of the DIMM slot to unlock it.2.

Align the key of the DIMM module with the receptive point on the memory 3.
slot.

Align the notches on both ends of the module with the receptive points on the 4.
ends of the slot.

Use two thumbs together to press the notches on both ends of the module 5.
straight down into the slot until the module snaps into place.

Press the release tabs to the lock positions to secure the DIMM module into 6.
the slot.

Notches

Press both notches straight down into
the memory slot at the same time.

Removing Memory Modules

Reverse the steps above to remove the DIMM modules from the motherboard.

Release Tabs

3-4

Chapter 3: Installation

3-3 Installing the Baseboard into the Chassis

Follow the instructions below to install the baseboard into the chassis.

Tools Needed

Phillips Screwdriver•

Pan_head #6 screws (23 pieces)•

Standoffs (20 pieces, if needed)•

Install the IO shield in the chassis.1.

Locate the mounting holes on the baseboard and the matching mounting 2.
holes on the chassis.

JWD1

JF1

JOH1

X8OBN-F Baseboard

JPT1
JUID_OW1

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

Rev. 1.01

LED15

LED13

LED16

LED17

LED14

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

Fan8

I/O Hub 2

JBT1

JPME1

JIPMB1

USB8

I/O Hub 1

Battery

BT1

ICH10R

JPME2

JWF1

I-SATA5

I-SATA3

JTPM1

USB2/3

USB4/5

I-SATA4

I-SATA2

KB/Mouse

USB 0/1

IPMI LAN

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

JPRST1

FP CRTL

Fan6

Fan5

JP18

Fan4

JP19
JP17

Fan3

JPWR4

JPWR3

JP3

Fan7

J26

Fan2

JPWR1

JPWR2

JD1

Buzzer

I-SATA1

Fan1

T-SGPIO2

COM2

JL1

I-SATA0

T-SGPIO1

JP16

PWR 1

JP22

PWR 2

JP21

Place the baseboard in the chassis, making sure that the mounting holes on 3.
the baseboard match the corresponding mounting holes on the chassis.

Install standoffs in the chassis as needed.4.

Using the Phillips screwdriver, insert a Pan head #6 screw into mounting hole 5.
on the baseboard and its matching mounting hole on the chassis. Repeat this
step to secure the baseboard to the chassis.

3-5

X8OBN-F Platform User's Manual

3-4 Installing the Populated CPU Board on the
Baseboard

JWD1

JF1

JOH1

X8OBN-F Baseboard

IPMI LAN

JPRST1

JPT1
JUID_OW1

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

Rev. 1.01

LED15

LED13

LED16

LED17

LED14

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 2

JBT1

JPME1

JIPMB1

USB8

I/O Hub 1

Battery

BT1

ICH10R

JPME2

JWF1

I-SATA5

I-SATA3

JTPM1

USB2/3

USB4/5

I-SATA4

I-SATA2

KB/Mouse

USB 0/1

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

FP CRTL

Fan6

Fan5

Fan4

Fan3

JPWR4

Fan8

JPWR3

JP3

Fan7

PWR 1

J26

JP22

Fan2

JPWR1

JPWR2

JD1

Buzzer

I-SATA1

I-SATA0

PWR 2

Fan1

T-SGPIO2

COM2

JL1

JP21

T-SGPIO 1

CPU Slot4

CPU Slot3

JP18

JP19

JP17

CPU Slot2

JP16

CPU Slot1

Note: Be sure to install the CPU board to the CPU board plate before

installing any components to the CPU board. (See Chapter 1.)

After processors, memory modules and heatsinks are installed on the CPU board,
and the baseboard is installed in the chassis, you can install the CPU board onto
the baseboard. Follow the instructions below to install the CPU board onto the
baseboard.

Locate the CPU_board slots on the X8OBN Baseboard. (Four CPU_board 1.
slots are available on the baseboard).

Align the pins on a CPU board against the receptive points of the CPU_board 2.
slot on the baseboard. Once they are aligned, press the CPU Board straight
down to the baseboard until it is fully seated on the baseboard.

Warning: To avoid damaging the CPU or CPU board, do not touch any
components on the CPU board when installing it. Also be sure that the
CPU board is fully seated on the CPU board slot.

Install Populated CPU Board to BaseBoard

P1-DIMM4A

P1-DIMM3A

MB1
(for CPU1)

P1-DIMM1A

P1-DIMM2A

P1-DIMM8A

P1-DIMM7A

P1-DIMM5A

P1-DIMM6A

MB3
(for CPU1)

CPU Board Slot

MB3
(for CPU2)

MB1
(for CPU2)

P2-DIMM6A

P2-DIMM5A

P2-DIMM7A

P2-DIMM8A

P2-DIMM2A

P2-DIMM1A

P2-DIMM3A

P2-DIMM4A

X8OBN-CPU

Rev.1.01

J35

MB4
(for CPU2)

MB2
(for CPU2)

J48J47

MB2

CPU2

CPU1

J43

J44

(for CPU1)

MB4
(for CPU1)

J45J46

J36

CPU Board

BaseBoard

3-6

Chapter 3: Installation

3-5 Installing the Bridge Card between the CPU Boards

Once you've installed populated CPU boards on the baseboard, you can install
the X8OBN-BRI Bridge card between the CPU boards. (If only one CPU board is
installed on the baseboard, please skip this step.)

Note: A Bridge card is needed to connect the pair(s) of the CPU boards
installed on Slot1 & Slot2, and/or Slot3 & Slot4. There is no Bridge card
needed between Slot2 and Slot3. Refer to the table below for details.

CPU Board

Installed on

Slot1

Yes Yes No No One card needed between Slot1 & Slot2
Yes Yes Yes Yes One card needed between Slot1 & Slot2;

CPU Board
Installed on

Slot2

CPU Board

Installed on

Slot3

CPU Board

Installed on

Slot4

X8OBN-BRI Bridge Card(s) to be Installed

Another card needed between Slot3 & Slot4

X8OBN Bridge Card

J1

J3

J2

X8OBN-BR1

Rev. 1.01

J4

To connect to the

CPU Board

Four CPU Boards

X8OBN CPU Board

Two Bridge Cards

3-7

X8OBN-F Platform User's Manual

3-6 Memory Support for the X8OBN-F Platform

Each X8OBN-F CPU Board supports up to 256 GB Registered ECC DDR3 1066
MHz memory in 16 DIMM slots. These RDIMMs run at 800/978/1066 via a memory
buffer.

X8OBN-CPU

Rev.1.01

P2-DIMM6A

P2-DIMM5A

MB3
(for CPU2)

MB1
(for CPU2)

P2-DIMM7A

P2-DIMM8A

P2-DIMM2A

P2-DIMM1A

P2-DIMM3A

P2-DIMM4A

MB4
(for CPU2)

MB2
(for CPU2)

J43

J35

J44

Processor & Memory Module Population Confi guration

For memor y to wor k pro perl y, follow the tab les be low for me mor y supp or t.

J48J47

CPU2

CPU1

J45J46

MB2
(for CPU1)

MB4
(for CPU1)

P1-DIMM4A

P1-DIMM3A

MB1
(for CPU1)

P1-DIMM1A

P1-DIMM2A

P1-DIMM8A

P1-DIMM7A

MB3
(for CPU1)

P1-DIMM5A

P1-DIMM6A

J36

CPUs and the Corresponding Memory Modules (on Each CPU Board)

CPU# Corresponding DIMM Modules

CPU 1 P1-1A P1-2A P1-3A P1-4A P1-5A P1-6A P1-7A P1-8A

CPU2 P2-1A P2-2A P2-3A P2-4A P2-5A P2-6A P2-7A P2-8A

Processor and Memory Module Population on Each CPU Board

Number of

CPUs+DIMMs

2 CPUs &

8 DIMMs

2 CPUs &

10~16 DIMMs

CPU1 + CPU2
P1-1A/P1-3A/P1-5A/P1-7A, P2-1A/P2-3A/P2-5A/P2-7A

CPU1/CPU2
P1-1A/P1-3A/P1-5A/P1-7A, P2-1A/P2-3A/P2-5A/P2-7A + Any memory pairs in P1, P2
DIMM slots

CPU and Memory Population Confi guration Table

(*For memory to work proper, please install DIMMs in pairs)

Note: To optimize system performance, we recommend that 4-CPU or

8-CPU confi guration be used in your system as shown in the table below.
Please note that 1-CPU confi guration has not been validated by SMC.

4-CPU or 8-CPU Confi guration (-Recommended for Optimal

System Performance)

4-CPU Confi guration 2 CPUs per CPU Board Two CPU Boards Required:

8-CPU Confi guration 2 CPUs per CPU Board Four CPU Boards Required:

One on CPU_Board Slot1;

Anther on CPU_Board Slot2

Two CPU Boards on each CPU_Board

Slot (from Slot1 to Slot4)

3-8

Chapter 3: Installation

RDIMM Support POR on the 7500 Series Processor Platform

DIMM Slots

per DDR
Channel

1 1 Reg. ECC DDR3 800,978, 1066 SR, DR, or QR

Note: Refer to the notes below for memory population instructions.

DIMMs

Populated

per DDR

Channel

RDIMM Type

(RDIMM: Reg.=

Registered)

POR Speeds (in

MHz)

Ranks per DIMM

(Any Combination)

Memory Capacity

Maximum Memory

Possible (8S)

Single Rank RDIMMs 512 GB (64 x 8GB DIMMs)

Dual Rank RDIMMs 1024 GB (64 x 16GB DIMMs)

4Gb DRAM

Notes

Populate DIMMs starting with DIMM1A.•

For the memory modules to work properly, please install DIMM modules in pairs •
(with even number of DIMMs installed).

All channels in a system will run at the fastest common frequency.

•

3-9

X8OBN-F Platform User's Manual

1

2

3

456

7

8

9

3-7 Control Panel Connectors/I/O Ports

The I/O p ort s are col or cod ed in co nforma nce wit h the PC 9 9 speci fi cation. See
the pic ture be low for t he co lors a nd loc atio ns of the var ious I /O por t s.

Back Panel Connectors/I/O Ports

JWD1

JF1

JOH1

X8OBN-F Baseboard

IPMI LAN

JPRST1

JPT1
JUID_OW1

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

Rev. 1.01

LED15

LED13

LED16

LED17

LED14

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 2

JBT1

JPME1

JIPMB1

USB8

I/O Hub 1

Battery

BT1

ICH10R

JPME2

JWF1

I-SATA5

I-SATA3

JTPM1

USB2/3

USB4/5

I-SATA4

I-SATA2

KB/Mouse

USB 0/1

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

FP CRTL

Fan6

Fan5

JP18

Fan4

JP19

JP17

Fan3

JPWR4

Fan8

JPWR3

JP3

Fan7

J26

Fan2

JPWR1

JPWR2

Buzzer

I-SATA1

Fan1

T-SGPIO2

COM2

JL1

I-SATA0

T-SGPIO1

JP16

PWR 1

JP22

JD1

PWR 2

JP21

10

Back Panel I/O Port Locations and Defi nitions

Keyboard1.
Mouse2.
Back Panel USB Port 03.
Back Panel USB Port 14.
IPMI_Dedicated LAN5.
COM Port 1 (Turquoise)6.
VGA (Blue)7.
Gigabit LAN 18.
Gigabit LAN 29.
UID Switch10.

3-10

Chapter 3: Installation

1

2

ATX PS/2 Keyboard and PS/2
Mouse Ports

The ATX PS/2 keyboard and PS/2
mouse are located next to the Back
Panel USB Ports 0~1 on the base­board. See the table at right for pin
defi nitions.

PS/2 Keyboard/Mouse Pin

Defi nitions

PS2 Keyboard PS2 Mouse
Pin# Defi nition Pin# Defi nition
1 KB Data 1 Mouse Data
2 No Connection 2 No Connection
3 Ground 3 Ground

4 Mouse/KB VCC

(+5V)

4 Mouse/KB VCC

(+5V)
5 KB Clock 5 Mouse Clock
6 No Connection 6 No Connection
VCC: with 1.5A PTC (current limit)

X8OBN-F Baseboard

IPMI LAN

JPRST1

JPT1
JUID_OW1

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

Rev. 1.01

LED15

LED13

LED16

LED17

LED14

LED18

LED19

I/O Hub 2

PLX
PCI Bridge

JBT1

JPME1

JIPMB1

USB10

USB8

KB/Mouse

USB 0/1

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

JWD1

JF1

JOH1

FP CRTL

Fan6

CPU Board Slot 4

Fan5

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 1

Battery

BT1

ICH10R

JPME2

JWF1

I-SATA5

I-SATA3

JTPM1

USB2/3

USB4/5

I-SATA4

I-SATA2

JPWR4

Fan8

JPWR3

JP3

Fan7

J26

Fan2

JPWR1

JPWR2

Buzzer

I-SATA1

Fan1

T-SGPIO2

COM2

I-SATA0

JL1

T-SGPIO1

JP18

Fan4

JP19
JP17

Fan3

JP16

PWR 1

JP22

JD1

PWR 2

JP21

1. Keyboard

2. Mouse

3-11

X8OBN-F Platform User's Manual

1

2

3

4

5

6

Universal Serial Bus (USB)

Two Universal Serial Bus ports (USB
0/1) are located on the I/O back panel.
Additionally , six Front Panel USB con­nections (USB 2/3, USB 4/5, USB 8,
USB 10) are also on the baseboard to
provide front chassis access. (Cables
are not included). See the tables on
the right for pin defi nitions.

Backplane USB

(0/1)

Pin Defi nitions

Pin# Defi nition
1 +5V
2 PO­3 PO+
4 Ground
5NA

FP USB (2/3, 4/5)

Pin Defi nitions

USB 2/4/8/10
Pin # Defi nition

USB 3/5
Pin # Defi nition

1 +5V 1 +5V
2 PO- 2 PO­3 PO+ 3 PO+
4 Ground 4 Ground
5 NC 5 Key

(NC= No connection)

X8OBN-F Baseboard

IPMI LAN

JPRST1

JPT1
JUID_OW1

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

Rev. 1.01

LED15

LED13

LED16

LED17

LED14

LED18

LED19

I/O Hub 2

PLX
PCI Bridge

JBT1

JPME1

ICH10R

JIPMB1

JTPM1

USB10

USB8

USB2/3

USB4/5

KB/Mouse

USB 0/1

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

Battery
BT1

I-SATA4

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

JPME2

JWF1

I-SATA5

JWD1

JF1

JOH1

FP CRTL

Fan6

Fan5

JP18

Fan4

JP19
JP17

Fan3

JL1

T-SGPIO1

JP16

PWR 1

JP22

JD1

PWR 2

JP21

JPWR4

Fan8

JPWR3

JP3

Fan7

I/O Hub 1

J26

Fan2

JPWR1

JPWR2

Buzzer

I-SATA3

I-SATA1

Fan1

T-SGPIO2

COM2

I-SATA2

I-SATA0

1. Backpanel USB 0

2. Backpanel USB 1

3. Front Panel USB 2/3

4. Front Panel USB 4/5

5. Front Panel USB 8

6. Front Panel USB 10

3-12

Chapter 3: Installation

1

2

3

2

1

Serial Ports

Two COM connections (COM1 &
COM2) are located on the motherboard.
COM1 is located on the Backplane I/O
panel. COM2 are located next to SATA
Ports 0/1 to provides front accessible
serial support. See the table on the right
for pin defi nitions.

Video Connection

Serial COM) Ports

Pin Defi nitions

Pin # Defi nition Pin # Defi nition
1 DCD 6 DSR
2 RXD 7 RTS
3 TXD 8 CTS
4 DTR 9 RI
5 Ground 10 N/A

A Video (VGA) port is located next to
COM1 on the I/O backplane. Refer
to the board layout below for the
location.

JWD1

JOH1

X8OBN-F Baseboard

IPMI LAN

JPRST1

JPT1
JUID_OW1

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

Rev. 1.01

LED15

LED13

LED16

LED17

LED14

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 2

JBT1

JPME1

JIPMB1

USB8

I/O Hub 1

Battery

BT1

ICH10R

JPME2

JWF1

I-SATA5

I-SATA3

JTPM1

USB2/3

USB4/5

I-SATA4

I-SATA2

KB/Mouse

USB 0/1

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

FP CRTL

JPWR4

Fan8

JPWR3

JP3

Fan7

J26

Fan2

JPWR1

JPWR2

Buzzer

I-SATA1

Fan1

T-SGPIO2

COM2

I-SATA0

JL1

T-SGPIO1

JF1

Fan6

Fan5

JP18

Fan4

JP19

JP17

Fan3

JP16

PWR 1

JP22

JD1

PWR 2

JP21

1. COM1

2. COM2

3. VGA

3-13

X8OBN-F Platform User's Manual

1

2

3

Ethernet Ports

Two Ethernet ports (LAN1/LAN2) are
located on the I/O backplane on the
baseboard. In addition, an IPMI_Dedi­cated LAN is located above USB 0/1
ports on the backplane to provide
KVM support for IPMI 2.0. All these
ports accept RJ45 type cables.

Note: Please refer to the
LED Indicator Section for
LAN LED information.

LAN Ports

Pin Defi nition

Pin# Defi nition
1 P2V5SB 10 SGND
2 TD0+ 11 Act LED
3 TD0- 12 P3V3SB
4 TD1+ 13 Link 100 LED (Yel-

low, +3V3SB)

5 TD1- 14 Link 1000 LED

(Yellow, +3V3SB)
6 TD2+ 15 Ground
7 TD2- 16 Ground
8 TD3+ 17 Ground
9 TD3- 18 Ground

(NC: No Connection)

X8OBN-F Baseboard

IPMI LAN

JPRST1

JPT1
JUID_OW1

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

Rev. 1.01

LED15

LED13

LED16

LED17

LED14

LED18

LED19

I/O Hub 2

PLX
PCI Bridge

JBT1

JPME1

ICH10R

JIPMB1

JTPM1

USB10

USB8

USB2/3

USB4/5

KB/Mouse

USB 0/1

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

Battery

BT1

I-SATA4

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

JPME2

JWF1

I-SATA5

JWD1

JF1

JOH1

FP CRTL

Fan6

Fan5

JP18

Fan4

JP19
JP17

Fan3

JL1

T-SGPIO1

JP16

PWR 1

JP22

JD1

PWR 2

JP21

JPWR4

Fan8

JPWR3

JP3

Fan7

I/O Hub 1

J26

Fan2

JPWR1

JPWR2

Buzzer

I-SATA3

I-SATA1

Fan1

T-SGPIO2

COM2

I-SATA2

I-SATA0

1. LAN1

2. LAN2

3. IPMI_LAN

3-14

Chapter 3: Installation

3

1

1

2

3

Unit Identifi er Switch

A Unit Identifi er (UID) switch and two LED
Indicators are located on the X8OBN-F
baseboard. The UID switch is located next
to the LAN ports on the backplane. The Rear
UID LED (LED6) is located next to the UID
switch. The Front Panel UID LED is located
at Pins 7/8 of the Front Control Panel at JF1.
Connect a cable to Pins 7/8 on JF1 for Front
Panel UID LED indication. When you press
the UID switch, both Rear UID LED and Front
Panel UID LED Indicators will be turned on.
Press the UID switch again to turn off both
LED Indicators. These UID Indicators provide
easy identifi cation of a system unit that may
be in need of service.

Note: UID can also be triggered via
IPMI on the baseboard. For more
information on IPMI, please refer
to the IPMI User's Guide posted on
our Website @http://www.supermi­cro.com.

UID Switch

Pin# Defi nition
1 Ground
2 Ground
3 Button In
4 Ground

UID LED (LE2)

Status

Color/State OS Status
Blue: On Windows OS Unit Identifi ed
Blue:

Linux OS Unit Identifi ed

Blinking

1. UID Switch

2. Rear UID LED (LED6)

3. Front UID LED

JWD1

JF1

JOH1

X8OBN-F Baseboard

IPMI LAN

JPRST1

JPT1
JUID_OW1

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

Rev. 1.01

LED15

LED13

LED16

LED17

LED14

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

Fan8

I/O Hub 2

JBT1

JPME1

JIPMB1

USB8

I/O Hub 1

Battery

BT1

ICH10R

JPME2

JWF1

I-SATA5

I-SATA3

JTPM1

USB2/3

USB4/5

I-SATA4

I-SATA2

KB/Mouse

USB 0/1

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

FP CRTL

Fan6

Fan5

JP18

Fan4

JP19
JP17

Fan3

JPWR4

JPWR3

JP3

Fan7

J26

Fan2

JPWR1

JPWR2

Buzzer

I-SATA1

Fan1

T-SGPIO2

COM2

JL1

I-SATA0

T-SGPIO1

JP16

PWR 1

Blue+ (OH/Fan Fail/

JP22

JD1

PWR FaiL/UID LED)

Power Fail LED

PWR 2

JP21

Ground

X

FP PWRLED

HDD LED

NIC1 Link LED

NIC2 Link LED

Ground

Ground

1920

NMI

X

3.3 V

ID_UID_SW/3/3V Stby

NIC1 Activity LED

NIC2 Activity LED

Red+ (Blue LED Cathode)

3.3V

Reset

Reset Button

Powe r Button

PWR

2

1

3-15

X8OBN-F Platform User's Manual

Front Control Panel

JF1 contains header pins for various buttons and indicators that are normally lo­cated on a control panel at the front of the chassis. These connectors are designed
specifi cally for use with Supermicro's server chassis. See the fi gure below for the
descriptions of the various control panel buttons and LED indicators. Refer to the
following section for descriptions and pin defi nitions.

JF1 Header Pins

JWD1

I/O Hub 1

I-SATA3

I-SATA2

JOH1

Fan8

Buzzer

I-SATA1

COM2

I-SATA0

X8OBN-F Baseboard

JPT1
JUID_OW1

LED13

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

LED14

LED15

Rev. 1.01

LED16

LED17

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 2

Battery

BT1

JBT1

JPME1

ICH10R

JPME2

JWF1

USB4/5

USB2/3

JTPM1

I-SATA5

I-SATA4

JIPMB1

USB8

KB/Mouse

USB 0/1

IPMI LAN

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

JPRST1

Fan7

Fan2

JPWR3

JPWR1

JF1

FP CRTL

Fan6

Fan5

JP18

Fan4

JP19
JP17

Fan3

JPWR4

JP3

J26

JP22

JPWR2

JD1

Fan1

T-SGPIO2

JL1

JP21

T-SGPIO1

JP16

PWR 1

PWR 2

Ground

X

FP PWRLED

HDD LED

NIC1 Link LED

NIC2 Link LED

Blue+ (OH/Fan Fail/
PWR FaiL/UID LED)

Power Fail LED

Ground

Ground

3-16

1920

NMI

X

3.3 V

ID_UID_SW/3/3V Stby

NIC1 Activity LED

NIC2 Activity LED

Red+ (Blue LED Cathode)

3.3V

Reset

PWR

2

1

Reset Button

Power Button

Front Control Panel Pin Defi nitions

Chapter 3: Installation

NMI Button

The non-maskable interrupt button
header is located on pins 19 and 20
of JF1. Refer to the table on the right
for pin defi nitions.

Power LED

The Power LED connection is located
on pins 15 and 16 of JF1. Refer to the
table o n the ri ght for p in defi nitions.

NMI Button

Pin Defi nitions (JF1)

Pin# Defi nition
19 Control
20 Ground

Power LED

Pin Defi nitions (JF1)

Pin# Defi nition
15 3.3V
16 PWR LED

A. NMI
B. PWR LED

JWD1

JF1

JOH1

X8OBN-F Baseboard

IPMI LAN

JPRST1

JPT1
JUID_OW1

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

Rev. 1.01

LED15

LED13

LED16

LED17

LED14

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 2

JBT1

JPME1

JIPMB1

USB8

I/O Hub 1

Battery

BT1

ICH10R

JPME2

JWF1

I-SATA5

I-SATA3

JTPM1

USB2/3

USB4/5

I-SATA4

I-SATA2

KB/Mouse

USB 0/1

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

FP CRTL

Fan6

Ground

Fan5

JP18

Fan4

Fan3

JPWR4

Fan8

JPWR3

JP3

Fan7

PWR 1

J26

JP22

Fan2

JPWR1

JPWR2

JD1

Buzzer

I-SATA1

I-SATA0

PWR 2

Fan1

T-SGPIO2

COM2

JL1

JP21

T-SGPIO1

FP PWRLED

B

JP19
JP17

JP16

NIC1 Link LED

NIC2 Link LED

Blue+ (OH/Fan Fail/
PWR FaiL/UID LED)

Power Fail LED

X

HDD LED

Ground

Ground

1920

NMI

A

X

3.3 V

ID_UID_SW/3/3V Stby

NIC1 Activity LED

NIC2 Activity LED

Red+ (Blue LED Cathode)

3.3V

Reset

Reset Button

Power Button

PWR

2

1

3-17

X8OBN-F Platform User's Manual

D

E

HDD LED

The HDD LED connection is located
on pins 13 and 14 of JF1. Attach a
cable here to indicate HDD activ­ity. See the table on the right for pin
defi nitions.

NIC1/NIC2 LED Indicators

The NIC (Network Interface Control­ler) LED connection for GLAN port 1 is
located on pins 11 and 12 of JF1, and
the LED connection for GLAN Port 2
is on Pins 9 and 10. Attach the NIC
LED cables to display network activity .
Refer to the table on the right for pin
defi nitions.

HDD LED

Pin Defi nitions (JF1)

Pin# Defi nition
13 3.3V Standby
14 HD Active

GLAN1/2 LED

Pin Defi nitions (JF1)

Pin# Defi nition
9 NIC 2 Activity LED
10 NIC 2 Link LED
11 NIC 1 Activity LED
12 NIC 1 Link LED

A. HDD LED
B. NIC1 Link LED
C. NIC1 Activity LED
D. NIC2 Link LED
E. NIC2 Activity LED

JWD1

JF1

JOH1

X8OBN-F Baseboard

IPMI LAN

JPRST1

JPT1
JUID_OW1

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

Rev. 1.01

LED15

LED13

LED16

LED17

LED14

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 2

JBT1

JPME1

JIPMB1

USB8

I/O Hub 1

Battery

BT1

ICH10R

JPME2

JWF1

I-SATA5

I-SATA3

JTPM1

USB2/3

USB4/5

I-SATA4

I-SATA2

KB/Mouse

USB 0/1

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

FP CRTL

Fan6

Ground

Fan5

JP18

Fan4

Fan3

JPWR4

Fan8

JPWR3

JP3

Fan7

PWR 1

J26

JP22

Fan2

JPWR1

JPWR2

JD1

Buzzer

I-SATA1

COM2

I-SATA0

PWR 2

Fan1

T-SGPIO2

JL1

JP21

T-SGPIO1

FP PWRLED

JP19
JP17

A

JP16

NIC1 Link LED

B

NIC2 Link LED

Blue+ (OH/Fan Fail/
PWR FaiL/UID LED)

Power Fail LED

X

HDD LED

Ground

Ground

1920

NMI

X

3.3 V

ID_UID_SW/3/3V Stby

NIC1 Activity LED

C

NIC2 Activity LED

Red+ (Blue LED Cathode)

3.3V

Reset

Reset Button

Power Button

PWR

2

1

3-18

Chapter 3: Installation

Overheat (OH)/Fan Fail/PWR Fail/
UID LED

Connect an LED cable to OH/Fan Fail/
FP UID connection on pins 7 and 8 of
JF1 to provide advanced warnings of
chassis overheat or fan failure. It also
works as the front panel UID LED
indicator. The Red LED t akes prece ­dence ove r the Blue L ED by default.
Refer to the table on the right for pin
defi nitions.

Power Fail LED

The Power Fail LED connection is
locate d on pins 5 and 6 of JF1. Re­fer to the table on the right for pin
defi nitions.

OH/Fan Fail/PWR Fail/UID LED

Pin Defi nitions (JF1)

Pin# Defi nition
7 Red+ (Blue LED Cathode)
8 Blue+ (OH/Fan Fail/PWR Fail/

UID LED)

OH/Fan Fail Indicator

Status

State Defi nition
Off Normal
On Overheat
Flash-

Fan Fail

ing

PWR Fail LED

Pin Defi nitions (JF1)

Pin# Defi nition
5 3.3V
6 PWR Supply Fail

A. Front UID LED (Blue)
B. OH/ Fail/PWR Fail LED (Red)
C. PWR Supply Fail

JWD1

JF1

JOH1

X8OBN-F Baseboard

IPMI LAN

JPRST1

JPT1
JUID_OW1

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

Rev. 1.01

LED15

LED13

LED16

LED17

LED14

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 2

JBT1

JPME1

JIPMB1

USB8

I/O Hub 1

Battery

BT1

ICH10R

JPME2

JWF1

I-SATA5

I-SATA3

JTPM1

USB2/3

USB4/5

I-SATA4

I-SATA2

KB/Mouse

USB 0/1

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

FP CRTL

Fan6

Ground

Fan5

JP18

Fan4

Fan3

JPWR4

Fan8

JPWR3

JP3

Fan7

PWR 1

B

J26

JP22

Fan2

JPWR1

JPWR2

JD1

Buzzer

I-SATA1

I-SATA0

PWR 2

Fan1

T-SGPIO2

COM2

JL1

JP21

T-SGPIO1

FP PWRLED

JP19
JP17

JP16

NIC1 Link LED

NIC2 Link LED

Blue+ (OH/Fan Fail/
PWR FaiL/UID LED)

Power Fail LED

C

X

HDD LED

Ground

Ground

1920

NMI

X

3.3 V

ID_UID_SW/3/3V Stby

NIC1 Activity LED

NIC2 Activity LED

A

Red+ (Blue LED Cathode)

3.3V

Reset

Reset Button

Power Button

PWR

2

1

3-19

X8OBN-F Platform User's Manual

Reset Button

The Reset Button connection is located
on pins 3 and 4 of JF1. Attach it to a
hardware reset switch on the computer
case. Refer to the table on the right for
pin defi nitions.

Power Button

The Power Button connection is located
on pins 1 and 2 of JF1. Momentarily
contacting both pins will power on/off
the system. This button can also be con­fi gured to function as a suspend button
(with a setting in BIOS - See Chapter 5).
To turn off the power when the system is
set to suspend mode, press the button
for at least 4 seconds. Refer to the table
on the right for pin defi nitions.

Reset Button

Pin Defi nitions (JF1)

Pin# Defi nition
3 Reset
4 Ground

Power Button

Pin Defi nitions (JF1)

Pin# Defi nition

1 Signal
2 Ground

A. Reset Button
B. PWR Button

JWD1

JF1

JOH1

X8OBN-F Baseboard

IPMI LAN

JPRST1

JPT1
JUID_OW1

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

Rev. 1.01

LED15

LED13

LED16

LED17

LED14

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 2

JBT1

JPME1

JIPMB1

USB8

I/O Hub 1

Battery

BT1

ICH10R

JPME2

JWF1

I-SATA5

I-SATA3

JTPM1

USB2/3

USB4/5

I-SATA4

I-SATA2

KB/Mouse

USB 0/1

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

FP CRTL

Fan6

Ground

Fan5

JP18

Fan4

Fan3

JPWR4

Fan8

JPWR3

JP3

Fan7

PWR 1

J26

JP22

Fan2

JPWR1

JPWR2

JD1

Buzzer

I-SATA1

COM2

I-SATA0

PWR 2

Fan1

T-SGPIO2

JL1

JP21

T-SGPIO1

FP PWRLED

JP19
JP17

JP16

NIC1 Link LED

NIC2 Link LED

Blue+ (OH/Fan Fail/
PWR FaiL/UID LED)

Power Fail LED

X

HDD LED

Ground

Ground

1920

NMI

X

3.3 V

ID_UID_SW/3/3V Stby

NIC1 Activity LED

NIC2 Activity LED

Red+ (Blue LED Cathode)

3.3V

Reset

Reset Button

Power Button

PWR

2

1

A

B

3-20

Chapter 3: Installation

D

E

F

G

3-8 Connecting Cables

Power Connectors

Two main power supply connectors (JP21/
JP22), four GPU 8-pin power connectors
(JPWR1/JPWR2/JPWR3/JPWR4), and four
HDD power connectors (JP16~JP19) are lo­cated on the X8OBN Baseboard. These power
connectors meet the SSI EPS 12V specifi cation.
These power connectors must be connected to
your power supply to provide adequate power
to your system and components. Failure to do
so will void the manufacturer warranty on your
power supply and the system. See the table on
the right for pin defi nitions.

GPU 8-pin PWR Con-

nector

Pin Defi nitions

Pins Defi nition
1~3 +12V
4~8 GND

(GPU PWR cable req'd for graphics cards)

HDD 8-pin PWR Con-

nector

Pin Defi nitions

Pins Defi nition
1~4 GND
5/6 +12V
7/8 +5V

(HDD PWR cable required for HDDs)

DOM Power Connector

A power connector for SATA DOM (Disk_On_
Module) Devices is located at JWF1. Connect
the appropriate cable here to provide power
support for your DOM devices.

JWD1

I/O Hub 1

I-SATA3

I-SATA2

JOH1

Fan8

I-SATA1

I-SATA0

Buzzer

JPWR3

Fan7

C

Fan2

JPWR1

COM2

X8OBN-F Baseboard

JPT1
JUID_OW1

LED13

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

LED14

LED15

Rev. 1.01

LED16

LED17

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 2

Battery

BT1

JBT1

JPME1

ICH10R

JPME2

JWF1

USB4/5

USB2/3

JTPM1

I-SATA5

I-SATA4

JIPMB1

USB8

KB/Mouse

USB 0/1

IPMI LAN

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

JPRST1

DOM PWR

Pin Defi nitions

Pin# Defi nition
1 +5V
2 Ground
3 Ground

JF1

FP CRTL

Fan6

A. PWR 1 (JP22)
(Req'd)

Fan5

JP18

Fan4

JP19
JP17

Fan3

PWR 1

PWR 2

JP16

A

B

JPWR4

JP3

J26

JP22

JPWR2

JD1

Fan1

T-SGPIO2

JL1

JP21

T-SGPIO1

B. PWR 2 (JP21)
(Req'd)

J

C. JPWR1: 8-pin Proces-

K

sor PWR (Req'd)

I

D. JPWR2: 8-pin Proces-

H

sor PWR (Req'd)
E. JPWR3: 8-pin Proces­sor PWR (Req'd)
F. JPWR4: 8-pin Proces­sor PWR (Req'd)
G. JPWF1: SATA Device
PWR (Req'd for SATA
devices)
H/I/J/K: HDD PWR

3-21

X8OBN-F Platform User's Manual

D

E

F

G

Fan Headers

The X8OBN Baseboard has six system
fan headers and four CPU_card fan
headers. All these are 4-pin fans and are
backward_compatible with the traditional
3-pin fans. In addition, two 3-pin IOH fan
headers are located at Fan1 and Fan2.
Fan speed control is available for 4-pin
fans only*. See the tables on the right for
more information. (*Fan speed control is
available via Hardware Health Monitoring
in the Advanced BIOS Section for 4-pin
fans only.)

Chassis Intrusion

A Chassis Intrusion header is located at
JL1 on the baseboard. Attach an appro­priate cable from the chassis to inform
you of possible chassis intrusion when
the chassis is opened.

Fan Headers

Fan Type # of Pins Q'ty Fan No.
IOH Fans 3-pin

Fan

CPU_
Board

4-pin
Fan

2 Fan7 (IOH1)/

Fan8 (IOH2)

4 Fans 3~6

Fans
System

Fans

4-pin
Fan

6 Fan1/Fan2, Fans

9~12

Fan Header

Pin Defi nitions

Pin# Defi nition
1 Ground
2 +12V
3 Tachometer
4 PWR Modulation (4-pin fans only)

Chassis Intrusion

Pin Defi nitions

Pin# Defi nition
1 Intrusion Input
2 Ground

COM1

VGA

USB 0/1

LAN1

LAN2

LED6

LED4

JWD1

I/O Hub 1

I-SATA3

I-SATA2

JOH1

Fan8

B

Buzzer

I-SATA1

COM2

I-SATA0

X8OBN-F Baseboard

KB/Mouse

IPMI LAN

Fan12

L

J30
J29

Fan 11

K

Fan 10

J

J25

UID

J32

Fan 9

JPT1
JUID_OW1

I

LAN CTRL

JPL1

BMC CTRL

JPG1

JPB1

JPRST1

Rev. 1.01

LED15

LED13

LED16

LED14

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

LED17

LED18

LED19

PLX
PCI Bridge

USB10

USB8

JPME1

JBT1

JIPMB1

I/O Hub 2

USB4/5

ICH10R

USB2/3

Battery

JTPM1

BT1

I-SATA4

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

JPME2

JWF1

I-SATA5

Fan7

Fan2

JPWR3

JPWR1

JF1

FP CRTL

Fan6

Fan5

JP18

Fan4

JP19
JP17

A. Fan7 (IOH1)

C

Fan3

JPWR4

JP3

A

PWR 1

B. Fan8 Fan (IOH2)

JP16

C. Fan3 (CPU Slot1)
D. Fan4 (CPU Slot2)
E. Fan5 (CPU Slot3)
F. Fan6 (CPU Slot4)
G. Fan1 (System Fan)

J26

JP22

H

JPWR2

JD1

PWR 2

Fan1

T-SGPIO2

JL1

JP21

M

T-SGPIO1

H. Fan2 (System Fan)
I/J. Fans 9/10 (System
Fans)
K/L. Fans 11/12 (System
Fans)
M. Chassis Intrusion

3-22

Chapter 3: Installation

Internal Buzzer

The Internal Speaker, located at SP1,
can be used to provide audible indica­tions for various beep codes. See the
table on the right for pin defi nitions.
Refer to the layout below for the loca­tion of the Internal Buzzer.

Power LED/Speaker

On the JD1 header, pins 1-3 are used
for power LED indication, and pins 4-7
are for the speaker. See the tables on
the right for pin defi nitions. Please note
that the speaker connector pins (4-7)
are for use with an external speaker. If
you wish to use the onboard speaker,
close pins 6-7 with a cap.

Internal Buzzer

Pin Defi nition

Pin# Defi nitions
Pin 1 Pos. (+) Beep In
Pin 2 Neg. (-) Alarm

Speaker

PWR LED Connector

Pin Defi nitions

Pin Setting Defi nition
Pin 1 Anode (+)
Pin2 Cathode (-)
Pin3 NA

Speaker Connector

Pin Settings

Pin Setting Defi nition
Pins 4-7 External Speaker
Pins 6-7 Internal Speaker

JWD1

I/O Hub 1

I-SATA3

I-SATA2

JOH1

Fan8

Buzzer

A

I-SATA1

COM2

I-SATA0

X8OBN-F Baseboard

JPT1

LED13

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

LED14

LED15

LED16

Rev. 1.01

LED17

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 2

Battery

BT1

JBT1

JPME1

ICH10R

JPME2

JWF1

USB4/5

USB2/3

JTPM1

I-SATA5

I-SATA4

JIPMB1

USB8

KB/Mouse

USB 0/1

IPMI LAN

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

JUID_OW1

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

JPRST1

Fan7

JPWR3

Fan2

JPWR1

JF1

FP CRTL

Fan6

Fan5

JP18

Fan4

JP19
JP17

Fan3

JP16

JPWR4

JP3

PWR 1

J26

JP22

JPWR2

B

JD1

PWR 2

Fan1

T-SGPIO2

JL1

JP21

T-SGPIO1

A. Internal Buzzer
B. PWR LED/Speaker

3-23

X8OBN-F Platform User's Manual

TPM Header/Port 80

A Trusted Platform Module/Port 80
header is located at JTPM1 to provide
TPM and Port 80 support, which will
enhance system performance and
data security. See the table on the
right for pin defi nitions.

Overheat LED/Fan Fail

The JOH1 header is used to connect
an LED indi cat or to p rovi de war ni ngs
of chass is overheat ing or fan fa ilure.
This LED w ill b link w he n a fan f ailu re
occu rs. Ref er to t he t abl e on r ight f or
pin defi nitions.

TPM/Port 80 Header

Pin Defi nitions

Pin # Defi nition Pin # Defi nition
1 LCLK 2 GND
3 LFRAME# 4 <(KEY)>
5 LRESET# 6 +5V (X)
7 LAD 3 8 LAD 2
9 +3.3V 10 LAD1
11 LAD0 12 GND
13 SMB_CLK4 14 SMB_DAT4
15 +3V_DUAL 16 SERIRQ
17 GND 18 CLKRUN# (X)
19 LPCPD# 20 LDRQ# (X)

Overheat LED

Pin Defi nitions

Pin# Defi nition
1 5vDC
2 OH Active

OH/Fan Fail LED

Status

State Message
Solid Overheat
Blinking Fan Fail

COM1

VGA

USB 0/1

LAN1

LAN2

LED6

LED4

JWD1

I/O Hub 1

I-SATA3

I-SATA2

JOH1

B

Fan8

Buzzer

I-SATA1

COM2

I-SATA0

X8OBN-F Baseboard

JPT1
JUID_OW1

LED13

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

LED14

LED15

Rev. 1.01

LED16

LED17

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 2

Battery

BT1

JBT1

JPME1

ICH10R

JPME2

JWF1

A

USB4/5

USB2/3

JTPM1

I-SATA5

I-SATA4

JIPMB1

USB8

KB/Mouse

IPMI LAN

Fan12

J30
J29

Fan 11

Fan 10

J25

UID

J32

Fan 9

LAN CTRL

JPL1

BMC CTRL

JPB1

JPRST1

JPWR3

Fan7

Fan2

JPWR1

JF1

FP CRTL

Fan6

Fan5

JP18

Fan4

JP19

JP17

Fan3

JP16

JPWR4

JP3

PWR 1

J26

JP22

JPWR2

JD1

PWR 2

Fan1

T-SGPIO2

JL1

JP21

T-SGPIO1

A. TPM/Port 80 Head­er
B. Overheat LED

3-24

Chapter 3: Installation

T-SGPIO 1/2 Headers

Two SGPIO (Serial-Link General
Purpose Input/Output) headers are lo­cated on the baseboard. These head­ers support Serial_Link interface for
onboard SATA connections. See the
table on the right for pin defi nitions.

T-SGPIO

Pin Defi nitions

Pin# Defi nition Pin Defi nition
1NC 2 NC
3 Ground 4 Data

5 Load 6 Ground
7 Clock 8 NC

Note: NC= No Connection

JWD1

I/O Hub 1

I-SATA3

I-SATA2

JOH1

Fan8

Buzzer

I-SATA1

COM2

I-SATA0

X8OBN-F Baseboard

JPT1

LED13

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

LED14

LED15

LED16

Rev. 1.01

LED17

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 2

Battery

BT1

JBT1

JPME1

ICH10R

JPME2

JWF1

USB4/5

USB2/3

JTPM1

I-SATA5

I-SATA4

JIPMB1

USB8

KB/Mouse

USB 0/1

IPMI LAN

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

JUID_OW1

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

JPRST1

Fan7

JPWR3

Fan2

JPWR1

JF1

FP CRTL

Fan6

Fan5

JP18

Fan4

JP19
JP17

Fan3

JP16

JPWR4

JP3

PWR 1

J26

JP22

JPWR2

JD1

PWR 2

B

Fan1

T-SGPIO2

JL1

JP21

T-SGPIO1

A

A. T-SGPIO1
B. T-SGPIO2

3-25

X8OBN-F Platform User's Manual

Connector

Pins

Jumper

Cap

Setting

3-9 Jumper Settings

Explanation of Jumpers

To modify the operation of the baseboard,
jumpers can be used to choose between
optional settings. Jumpers create shorts be­tween two pins to change the function of the
connector. Pin 1 is identifi ed with a square
solder pad on the printed circuit board. See the
baseboard layout pages for jumper locations.

Note: On two pin ju mpe r s, "C lo sed "
means the jumper is on, and "Open"
means th e jumpe r is of f the pi ns.

GLAN Enable/Disable

JPL1 enables or disables the GLAN
Port1/GLAN Port2 on the baseboard.
See the table on the right for jumper
settings. The default setting is En­abled.

3 2 1

3 2 1

Pin 1-2 short

GLAN Enable

Jumper Settings

Jumper Setting Defi nition
1-2 Enabled (default)
2-3 Disabled

COM1

VGA

USB 0/1

LAN1

LAN2

LED6

A

LED4

JWD1

I/O Hub 1

I-SATA3

I-SATA2

JOH1

Fan8

Buzzer

I-SATA1

COM2

I-SATA0

X8OBN-F Baseboard

JPT1
JUID_OW1

LED13

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

LED14

LED15

Rev. 1.01

LED16

LED17

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 2

Battery

BT1

JBT1

JPME1

ICH10R

JPME2

JWF1

USB4/5

USB2/3

JTPM1

I-SATA5

I-SATA4

JIPMB1

USB8

KB/Mouse

IPMI LAN

Fan12

J30
J29

Fan 11

Fan 10

J25

UID

J32

Fan 9

LAN CTRL

JPL1

BMC CTRL

JPB1

JPRST1

JPWR3

Fan7

Fan2

JPWR1

JF1

FP CRTL

Fan6

Fan5

Fan4

Fan3

JPWR4

JP3

PWR 1

J26

JP22

JPWR2

JD1

PWR 2

Fan1

T-SGPIO2

JL1

JP21

T-SGPIO1

A. GLAN Ports Enable

JP18

JP19

JP17

JP16

3-26

Chapter 3: Installation

CMOS Clear

JBT1 is used to clear CMOS. Instead of pins, this "jumper" consists of contac t
pads to prevent t he accident al clearin g of CMOS. To clear CMOS , use a metal
objec t such as a sma ll screwdr iver to touc h both pad s at the same t ime to shor t
the co nnec ti on. A lways rem ove the AC p ower c ord f rom t he syste m befo re cl ear­ing CMOS.

Note 1. For an ATX power supply, you must completely shut down the sys­tem, remove the AC power cord, and then short JBT1 to clear CMOS.

Note 2. Be sure to remove the onboard CMOS Battery before you short
JBT1 to clear CMOS.

Note 3. Clearing CMOS will also clear any passwords.

Watch Dog Enable/Disable

Watch Dog (JWD1) is a system moni to r t h at
can reb oot t he sys tem w hen a s of tware ap­plicat ion han gs. Clo se Pins 1-2 to res et the
system if an app lication ha ngs. Close Pins
2-3 to generate a non-maskable interrupt
signal for the application that hangs. See the
table on the right for jumper settings. Watch
Dog must also be enabled in the BIOS.

X8OBN-F Baseboard

JPT1

LED13

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

LED14

LED15

LED16

Rev. 1.01

LED17

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 2

I/O Hub 1

Battery

BT1

JBT1

A

JPME1

ICH10R

JPME2

JWF1

I-SATA5

I-SATA4

I-SATA3

I-SATA2

JIPMB1

USB4/5

USB2/3

JTPM1

USB8

KB/Mouse

USB 0/1

IPMI LAN

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

JUID_OW1

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

JPRST1

Watch Dog

Jumper Settings

Jumper Setting Defi nition
Pins 1-2 Reset (default)
Pins 2-3 NMI
Open Disabled

B

JWD1

JOH1

Fan8

Buzzer

I-SATA1

COM2

I-SATA0

Fan7

JPWR3

Fan2

JPWR1

JF1

FP CRTL

Fan6

Fan5

Fan4

Fan3

JPWR4

JP3

PWR 1

J26

JP22

JPWR2

JD1

PWR 2

Fan1

T-SGPIO2

JL1

JP21

T-SGPIO1

A. Clear CMOS
B. Watch Dog Enable

JP18

JP19
JP17

JP16

3-27

X8OBN-F Platform User's Manual

VGA Enable

Jumper JPG1 allows the user to enable
the onboard VGA connector. The default
setting is 1-2 to enable the connection.
See the table on the right for jumper
settings.

TPM Support Enable

JPT1 allows the user to enable TPM
(Trusted Platform Modules) support
which will enhance data integrity and
system security. See the table on the
right for jumper settings. The default
setting is enabled.

Note: For more information on IPMI confi guration, please refer to the
WPCM 450 IPMI BMC User's Guide posted on our Website @ http://www.
supermicro.com.

VGA Enable

Jumper Settings

Jumper Setting Defi nition
1-2 Enabled (Default)
2-3 Disabled

TPM Support Enable

Jumper Settings

Jumper Setting Defi nition
1-2 Enabled
2-3 Disabled

COM1

VGA

USB 0/1

LAN1

LAN2

LED6

LED4

JWD1

I/O Hub 1

I-SATA3

I-SATA2

JOH1

Fan8

Buzzer

I-SATA1

COM2

I-SATA0

X8OBN-F Baseboard

JPT1
JUID_OW1

LED13

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

A

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

LED14

LED15

Rev. 1.01

LED16

LED17

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 2

Battery

BT1

JBT1

JPME1

ICH10R

JPME2

JWF1

USB4/5

USB2/3

JTPM1

I-SATA5

I-SATA4

JIPMB1

USB8

KB/Mouse

IPMI LAN

Fan12

J30
J29

Fan 11

Fan 10

J25

B

UID

J32

Fan 9

LAN CTRL

JPL1

BMC CTRL

JPB1

JPRST1

JPWR3

Fan7

Fan2

JPWR1

JF1

FP CRTL

Fan6

Fan5

JP18

Fan4

JP19

JP17

Fan3

JP16

JPWR4

A. VGA Enabled

JP3

PWR 1

J26

JP22

JPWR2

JD1

PWR 2

Fan1

T-SGPIO2

JL1

JP21

T-SGPIO1

B. TPM Enabled

3-28

Chapter 3: Installation

BMC Enable

Jumper JPB1 allows you to enable the
embedded BMC (Baseboard Manage­ment) Controller to provide IPMI 2.O/
KVM support on the motherboard. See
the table on the right for jumper set­tings.

ME Recovery

Close Jumper JPME1 to use ME Firm­ware Recovery mode, which will limit
system resource for essential function­ality use only without putting restrictions
on power use. In single operation mode,
online upgrade will be available via Re­covery mode. See the table on the right
for jumper settings.

BMC Enable

Jumper Settings

Jumper Setting Defi nition
Pins 1-2 BMC Enable
Pins 2-3 Normal (Default)

ME Recovery Select

Jumper Settings

Jumper Setting Defi nition
Open Normal (Default)
Closed Manufacture Mode

JWD1

I/O Hub 1

I-SATA3

I-SATA2

JOH1

Fan8

Buzzer

I-SATA1

COM2

I-SATA0

X8OBN-F Baseboard

JPT1

LED13

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

LED14

LED15

LED16

Rev. 1.01

LED17

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 2

Battery

BT1

JBT1

B

JPME1

ICH10R

JPME2

JWF1

USB4/5

USB2/3

JTPM1

I-SATA5

I-SATA4

JIPMB1

USB8

KB/Mouse

USB 0/1

IPMI LAN

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

JUID_OW1

LAN CTRL

JPL1

LED4

BMC CTRL

A

JPB1

JPRST1

Fan7

JPWR3

Fan2

JPWR1

JF1

FP CRTL

Fan6

Fan5

JP18

Fan4

JP19
JP17

Fan3

JP16

JPWR4

JP3

A. BMC Enabled
B. ME Mode Se-

PWR 1

J26

JP22

JPWR2

JD1

PWR 2

Fan1

T-SGPIO2

JL1

JP21

T-SGPIO1

lect

3-29

X8OBN-F Platform User's Manual

Manufacturer Mode Select

Close this jumper (JPME2) to bypass SPI fl ash
security and force the system to use the Manu­facturer Mode which will allow you to fl ash the
system fi rmware from a host server to modify
system settings. See the table on the right for
jumper settings.

JUID_OW1 (UID_Overwriting)

When the jumper JUID_OW1 is set to Off (de­fault), the Red LED (Overheat/Fan Fail/PWR
Fail/UID LED) located on Pin 8 of the Front
Control Panel (JF1) will take precedence over
the Blue UID_LED located on Pin 7 of JF1. In
this case, when the Red LED is on, the Blue
LED will be turned off. When the RED LED
is off, the Blue UID_LED can be on or off. In
other words, the Red LED signal overwrites the
Blue UID_LED signal if J_UID-OW is set to off.
When the jumper J_UID_OW is On, the Red
LED (OH/Fan Fail/PWR Fail/UID LED) and the
Blue_UID_LED work independently. The Red
LED will have no effects on the Blue LED. See
the table on the right for jumper settings.

ME Mode Select

Jumper Settings

Jumper Setting Defi nition
Open Normal (Default)
Closed Manufacture Mode

UID_Overwriting
Jumper Settings

Jumper Defi nition
Off

Red OH/Fan Fail/PWR Fail LED

(De-

(Pin 8 of JF1) takes precedence

fault)

over (overwrites) the Blue
UID_LED (Pin 7 of JF1).

Red LED: On, Blue LED: Off,
Red LED: Off, Blue LED: On
or Off

On Red LED (OH/Fan Fail/PWR

Fail LED) and the Blue UID_
LED function independently.
Red LED does not overwrite the
Blue LED. The Red LED has no
effects on the Blue_UID LED

Red LED: On, Blue LED: On,Off
Red LED: Off, Blue LED: On,
Off

X8OBN-F Baseboard

IPMI LAN

JPRST1

JPT1
JUID_OW1

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

Rev. 1.01

B

LED15

LED13

LED16

LED17

LED14

LED18

LED19

I/O Hub 2

PLX
PCI Bridge

JBT1

JPME1

ICH10R

JIPMB1

USB10

USB8

USB2/3

USB4/5

KB/Mouse

USB 0/1

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

Battery

JTPM1

BT1

A

JWF1

I-SATA4

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

JPME2

I-SATA5

JWD1

JF1

JOH1

FP CRTL

Fan6

A. JPME2
B. JUID_OW1

Fan5

JP18

Fan4

JP19
JP17

Fan3

JPWR4

Fan8

JPWR3

JP3

Fan7

I/O Hub 1

J26

Fan2

JPWR1

JPWR2

Buzzer

I-SATA3

I-SATA1

Fan1

T-SGPIO2

COM2

I-SATA2

I-SATA0

T-SGPIO1

JP16

PWR 1

JP22

JD1

PWR 2

JL1

JP21

3-30

Chapter 3: Installation

BMC Reset

Use Jumper JPRST1 to reset the BMC
settings on the motherboard. See the
table on the right for jumper settings.

BMC Reset

Jumper Settings

Jumper Setting Defi nition
Closed BMC Reset
Closed Normal (Default)

X8OBN-F Baseboard

IPMI LAN

JPRST1

A

JPT1
JUID_OW1

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

Rev. 1.01

LED15

LED13

LED16

LED17

LED14

LED18

LED19

I/O Hub 2

PLX
PCI Bridge

JBT1

JPME1

JIPMB1

USB10

USB8

KB/Mouse

USB 0/1

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

JWD1

JF1

JOH1

FP CRTL

Fan6

CPU Board Slot 4

Fan5

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 1

Battery

BT1

ICH10R

JPME2

JWF1

I-SATA5

I-SATA3

JTPM1

USB2/3

USB4/5

I-SATA4

I-SATA2

JPWR4

Fan8

JPWR3

JP3

Fan7

J26

Fan2

JPWR1

JPWR2

Buzzer

I-SATA1

Fan1

T-SGPIO2

COM2

I-SATA0

JL1

T-SGPIO1

JP18

Fan4

JP19
JP17

Fan3

JP16

PWR 1

JP22

JD1

PWR 2

JP21

A. BMC Reset En­able

3-31

X8OBN-F Platform User's Manual

3-10 Onboard LED Indicators

GLAN LEDs

Two LAN ports (LAN 1/LAN 2) are located
on the I/O Backplane of the baseboard.
Each Ethernet LAN port has two LEDs. The
yellow LED indicates activity, while the oth­er Link LED may b e green, a mber or o ff to
indic ate th e sp ee d of th e c on ne ct io ns . Se e
the tab les at ri ght for mo re infor matio n.

IPMI Dedicated LAN LEDs

In addition to LAN 1/LAN 2, an IPMI Dedi­cated LAN is also located on the I/O Back­plane of the baseboard. The amber LE D on
the ri ght indica tes activi ty, while the gre en
LED on the l eft indic ates the spee d of the
connection. See the tables at right for more
information.

Activity LED

Link LED

Rear View (when facing the

rear side of the chassis)

LAN 1/LAN 2 Link LED (Right)

LED Color Defi nition
Off No Connection or 10 Mbps
Green 100 Mbps
Amber 1 Gbps

LAN 1/LAN 2 Activity LED (Left)

Color Status Defi nition
Yellow Flashing Active

IPMI LAN (F models only)

Link LED

IPMI LAN Link LED (Left) &

Color/State Defi nition
Link (Left) Green: Solid 100 Mbps
Activity (Right) Amber: Blinking Active

LED State

LED State

Activity LED

Activity LED (Right)

X8OBN-F Baseboard

IPMI LAN

JPRST1

JPT1
JUID_OW1

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

Rev. 1.01

LED15

LED13

LED16

LED17

LED14

LED18

LED19

I/O Hub 2

PLX
PCI Bridge

JBT1

JPME1

ICH10R

JIPMB1

USB10

USB8

USB2/3

USB4/5

KB/Mouse

USB 0/1

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

LED6

UID

J32

Fan 9

LAN CTRL

JPL1

LED4

BMC CTRL

JPB1

Battery

JTPM1

BT1

JWF1

I-SATA4

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

JPME2

I-SATA5

JWD1

JF1

JOH1

FP CRTL

Fan6

A. LAN1/2 LEDs
B. IPMI LAN LEDs

Fan5

JP18

Fan4

JP19

JP17

Fan3

JL1

T-SGPIO1

JP16

B

PWR 1

JP22

A

JD1

PWR 2

JP21

JPWR4

Fan8

JPWR3

JP3

Fan7

I/O Hub 1

J26

Fan2

JPWR1

JPWR2

Buzzer

I-SATA3

I-SATA1

Fan1

T-SGPIO2

COM2

I-SATA2

I-SATA0

3-32

Chapter 3: Installation

Rear UID LED

The rear UID LED is located at LED6
on the backplane. This LED is used in
conjunction with the rear UID switch to
provide easy identifi cation of a system
that might be in need of service. Refer
to UID Switch on Page 3-15 for more
information.

BMC Heartbeat LED

A BMC Heartbeat LED is located at LED4
on the baseboard. When LED4 is blink­ing, BMC functions normally. See the
table at r ight for m ore info rmati on.

UID LED

Status

Color/State OS Status
Blue: On Windows OS Unit Identifi ed
Blue:

Linux OS Unit Identifi ed

Blinking

BMC Heartbeat LED

Status

Color/State Defi nition
Green:

BMC: Normal

Blinking

Note: LED Indicators that are not documented in the manual are for test­ing only.

JWD1

I/O Hub 1

I-SATA3

I-SATA2

JOH1

Fan8

Buzzer

I-SATA1

COM2

I-SATA0

X8OBN-F Baseboard

JPT1

LED13

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

LED14

LED15

LED16

Rev. 1.01

LED17

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 2

Battery

BT1

JBT1

JPME1

ICH10R

JPME2

JWF1

USB4/5

USB2/3

JTPM1

I-SATA5

I-SATA4

JIPMB1

USB8

KB/Mouse

USB 0/1

IPMI LAN

COM1

Fan12

J30
J29

Fan 11

VGA

LAN1

LAN2

Fan 10

J25

A

LED6

UID

J32

Fan 9

JUID_OW1

LAN CTRL

JPL1

LED4

BMC CTRL

B

JPB1

JPRST1

Fan7

JPWR3

Fan2

JPWR1

JF1

FP CRTL

Fan6

Fan5

JP18

Fan4

JP19
JP17

Fan3

JP16

JPWR4

JP3

A. Rear UID LED
B. BMC Heartbeat LED

PWR 1

J26

JP22

JPWR2

JD1

PWR 2

Fan1

T-SGPIO2

JL1

JP21

T-SGPIO1

3-33

X8OBN-F Platform User's Manual

D

E

F

3-11 Serial ATA Connections

Serial ATA Ports

There are six Serial ATA Ports (I­SATA0~I-SATA5) located on the
X8OBN-F. These ports, supported by
the Intel I CH10R Sout h Bridge, pr o­vide serial-link signal connections,
which are fast er than the connections
of Parall el ATA. Se e the t ab le on t he
right fo r pin defi nitions.

Note: For more information on SATA HostRAID confi guration, please refer
to the Intel SATA HostRAID User's Guide posted on our Website @ http://
www.supermicro.com..

Serial_ATA

Pin Defi nitions

Pin# Defi nition
1 Ground
2 TX_P
3 TX_N
4 Ground
5 RX_N
6 RX_P
7 Ground

VGA

COM1

USB 0/1

LAN1

LAN2

LED6

LED4

JWD1

I/O Hub 1

I-SATA3

I-SATA2

C

JOH1

Fan8

Buzzer

B

I-SATA1

COM2

I-SATA0

A

X8OBN-F Baseboard

JPT1
JUID_OW1

LED13

LED12

Slot10 PCI-E 2.0 x16

Slot9 PCI-E 2.0 x8

Slot8 PCI-E 2.0 x16

Slot7 PCI-E 2.0 x8

JPG1

Slot6 PCI-E 2.0 x16

Slot5 PCI-E 2.0 x8

Slot4 PCI-E 2.0 x16

Slot3 PCI-E 2.0 x8

Slot2 PCI-E 2.0 x8 in x16

Slot1 PCI-E 2.0 x8 in x16

LED14

LED15

Rev. 1.01

LED16

LED17

LED18

LED19

PLX
PCI Bridge

USB10

CPU Board Slot 4

CPU Board Slot 3

CPU Board Slot 2

CPU Board Slot 1

I/O Hub 2

Battery

BT1

JBT1

JPME1

ICH10R

JPME2

JWF1

USB4/5

USB2/3

JTPM1

I-SATA5

I-SATA4

JIPMB1

USB8

KB/Mouse

IPMI LAN

Fan12

J30
J29

Fan 11

Fan 10

J25

UID

J32

Fan 9

LAN CTRL

JPL1

BMC CTRL

JPB1

JPRST1

Fan7

Fan2

JPWR3

J26

JPWR1

Fan1

JP3

JPWR2

FP CRTL

JPWR4

T-SGPIO2

JD1

JL1

T-SGPIO1

JF1

Fan6

Fan5

JP18

Fan4

JP19
JP17

Fan3

JP16

A. I-SATA0
B. I-SATA1

PWR 1

C. I-SATA2
D. I-SATA3

JP22

E. I-SATA4
F. I-SATA5

PWR 2

JP21

3-34

Chapter 4: Troubleshooting

Chapter 4

Troubleshooting

4-1 Troubleshooting Procedures

Use the following procedures to troubleshoot your system. If you have followed all
of the procedures below and still need assistance, refer to the ‘Technical Support
Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter.
Note: Always disconnect the power cord before adding, changing or installing any
hardware components.

Before Power On

Make sure that there are no short circuits between the baseboard and chas-1.
sis.

Disconnect all ribbon/wire cables from the baseboard, including those for the 2.
keyboard and mouse.

Remove all add-on cards.3.

Install CPU Card1 fi rst (-making sure it is fully seated) and connect the front 4.
panel connectors to the baseboard.

No Power

Make sure that no short circuits between the baseboard and the chassis.1.

Make sure that the ATX power connectors are properly connected2.

Check that the 115V/230V switch on the power supply is properly set, if avail-3.
able.

Turn the power switch on and off to test the system, if applicable.4.

The battery on your baseboard may be old. Check to verify that it still sup-5.
plies ~3VDC. If it does not, replace it with a new one.

4-1

X8OBN-F Platform User's Manual

No Video

If the power is on but you have no video, remove all the add-on cards and 1.
cables.

Use the speaker to determine if any beep codes exist. Refer to the Appendix 2.
for details on beep codes.

System Boot Failure

If the system does not display POST or does not respond after the power is turned
on, check the following:

Check for any error beep from the baseboard speaker. 1.

If there is no error beep, try to turn on the system without DIMM modules. If there

•

is still no error beep, try to turn on the system again with only one processor in
CPU Socket#1. If there is still no error beep, replace the baseboard.

If there are error beeps, clear the CMOS settings by unplugging the power

•

cord and contracting both pads on the CMOS Clear Jumper (JBT1). (Refer to
Section 3-7 in Chapter 3.)

Remove all components from the baseboard, especially the DIMM modules. 2.
Make sure that the system's power is on and memory error beeps are acti­vated.

Turn on the system with only one DIMM module. If the system boots, check 3.
for bad DIMM modules or slots by following the Memory Errors Troubleshoot­ing procedure in this Chapter.

Losing the System’s Setup Confi guration

Make sure that you are using a high quality power supply. A poor quality 1.
power supply may cause the system to lose the CMOS setup information.
Refer to Section 3-6 for details on recommended power supplies.

The battery on your baseboard may be old. Check to verify that it still sup-2.
plies ~3VDC. If it does not, replace it with a new one.

If the above steps do not fi x the Setup Confi guration problem, contact your 3.
vendor for repairs.

4-2

Chapter 4: Troubleshooting

Memory Errors

When a No_Memory_Beep_Code is issued by the system, check the following:

Make sure that the memory modules are compatible with the system and that 1.
the DIMM modules are properly and fully installed. (For memory compatibility,
refer to the Memory Compatibility Chart posted on our Website at http://www.
supermicro.com.)

Check if different speeds of DIMMs have been installed. It is strongly recom-2.
mended that the same RAM speed of DIMMs are used in the system.

Make sure that you are using the correct type of DDR3 Registered ECC1066 3.
MHz SDRAM (recommended by the manufacturer).

Check for bad DIMM modules or slots by swapping a single module among 4.
all memory slots and check the results.

Make sure that all memory modules are fully seated in their slots. Follow the 5.
instructions given in Chapter 3.

Please follow the instructions given in the DIMM Population Tables listed on 6.
Page 3-8 to install your memory modules.

When the System Becomes Unstable

A. When the system becomes unstable during or after OS installation, check
the following:

CPU/BIOS support: Check if your CPU is supported and if you have the latest 1.
BIOS installed.

Memory support: Make sure that the memory modules are supported by test-2.
ing the modules using memtest86 or a similar utility.

Note: Refer to the product page on our Website at http:\\www.supermicro.
com for memory compatibility list.

HDD support: Check if all hard disk drives (HDDs) work properly. Replace the 3.
bad HDDs with good ones.

System cooling: Check system cooling to make sure that all heatsink fans, 4.
and CPU/system fans, etc., work properly. Check Hardware Monitoring set­tings in the BIOS to make sure that the CPU and System temperatures are

4-3

X8OBN-F Platform User's Manual

within normal range. Also check the front panel Overheat LED and make sure
that the Overheat LED is not on.

Adequate power supply: Make sure that the power supply provides adequate 5.
power to the system. Make sure that all power connectors are connected.
Please refer to our Website for more information on minimum power require­ment.

Proper software support: Make sure that the correct drivers are used. 6.

B. When the system becomes unstable before or during OS installation, check
the following:

Source of installation: Make sure that the devices used for installation are 1.
working properly, including boot devices such as CD/DVD disc, CD/DVD­ROM.

Cable connection: Check to make sure that all cables are connected and 2.
working properly.

Using minimum confi guration for troubleshooting: Remove all unnecessary 3.
components (starting with add-on cards fi rst), and use minimum confi guration
(with a CPU and a memory module installed) to identify the trouble areas.
Refer to the steps listed in Section A above for proper troubleshooting proce­dures.

Identifying bad components by isolating them: If necessary, remove a compo-4.
nent in question from the chassis, and test it in isolation to make sure that it
works properly. Replace a bad component with a good one.

Check and change one component at a time instead of changing several 5.
items at the same time. This will help isolating and identifying the problem.

To fi nd out if a component is good, swap it with a new one to see if the 6.
system will work properly. If so, then the old component is bad. You can also
install the component in question in another system. If the new system works,
the component is good and the old system has problems.

4-2 Technical Support Procedures

Before contacting Technical Support, please take the following steps. Also, please
note that as a baseboard manufacturer, Supermicro also sells motherboards through
its channels, so it is best to fi rst check with your distributor or reseller for trouble-

4-4

Chapter 4: Troubleshooting

shooting services. They should know of any possible problem(s) with the specifi c
system confi guration that was sold to you.

Please go through the ‘Troubleshooting Procedures’ and 'Frequently Asked 1.
Question' (FAQ) sections in this chapter or see the FAQs on our Website
(

http://www.supermicro.com/) before contacting Technical Support.

BIOS upgrades can be downloaded from our Website 2.

com

).

If you still cannot resolve the problem, include the following information when 3.
contacting Supermicro for technical support:

Baseboard model and PCB revision number

•

BIOS release date/version (This can be seen on the initial display when your •
system fi rst boots up.)

System confi guration

•

An example of a Technical Support form is on our Website at 4. (http://www.

supermicro.com).

Distributors: For immediate assistance, please have your account number ready •
when placing a call to our technical support department. We can be reached
by e-mail at [e-mail].

(http://www.supermicro.

4-3 Frequently Asked Questions

Question: What are the various types of memory that my baseboard can
support?

Answer: The X8OBN supports Registered ECC DDR3 1066 MHz SDRAM memory.

It is strongly recommended that you do not mix memory modules of different speeds
and sizes. Please follow all memory installation instructions given on Section 3-3
in Chapter 3.

Que stio n: How do I u pda te my BI OS?

It is recommended that you do not upgrade your BIOS if you are not experiencing
any problems with your system. Updated BIOS fi les are located on our website
at

http://www.supermicro.com. Please check our BIOS warning message and the

information on how to update your BIOS on our website. Select your baseboard
model and download the BIOS fi le to your computer. Also, check the current BIOS
revision and make sure that it is newer than your BIOS before downloading. You

4-5

X8OBN-F Platform User's Manual

can choose from the zip fi le and the .exe fi le. If you choose the zip BIOS fi le, please
unzip the BIOS fi le onto a bootable USB device. Run the batch fi le using the format
AMI.bat fi lename.rom from your bootable USB device to fl ash the BIOS. Then, your
system will automatically reboot.

Warning: Do not shut down or reset the system while updating BIOS to
prevent possible system boot failure!)

Note: The SPI BIOS chip used on this baseboard cannot be removed.

Send your baseboard back to our RMA Department at Supermicro for
repair. For BIOS Recovery instructions, please refer to the AMI BIOS
Recovery Instructions posted at http://

Question: What's on the CD that came with my baseboard?
Answer: The supplied compact disc has quite a few drivers and programs that will

greatly enhance your system performance. We recommend that you review the
CD and inst all t he appl icat ions yo u need. A ppli cat ions o n the CD i nclu de chi pset
driver s for th e Windo ws OS, se curi ty an d audio dr iver s.

www.supermicro.com.

Question: H ow do I ha ndl e the u sed ba tt er y?
Answer: Please handle used batteries carefully. Do not damage the battery in any

way; a damaged battery may release hazardous materials into the environment.
Do not discard a used battery in the garbage or a public landfi ll. Please comply
with the regulations set up by your local hazardous waste management agency to
dispose of your used battery properly.

4-4 Returning Merchandise for Service

A receipt or copy of your invoice marked with the date of purchase is required be­fore any warranty service will be rendered. You can obtain service by calling your
vendor for a Returned Merchandise Authorization (RMA) number. When returning
to the manufacturer, the RMA number should be prominently displayed on the
outside of the shipping carton, and mailed prepaid or hand-carried. Shipping and
handling charges will be applied for all orders that must be mailed when service
is complete. For faster service, You can also request a RMA authorization online
(http://

This warranty only covers normal consumer use and does not cover damages in­curred in shipping or from failure due to the alternation, misuse, abuse or improper
maintenance of products.

www.supermicro.com).

During the warranty period, contact your distributor fi rst for any product problems.

4-6

Chapter 4: AMI BIOS

Chapter 5

BIOS

5-1 Introduction

This chapter describes the AMI BIOS Setup Utility for the X8OBN-F Baseboard.
The AMI ROM BIOS is stored in a Flash EEPROM and can be easily updated. This
chapter describes the basic navigation of the AMI BIOS Setup Utility screens.

Starting BIOS Setup Utility

To enter the AMI BIOS Setup Utility screens, press the <Delete> key while the
system is booting up.

Note: In most cases, the <Delete> key is used to invoke the AMI BIOS
setup screen. There are a few cases when other keys are used, such as
<F1>, <F2>, etc.

Each main BIOS menu option is described in this manual. The Main BIOS setup
menu screen has two main frames. The left frame displays all the options that can
be confi gured. Grayed-out options cannot be confi gured. Options in blue can be
confi gured by the user. The right frame displays the key legend. Above the key
legend is an area reserved for a text message. When an option is selected in the
left frame, it is highlighted in white. Often a text message will accompany it.

Note: the AMI BIOS has default text messages built in. Supermicro retains
the option to include, omit, or change any of these text messages.

The AMI BIOS Setup Utility uses a key-based navigation system called "hot keys".
Most of the AMI BIOS setup utility "hot keys" can be used at any time during the
setup navigation process. These keys include <F1>, <F10>, <Enter>, <ESC>, ar­row keys, etc.

Note: Options printed in Bold are default settings.

How To Change the Confi guration Data

The confi guration data that determines the system parameters may be changed by
entering the AMI BIOS Setup Utility. This setup utility can be accessed by pressing
<Del> at the appropriate time during system boot.

Note: For UEFI BIOS Recovery, please refer to the UEFI BIOS Recovery
Instructions posted on our website at http://www.supermicro.com/support/
manuals/.

5-1

X8OBN-F Platform User's Manual

Starting the Setup Utility

Normally, the only visible Power-On Self-Test (POST) routine is the memory test.
As the memory is being tested, press the <Delete> key to enter the main menu of
the AMI BIOS Setup Utility. From the main menu, you can access the other setup
screens. An AMI BIOS identifi cation string is displayed at the left bottom corner of
the screen below the copyright message.

Warning! Do not upgrade the BIOS unless your system has a BIOS-related
issue. Flashing the wrong BIOS can cause irreparable damage to the
system. In no event shall Supermicro be liable for direct, indirect, special,
incidental, or consequential damages arising from a BIOS update. If you
have to update the BIOS, do not shut down or reset the system while the
BIOS is updating. This is to avoid possible boot failure.

5-2 Main Setup

When you fi rst enter the AMI BIOS Setup Utility , you will enter the Main setup screen.
You can always return to the Main setup screen by selecting the Main tab on the
top of the screen. The Main BIOS Setup screen is shown below.

BIOS Information: The following BIOS information will be displayed:

BIOS Vendor: This item displays the name of the BIOS vendor.

•

Core Version: This item displays the version of the BIOS Core currently used •
in the system.

Project Version: This item displays the version of the motherboard currently

•

used in the system.

5-2

Chapter 4: AMI BIOS

Build Date: This item displays the date when this BIOS was completed. •

Memory Information: The following memory information will be displayed:

Total Memory: This item displays the size of memory available in the system.

•

System Language

The feature allows the user to select a language setting for the Setup utility. The
default setting is English.

System Time/System Date

These features allow the user to change the system time and date. Highlight System
Time or System Date using the arrow keys. Enter new values through the keyboard

and press <Enter>. Press the <Tab> key to move between fi elds. The date must be
entered in MM/DD/YY format. The time is entered in HH:MM:SS format.

Note: The time is in the 24-hour format. For example, 5:30 P.M. appears
as 17:30:00.

Access Level

The feature displays the privilege level that has been pre-set for the user for ac­cessing the setup utility or the system.

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X8OBN-F Platform User's Manual

5-3 Advanced Setup Confi guration

Use the arrow keys to select the Advanced Setup menu and press <Enter> to ac­cess the submenu items.

PCI Subsystem Settings

PCI Bus Driver Version: This feature displays the version number of the PCI Bus
Driver used in this system.

PCI Bus Driver Version: This item displays the version of the PCI bus driver
currently used in the system.

PCI ROM Priority

This feature allows the user to specify which PCI Option ROM to use when multiple
Option ROMs are installed in the system. The options are Legacy ROM and EFI

(Extensible Firmware Interface)_Compatible ROM.

Above 4G Decoding

Select Enabled to allow a 64_bit_capable device to be decoded in the address
space above 4G if 64-bit_PCI_decoding is supported by the system. The options
are Enabled and Disabled.

PCI Common Settings

PCI Latency Timer

Select a value to be used by the PCI Latency Timer Register in bus clock calculation.
The options are 32 PCI Bus Clocks, 64 PCI Bus Clocks, 96 PCI Bus Clocks, 128
PCI Bus Clocks, 160 PCI Bus Clocks, 192 PCI Bus Clocks, 224 PCI Bus Clocks,
and 248 PCI Bus Clocks.

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Chapter 4: AMI BIOS

VGA Palette Snoop

If this feature is set to Enabled, a PCI card that does not have its own VGA color
palette built-in will detect a video_card palette to mimic it for color scheme support.
The options are Enabled and Disabled.

PERR# Generation

Select Enabled to allow a PCI device to generate a PERR number for a PCI Bus
Signal Error Event. The options are Enabled and Disabled.

SERR# Generation

Select Enabled to allow a PCI device to generate an SERR number for a PCI Bus
Signal Error Event. The options are Enabled and Disabled.

PCI Express Device Settings

Relaxed Ordering

Select Enabled to allow a PCI-E transaction to be completed prior to other transac­tions that were already enqueued. This violates PCI strict-ordering rules. The options
are Enabled and Disabled.

Extended Tag

Select Enabled to allow a PCI-E device to use the 8-bit Tag fi eld as a requester.
The options are Enabled and Disabled.

No Snoop

Select Enabled to enable the "no_snoop bit" for a PCI-E device, which will reduce
front_side bus traffi c for performance enhancement. The options are Enabled and
Disabled.

Maximum Payload

Select Auto to allow the system BIOS to automatically set the maximum payload
value for a PCI-E device to enhance system performance. The options are Auto,
128 Bytes, 256 Bytes, 512 Bytes, 1024 Bytes, 2048 Bytes, and 4096 Bytes.

Maximum Read Request

Select Auto to allow the system BIOS to automatically set the maximum Read
Request size for a PCI-E device to enhance system performance. The options
are Auto, 128 Bytes, 256 Bytes, 512 Bytes, 1024 Bytes, 2048 Bytes, and 4096
Bytes.

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X8OBN-F Platform User's Manual

PCI Express Link Settings

ASPM Support

This feature allows the user to set the Active State Power Management (ASPM)
level for a PCI-E device. Select Force L0 to force all PCI-E links to operate at L0
state. Select Auto to allow the system BIOS to automatically set the ASPM level for
the system. Select Disabled to disable ASPM support. The options are Disabled,
Force L0, and Auto.

Warning: Enabling ASPM support may cause some PCI-E devices to
fail!

Extended Synch

Select Enabled to generate extended synchronization patters to enhance system
performance. The options are Disabled and Enabled.

ACPI (Advanced Confi guration and Power Interface)
Settings

This feature allows the user to set Advanced Confi guration and Power Interface
parameters for this system.

Enable ACPI Auto Confi guration

Select Enabled to allow the system BIOS to automatically confi gure ACPI param-
eters for the system. The options are Disabled and Enabled.

Enable Hibernation

Select Enabled for Hibernation support which will allow a system to enter an OS/S4
state. Hibernation may not be supported by some operation systems. The options
are Enabled and Disabled.

ACPI Sleep State

Use this feature to set the highest ACPI sleep state when the suspend button is
pressed. The options are S1 (CPU_Stop_Clock) and Suspend Disabled.

Trusted Computing

This feature allows the user to confi gure Trusting Computing settings.

TPM Confi guration

This future allows the user to set Trusted Platform Module Confi guration settings.

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Chapter 4: AMI BIOS

TPM Support

Select Enabled to enable TPM (Trusted Platform Module) support for system
security and data integrity. The options are Disabled and Enabled. If this option
is set to Enabled, the following items will display.

TPM State

Select Enabled to display the status of TPM support for this system. The options
are Disabled and Enabled. Please note that a system reboot is needed before
a change on the TPM state to take effect.

Pending TPM Operation

This feature is used to schedule a TPM operation that is pending. Select "Enable
Take Ownership" to allow the pending TPM operation to take precedence over other
operations in the queue and be processed and executed immediately. If the option
"Disable Take Ownership" is selected, the pending TPM operation will not take
precedence over other operations and will be processed based on the order that
are placed in the queue. Select the option "TPM Clear" to delete all pending TPM
operations from the queue. If the option "None" is displayed, there is no pending
TPM operation in the queue. Please note that a system reboot is needed for any
change on the feature to become effective. The options are None, Enable Take
Ownership, Disable Take Ownership, and TPM Clear.

Current TPM Status Information

This feature displays the current status of the TPM items listed below.

TPM Enabled State

Select Enabled to display the status of "TPM Enabled" in this system. The op­tions are Disabled and Enabled.

TPM Active State
Select Deactivate to disable TPM support for this system. The options are De-

activated and Activate.

TPM Owner Status

This feature lists the status of the TPM Owner. The default setting is UnOwned
which indicates that there is no owner listed for TPM support.

WHEA Confi guration

This feature allows the user to confi gure WHEA (Windows Hardware Error Ar-
chitecture) settings.

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X8OBN-F Platform User's Manual

WHEA Support

Selec t En ab le d to e na bl e W H EA supp ort whi c h w il l pr ov id e a c o mm o n in f ra st r u c­ture for t he system to handle har dware errors o n the Windows OS p latforms in
order to r educe system c rashes due t o hardware er rors and to e nhance syste m
recove ry an d healt h moni tori ng. The de fault set tin g is Enabled.

CPU Confi guration

CPU Confi guration

This feature allows the user to confi gure CPU support settings. It also displays the
status of the processor used in the system.

CPU Type

• : This item displays the CPU type for the motherboard.

Physical Processors

• : This item displays the number of physical processors

used in this system.

Logical Processors

• : This item displays the number of logical processors avail-

able for this system.

Socket 0 ~ Socket 7 CPU Information

CPU Type•

CPU Signature•

Microcode Patch•

Max Processor Speed/Min Processor Speed• : This item displays the maxi-

mum and minimum speed of the processor used in the system.

Processor Cores

• : This item indicates the number of processor cores avail-

able in the system.

Intel HT Technology

• : This item indicates if Intel Hyper-Threading Technol-

ogy is supported by the system. Intel TH Technology is used to enhance
CPU performance.

Intel VT-x Technology

• : This item indicates if Intel Virtualization Technology

is supported by the motherboard.

L1 Data Cache/L1 Code Cache/L2 Cache/L3 Cache

•

CPU Speed• : This item displays the CPU speed of the motherboard.

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Chapter 4: AMI BIOS

64-bit• : This item indicates if 64-bit is supported by the CPU.

CPU Spread Spectrum

Select Enable to enable CPU Clock Spectrum support, which will allow the BIOS to
monitor and attempt to reduce the level of Electromagnetic Interference caused by
the components whenever needed. The options are Disabled and Enabled.

Hyper-threading

Select Enabled to use Hyper-Threading Technology, which will result in increased
CPU performance. The options are Disabled and Enabled.

Active Processor Core

Select Enabled to use a processor's second core and beyond. (Please refer to Intel's
website for more information.) The options are All, 1 and 2.

Limit CPUID Maximum

This feature allows the user to set the maximum CPU ID value. Enable this func­tion to launch the legacy operating systems that cannot support processors with
extended CPUID functions. The options are Enabled and Disabled (for the Win­dows OS.)

Execute Disable Bit Capability (Available when supported by the OS and
the CPU)

Set to Enabled to support Execute Disable Bit which will allow the processor to
designate areas in the system memory where an application code can execute
and where it cannot, thus preventing a worm or a virus from fl ooding illegal codes
to overwhelm the processor or damage the system during an attack. The default is

Enabled. (Refer to Intel and Microsoft web Sites for more information.)

Hardware Prefetcher (Available when supported by the CPU)

If enabled, the hardware prefetcher will prefetch streams of data and instructions
from the main memory to the L2 cache in the forward or backward manner to im­prove CPU performance. The options are Disabled and Enabled.

Adjacent Cache Line Prefetch (Available when supported by the CPU)

If this item is set to Disabled, the CPU prefetches the cache line for 64 bytes. The
CPU prefetches both cache lines for 128 bytes as comprised if this item is set to
Enabled. The options are Disabled and Enabled.

Intel® Virtualization Technology (Available when supported by the CPU)

Select Enabled to use Intel Virtualization Technology which will allow one platform
to run multiple operating systems and applications in independent partitions, creat-

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X8OBN-F Platform User's Manual

ing mult iple " vir tual" sy stems in o ne physic al co mputer. The opt ions ar e Enable d
and Disabled. Note: Please rebo ot the system for any c hange in thi s setting to
take effe ct. Pl ease refer to I ntel’s website fo r detail ed infor matio n.

Power Technology

Use this feature to select power management features for the system. Select Energy
Effi cient to minimize power use. Select Custom to customize power use settings.
The options are Disabled, Energy Effi cient and Custom.

EIST (Available when supported by the OS and the CPU)

EIST (Enhanced Intel SpeedStep Technology) allows the system to automatically
adjust processor voltage and core frequency in an effort to reduce power consump­tion and heat dissipation. Please refer to Intel’s web site for detailed information.
The options are Disabled and Enabled.

Turbo Boost Mode (Available when EIST Tech. is enabled)

Select Enabled to enable Turbo Mode support to boost system performance. The
options are Enabled and Disabled.

Performance/Watt (Available when supported by the OS and the CPU

Select Optimized to activate the Turbo Boost mode after the highest performance
power state has lasted more than two seconds. Select Traditional to use the Turbo
mode whenever possible. The options are Traditional and Optimized.

P-STATE Coordination (Available when supported by the OS and the CPU

This feature allows the user to decide how to change a P-State Coordination type.
A P-state is the operational state when a processor/core is performing meaningful
and useful tasks. The options are HW_All (All Hardware-related events), SW_All
(All Software-related events), and SW_Any (Any Software-related events).

CPU C3 Report (Available when the C-State Tech is enabled)

This feature allows the user to decide at what power state should the CPU treat
it as a CPU C3 state and report it to the OS as so. Select ACPI C-2 to report an
ACPI C-2 event as a CPU C3 state to the OS. Select ACPI C-3 to report an ACPI
C-3 event as a CPU C3 state to the OS. The options are ACPI-C2, ACPI-C-3, and

Disabled.

CPU C6 Report (Available when the C-State Tech is enabled)

Select Enabled to report a CPU C6 (ACPI C-3) event to the OS. The options are
Enabled and Disabled.

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Chapter 4: AMI BIOS

Package C-State Limit (Available when the C-State Tech is enabled)

If this package is set to Auto, the AMI BIOS will automatically set a limit on the reg­ister of the C-State package. The options are No Limit, C0, C1, C3, C6, and C7.

Local APIC (Available when supported by the CPU and the OS)

The local Advanced Programmable Interrupt controller (Local APIC), embedded in
a CPU, manages all external interrupts for the CPU in a 4-way or 8-way system.
It also interacts with the interrupts that are generated by other Local APIC control­lers inside other CPUs. If this feature is set to Auto, the AMIBIOS will automatically
detect if the system is using the Nehalem processor or the Westmere EX processor .
If the system uses the Nehalem EX processor, the BIOS will select xAPIC to boost
system performance. If the system uses the Westmere EX processor, the BIOS will
select x2APIC to boost performance. If your system uses the Westmere processor
and your OS does not support x2APIC, please select Compatible to enhance your
system performance. The options are Compatible and Auto.

Note: Currently , x2APIC is supported by newer operating systems such as
Windows 2008 R2 SP1 OS or Redhat 6.0 (or newer) OS.

Runtime Error Logging

Runtime Error Logging

Select Enabled to support Runtime Error Logging. The options are Enabled and

Disabled. If this feature is set to Enabled, the following items will display:

PCI Error Logging Support

Select Enabled to enable error logging occurred in PCI/PCI-E connections. The
options are Enabled and Disabled.

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X8OBN-F Platform User's Manual

Memory Correctable Error Threshold

This feature allows the user to enter the threshold value for memory correctable
errors. The default setting is 10.

Legacy OpROM (Option ROM) Confi guration

Legacy OpROM Support

Use this feature to confi gure Option ROM settings which will allow the system to
boot up via a legacy network device.

Onboard Gigabit LAN 0/ Onboard Gigabit LAN 1

Select Enabled to boot up the system via a legacy network device installed on
Onboard G-LAN Port 0 or G-LAN Port 1. The options are Enabled and Disabled.

Select Option ROM [PXE}

Slot1 Option ROM~Slot10 Option ROM

Select Enabled to boot up the system via a legacy mass storage device installed
a slot specifi ed. The options are Enabled and Disabled.

SATA Confi guration

When this submenu is selected, the AMI BIOS automatically detects the presence
of the SATA devices and displays the following items:

SATA Port0/SATA Port1/SATA Port2/SATA Port3/SATA Port4/SATA Port5

•

SATA Mode

Use this feature to set the SATA mode for a SATA port selected by the user. Select
IDE mode to confi gure the SATA drive as an IDE drive. Select AHCI Mode to enable
the SATA drive to support AHCI Interface (Advanced Host Controller Interface).
Select RAID Mode to enable the SATA drive for RAID support. The options are IDE
Mode, AHCI Mode and RAID Mode.

When AHCI is selected, the item-AHCI CodeBase will display:

AHCI CodeBase (Available when RAID or AHCI is selected)

Select BIOS Native Module to use the BIOS Native Mode for the AHCI Interface.
Select Intel AHCI ROM to use the Intel AHCI ROM for the AHCI Interface. (Take
caution when using this function for this mode is for advanced programmers
only.)

When RAID is selected, the items: "AHCI CodeBase" (above), and "ICH RAID
Code Base" will appear.

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Chapter 4: AMI BIOS

ICH RAID Code Base (Available when the option-RAID is selected)

Select Intel to use Intel SATA RAID fi rmware for Intel SATA RAID confi guration.
Select Adaptec to use Adaptec fi rmware for Adaptec SATA RAID confi guration.
The options are Intel and Adaptec.

SATA Port0 Confi guration/SATA Port1 Confi guration/SATA Port2
Confi guration/SATA Port3 Confi guration//SATA Port4 Confi guration//SATA
Port51 Confi guration

These submenus allow the user to confi gure the following item for a SATA port
selected by the user.

eSATA Port Support

Select Enabled to enable a SATA port specifi ed by the user for external SATA con-
nection support. The options are Enable and Disabled.

USB Confi guration

USB Devices: This feature displays the status of the USB devices detected in •
the system.

Legacy USB Support

Select Enabled to support Legacy USB devices. If this item is set to Auto, the AMI
BIOS will automatically enable Legacy USB support if a legacy USB device is de­tected. The settings are Enabled, Disabled and Auto.

EHCI Hand-Off

Select Enabled to support the BIOS-Enhanced Host Controller Interface to provide a
workaround solution for an operating system that does not have EHCI Hand-Off sup­port. When enabled, the EHCI Interface will be changed from the BIOS-controlled
to the OS-controlled. The options are Disabled and Enabled.

USB Hardware Delay

USB Transfer Timeout

This setting allows you to decide how long the system should wait in an attempt to
detect the presence of a USB Mass Storage Device before a USB Transfer is ex­ecuted. The options are 10 Seconds, 20 Seconds, 30 Seconds and 40 Seconds.

Device Reset Timeout

This setting allows you to decide how long the system should wait in an attempt
to detect the presence of a USB Mass Storage Device before it proceeds with the
next operation during POST. The options are 10 Seconds, 20 Seconds, 30 Seconds
and 40 Seconds.

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X8OBN-F Platform User's Manual

Device Power-up Delay

Select Auto to use the default maximum time value for a USB device to wait before it
reports itself to the Host Controller. The default maximum wait time for a root port is
100 ms. The maximum wait time for a Hub port is determined by the Hub Descriptor .
Select Manual to manually enter a maximum wait time for a USB device before this
device reports itself to the Host Controller. The options are Auto and Manual.

Hardware Monitoring Confi guration

This feature allows the user to monitor system health and review the status of each
item as displayed.

CPU Overheat Alarm

This option allows the user to select the CPU Overheat Alarm setting that deter­mines when the CPU OH alarm will be activated to provide warning of possible
CPU overheat.

The options are:

The Early Alarm: Select this setting to trigger the CPU overheat alarm as soon

•

as the CPU temperature reaches the CPU overheat threshold as predefi ned by
the CPU manufacturer.

The Default Alarm

• : Select this setting to trigger the CPU overheat alarm when

the CPU temperature reaches about 5oC above the threshold temperature as
predefi ned by the CPU manufacturer to give the CPU and system fans additional
time needed for CPU and system cooling.

Warning! To avoid possible system overheating, please be sure to provide
adequate airfl ow to your system.

Fan Speed Control Modes

This feature allows the user to decide how the system controls the speeds of the
onboard fans. The CPU temperature and the fan speed are correlated. When the
CPU on-die temperature increases, the fan speed will also increase for effective
system cooling. Select "Full Speed/FS" to allow the onboard fans to run at full
speed for maximum cooling. The FS setting is recommended for special system
confi guration or debugging. Select "Performance/PF" for better system cooling. The
PF setting is recommended for high-power-consuming and high-density systems.
Select "Balanced/BL" for the onboard fans to run at a speed that will balance the
needs between system cooling and power saving. The BL setting is recommended
for regular systems with normal hardware confi guration. Select "Energy Saving/ES"
for best power effi ciency and maximum quietness. The Options are: Full Speed/FS,
Performance/PF, Balanced/BL, and Energy Saving/ES.

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Chapter 4: AMI BIOS

Fan Speed Readings

The following fan speeds are displayed: Fan1 Speed~Fan 12 Speeds

Baseboard Voltage and Temperature

The he following temperature and voltage settings will be displayed (in degrees in
Celsius and Fahrenheit) as detected by the BIOS:

System Temperature, +1.8V Aux, +1.2V BM C, +1.0V NIC, +1,1V AUX, +1.0V

•

P E X, + 5.0V, + 1.1 V, +1 . 8 V, + 12.0 V, + 1.5 V, V BAT, + 3 .3V, a nd + 3 .3V V SB.

CPU0 Voltage and Temperature~CPU7 Voltage and

Temperature

The following temperature and voltage settings of a CPU specifi ed will be displayed
as detected by the BIOS:

CPU Temperature

•

Low – This level is considered as the ‘normal’ operating state. The CPU tem­perature is well below the CPU ‘Temperature Tolerance’ level. The onboard
fans and CPU run normally as confi gured in the BIOS. User intervention:
No action required.

Medium – The processor is running warmer. This is a ‘precautionary’ level
and generally means that there may be factors contributing to this condition,
but the CPU is still within its normal operating state and the CPU ‘Tempera­ture Tolerance’ level. The onboard fans and CPU run normally as confi gured
in the BIOS. The fans may adjust to a faster speed depending on the Fan
Speed Control settings. User intervention: No action is required. However,
consider checking the CPU fans and the chassis ventilation for blockage.

High – The processor is running hot. This is a ‘caution’ level since the CPU’s
‘T emperature Tolerance’ has been reached or exceeded. The overheat alarm
may be triggered. The system may shut down if it continues for a long period
to prevent damage to the CPU.

CPU Vcore, CPU Vcache, CPU Millbrook 1.1V, CPU Branch0 VDD 1.5V, and

•

CCPU Branch1 VDD 1.5V

Super IO Confi guration (for the W83527 HG chip)

Super IO Chip: This item displays the status of the onboard Super IO chip.•

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X8OBN-F Platform User's Manual

Watchdog Function

If enabl ed, t he Watc hD o g Ti mer w il l c aus e th e syste m to re bo ot w hen t he sy stem
is inact ive for mo re tha n 5 minutes. T he opti ons are En abled a nd Disabled.

Super IO Confi guration (for the WPCM450 chip)

Super IO Confi guration (Winbond WPCM450)

Super IO Chip: This item displays the status of the onboard Super IO chip.

•

Watchdog Function

Select Enabled to enable the Watch Dog Timer. The options are Enabled and
Disabled.

Serial Port 0 Confi guration/Serial Port 1 Confi guration

Serial Port

Select Enabled to enable a serial port specifi ed by the user. The options are

Enabled and Disabled.

Device Settings

This feature indicated if reset is required or not for a serial port specifi ed.

Change Settings

Use this feature to set the optimal Environment_Control_Interface (PECI) setting
for a serial port specifi ed. The default setting is Auto, which will allow the AMI
BIOS to automatically select the best setting for the PECI platform.

Device Mode

Use this feature to select the desired mode for a serial port specifi ed. The options
are Normal and High Speed.

Serial Port Console Redirection

COM 1/COM2•

These two submenus allow the user to confi gure the following Console Redirection
settings for a COM Port specifi ed by the user.

Console Redirection

Select Enabled to use a COM Port selected by the user for Console Redirection.
The options are Enabled and Disabled.

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Chapter 4: AMI BIOS

Console Redirection Settings

This feature allows the user to specify how the host computer will exchange data
with the client computer, which is the remote computer used by the user.

Terminal Type

This feature allows the user to select the target terminal emulation type for
Console Redirection. Select VT100 to use the ASCII Character set. Select
VT100+ to add color and function key support. Select ANSI to use the Extended
ASCII Character Set. Select VT-UTF8 to use UTF8 encoding to map Unicode
characters into one or more bytes. The options are ANSI, VT100, VT100+, and
VT-UTF8.

Bits Per second

Use this feature to set the transmission speed for a serial port used in Console
Redirection. Make sure that the same speed is used in the host computer and the
client computer. A lower transmission speed may be required for long and busy
lines. The options are 9600, 19200, 57600 and 115200 (bits per second).

Data Bits

Use this feature to set the data transmission size for Console Redirection. The
options are 7 Bits and 8 Bits.

Parity

A parity bit can be sent along with regular data bits to detect data transmission
errors. Select Even if the parity bit is set to 0, and the number of 1's in data bits
is even. Select Odd if the parity bit is set to 0, and the number of 1's in data bits
is odd. Select None if you do not want to send a parity bit with your data bits
in transmission. Select Mark to add a mark as a parity bit to be sent along with
the data bits. Select Space to add a Space as a parity bit to be sent with your
data bits. The options are None, Even, Odd, Mark and Space.

Stop Bits

A stop bit indicates the end of a serial data packet. Select 1 Stop Bit for standard
serial data communication. Select 2 Stop Bits if slower devices are used. The
options are 1 and 2.

Flow Control

This feature allows the user to set the fl ow control for Console Redirection to
prevent data loss caused by buffer overfl ow. Send a "Stop" signal to stop send-
ing data when the receiving buffer is full. Send a "Start" signal to start sending
data when the receiving buffer is empty. The options are None, Hardware RTS/
CTS, and Software Xon/Xoff.

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X8OBN-F Platform User's Manual

Resolution 100x31
Select Enabled for extended-terminal resolution support. The options are Dis-

abled and Enabled.

Legacy OS Redirection

Use this feature to select the number of rows and columns used in Console
Redirection for legacy OS support. The options are 80x24 and 80x25.

Serial Port for Out-of-Band Management/Windows Emergency
Management Services (EMS)

The submenu allows the user to confi gure the following Console Redirection
settings to support Out-of-Band Serial Port management.

Console Redirection

Select Enabled to use COM Port1 for Console Redirection. The options are

Enabled and Disabled.

Out-of_Band Management Port

This feature allows the user to select a serial port to be used by the Windows
Emergency Management Services (EMS) for remote system management during
an emergency. The options are COM 1 and COM 2.

Data Bits

This feature allows the user to select data bits for console redirection transmis­sion. The options are 7 Bits and 8 Bits.

Parity

A parity bit can be sent with the data bits for data transmission errors. Select
Even if the parity bit is set to 0 and the number of 1's in data bits is even. Select
Odd if the parity bit is set to 0 and the number of 1's in data bits is odd. Select
None if you do not want to send a parity bit with your data bits in transmission.
Select Mark to add a mark as a parity bit to be sent with the data bits. Select
Space to add a Space as a parity bit to be sent with your data bits. The options
are None, Even, Odd, Mark and Space.

Stop Bits

A stop bit indicates the end of a serial data packet. Select 1 Stop Bit for standard
serial data communication. Select 2 Stop Bits if slower devices are used.

Terminal Type

This feature allows the user to select the target terminal emulation type for Con­sole Redirection. Select VT100 to use ASCII Character set, Select VT100+ to
also include color, function key support. Select ANSI to use Extended ASCII Char-

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Chapter 4: AMI BIOS

acter Set. Select VT-UTF8 to use UTF8 encoding to map Unicode characters into
one or more bytes. The options are ANSI, VT100, VT100+, and VT-UTF8.

Network Stack

Network Stack

Select Enabled enable PXE (Preboot Execution Environment) or UEFI (Unifi ed
Extensible Firmware Interface) for network stack support. The options are Enabled
and Disabled.

5-4 Chipset

Use the arrow keys to select Chipset and press <Enter> to access the submenu
items. This submenu allows the user to confi gure chipset settings.

North Bridge

This submenu allows the user to confi gure the following North Bridge parameters.

Boxboro IOH Confi guration

NB Revision• : This item displays the Boxboro IOH revision number.

Intel® VT for Direct I/O Confi guration

This feature allows the user to confi gure Intel Virtualization Technology for Directed
I/O settings.

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X8OBN-F Platform User's Manual

Intel® VT-d

Select Enabled to enable Intel Virtualization Technology support for Direct I/O
VT-d

by reporting the I/O device assignments to VMM through the DMAR ACPI

Tables. This feature offers fully-protected I/O resource-sharing across the Intel
platforms, providing the user with greater reliability, security and availability in
networking and data-sharing. The options are Enabled and Disabled.

Interrupt Remapping
Select Enabled to support VT-d Engine Interrupt Remapping. The options are

Enabled and Disabled.

Coherency Support

Select Enabled to enable Non-Isoch VT-d Engine Coherency support. The op­tions are Enabled and Disabled.

ATS Support

Select Enabled to enable VT-d Engine Address Translation Services support.
The options are Enabled and Disabled.

Pass-through DMA

Select Enabled to enable Isoch/Non-Isoch VT-d Engine Pass-through DMA sup­port. The options are Enabled and Disabled.

Intel® I/OAT

The Intel I/OAT (I/O Acceleration Technology) signifi cantly reduces CPU overhead
by leveraging CPU architectural improvements, freeing resources for more other
tasks. The options are Disabled and Enabled.

DCA Support (Available when Intel I/OAT is enabled)

Select Enabled to use Intel's DCA (Direct Cache Access) Technology for data
transferring enhancement. The options are Enabled and Disabled.

PCIe Gen1 Device Support (Available when Intel I/OAT is enabled)

Select Enabled to support PCI-Express Gen. 1 devices. The options are Enabled
and Disabled.

IOH PCIe Port Bifurcation Support

This feature displays the following IOH PCIe Port Bifurcation Control settings,
which indicate how PCI-Express connections are split into different PCI-E signals
for various device support.

IOH1/IOU2

•

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Chapter 4: AMI BIOS

IOH1/IOU0•

IOH1/IOU1•

IOH2/IOU2•

IOH2/IOU0•

IOH2/IOU1•

IOH Thermal Sensors

This feature allows the user to confi gure integrated thermal sensor settings embed-
ded in the 7500 chipset.

Thermal Sensors

Select Enabled to enable integrated thermal sensors embedded in the 7500
chipset. The options are Enabled and Disabled.

Low Threshold: This item displays the value of the low thermal threshold.

•

High Threshold: This item displays the value of the high thermal threshold.•

Catastrophe Threshold: This item displays the value of the catastrophic thresh-•
old, beyond which the system enters into the catastrophic state.

QPI Link

QuickPath Interconnect (QPI) is the connection between the processors and
the I/O hubs (IOH's). This submenu allows the user to confi gure the following
QPI settings.

Current QPI Link Speed: This item displays the current QPI Link speed.

•

Current QPI Link Frequency: This item displays the current QPI Link fre-•
quency.

CSI (Common System Interface) Link Speed

This feature allows the user to select the speed for CSI (Common System
Interface) Link, which is the former name for QPI Link. Select Fast for POR
(Power_On Reset)-related devices. The options are Slow and Fast.

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X8OBN-F Platform User's Manual

QPI Link Frequency Select

This feature allows the user to set the QPI Link Frequency. Select Auto for the
AMI BIOS to automatically set the QPI Link Frequency for optimal system per­formance. The options are Auto, 4.8 GT/s, 5.866 GT/s, and 6.4 GT/s.

CRC Mode

Use this feature to enable the CRC (Cyclic Redundancy Check) mode in CSI and
select the method used by the CRC mode to detect any accidental changes to
raw computer data occurred in digital networks or storage devices. The options
are 8_bit CRC and 16_bit Rolling CRC.

CSI (Common System Interface) Scrambling

Select Enabled to support CSI data scrambling via 0:10h/11h:0:44h:22. The op­tions are Enabled and Disabled.

Logical Interrupt Mode

Use this feature to select the Logical Interrupt mode for the programmable inter­rupt controller (PIC) embedded in a multiple-processor system. Select Flat mode
for the PIC to process interrupts in the linear, sequential format. Select Cluster
Mode for the PIC to process interrupts in the cascade format. The options are

Flat Mode and Cluster Mode.

Cluster Mode Check Sampling

Select Enabled for a system to check the APIC ID for non-zero. APIC ID is used
to identify a processor in multi-processor systems. The options are Enabled
and Disabled.

MMIOH Size per IOH

Use this feature to select the MMIOH Size to be allocated to every IOH in the
system. The options are 2G, 4G, 6G and 8G.

Intel reference Code

This item displays Intel IOH Reference code for the system.

Memory Information

The item displays the following memory information:

Total Memory: This item displays the total memory available in the sys-

•

tem.

Current Memory Mode: This item displays the current memory mode used

•

in the system.

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Chapter 4: AMI BIOS

Current Memory Speed: This item displays the current memory speed of •
the system.

Mirroring: This item indicates if memory mirroring is supported by the system

•

for data security enhancement.

•

Sparing: This item indicates if memory sparing is supported by the system
for memory performance enhancement.

Memory Confi guration

This feature allows the user to confi gure the following memory settings:

Memory Init mode

Select Serial to set the memory initialization mode to Serial. Select Parallel to set
the memory initialization mode to Parallel. The options are Serial and Parallel.

Page Policy

This feature allows the user to select the memory page policy for virtual memory
support. Select Open for a memory control unit to issue a command to open a
memory page. Select Closed for the memory control unit to issue a command
to close a memory page. Select Adaptive to provide a fl exible page policy to
better support each individual event. Select Multi-Cas Widget to simultaneously
provide memory support to multiple users in a multi-casting format. The options
are Closed, Open, Adaptive and Muliti-Cas Widget.

Mapping Policy

This feature allows the user to set the policy for memory mapping, which is a
fi le used by the virtual memory system of the OS to access the data in the fi le
system directly instead of accessing the contents stored in a fi le, one piece at a
time, to improve I/O performance. The options are Closed and Open.

Scheduler Policy

This feature allows the user to set the policy for memory scheduling for dynamic
RAM accessing. The options are Adaptive, Static T rade Off, Static Read Primary
and Static Write Primary.

NUMA

Select Enabled to enable Non-Uniform Memory Access support to improve CPU
performance. The options are Enabled and Disabled.

DDR Speed

This feature allows the user to set a speed for onboard DDR modules. Select
Auto for the AMI BIOS to set the DDR speed based on the DDR specifi cations

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X8OBN-F Platform User's Manual

detected in the system. The options are Auto, Force DDR3 800, Force DDR3
978 and Force DDR3 1067.

High Temperature

Select Enabled for high temperature support for onboard memory modules. The
options are Enabled and Disabled.

Hemisphere

Select Enabled for Hemisphere Mode support to improve the latency of individual
memory accessing. The options are Enabled and Disabled.

Patrol Scrub

It is a memory error-correction scheme that works in the background looking for
and correcting resident errors. The options are Enabled and Disabled.

Patrol Scrub Interval

Use this feature to set the hours needed for each Patrol Scrub cycle to complete
the task. Select 5 hours for the AMI BIOS to automatically set the time needed
for a Patrol Scrub cycle to complete the task. The default setting is 5 (hours).

Socket 0 Branch 0 Sparing/Socket 0 Branch 1 Sparing/ Socket 1 Branch
0 Sparing/Socket 1 Branch 1 Sparing/~/Socket 7 Branch 1 Sparing

Use this feature to enable or disable memory sparing support for the memory
modules specifi ed. The options are Disabled, DIMM Sparing Enable, and Rank
DIMM Enable.

Spare Copy Duration

Use this feature to set the hours needed for each Spare-Copy cycle to complete
the task. Select 5 hours for the AMI BIOS to automatically set the time needed
for spare copy to complete the task. The default setting is 5 (hours).

Mirroring/Migration

Select Mirror to support memory mirroring to enhance data security. Select
Migration to support memory Migration. The options are Disabled, Mirror, and
Migration.

Mirroring/Migration Error

This item indicates the Mirror/Migration Error threshold.

Memory Throttling

Select Enabled for closed loop memory thermal throttling support. The options
are Enabled and Disabled.

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Chapter 4: AMI BIOS

South Bridge

This submenu allows the user to confi gure the following South Bridge settings.

South Bridge Chipset Confi guration

This feature allows the user to confi gure the following South Bridge parameters.

SMBus Controller

Select Enabled to enable the SMBus (System Management Bus) controller to im­prove system management. The options are Enabled and Disabled.

GbE Controller

Select Enabled to enable the Gigabit PCI-Express controller to enhance PCI-E
performance. The options are Enabled and Disabled.

Wake On LAN from S5

Select Enabled to "wake up" the system when a network device installed in a LAN
port receives a signal while the system is in the S5 state. The options are Enabled
and Disabled.

Restore on AC Power Loss

Use this feature to set the power state after a power outage. Select Power-Off
for the system power to remain off after a power outage. Select Power-On for
the system power to be turned on after an outage. Select Last State to allow the
system to resume its last state before a power loss. The options are Power-On,

Power-Off and Last State.

Power Button Function

If this item is set to Instant_Off, the system will power off immediately as soon as
the user presses the power button. If set to 4_Second_Override, the system will
power off when the user presses the power button for 4 seconds or longer. The
options are Instant_Off and 4_Second_Override.

High precision Event Timer Confi guration

This feature allows the user to confi gure the following South Bridge parameters.

High Precision Event Timer

Select Enabled to activate the High Precision Event Timer (HPET) that produces
periodic interrupts at a much higher frequency than a Real-time Clock (RTC) does
in synchronizing multimedia streams, providing smooth playback and reducing the
dependency on other timestamp calculation devices, such as an x86 RDTSC In-

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X8OBN-F Platform User's Manual

struction embedded in the CPU. The High Precision Event Timer is used to replace
the 8254 Programmable Interval Timer. The options are Enabled and Disab led.

PCI-Express_Port Confi guration

This feature allows the user to confi gure the following PCI-E_port settings:

PCI-Express Port 1~ PCI-Express Port 5

Select Enabled to enable the PCI-E port specifi ed by the user. The options are
Enabled and Disabled.

USB Confi guration

This submenu allows the user to confi gure the following USB settings.

All USB Devices

Select Enabled to enable all USB devices in the system. The options are Enabled
and Disabled.

USB 2.0 (EHCI) Support

Select Enabled for USB 2.0 EHCI (Extended Host Controller Interface) support. The
options are Enabled and Disabled.

EHCI Controller 1/2

Select Enabled to enable the EHCI controller specifi ed by the user to enhance USB
communication. The options are Enabled and Disabled.

UHCI Controller1~UHCI Controller 6

Select Enabled to enable the UHCI (Universal Host Controller Interface) controller
specifi ed by the user to enhance USB1.0 communication. The options are Enabled
and Disabled.

USB Port0~USB Port11

Select Enabled to enable the USB port specifi ed by the user for USB communica-
tion. The options are Enabled and Disabled.

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Chapter 4: AMI BIOS

5-5 Server Management

This section allows the user to confi gure Server Management settings.

BMC Support

Select Enabled to enable the Baseboard Management Controller. The options are
Enabled and Disabled.

System Event Log

Enabling/Disabling Options

Use this feature to enable or disable the following System Event Log (SEL) set­tings.

SEL Components

Select Enabled to support all features of System Event Logging (SEL) during bootup.
The options are Enabled and Disabled.

Erasing Settings

This feature allows the user to decide when to erase a System Event Log.

Erase SEL
Select Yes to erase all System Event Logs. The options are Yes and No.

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X8OBN-F Platform User's Manual

When SEL is Full

This feature allows the user to decide what the system shall do when the System
Event Log is full. This feature is not available when the FRB-2 Timer is disabled.
The options are Do Nothing, Power Down and Reset.

Custom EFI Logging Options

Use this feature to customize the settings of Extensible_Firmware_Interface (EFI)
Logging between an operation system and the system platform fi rmware.

Log EFI Status Codes

Select Both to record the microcodes for both OS and the system platform fi rmware
during EFI logging. The default setting is Both.

Note: Be sure to reboot the computer for all the changes on the setting
indicated above to take effect.

BMC Network Confi guration

Use this feature to confi gure BMC (Baseboard Management Controller) Network
settings.

LAN Channel 1/ LAN Channel 2

Update IPMI LAN Confi guration

Select Yes to update the following IPMI settings at the next boot.

Confi guration Address

•

Use this feature to select the source or the parameter of an IP address for the
LAN channel specifi ed by the user. If Static is selected, you will need to know and
manually enter the IP address for the LAN channel specifi ed. If DHCP is selected,
BIOS will search for a DHCP (Dynamic Host Confi guration Protocol) server in the
network it is attached to, and request the next available IP address. If "Do Nothing"
is selected, BMC Network parameters will not be modifi ed when the BIOS Setup
Utility is in operation. The options are DHCP, Static, and Do nothing.

Current IP Address

•

Current Subnet Mask•

Current MAC Address•

Current Router IP Address•

Current Router MAC Address•

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