Supermicro X11DPX-T operation manual

X11DPX-T

USER’S MANUAL

Revision 1.1

The information in this user’s manual has been carefully reviewed and is believed to be accurate. The vendor assumes

!

no responsibility for any inaccuracies that may be contained in this document, and makes no commitment to update
or to keep current the information in this manual, or to notify any person or organization of the updates. Please Note:

For the most up-to-date version of this manual, please see our website at www.supermicro.com.

Super Micro Computer, Inc. ("Supermicro") reserves the right to make changes to the product described in this manual
at any time and without notice. This product, including software and documentation, is the property of Supermicro and/
or its licensors, and is supplied only under a license. Any use or reproduction of this product is not allowed, except
as expressly permitted by the terms of said license.

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OR DOCUMENTATION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, SUPER
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pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful
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to products containing CR (Manganese Dioxide) Lithium coin cells. “Perchlorate Material-special handling may apply.
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WARNING: This product can expose you to chemicals including
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to www.P65Warnings.ca.gov.

The products sold by Supermicro are not intended for and will not be used in life support systems, medical equipment,
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systems whose failure to perform be reasonably expected to result in signicant injury or loss of life or catastrophic

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Manual Revision 1.1

Release Date: October 08, 2020

Unless you request and receive written permission from Super Micro Computer, Inc., you may not copy any part of this

document. Information in this document is subject to change without notice. Other products and companies referred

to herein are trademarks or registered trademarks of their respective companies or mark holders.

Copyright © 2020 by Super Micro Computer, Inc.
All rights reserved.

Printed in the United States of America

Preface

Preface

About This Manual

This manual is written for system integrators, IT technicians, and knowledgeable end users.
It provides information for the installation and use of the X11DPX-T motherboard.

About This Motherboard

The X11DPX-T motherboard supports dual Intel® Xeon® Scalable-SP and 2nd Generation
Intel Xeon Scalable-SP processors (Socket P) with a TDP (Thermal Design Power) of up to
205W and three UPI (Ultra Path Interconnect) links of up to 10.4 GT/s (Note 1 below). With
the Intel C621 chipset built-in, this motherboard supports 3DS LRDIMM/RDIMM/LRDIMM/
NVDIMM DDR4 ECC memory of up to 2933*/2666 MHz in 16 slots (Note 2 below). It also
supports up to 2TB Intel Optane™ DC Persistent Memory in memory mode (2nd Gen Intel
Xeon Scalable-SP 82xx/62xx/52xx/4215 series processors only). The X11DPX-T provides
maximum performance, system cooling, and PCIe capacity. Also, this motherboard is optimized
for high-performance computing head-node, I/O intensive storage, security monitoring/DVR,
and industry applications. Please note that this motherboard is intended to be installed and
serviced by professional technicians only. For processor/memory updates, please refer to our
website at http://www.supermicro.com/products/.

Notes: 1. UPI/memory speeds are dependent on the processors installed in your sys-

tem. 2. Support for 2933MHz memory is dependent on the CPU SKU.

Manual organization

Chapter 1 describes the features, specications and performance of the motherboard, and

provides detailed information on the Intel C621 chipset.

Chapter 2 provides hardware installation instructions. Read this chapter when installing the

processor, memory modules, and other hardware components into the system.

Chapter 3 describes troubleshooting procedures for video, memory, and system setup stored

in the CMOS.

Chapter 4 includes an introduction to the BIOS, and provides detailed information on running

the CMOS Setup utility.

Appendix A provides BIOS Error Beep Codes.

Appendix B lists software program installation instructions.

Appendix C lists standardized warning statements in various languages.

Appendix D contains UEFI BIOS Recovery instructions.

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Super X11DPX-T User's Manual

Appendix E explains Intel VROC RAID settings.

Appendix F describes secure boot settings.

Appendix G states iSCSI settings.

Appendix H provides Network Interface Card (NIC) settings.

4

Contacting Supermicro

Headquarters

Address: Super Micro Computer, Inc.

980 Rock Ave.

San Jose, CA 95131 U.S.A.

Tel: [phone]

Fax: [phone]

Email: [e-mail] (General Information)

[e-mail] (Technical Support)

Website: www.supermicro.com

Europe

Contacting Supermicro

Address: Super Micro Computer B.V.

Het Sterrenbeeld 28, 5215 ML

's-Hertogenbosch, The Netherlands

Tel: [phone]

Fax: [phone]

Email: [e-mail] (General Information)

[e-mail] (Technical Support)

[e-mail] (Customer Support)

Website: www.supermicro.nl

Asia-Pacic

Address: Super Micro Computer, Inc.

3F, No. 150, Jian 1st Rd.

Zhonghe Dist., New Taipei City 235

Taiwan (R.O.C)

Tel: [phone]

Fax: [phone]

Email: [e-mail]

Website: www.supermicro.com.tw

5

Super X11DPX-T User's Manual

Table of Contents

Chapter 1 Introduction

Quick Reference ...............................................................................................................12

Quick Reference Table ......................................................................................................13

Motherboard Features .......................................................................................................15

1.1 Processor and Chipset Overview .......................................................................................19

1.2 Special Features ................................................................................................................20

Recovery from AC Power Loss .........................................................................................20

1.3 System Health Monitoring ..................................................................................................20

Onboard Voltage Monitors ................................................................................................21

Fan Status Monitor with Firmware Control .......................................................................21

Environmental Temperature Control .................................................................................21

System Resource Alert......................................................................................................21

1.4 ACPI Features ....................................................................................................................21

1.5 Power Supply .....................................................................................................................22

1.6 Advanced Power Management ..........................................................................................22

Intel Intelligent Power Node Manager (IPNM) ..................................................................22

Management Engine (ME) ................................................................................................22

1.7 Intel Optane DC Persistent Memory Overview ..................................................................22

Chapter 2 Installation

2.1 Static-Sensitive Devices .....................................................................................................23

Precautions .......................................................................................................................23

Unpacking .........................................................................................................................23

2.2 Motherboard Installation .....................................................................................................24

Location of Mounting Holes ..............................................................................................24

Tools Needed ....................................................................................................................24

Installing the Motherboard.................................................................................................25

2.3 Processor and Heatsink Installation ...................................................................................26

Intel Xeon Scalable-SP and 2nd Gen Intel Xeon Scalable-SP Processors .....................26

Overview of the Processor Socket Assembly ...................................................................27

Overview of the Processor Heatsink Module (PHM) ........................................................28

Attaching the Processor to the Narrow Processor Clip to Create the Processor Package

Assembly ...........................................................................................................................29

6

Table of Contents

Attaching the Processor Package Assembly to the Heatsink to Form the Processor

Heatsink Module (PHM) ....................................................................................................30

Preparing the CPU Socket for Installation ........................................................................31

Removing the Dust Cover from the CPU Socket .............................................................31

Installing the Processor Heatsink Module (PHM) ............................................................32

Removing the Processor Heatsink Module (PHM) from the Motherboard .......................33

2.4 Memory Support and Installation .......................................................................................34

Memory Support ................................................................................................................34

Memory Installation Sequence ..........................................................................................34

General Memory Population Requirements ......................................................................34

DDR4 Memory Support for Intel Xeon Scalable-SP Processors ......................................35

DDR4 Memory Support for 2nd Gen Intel Xeon Scalable-SP Processors .......................35

DIMM Population Guidelines for Optimal Performance ....................................................36

DIMM Population Table .....................................................................................................37

DIMM Installation ..............................................................................................................40

DIMM Removal .................................................................................................................40

2.5 Rear I/O Ports ....................................................................................................................41

2.6 Front Control Panel ............................................................................................................45

2.7 Connectors .........................................................................................................................49

Power Connections ...........................................................................................................49

Headers .............................................................................................................................50

2.8 Jumper Settings .................................................................................................................60

How Jumpers Work ...........................................................................................................60

2.9 LED Indicators ....................................................................................................................64

Chapter 3 Troubleshooting

3.1 Troubleshooting Procedures ..............................................................................................66

3.2 Technical Support Procedures ...........................................................................................70

3.3 Battery Removal and Installation .......................................................................................71

3.4 Frequently Asked Questions ..............................................................................................72

3.5 Returning Merchandise for Service ....................................................................................74

Chapter 4 UEFI BIOS

4.1 Introduction .........................................................................................................................75

4.2 Main Setup .........................................................................................................................76

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Super X11DPX-T User's Manual

4.3 Advanced Setup Congurations .........................................................................................78

4.4 Event Logs .......................................................................................................................157

4.5 IPMI ..................................................................................................................................159

4.6 Security .............................................................................................................................162

4.7 Boot ..................................................................................................................................165

4.8 Save & Exit .......................................................................................................................167

Appendix A BIOS Codes

Appendix B Software

B.1 Microsoft Windows OS Installation ...................................................................................171

B.2 Driver Installation ..............................................................................................................173

B.3 SuperDoctor 5 ..................................................................................................................174

B.4 IPMI ..................................................................................................................................175

B.5 Logging into the BMC (Baseboard Management Controller) ...........................................175

Appendix C Standardized Warning Statements

Appendix D UEFI BIOS Recovery

D.1 Overview ...........................................................................................................................179

D.2 Recovering the UEFI BIOS Image ...................................................................................179

D.3 Recovering the Main BIOS Block with a USB Device .....................................................180

Appendix E Conguring VROC RAID Settings

E.1 All Intel VMD Controllers Menu ........................................................................................184

E.2 Conguring RAID Settings ...............................................................................................188

E.3 Use of Journaling Drive ....................................................................................................204

Appendix F Secure Boot Settings

F.1 Boot mode select Feature ................................................................................................208

F.2 Secure Boot/ Secure Boot Mode/ CSM Support Features ..............................................209

F.3 Secure Boot Settings .......................................................................................................210

F.4 Key Management Settings ...............................................................................................213

Appendix G Conguring iSCSI Settings

G.1 PCIe/PCI/PnP Features ....................................................................................................230

G.2 Conguring iSCSI Settings ...............................................................................................233

Appendix H Conguring Network Interface Card (NIC) Settings

H.1 Network Interface Card (NIC) Settings ............................................................................252

8

Chapter 1: Introduction

Chapter 1

Introduction

Congratulations on purchasing your computer motherboard from an acknowledged leader
in the industry. Supermicro motherboards are designed with the utmost attention to detail to
provide you with the highest standards in quality and performance.

The X11DPX-T motherboard was designed to be used with a Supermicro-proprietary chassis
as an integrated server platform. It is not to be used as a stand-alone product and will not
be shipped independently in a retail box. No motherboard shipping package will be provided
in your shipment.

Important Links

For your system to work properly, please follow the links below to download all necessary
drivers/utilities and the user’s manual for your server.

• Supermicro product manuals: http://www.supermicro.com/support/manuals/

• Product drivers and utilities: http://www.supermicro.com/wftp

• Product safety info: http://www.supermicro.com/about/policies/safety_information.cfm

• A secure data deletion tool designed to fully erase all data from storage devices can be

found at our website: https://www.supermicro.com/about/policies/disclaimer.cfm?url=/

wftp/utility/Lot9_Secure_Data_Deletion_Utility/

• If you have any questions, please contact our support team at: support@supermicro.

com

This manual may be periodically updated without notice. Please check the Supermicro website

for possible updates to the manual revision level.

9

Super X11DPX-T User's Manual

Figure 1-1. X11DPX-T Motherboard Image

Note: All graphics shown in this manual were based upon the latest PCB revision

available at the time of publication of the manual. The motherboard you received may
or may not look exactly the same as the graphics shown in this manual.

10

Chapter 1: Introduction

FAN6

JIPMB1

JPTG1

COM2

JRK1

JWD1

JSEN1

JSTBY1

DESIGNED IN USA

FANC FAND

JPCIE1

JPCIE2

(CPU1 SLOT1 PCI-E 3.0 x8)

(CPU1 SLOT2 PCI-E 3.0 x16)

JNVI2C1

S-UM12

X11DPX-T

REV:1.01A

JPCIE4

JPCIE3

(CPU1 SLOT4 PCI-E 3.0 x16)

(CPU1 SLOT3 PCI-E 3.0 x8)

BIOS
LICENSE

Figure 1-2. X11DPX-T Motherboard Layout

(not drawn to scale)

JUIDB1

LED2

(UID)

BMC

JPCIE6

JPCIE5

(CPU2 SLOT6 PCI-E 3.0 x16)

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

JPCIE8

(CPU1 SLOT7 PCI-E 3.0 x8)

(CPU2 SLOT8 PCI-E 3.0 x16)

LEDBMC

LAN
CTRL

JNCSI1

JPCIE11

JNVI2C2

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPCIE10

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

(CPU2 SLOT10 PCI-E 3.0 x8)

P1-DIMMF1

P1-DIMME1

P1-DIMMD1

P1-DIMMD2

(UID-LED)

P2-DIMMC1

P2-DIMMB1

VGA

ALWAYS POPULATE DIMMx1 FIRST

P2-DIMMA1

P2-DIMMA2

LAN 2 LAN 1

FAN4

CPU2

USB 0/1

USB 4/5 (3.0)

IPMI_LAN

FAN3

P1-DIMMA2

P1-DIMMA1

COM1

ALWAYS POPULATE DIMMx1 FIRST

P2-DIMMD2

P1-DIMMB1

P1-DIMMC1

P2-DIMMF1

P2-DIMMD1

P2-DIMME1

S-SGPIO

JSD2

S-SATA1

USB 2/3

JL1

M.2 CONNECTOR

ALWAYS POPULATE DIMMx1 FIRST

JBT1

BT1

JSD1

PCH

S-SATA0

USB 6/7 (3.0)

FANB

IPMI CODE

I-SATA4~7 I-SATA0~3

JPME2

USB8 (3.0)

BAR CODE

SAN MAC
MAC CODE

JF1

JTPM1

LEDPWR

SP1

FANA

FAN2

Notes:

1. Components not documented are for internal testing only.

CPU1

ALWAYS POPULATE DIMMx1 FIRST

JPI2C1

JPWR4

JPWR3

JPWR2

JPWR1

FAN5

FAN1

2. Intel VMD is supported by CPU2 SLOT9 and CPU2 SLOT10. After you’ve enabled
VMD in the BIOS on a PCIe slot of your choice, this PCIe slot will be dedicated for
VMD use only, and it will no longer support any PCIe device. To re-activate this slot
for PCIe use, please disable VMD in the BIOS.

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Super X11DPX-T User's Manual

Quick Reference

COM2

JPTG1

JRK1

JIPMB1

CPU1 SLOT1

JWD1

JSEN1

JSTBY1

S-SGPIO

JSD2
JSD1

S-SATA1

USB 2/3
USB 6/7

(3.0)

CPU1 SLOT2

FANC

JNVI2C1

S-SATA0

JL1

FANB

DESIGNED IN USA

FAND

CPU1 SLOT3

CPU1 SLOT4

JBT1

PCH

IPMI CODE

I-SATA4~7

I-SATA0~3

X11DPX-T

REV:1.01A

CPU2 SLOT5

BIOS
LICENSE

USB8 (3.0)

CPU2 SLOT6

BMC

CPU1 SLOT7

M.2 CONNECTOR

BT1

BAR CODE

JPME2

SAN MAC
MAC CODE

JF1

LEDPWR

CPU2 SLOT8

CPU2 SLOT9

JNVI2C2

CPU2 SLOT10

CPU2 SLOT11

JTPM1

SP1

FAN2

FANA

LED2

LEDBMC

JNCSI1

LAN
CTRL

P1-DIMME1

P1-DIMMF1

P1-DIMMD2

P1-DIMMD1

JUIDB1

VGA

P2-DIMMB1

P2-DIMMC1

P2-DIMMA1

LAN2

FAN4

USB 4/5 (3.0)

P2-DIMMA2

CPU1

LAN1

USB 0/1

CPU2

IPMI_LAN

FAN3

P1-DIMMA1

P1-DIMMA2

P1-DIMMC1

P1-DIMMB1

COM1

FAN1

FAN5

P2-DIMMF1

P2-DIMME1

P2-DIMMD1

P2-DIMMD2

FAN6

JPI2C1

JPWR4

JPWR3

JPWR2

JPWR1

Notes:

• See Chapter 2 for detailed information on jumpers, I/O ports, and JF1 front panel connec-

tions.

• " " indicates the location of Pin 1.

• Components/jumpers/LED indicators not documented are reserved for internal testing only.

• Use only the correct type of onboard CMOS battery as specied by the manufacturer. Do

not install the onboard battery upside down to avoid possible explosion.

12

Chapter 1: Introduction

Quick Reference Table

Jumper Description Default Setting

JBT1 CMOS Clear Open (Normal)

JPME2 ME Manufacturing Mode Pins 1-2 (Normal)

JPTG1 Onboard 10Gb LAN1/LAN2 Enable/Disable Pins 1-2 (Enabled)

JWD1 Watch Dog Timer Reset Pins 1-2 (Reset)

Connector Description

BT1 Onboard Battery

COM1 COM Port (COM1) on the I/O Back Panel

COM2 COM Header

FAN1 ~ FAN6, FANA,

FANB, FANC, FAND

I-SATA0~3, I-SATA4~7 Intel PCH SATA 3.0 Ports (0~3, 4~7)

IPMI_LAN Dedicated IPMI LAN Port

JF1 Front Control Panel Header

JIPMB1 4-pin BMC External I2C Header (for an IPMI card)

JL1

JNCSI1 NC-SI Header for IPMI Support

JNVI2C1

JNVI2C2

JPI2C1 Power Supply SMBus I2C Header

JPWR1 24-pin ATX Power Connector

JPWR2, JPWR3 12V 8-pin CPU Power Connectors

JPWR4 12V 4-pin Power Connector

JRK1 (VROC) Intel VROC RAID Key Header for NVMe SSD

JSD1, JSD2 SATA DOM Power Connectors 1/2

JSEN1 Inlet Sensor Header

JSTBY1 Standby Power Connector

JTPM1 Trusted Platform Module/Port 80 connector

JUIDB1 UID (Unit Identier) Switch

System/CPU Fan Headers (FAN5: CPU1 Fan, FAN6: CPU2 Fan)

Chassis Intrusion Header (Note: Please connect a cable from the Chassis Intrusion header at JL1

to the chassis to receive an alert via IPMI.)

NVMe SMBus (I2C) headers used for PCIe hot-plug SMBus clock & data connections, and for

the NVMe Add-on Card on PCIe Slot9 (an SMCI-proprietary NVMe add-on card and cable are

required; available for a Supermicro complete system only)

NVMe SMBus (I2C) headers used for PCIe hot-plug SMBus clock & data connections, and for

the NVMe Add-on Card on PCIe Slot10 (an SMCI-proprietary NVMe add-on card and cable are

required; available for a Supermicro complete system only)

Note 1: Intel VMD is supported by CPU2 SLOT9 and CPU2 SLOT10.

Note 2: After you’ve enabled VMD in the BIOS on a PCIe slot of your choice, this PCIe

slot will be dedicated for VMD use only, and it will no longer support any PCIe device.
To re-activate this slot for PCIe use, please disable VMD in the BIOS.

13

Super X11DPX-T User's Manual

Connector Description

LAN1, LAN2 LAN Ports

M.2 CONNECTOR

S-SATA0, S-SATA1 SATA 3.0 Ports with Power-pin Built-in w/support of SuperDOM (Disk-On-Module)

S-SGPIO Serial Link General Purpose I/O Header

SP1 Internal Speaker/Buzzer

USB0, USB1 Back Panel USB 2.0 Ports

USB2, USB3 Front Access USB 2.0 Header

USB4, USB5 Back Panel USB 3.0 Ports

USB6, USB7 Front Access USB 3.0 Header

USB8 USB 3.0 Type A Header

VGA VGA Port (Back Panel)

LED Description Status

LED2 UID (Unit Identier) LED Solid Blue: Unit Identied

LEDBMC BMC Heartbeat LED Blinking Green: BMC Normal

LEDPWR Onboard Power LED Solid Green: Power On

PCIe M.2 Connector (small form factor devices and other portable devices for high speed NVMe

SSDs)

Note: To avoid causing interference with other components, please be sure to use an

add-on card that is fully compliant with the PCIe standard on a PCIe slot.

14

Chapter 1: Introduction

Motherboard Features

Motherboard Features

CPU

• Dual Intel Xeon Scalable-SP and 2nd Gen Intel Xeon Scalable-SP processors (Socket P) with three Intel UltraPath

Interconnect (UPI) links of up to 10.4 GT/s

Note: For the latest CPU/memory updates, please refer to our website at http://www.supermicro.com/products/

motherboard.

Memory

• Integrated memory controller embedded in the processor supports up to 4TB of 3DS Load Reduced DIMM (3DS LRDIMM),

3DS Registered DIMM (3DS RDIMM), or up to 2TB of Load Registered DIMM (LRDIMM), with speeds of 2933*/2666/24

00/2133/1866/1600/1333 MHz modules in 16 memory slots

Notes: 1. The memory capacity support will di󰀨er according to the processor SKUs. 2. Up to 2TB DCPMM memory

is supported (2nd Gen Intel Xeon Scalable-SP 82xx/62xx/52xx/4215 series processors only). 3. Support for 2933MHz

memory is dependent on the CPU SKU. 4. Refer to page 35 for detailed DDR4 memory support list.

DIMM Size

• Up to 256GB at 1.2V

Note 1: Memory speed support depends on the processors used in the system.

Note 2: For the latest CPU/memory updates, please refer to our website at http://www.supermicro.com/products/

motherboard.

Chipset

• Intel C621

Expansion Slots

• Two PCIe 3.0 x16 Slots (Slot4, Slot8)

• Two PCIe 3.0 x16 Slots (Slot2, Slot6), or four PCIe 3.0 x8 Slots (Slot1, Slot2, Slot5, Slot6)

• Two PCIe 3.0 x8 Slots (Slot9, Slot10)

• One PCIe 3.0 x4 in x8 Slot (Slot11)

Non Volatile Memory Express (NVMe) Slot

• One PCIe 3.0 x4 M.2 Slot

• M.2 Form Factor: 2280, 22110

• M.2 Key: M-Key

BaseBoard Management Controller (BMC)

• ASPEED AST2500 Baseboard Controller (BMC) supports IPMI 2.0

• One IPMI_dedicated_LAN located on the rear IO back panel

Graphics

• Graphics controller via ASPEED AST2500 BMC

Note: The table above is continued on the next page.

15

Super X11DPX-T User's Manual

Motherboard Features

I/O Devices

• Serial (COM) Port

• SATA 3.0

• RAID (PCH) • RAID 0/1/5/10 (RSTe 5.x)

Peripheral Devices

• Two USB 3.0 ports on the rear I/O panel (USB 4/5)

• One internal USB 3.0 header with two USB connections on the motherboard for front access (USB 6/7)

• One Type A USB 3.0 connector for front access (USB 8)

• Two USB 2.0 ports on the rear I/O panel (USB 0/1)

• One internal USB 2.0 header with two USB connections on the motherboard for front access (USB 2/3)

BIOS

• 32 MB SPI AMI BIOS

®

SM Flash UEFI BIOS

• ACPI 3.0/4.0, USB keyboard, Plug-and-Play (PnP), SPI dual/quad speed support, and SMBIOS 2.7 or later

• Two Fast UART 16550 ports (one port on the I/O back panel, one header on

the motherboard)

• Eight SATA 3.0 connections supported by Intel PCH (I-SATA 0-3, 4-7)

• Two SATA 3.0 ports with power-pin built-in, w/support of Supermicro SuperDOM

(S-SATA0/S-SATA1)

Power Management

• Main switch override mechanism

• Power-on mode for AC power recovery

• Intel Intelligent Power Node Manager 4.0 (Available when the Supermicro Power Manager [SPM] is installed and a special

power supply is used. See the note on page 22.)

• Management Engine (ME)

System Health Monitoring

• Onboard voltage monitoring for +3.3V, 3.3V standby, +5V, +5V standby, +12V, CPU core, memory, chipset, BMC, and

PCH voltages

• CPU System LED and control

• CPU Thermal Trip support

• Status monitor for on/o󰀨 control

• CPU Thermal Design Power (TDP) support of up to 205W (See Note 1 on the next page.)

Fan Control

• Fan status monitoring via IPMI

• Dual cooling zone

• Multi-speed fan control via onboard BMC

• Pulse Width Modulation (PWM) fan control

Note: The table above is continued on the next page.

16

Chapter 1: Introduction

Motherboard Features

System Management

• Trusted Platform Module (TPM) support

• PECI (Platform Environment Control Interface) 2.0 support

• UID (Unit Identication)/Remote UID

• System resource alert via SuperDoctor 5

• SuperDoctor 5, Watch Dog, NMI

• Chassis intrusion header and detection (Note: Please connect a cable from the Chassis Intrusion header at JL1 to the

chassis to receive an alert via IPMI.)

LED Indicators

• CPU/Overheating

• Fan Failure

• UID/remote UID

• HDD activity, LAN activity

Dimensions

• 15.12" (L) x 13.2" (W) (384 mm x 335.3 mm)

Note 1: The CPU maximum thermal design power (TDP) is subject to chassis and

heatsink cooling restrictions. For proper thermal management, please check the chas-

sis and heatsink specications for proper CPU TDP sizing.

Note 2: For IPMI conguration instructions, please refer to the Embedded IPMI Con­guration User's Guide available at http://www.supermicro.com/support/manuals/.

17

Super X11DPX-T User's Manual

JPCIE9 Slot 9

PCIE 3.0 x8

JPCIE10 Slot 10

PCIE 3.0 x8

JPCIE8
Slot 8

PCIE 3.0 x16

Figure 1-3.

System Block Diagram

16GB/s

x8 x8

x8

16GB/s

32GB/s

x16

16GB/s

16GB/s

x8

x4

8GB/s

JPCIE5 Slot 5

PCIE 3.0 x8

JPCIE6 Slot 6

PCIE 3.0 x16

JPCIE11
Slot 11

PCIE 3.0 x4

ASMedia Switch

ASM1480

VCCP1&2 12v

VR13
6+1 PHASE
205W

ASMedia Switch

ASM1480

#1

#1

LANE Reversal

32MB BIOS

SPI FLASH

DDR4 DIMM

DDR4 DIMM

M

F

#1

DDR4 DIMM

#1

DDR4 DIMM

JPCIE4
Slot 4

PCIE 3.0 x16

JPCIE7 Slot 7

PCIE 3.0 x8

JPCIE3 Slot 3

PCIE 3.0 x8

JPCIE2 Slot 2

PCIE 3.0 x16

JPCIE1 Slot 1

PCIE 3.0 x8

BMC SPI

MUX

PCH SPI

#1

#2

L

E

3 CH 3 CH

DDR4 DIMM

#1

#2

3 CH 3 CH

DDR4 DIMM

32GB/s

x16

16GB/s

x8

x8

16GB/s

16GB/s

x8

x8

EXT CONN

JNCSI1

16GB/s

32MB BMC

SPI FLASH

DDR4

VGA

K

PE2 PE1 DMIPE3

CPU 2

P2 P1 P0

UPI

P2 P0

CPU 1

NC-SI(RMII)

BMC

AST2500

HWM

UPI

UL1

UPI

P1

DMIPE3 PE2 PE1

8GB/s

10.4GT/s
Polarity Inversion

G

AD

PET [0,1,2,3]

PET [4,5,6,7]

DMI

PET9

SPI

PHY
RTL8211E

COM1

COM2

#1

#2

DDR4 DIMM

#2

#1

DDR4 DIMM

SATA Gen3 [0..3]

SATA Gen3 [4..7]

sSATA Gen3 [4..5]

PCH

USB2.0 [2..5]
USB2.0 [7..12]
USB3.0 [1..5]

USB2.0 [9] ESPI

#1

H J

#1

B C

x4x48GB/s

TPM Header

IPMI LAN
RJ45

DDR4 DIMM

DDR4 DIMM

8GB/s

I-SATA-0~3
IPASS CONN

I-SATA-4~7
IPASS CONN

S-SATA0
S-SATA1

port 4,5(USB2.0)

REAR USB0/1

#1

DDR4 DIMM

#1

DDR4 DIMM

port 1,2(USB3.0)
+
port 11,12(USB2.0)

REAR USB4/5 (3.0)

M.2 CONN
PCIE 3.0 x4

X550

port 3,4(USB3.0)
+
port 2,3(USB2.0)

HDR 2x10

USB6/7 (3.0) USB2/3

JLAN1

10G

RJ45

10G

JLAN2
RJ45

NC-SI

To BMC RMII port

port 8,9(USB2.0)

HDR 2x5

port 5(USB3.0)
+
port 10(USB2.0)

TYPE A USB8 (3.0)

Note: This is a general block diagram and may not exactly represent the features on

your motherboard. See the previous pages for the actual specications of your moth­erboard.

18

Chapter 1: Introduction

1.1 Processor and Chipset Overview

Built upon the functionality and capability of the Intel Xeon Scalable-SP series and 2nd
Gen Intel Xeon Scalable-SP series processors with the Intel C621 chipset, the X11DPX-T

motherboard provides system performance, power e󰀩ciency, and feature sets to address the

needs of next-generation computer users. This motherboard is ideal for high-performance
computing, I/O intensive storage and application, and industry embedded appliances.

The Intel C621 chipset provides Enterprise SMbus support and includes the following features:

• DDR4 288-pin memory support on Socket P

• Support for MCTP Protocol

• Support for Management Engine (ME)

• Support of SMBus speeds of up to 400KHz for BMC connectivity

• Improved I/O capabilities to high-storage-capacity congurations

• SPI enhancements

• Intel Node Manager 4.0 for advanced power monitoring, capping, and management for

BMC enhancement

• The BMC supports remote management, virtualization, and the security package for en-

terprise platforms

Note: Node Manager 4.0 support is dependent on the power supply used in the system.

Features Supported by Intel Xeon Scalable-SP Processors

Intel Xeon Scalable-SP processors support the following features:

• Intel AVX-512 instruction support to handle complex workloads

• 1.5x memory bandwidth increased to 6 channels

• Hot plug and enclosure management with Intel Volume Management Device (Intel VMD)

• Rich set of available IOs with increased PCIe lanes (48 lanes)

19

Super X11DPX-T User's Manual

New features supported by 2nd Gen Intel Xeon Scalable-SP Series Processors

2nd Generation Intel Xeon Scalable-SP processors support the following features:

• Higher performance for a wider range of workloads with per-core performance increase

• Support of Optane DC Persistent Memory (DCPMM) with a󰀨ordable, persistent, and

large capacity (Refer to Section 1.7 for details.)

• Up to 2933 MHz memory supported

• Vector Neural Network Instruction (VNNI) support for Accelerate Deep Learning & Arti-

cial Intelligence (AI) workloads

• Speed Select Technology provides multiple CPU proles that can be set in the BIOS.

(This feature is available on select CPU SKUs).

• Seamless hardware security mitigations & performance/frequency exibility

Note: Support for 2933MHz memory and DCPMM memory is dependent on the CPU

SKU.

1.2 Special Features

This section describes the health monitoring features of the X11DPX-T motherboard. The
motherboard has an onboard ASPEED AST2500 Baseboard Management Controller (BMC)
that supports system health monitoring.

Recovery from AC Power Loss

The Basic I/O System (BIOS) provides a setting that determines how the system will respond
when AC power is lost and then restored to the system. You can choose for the system to

remain powered o󰀨 (in which case you must press the power switch to turn it back on), or

for it to automatically return to the power-on state. See the Advanced BIOS Setup section
for this setting. The default setting is Last State.

1.3 System Health Monitoring

This section describes the health monitoring features of the X11DPX-T motherboard. The
motherboard has an onboard Baseboard Management Controller (BMC) chip that supports
system health monitoring.

20

Chapter 1: Introduction

Onboard Voltage Monitors

The onboard voltage monitor will continuously scan crucial voltage levels. Once a voltage
becomes unstable, it will give a warning or send an error message to the IPMI WebGUI and
IPMIView. Real time readings of these voltage levels are all displayed in IPMI.

Fan Status Monitor with Firmware Control

The system health monitor embedded in the BMC chip can check the RPM status of the
cooling fans. The CPU and chassis fans are controlled via lPMI.

Environmental Temperature Control

System Health sensors in the BMC monitor the temperatures and voltage settings of onboard
processors and the system in real time via the IPMI interface. Whenever the temperature

of the CPU or the system exceeds the manufacturer-dened threshold, system/CPU cooling
fans will increase fan spin to provide better air ow to prevent the CPU or the system from

overheating.

Note: To avoid possible system overheating, please be sure to provide adequate air-

ow to your system.

System Resource Alert

This feature is available when used with SuperDoctor® 5. SuperDoctor 5 is used to notify the

user of certain system events. For example, you can congure SuperDoctor 5 to provide you

with warnings when the system temperature, CPU temperatures, voltages and fan speeds

go beyond a predened range.

1.4 ACPI Features

ACPI stands for Advanced Conguration and Power Interface. The ACPI specication denes
a exible and abstract hardware interface that provides a standard way to integrate power

management features throughout a computer system including its hardware, operating system

and application software. This enables the system to automatically turn on and o󰀨 peripherals

such as network cards, hard disk drives and printers.

In addition to enabling operating system-directed power management, ACPI also provides a
generic system event mechanism for Plug and Play and an operating system-independent

interface for conguration control. ACPI leverages the Plug and Play BIOS data structures

while providing a processor architecture-independent implementation that is compatible with
appropriate Windows operating systems. For detailed information on OS support, please refer
to our website at www.supermicro.com.

21

Super X11DPX-T User's Manual

1.5 Power Supply

As with all computer products, a stable power source is necessary for proper and reliable
operation. It is even more important for processors that have high CPU clock rates.

1.6 Advanced Power Management

The following new advanced power management features are supported by the motherboard.

Intel Intelligent Power Node Manager (IPNM)

Intel's Intelligent Power Node Manager (IPNM) provides your system with real-time thermal
control and power management for maximum energy e󰀩ciency. Although IPNM Specication

Version 2.0/3.0 is supported by the BMC (Baseboard Management Controller), your system

must also have IPNM-compatible Management Engine (ME) rmware installed to use this

feature.

Note: Support for IPNM 2.0/3.0 support is dependent on the power supply used in the

system.

Management Engine (ME)

The Management Engine, which is an ARC controller embedded in the IOH (I/O Hub), provides

Server Platform Services (SPS) to your system. The services provided by SPS are di󰀨erent

from those provided by the ME on client platforms.

1.7 Intel Optane DC Persistent Memory Overview

2nd Generation Intel Xeon Scalable-SP processors support new DCPMM (Optane™ DC

Persistent Memory Modules) technology that o󰀨ers data persistence with higher capacity than

existing memory modules and lower latency than NVMe SSDs. DCPMM memory provides

hyper-speed storage capability for high performance computing platforms with exible
conguration options.

22

Chapter 2: Installation

Chapter 2

Installation

2.1 Static-Sensitive Devices

Electrostatic Discharge (ESD) can damage electronic com ponents. To avoid damaging
your motherboard and your system, it is important to handle it very carefully. The following

measures are generally su󰀩cient to protect your equipment from ESD.

Precautions

• Use a grounded wrist strap designed to prevent static discharge.

• Touch a grounded metal object before removing the motherboard from the antistatic bag.

• Handle the motherboard by its edges only; do not touch its components, peripheral chips,

memory modules or gold contacts.

• When handling chips or modules, avoid touching their pins.

• Put the motherboard and peripherals back into their antistatic bags when not in use.

• For grounding purposes, make sure that your chassis provides excellent conductivity be-

tween the power supply, the case, the mounting fasteners and the motherboard.

• Use only the correct type of CMOS onboard battery as specied by the manufacturer. Do

not install the CMOS battery upside down, which may result in a possible explosion.

Unpacking

The motherboard is shipped in antistatic packaging to avoid static damage. When unpacking
the motherboard, make sure that the person handling it is static protected.

23

Super X11DPX-T User's Manual

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

CPU2

CPU1

BIOS
LICENSE

SAN MAC
MAC CODE

BAR CODE

PCH

IPMI CODE

BMC

2.2 Motherboard Installation

All motherboards have standard mounting holes to t di󰀨erent types of chassis. Make sure

that the locations of all the mounting holes for both the motherboard and the chassis match.
Although a chassis may have both plastic and metal mounting fasteners, metal ones are
highly recommended because they ground the motherboard to the chassis. Make sure that

the metal stando󰀨s click in or are screwed in tightly.

Tools Needed

Philips
Screwdriver (1)

Location of Mounting Holes

Philips Screws (14)

Stando󰀨s (14)

Only if Needed

Notes: 1. To avoid damaging the motherboard and its components, please do not use

a force greater than 8 lb/inch on each mounting screw during motherboard installation.

2. Some components are very close to the mounting holes. Please take precautionary
measures to avoid damaging these components when installing the motherboard to
the chassis.

24

Chapter 2: Installation

Installing the Motherboard

1. Install the I/O shield into the back of the chassis if needed.

2. Locate the mounting holes on the motherboard. See the previous page for the location.

3. Locate the matching mounting holes on the chassis. Align the mounting holes on the
motherboard against the mounting holes on the chassis.

4. Install stando󰀨s in the chassis as needed.

5. Install the motherboard into the chassis carefully to avoid damaging other motherboard
components.

6. Using the Phillips screwdriver, insert a Phillips head #6 screw into a mounting hole on
the motherboard and its matching mounting hole on the chassis.

7. Repeat Step 6 to insert Pan head #6 screws into all mounting holes.

8. Make sure that the motherboard is securely placed in the chassis.

Note: Images displayed in this manual are for illustration only. Your chassis or compo-

nents might look di󰀨erent from those shown in this manual.

25

Super X11DPX-T User's Manual

2.3 Processor and Heatsink Installation

Warning: When handling the processor package, avoid placing direct pressure on the label

area of the CPU or CPU socket. Also, improper CPU installation or socket misalignment can
cause serious damage to the CPU or motherboard which may result in RMA repairs. Please
read and follow all instructions thoroughly before installing your CPU and heatsink.

Notes:

• Always connect the power cord last, and always remove it before adding, removing, or

changing any hardware components. Please note that the processor and heatsink should

be assembled together rst to form the Processor Heatsink Module (PHM), and then install

the entire PHM into the CPU socket.

• When you receive a motherboard without a processor pre-installed, make sure that the

plastic CPU socket cap is in place and that none of the socket pins are bent; otherwise,
contact your retailer immediately.

• Refer to the Supermicro website for updates on CPU support.

• Please follow the instructions given in the ESD Warning section on the rst page of this

chapter before handling, installing, or removing system components.

Intel Xeon Scalable-SP and 2nd Gen Intel Xeon Scalable-SP
Processors

Intel Xeon Scalable-SP and 2nd Gen Intel Xeon Scalable-SP Processor

Note: All graphics, drawings, and pictures shown in this manual are for illustration only.

The components that came with your machine may or may not look exactly the same
as those shown in this manual.

26

Chapter 2: Installation

Overview of the Processor Socket Assembly

The processor socket assembly contains 1) Intel Xeon Scalable-SP or 2nd Generation Intel
Xeon Scalable-SP processor, 2) the narrow processor clip, 3) the dust cover, and 4) the CPU
socket.

1. Intel Processor

2. Narrow processor clip (the plastic processor package carrier used for the CPU)

3. Dust Cover

4. CPU Socket

Note: Be sure to cover the CPU socket with the dust cover when the CPU is not installed.

27

Super X11DPX-T User's Manual

Overview of the Processor Heatsink Module (PHM)

The Processor Heatsink Module (PHM) contains 1) a heatsink, 2) a narrow processor clip,
and 3) Intel Xeon Scalable-SP or 2nd Generation Intel Xeon Scalable-SP processor.

1. Heatsink

2. Narrow processor clip

3. Intel Processor

Processor Heatsink Module (PHM)

(Bottom View)

28

Chapter 2: Installation

A

Allow Notch B to
latch on to CPU

Attaching the Processor to the Narrow Processor Clip to Create
the Processor Package Assembly

To properly install the CPU into the narrow processor clip, please follow the steps below.

1. Locate pin 1 (notch A), which is the triangle located on the top of the narrow processor
clip. Also locate notch B and notch C on the processor clip.

2. Locate pin 1 (notch A), which is the triangle on the substrate of the CPU. Also, locate
notch B and notch C on the CPU as shown below.

3. Align pin 1 (the triangle on the substrate) of the CPU with pin 1 (the triangle) of
the narrow processor clip. Once they are aligned, carefully insert the CPU into the
processor clip by sliding notch B of the CPU into notch B of the processor clip, and

sliding notch C of the CPU into notch C of the processor clip.

4. Examine all corners of the CPU to ensure that it is properly seated on the processor
clip. Once the CPU is securely attached to the processor clip, the processor package
assembly is created.

Note: Please exercise extreme caution when handling the CPU. Do not touch the CPU

LGA-lands to avoid damaging the LGA-lands or the CPU. Be sure to wear ESD gloves
when handling components.

CPU (Upside Down)
w/CPU LGA Lands up

Align Notch B of the CPU
and Notch B of the Processor Clip

Align CPU Pin 1

C

Align Notch C of the CPU
and Notch C of the Processor Clip

B

Allow Notch C to
latch on to CPU

A

Pin 1

C

C

B

CPU/Heatsink Package
(Upside Down)

B

A

Processor Package Carrier (w/CPU mounted

on the Processor Clip)

29

Super X11DPX-T User's Manual

Attaching the Processor Package Assembly to the Heatsink to
Form the Processor Heatsink Module (PHM)

After you have made a processor package assembly by following the instructions on the
previous page, please follow the steps below to mount the processor package assembly onto
the heatsink to create the Processor Heatsink Module (PHM).

1. Locate "1" on the heatsink label and the triangular corner next to it on the heatsink.

With your index nger pressing against the screw at this triangular corner, carefully hold

and turn the heatsink upside down with the thermal-grease side facing up. Remove the

protective thermal lm if present, and apply the proper amount of the thermal grease

as needed. (Skip this step if you have a new heatsink because the necessary thermal
grease is pre-applied in the factory.)

2. Holding the processor package assembly at the center edge, turn it upside down. With
the thermal-grease side facing up, locate the hollow triangle located at the corner of the
processor carrier assembly ("a" in the graphic). Note a larger hole and plastic mounting
clicks located next to the hollow triangle. Also locate another set of mounting clicks and
a larger hole at the diagonal corner of the same (reverse) side of the processor carrier
assembly ("b" in the graphic).

3. With the back of heatsink and
the reverse side of the processor
package assembly facing up,
align the triangular corner on
the heatsink ("A" in the graphic)
against the mounting clips next
to the hollow triangle ("a") on the
processor package assembly.

4. Also align the triangular corner
("B") at the diagonal side of the
heatsink with the corresponding
clips on the processor package
assembly ("b").

5. Once the mounting clips on the
processor package assembly
are properly aligned with the
corresponding holes on the back
of heatsink, securely attach
the heatsink to the processor
package assembly by snapping the
mounting clips at the proper places
on the heatsink to create the
processor heatsink module (PHM).

Triangle on the CPU

Triangle on the
Processor Clip

On Locations (A, B), the notches
snap onto the heatsink’s sides

Non-Fabric CPU and Processor Clip

(Upside Down)

b

d

B

a

D

Heatsink

(Upside Down)

A

On Locations of (C, D), the notches

snap onto the heat sink’s

B

D

A

Make sure Mounting

Notches snap into place

c

C

mounting holes

C

30

Chapter 2: Installation

Preparing the CPU Socket for Installation

This motherboard comes with the CPU socket pre-assembled in the factory. The CPU socket
contains 1) a dust cover, 2) a socket bracket, 3) the CPU socket, and 4) a back plate. These
components are pre-installed on the motherboard before shipping.

CPU Socket w/Dust Cover On

Removing the Dust Cover from the CPU Socket

Remove the dust cover from the CPU socket, exposing the CPU socket and socket pins as
shown on the illustration below.

Note: Do not touch the socket pins to avoid damaging them, causing the CPU to mal-

function.

Dusk Cover

Remove the dust cover from

the CPU socket. Do not

touch the socket pins!

CPU Socket

31

Socket Pins

Super X11DPX-T User's Manual

Installing the Processor Heatsink Module (PHM)

1. Once you have assembled the processor heatsink module (PHM) by following the
instructions listed on page 29 or page 30, you are ready to install the processor heatsink
module (PHM) into the CPU socket on the motherboard. To install the PHM into the
CPU socket, follow the instructions below.

2. Locate the triangle (pin 1) on the CPU socket, and locate the triangle (pin 1) at the

corner of the PHM that is closest to "1." (If you have di󰀩culty locating pin 1 of the PHM,

turn the PHM upside down. With the LGA-lands side facing up, you will note the hollow
triangle located next to a screw at the corner. Turn the PHM right side up, and you will
see a triangle marked on the processor clip at the same corner of hollow triangle.)

3. Carefully align pin 1 (the triangle) on the PHM against pin 1 (the triangle) on the CPU
socket.

4. Once they are properly aligned, insert the two diagonal oval holes on the heatsink into
the guiding posts.

5. Using a T30 Torx-bit screwdriver, install four screws into the mounting holes on the
socket to securely attach the PHM onto the motherboard starting with the screw marked

"1" (in the sequence of 1, 2, 3, and 4).

Note: Do not use excessive force when tightening the screws to avoid damaging the

LGA-lands and the processor.

Oval C

Use a torque

Oval D

Large Guiding Post

T30 Torx Driver

of 12 lbf·in

#4

#1

#2

Small Guiding Post

Printed Triangle

Mounting the Processor Heatsink Module

into the CPU socket (on the motherboard)

#3

Tighten the screws in the

sequence of 1, 2, 3, 4 (top 3 quarter view)

32

Chapter 2: Installation

Removing the Processor Heatsink Module (PHM) from the
Motherboard

Before removing the processor heatsink module (PHM), unplug power cord from the power
outlet.

1. Using a T30 Torx-bit screwdriver, turn the screws on the PHM counterclockwise to

loosen them from the socket, starting with screw marked #4 (in the sequence of 4, 3, 2,

1).

2. After all four screws are removed, wiggle the PHM gently and pull it up to remove it
from the socket.

Note: To properly remove the processor heatsink module, be sure to loosen and remove

the screws on the PHM in the sequence of 4, 3, 2, 1 as shown below.

#1

Removing the screws in
the sequence of 4, 3, 2, 1

#4

#2

#3

Printed Triangle on Motherboard

CPU Socket

After removing the screws,

lift the Processor Heatsink
Module off the CPU socket.

33

Super X11DPX-T User's Manual

2.4 Memory Support and Installation

Note: Check the Supermicro website for recommended memory modules. Exercise

extreme care when installing or removing DIMM modules to prevent any damage.

Memory Support

The X11DPX-T supports up to 4TB of 3DS Load Reduced DIMM (3DS LRDIMM), 3DS
Registered DIMM (3DS RDIMM), or up to 2TB of Load Registered DIMM (LRDIMM), with
speeds of 2933*/2666/2400/2133/1866/1600/1333 MHz modules in 16 memory slots.
Populating these DIMM modules with a pair of memory modules of the same type and size
will result in interleaved memory, which will improve memory performance.

Notes: 1. Be sure to use the memory modules of the same type and speed on the

motherboard. Mixing of memory modules of di󰀨erent types and speeds is not allowed.

2. When installing memory modules, be sure to populate the rst DIMM module on the
blue memory slot, which is the rst memory slot of a memory channel, and then populate
the second DIMM in the black slot if 2DPC memory conguration is used. 3. Memory

speed is dependent on the type of processors used in your system. 4. Populating DDR4

memory modules in a two-DIMMs per-channel (2DPC) conguration on this motherboard
will a󰀨ect memory bandwidth and performance. 5. Unbalanced memory conguration is

not recommended. 6. Support for 2933MHz memory is dependent on the CPU SKU. 7.
The memory capacity support will di󰀨er according to the processor SKUs. 8. 16Gb-based
memory modules are supported by 2nd Gen Intel Xeon Scalable-SP processors only.

Memory Installation Sequence

Memory modules for this motherboard are populated using the "Fill First" method. The blue

memory slot of each channel is considered the "rst DIMM module" of the channel, and the

black slot, the second module of the channel. When installing memory modules, be sure to

populate the blue memory slots rst and then populate the black slots.

General Memory Population Requirements

1. Be sure to use the memory modules of the same type and speed on the motherboard.

Mixing of memory modules of di󰀨erent types and speeds is not allowed.

2. Using unbalanced memory topology such as populating two DIMMs in one channel while
populating one DIMM in another channel on the same motherboard will result in reduced
memory performance.

3. Populating memory slots with a pair of DIMM modules of the same type and size will
result in interleaved memory, which will improve memory performance.

34

Chapter 2: Installation

DDR4 Memory Support for Intel Xeon Scalable-SP Processors

DDR4 Memory Support

DIMM Capacity (GB)

Type

RDIMM SRx4 4GB 8GB 2666 2666 2666

RDIMM SRx8 8GB 16GB 2666 2666 2666

RDIMM DRx8 8GB 16GB 2666 2666 2666

RDIMM DRx4 16GB 32GB 2666 2666 2666

RDIMM 3Ds QRX4 N/A 2H-64GB 2666 2666 2666

RDIMM 3Ds 8RX4 N/A 4H-128GB 2666 2666 2666

LRDIMM QRx4 32GB 64GB 2666 2666 2666

LRDIMM 3Ds QRX4 N/A 2H-64GB 2666 2666 2666

LRDIMM 3Ds 8Rx4 N/A 4H-128GB 2666 2666 2666

Ranks Per DIMM

& Data Width

DRAM Density

4Gb* 8Gb 1.2 V 1.2 V 1.2 V

Speed (MT/s); Voltage (V); Slots Per Channel (SPC) and DIMMs Per Channel

1 Slot Per Channel 2 Slots Per Channel

1DPC (1-DIMM

Per Channel)

(DPC)

1DPC (1-DIMM Per

Channel)

2DPC (2-DIMM Per

Channel)

DDR4 Memory Support for 2nd Gen Intel Xeon Scalable-SP

Processors

DDR4 Memory Support

Ranks

Type

RDIMM SRx4 4GB 8GB 16GB 2933 2933 2933

RDIMM SRx8 8GB 16GB 32GB 2933 2933 2933

RDIMM DRx8 8GB 16GB 32GB 2933 2933 2933

RDIMM DRx4 16GB 32GB 64GB 2933 2933 2933

RDIMM 3Ds QRX4 N/A 2H-64GB 2H-128GB 2933 2933 2933

RDIMM 3Ds 8RX4 N/A 4H-128GB 4H-256GB 2933 2933 2933

LRDIMM QRx4 32GB 64GB 128GB 2933 2933 2933

LRDIMM 3Ds QRX4 N/A 2H-64GB 2H-128GB 2933 2933 2933

LRDIMM 3Ds 8Rx4 N/A 4H-128GB 4H-256GB 2933 2933 2933

Per DIMM

&

Data Width

DIMM Capacity (GB)

DRAM Density

4Gb* 8Gb 16Gb 1.2 V 1.2 V 1.2 V

Speed (MT/s); Voltage (V); Slots Per Channel (SPC) and DIMMs Per Channel

1 Slot Per Channel 2 Slots Per Channel

1DPC (1-DIMM

Per Channel)

(DPC)

1DPC (1-DIMM

Per Channel)

2DPC (2-DIMM

Per Channel)

Notes: 1. 2933 MHz memory support in two-DIMMs per-channel (2DPC) conguration

can be achieved by using memory purchased from Supermicro. 2. Support for 2933MHz
memory is dependent on the CPU SKU. 3. 16Gb-based memory modules are supported
by 2nd Gen Intel Xeon Scalable-SP processors only.

35

Super X11DPX-T User's Manual

DIMM Population Guidelines for Optimal Performance

For optimal memory performance, follow the instructions listed in the tables below when
populating memory modules.

Key Parameters for DIMM Conguration

Key Parameters for DIMM Congurations

Parameters Possible Values

Number of Channels 1, 2, 3, 4, 5, or 6

Number of DIMMs per Channel 1DPC (1 DIMM Per Channel) or 2DPC (2 DIMMs Per Channel)

DIMM Type RDIMM (w/ECC), 3DS RDIMM, LRDIMM, 3DS LRDIMM

DIMM Construction non-3DS RDIMM Raw Cards: A/B (2Rx4), C (1Rx4), D (1Rx8), E (2Rx8)

DIMM Mixing Guidelines

3DS RDIMM Raw Cards: A/B (4Rx4)

non-3DS LRDIMM Raw Cards: D/E (4Rx4)

3DS LRDIMM Raw Cards: A/B (8Rx4)

General DIMM Mixing Guidelines

DIMM Mixing Rules

• All DIMMs must be all DDR4 DIMMs.

• x4 and x8 DIMMs can be mixed in the same channel.

• Mixing of LRDIMMs and RDIMMs is not allowed in the same channel, across di󰀨erent channels, and across di󰀨erent

sockets.

• Mixing of non-3DS and 3DS LRDIMM is not allowed in the same channel, across di󰀨erent channels, and across

di󰀨erent sockets.

Mixing of DIMM Types within a Channel

DIMM Types

RDIMM Allowed Not Allowed Not Allowed

LRDIMM Not Allowed Allowed Not Allowed

3DS LRDIMM Not Allowed Not Allowed Allowed

RDIMM LRDIMM 3DS LRDIMM

36

Chapter 2: Installation

DIMM Population Table

Note: Unbalanced memory conguration decreases memory performance and is not

recommended for Supermicro motherboards.

Memory Population Table for the Motherboard Using Intel Xeon Scalable-SP
and 2nd Gen Intel Xeon Scalable-SP Processors

Memory Population Table for the X11DP Motherboard w/16 DIMM Slots Onboard

When 1 CPU is used: Memory Population Sequence

1 CPU & 1 DIMM CPU1: P1-DIMMA1

1 CPU & 2 DIMMs CPU1: P1-DIMMA1/P1-DIMMD1

1 CPU & 3 DIMMs CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1

1 CPU & 4 DIMMs CPU1: P1-DIMMB1/P1-DIMMA1/P1-DIMMD1/P1-DIMME1

1 CPU & 5 DIMMs

(Unbalanced: not recommended)

1 CPU & 6 DIMM CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMD1/P1-DIMME1/P1-DIMMF1

1 CPU & 7 DIMMs

(Unbalanced: not recommended)

1 CPU & 8 DIMMs

(Unbalanced: not recommended)

When 2 CPUs are used: Memory Population Sequence

2 CPUs & 2 DIMMs

2 CPUs & 4 DIMMs

2 CPUs & 6 DIMMs

2 CPUs & 8 DIMMs

2 CPUs & 10 DIMMs

2 CPUs & 12 DIMMs

2 CPUs & 14 DIMMs

(Unbalanced: not recommended)

2 CPUs & 16 DIMMs

(Unbalanced: not recommended)

CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMD1/P1-DIMME1

CPU1:P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMA2/P1-DIMMD1/P1-DIMME1/P1-DIMMF1

CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMA2/P1-DIMMD2/P1-DIMMD1/P1-DIMME1/P1-DIMMF1

CPU1: P1-DIMMA1
CPU2: P2-DIMMA1

CPU1: P1-DIMMA1/P1-DIMMD1
CPU2: P2-DIMMA1/P2-DIMMD1

CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1
CPU2: P2-DIMMC1/P2-DIMMB1/P2-DIMMA1

CPU1: P1-DIMMB1/P1-DIMMA1/P1-DIMMD1/P1-DIMME1
CPU2: P2-DIMMB1/P2-DIMMA1/P2-DIMMD1/P2-DIMME1

CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMD1/P1-DIMME1/P1-DIMMF1
CPU2: P2-DIMMB1/P2-DIMMA1/P2-DIMMD1/P2-DIMME1

CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMD1/P1-DIMME1/P1-DIMMF1
CPU2: P2-DIMMC1/P2-DIMMB1/P2-DIMMA1/P2-DIMMD1/P2-DIMME1/P2-DIMMF1

CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMA2/P1-DIMMD1/P1-DIMME1/P1-DIMMF1
CPU2: P2-DIMMC1/P2-DIMMB1/P2-DIMMA1/P2-DIMMA2/P2-DIMMD1/P2-DIMME1/P2-DIMMF1

CPU1: P1-DIMMC1/P1-DIMMB1/P1-DIMMA1/P1-DIMMA2/P1-DIMMD2/P1-DIMMD1/P1-DIMME1/P1-DIMMF1
CPU2: P2-DIMMC1/P2-DIMMB1/P2-DIMMA1/P2-DIMMA2/P2-DIMMD2/P2-DIMMD1/P2-DIMME1/P2-DIMMF1

Note: Please refer to the Memory Conguration User Guide for the X11 UP/DP/MP

Motherboards that is posted on our website for detailed information on memory sup­port for this motherboard.

37

Super X11DPX-T User's Manual

Memory Rank Sparing Tables

Dual Rank Memory Rank Sparing (16GB DIMM)

Memory Population Total RAM Detected

A1 8GB 8GB

A1+B1 16GB 16GB

A1+B1+C1 24GB 24GB

A1+B1+C1+D1 32GB 32GB

A1+B1+C1+D1+E1 40GB 40GB

A1+B1+C1+D1+E1+F1 49GB 49GB

A1+A2+B1+C1+D1+D2+E1+F1 80GB 64GB

Quad Rank Memory Rank Sparing (64GB DIMM)

Memory Population Total RAM Detected

A1 48GB 32GB

A1+B1 96GB 64GB

A1+B1+C1 144GB 96GB

A1+B1+C1+D1 192GB 128GB

A1+B1+C1+D1+E1 240GB 160GB

A1+B1+C1+D1+E1+F1 288GB 192GB

A1+A2+B1+C1+D1+D2+E1+F1 416GB 320GB

One Rank Conguration Two Rank Conguration

One Rank Conguration Two Rank Conguration

38

Chapter 2: Installation

DCPMM Memory Population Tables for 2nd Gen Intel Xeon Scalable-SP
Processors

Note: Only 2nd Gen Intel Xeon Scalable-SP (82xx/62xx/52xx/4215 series) processors

support DCPMM memory.

Symmetric Population within 1 CPU Socket

Modes P1-DIMMF1 P1-DIMME1 P1-DIMMD1 P1-DIMMD2 P1-DIMMA2 P1-DIMMA1 P1-DIMMB1 P1-DIMMC1 Channel Cong.

AD DRAM1 DRAM1 DRAM1 DCPMM DCPMM DRAM1 DRAM1 DRAM1 2-1-1

MM DRAM2 DRAM2 DRAM2 DCPMM DCPMM DRAM2 DRAM2 DRAM2 2-1-1

AD + MM DRAM3 DRAM3 DRAM3 DCPMM DCPMM DRAM3 DRAM3 DRAM3 2-1-1

AD DCPMM DRAM1 DRAM1 - - DRAM1 DRAM1 DCPMM 1-1-1

MM DCPMM DRAM1 DRAM1 - - DRAM1 DRAM1 DCPMM 1-1-1

AD + MM DCPMM DRAM3 DRAM3 - - DRAM3 DRAM3 DCPMM 1-1-1

Asymmetric Population within 1 CPU Socket

Modes P1-DIMMF1 P1-DIMME1 P1-DIMMD1 P1-DIMMD2 P1-DIMMA2 P1-DIMMA1 P1-DIMMB1 P1-DIMMC1 Channel Cong.

AD DRAM1 DRAM1 DRAM1 - DCPMM DRAM1 DRAM1 DRAM1 2-1-1

AD* DRAM1 DRAM1 DRAM1 - DCPMM DRAM1 DRAM1 DRAM1 2-1-1

(for the two tables above)

DDR4 Type Capacity

DRAM1 RDIMM 3DS RDIMM LRDIMM 3DS LRDIMM

DRAM2 RDIMM - - -

DRAM3 RDIMM 3DS RDIMM LRDIMM -

Note: DDR4 single rank x8 is not available for DCPMM Memory Mode or App-Direct

Legend

Refer to Validation Matrix (DDR4

DIMMs validated with DCPMM)

below.

Mode.

(for the rst two tables above)

DCPMM Any Capacity (Uniformly for all channels for a given conguration)

Legend

Capacity

• * 2nd socket has no DCPMM DIMM

• Mode denitions: AD=App Direct Mode, MM=Memory Mode, AD+MM=Mixed Mode

• For MM, general DDR4+DCPMM ratio is between 1:4 and 1:16. Excessive capacity for DCPMM can be used for AD.

• For each individual population, rearrangements between channels are allowed as long as the resulting population is

compliant with the X11 memory population rules for the 2nd Gen Intel Xeon Scalable-SP processors.

• For each individual population, please use the same DDR4 DIMM in all slots.

• For each individual population, sockets are normally symmetric with exceptions for 1 DCPMM per socket and 1 DCPMM

per node case. Currently, DCPMM modules operate at 2666 MHz.

• No mixing of DCPMM and NVMDIMMs within the same platform is allowed.

• This DCPMM population guide targets a balanced DCPMM-to-DRAM-cache ratio in MM and MM + AD modes.

Validation Matrix (DDR4 DIMMs Validated w/DCPMM)

DIMM Type

RDIMM

LRDIMM 4Rx4 N/A 64GB

LRDIMM 3DS 8Rx4 (4H) N/A 128GB

Ranks Per DIMM

& Data Width

(Stack)

1Rx4 8GB 16GB

2Rx8 8GB 16GB

2Rx4 16GB 32GB

DIMM Capacity (GB)

DRAM Density

4Gb 8Gb

39

Super X11DPX-T User's Manual

DIMM Installation

1. Insert the desired number of DIMMs into
the memory slots, starting with P1-DIMM
A1. For the system to work properly,
please use memory modules of the same
type and speed on the motherboard.

2. Push the release tabs outwards on both
ends of the DIMM slot to unlock it.

3. Align the key of the DIMM module with the
receptive point on the memory slot.

4. Align the notches on both ends of the
module against the receptive points on the
ends of the slot.

5. Use two thumbs together to press the
notches on both ends of the module
straight down into the slot until the module
snaps into place.

DESIGNED IN USA

IPMI CODE

BMC

LAN

X11DPX-T

REV:1.01A

BIOS
LICENSE

PCH

BAR CODE

SAN MAC
MAC CODE

CTRL

CPU2

CPU1

Notches

6. Press the release tabs to the lock positions
to secure the DIMM module into the slot.

Release Tabs

Insert the DIMM module into the memory slot.

DIMM Removal

Press the release tabs on both ends of the
DIMM socket to release the DIMM module from
the socket as shown in the drawing below.

Warnings: 1. Please do not use excessive force when pressing the release tabs on the ends
of the DIMM socket to avoid causing any damage to the DIMM module or the DIMM socket.

2. Please handle DIMM modules with care. Carefully follow all the instructions given on Page
1 of this chapter to prevent ESD-related damages to your memory modules or components.

40

Chapter 2: Installation

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

CPU2

CPU1

BIOS
LICENSE

SAN MAC
MAC CODE

BAR CODE

PCH

IPMI CODE

BMC

2.5 Rear I/O Ports

See Figure 2-2 below for the locations and descriptions of the various I/O ports on the rear
of the motherboard.

Figure 2-2. I/O Port Locations and Denitions

5

1

326 7

4

Rear I/O Ports

# Description # Description

1. COM Port 1 6. USB Port 1

2. IPMI Dedicated LAN 7. LAN Port 1

3. USB 3.0 Port 4 8. LAN Port 2

4. USB 3.0 Port 5 9. VGA Port

5. USB Port 0

8 9

41

Super X11DPX-T User's Manual

COM1

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

I-SATA4~7I-SATA0~3

FANC FAND

CPU2

CPU1

BIOS
LICENSE

JBT1

M.2 CONNECTOR

SAN MAC
MAC CODE

JF1

BAR CODE

IPMI CODE

VGA

USB 2/3

BT1

JNVI2C2

JNVI2C1

PCH

FANA

FAN2

FAN5

FAN1

P2-DIMMC1

P2-DIMMB1

P2-DIMMA1

P2-DIMMA2

P2-DIMMD2

P2-DIMMD1

P2-DIMME1

P2-DIMMF1

FAN6

P1-DIMMA2

P1-DIMMA1

P1-DIMMB1

P1-DIMMC1

JPWR1

JPWR2

JPWR3

JPI2C1

FAN4

LEDBMC

S-UM12

S-SATA0

S-SATA1

FANB

FAN3

JNCSI1

S-SGPIO

JSTBY1

JWD1

JSEN1

COM2

P1-DIMMF1

P1-DIMME1

P1-DIMMD1

P1-DIMMD2

SP1

USB8 (3.0)

JTPM1

JPWR4

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

JUIDB1

(UID)

LED2

(UID-LED)

USB 6/7 (3.0)

JL1

LEDPWR

JSD1

JSD2

JIPMB1

JRK1

JPTG1

JPCIE11

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPME2

LAN 2 LAN 1

USB 0/1

IPMI_LAN

USB 4/5 (3.0)

BMC

JPCIE2

(CPU1 SLOT2 PCI-E 3.0 x16)

JPCIE1

(CPU1 SLOT1 PCI-E 3.0 x8)

JPCIE3

(CPU1 SLOT3 PCI-E 3.0 x8)

JPCIE6

(CPU2 SLOT6 PCI-E 3.0 x16)

JPCIE5

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

(CPU1 SLOT7 PCI-E 3.0 x8)

JPCIE8

(CPU2 SLOT8 PCI-E 3.0 x16)

JPCIE4

(CPU1 SLOT4 PCI-E 3.0 x16)

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

JPCIE10

(CPU2 SLOT10 PCI-E 3.0 x8)

VGA Port

One VGA port is located next to LAN Port 2 on the I/O back panel. Use this connection for
VGA display.

Serial Port

There is one COM port (COM1) on the I/O back panel and one COM header (COM2) on the
motherboard. The COM1/COM2 provide serial communication support. See the table below

for pin denitions.

COM Port

Pin Denitions

Pin# Denition Pin# Denition

1 DCD 6 DSR

2 RXD 7 RTS

3 TXD 8 CTS

4 DTR 9 RI

5 Ground 10 N/A

LAN Ports

Two LAN ports (LAN1, LAN2) are located on the I/O back panel. These ports accept RJ45
type cables.

Pin# Denition Pin# Denition

1 TX_D1+ 5 BI_D3-

2 TX_D1- 6 RX_D2-

3 RX_D2+ 7 BI_D4+

4 BI_D3+ 8 BI_D4-

1

LAN Port

Pin Denition

4

2

1. VGA Port

3

2. COM Port 1

3. COM Port 2

4. LAN Ports 1/2

4

2

42

1

Chapter 2: Installation

COM1

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

I-SATA4~7I-SATA0~3

FANC FAND

CPU2

CPU1

BIOS
LICENSE

JBT1

M.2 CONNECTOR

SAN MAC
MAC CODE

JF1

BAR CODE

IPMI CODE

VGA

USB 2/3

BT1

JNVI2C2

JNVI2C1

PCH

FANA

FAN2

FAN5

FAN1

P2-DIMMC1

P2-DIMMB1

P2-DIMMA1

P2-DIMMA2

P2-DIMMD2

P2-DIMMD1

P2-DIMME1

P2-DIMMF1

FAN6

P1-DIMMA2

P1-DIMMA1

P1-DIMMB1

P1-DIMMC1

JPWR1

JPWR2

JPWR3

JPI2C1

FAN4

LEDBMC

S-UM12

S-SATA0

S-SATA1

FANB

FAN3

JNCSI1

S-SGPIO

JSTBY1

JWD1

JSEN1

COM2

P1-DIMMF1

P1-DIMME1

P1-DIMMD1

P1-DIMMD2

SP1

USB8 (3.0)

JTPM1

JPWR4

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

JUIDB1

(UID)

LED2

(UID-LED)

USB 6/7 (3.0)

JL1

LEDPWR

JSD1

JSD2

JIPMB1

JRK1

JPTG1

JPCIE11

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPME2

LAN 2 LAN 1

USB 0/1

IPMI_LAN

USB 4/5 (3.0)

BMC

JPCIE2

(CPU1 SLOT2 PCI-E 3.0 x16)

JPCIE1

(CPU1 SLOT1 PCI-E 3.0 x8)

JPCIE3

(CPU1 SLOT3 PCI-E 3.0 x8)

JPCIE6

(CPU2 SLOT6 PCI-E 3.0 x16)

JPCIE5

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

(CPU1 SLOT7 PCI-E 3.0 x8)

JPCIE8

(CPU2 SLOT8 PCI-E 3.0 x16)

JPCIE4

(CPU1 SLOT4 PCI-E 3.0 x16)

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

JPCIE10

(CPU2 SLOT10 PCI-E 3.0 x8)

Universal Serial Bus (USB) Ports

There are two USB 3.0 ports (USB 4/5) located on the I/O back panel. The motherboard also
has a front access USB 3.0 header that supports two USB connections (USB 6/7). A USB
Type A header, USB 8, provides also USB 3.0 support. The onboard headers can be used
to provide front side USB access with a cable (not included).

Back Panel USB 4/5 (3.0)

Pin Denitions

Pin# Denition Pin# Denition

1 VBUS 10 Power

2 D- 11 USB 2.0 Di󰀨erential Pair

3 D+ 12

4 Ground 13 Ground of PWR Return

5 StdA_SSRX- 14 SuperSpeed Receiver

6 StdA_SSRX+ 15 Di󰀨erential Pair

7 GND_DRAIN 16 Ground for Signal Return

8 StdA_SSTX- 17 SuperSpeed Transmitter

9 StdA_SSTX+ 18 Di󰀨erential Pair

Type A USB 8 (3.0)

Pin Denitions

Pin# Denition Pin# Denition

1 VBUS 5 SSRX-

2 USB_N 6 SSRX+

3 USB_P 7 Ground

4 Ground 8 SSTX-

9 SSTX+

Front Panel USB 6/7 3.0

Header Pin Denitions

Pin# Denition Pin# Denition

1 VBUS 19 Power

2 Stda_SSRX- 18 USB3_RN

3 Stda_SSRX+ 17 USB3_RP

4 Ground 16 Ground

5 Stda_SSTX- 15 USB3_TN

6 Stda_SSTX+ 14 USB3_TP

7 Ground 13 Ground

8 D- 12 USB_N

9 D+ 11 USB_P

10 x

2

4

5

1

1. USB 0/1

2. USB 2/3

3

3. USB 4/5 (USB 3.0)

4. USB 6/7 (USB 3.0)

5. Type A USB 8 (USB 3.0)

1

3

43

Super X11DPX-T User's Manual

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

CPU2

CPU1

BIOS
LICENSE

SAN MAC
MAC CODE

BAR CODE

PCH

IPMI CODE

BMC

UID LED

NIC1 Active LED

HDD LED

PWR LED

3.3V Stby

3.3V Stby

Ground

19

Ground

3.3V Stby

20

1 2

Ground

Power Fail LED

NIC2 Active LED

NMI

3.3V

3.3V

OH/PWR Fail/Fan Fail LED

Power Button

Reset Button

x

x

Unit Identier Switch/UID LED Indicator

A rear Unit Identier (UID) switch (JUIDB1) and an rear LED Indicator (LED2) are located

on the rear side of the system. The front UID LED is located on Pin 7 of the Front Control
Panel (JF1). When you press the UID switch, both front and rear UID LED indicators will be

turned on. Press the UID switch again to turn o󰀨 the LEDs. The UID Indicators provide easy
identication of a system unit that may be in need of service.

Note: UID can also be triggered via IPMI on the motherboard. For more information
on IPMI, please refer to the IPMI User's Guide posted on our website at http://www.
supermicro.com.

UID Switch

Pin Denitions

Pin# Denition

1 Ground

2 Ground

3 Button In

4 Button In

Color Status

Blue: On Unit Identied

UID LED

Pin Denitions

3

IPMI LAN Port

An IPMI_Dedicated LAN that supports Gigabit LAN is located next to USB ports 0/1 on the
back panel. This LAN port is supported by the onboard AST2500 BMC and accepts an RJ45
type cable. Refer to the LED Indicator Section for LAN LED information.

LAN Ports

Pin Denitions

Pin# Denition Pin# Denition

1 P2V5SB 10 SGND

2 TD0+ 11 Act LED

3 TD0- 12 P3V3SB

TD1+

4

TD1-

5

1

4

2

1. UID

2. IPMI_LAN

6 TD2+ 15 Ground

7 TD2- 16 Ground

8 TD3+ 17 Ground

Link 100 LED (Yellow,

13

+3V3SB)

Link 1000 LED (Yel-

14

low, +3V3SB)

9 TD3- 18 Ground

3. Front UID LED

4. LED2

2

44

Chapter 2: Installation

FAN6

JIPMB1

JRK1

JPTG1

19

20

1 2

2.6 Front Control Panel

JF1 contains header pins for various buttons and indicators that are normally located on a

control panel at the front of the chassis. These connectors are designed specically for use
with Supermicro chassis. See the gure below for the descriptions of the front control panel

buttons and LED indicators.

JUIDB1

LED2

(UID)

DESIGNED IN USA

COM2

FANC FAND

JPCIE1

(CPU1 SLOT1 PCI-E 3.0 x8)

X11DPX-T

REV:1.01A

JPCIE4

JPCIE3

JPCIE2

(CPU1 SLOT4 PCI-E 3.0 x16)

(CPU1 SLOT3 PCI-E 3.0 x8)

(CPU1 SLOT2 PCI-E 3.0 x16)

BMC

JPCIE6

JPCIE5

(CPU2 SLOT6 PCI-E 3.0 x16)

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

JPCIE8

(CPU1 SLOT7 PCI-E 3.0 x8)

(CPU2 SLOT8 PCI-E 3.0 x16)

LEDBMC

LAN
CTRL

JNCSI1

(UID-LED)

VGA

LAN 2 LAN 1

FAN4

USB 0/1

USB 4/5 (3.0)

IPMI_LAN

COM1

FAN3

JSD2

S-SATA1

JL1

JWD1

JSEN1

JSTBY1

S-SGPIO

JSD1

S-SATA0

USB 2/3

USB 6/7 (3.0)

FANB

JNVI2C1

S-UM12

IPMI CODE

I-SATA4~7I-SATA0~3

PCH

BIOS
LICENSE

JBT1

JPME2

JPCIE11

JNVI2C2

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPCIE10

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

(CPU2 SLOT10 PCI-E 3.0 x8)

P1-DIMMD1

P1-DIMMD2

P2-DIMMC1

ALWAYS POPULATE DIMMx1 FIRST

M.2 CONNECTOR

BT1

USB8 (3.0)

BAR CODE

SAN MAC
MAC CODE

P1-DIMMF1

P1-DIMME1

JTPM1

SP1

FAN2

FANA

LEDPWR

JF1

Figure 2-3. JF1 Header Pins

P2-DIMMB1

P2-DIMMA1

ALWAYS POPULATE DIMMx1 FIRST

P2-DIMMA2

CPU1

CPU2

P1-DIMMA2

ALWAYS POPULATE DIMMx1 FIRST

P1-DIMMA1

P1-DIMMB1

ALWAYS POPULATE DIMMx1 FIRST

P2-DIMMD2

P2-DIMMD1

P1-DIMMC1

JPWR4

JPWR3

JPWR2

JPWR1

FAN5

P2-DIMMF1

P2-DIMME1

JPI2C1

FAN1

Power Button

Reset Button

3.3V

UID LED

3.3V Stby

3.3V Stby

3.3V Stby

3.3V

x

NMI

Ground

Ground

Power Fail LED

OH/PWR Fail/Fan Fail LED

NIC2 Active LED

NIC1 Active LED

HDD LED

PWR LED

x

Ground

45

Super X11DPX-T User's Manual

1 2

NMI Button

The non-maskable interrupt button header is located on pins 19 and 20 of JF1. Refer to the

table below for pin denitions.

Power LED

Pin Denitions (JF1)

Pin# Denition

19 NMI

20 Ground

Power LED

The Power LED connection is located on pins 15 and 16 of JF1. Refer to the table below

for pin denitions.

Power LED

Pin Denitions (JF1)

Pin# Denition

15 Vcc

16 FP PWR LED

HDD LED

The HDD LED connection is located on pins 13 and 14 of JF1. Attach a cable here to indicate
the status of HDD-related activities, including IDE, SATA activities. See the table below for

pin denitions.

Power LED

Pin Denitions (JF1)

Pin# Denition

13 Vcc

14 HDD LED

1. NMI

Power Button

Reset Button

Ground

Ground

2. FP PWR LED

3. HDD LED

Power Fail LED

OH/PWR Fail/Fan Fail LED

NIC2 Active LED

NIC1 Active LED

HDD LED

PWR LED

3

2

3.3V

UID LED

3.3V Stby

3.3V Stby

3.3V Stby

3.3V

x

NMI

1

19

x

Ground

20

46

Chapter 2: Installation

1 2

NIC1/NIC2 (LAN1/LAN2)

The NIC (Network Interface Controller) LED connection for LAN port 1 is located on pin 12 of
JF1, and LAN port 2 is on pin 10. Attach the NIC LED cables here to display network activity.

Refer to the table below for pin denitions.

LAN1/LAN2 LED

Pin Denitions (JF1)

Pin# Denition

10 NIC2 Activity LED

12 NIC1 Activity LED

UID/OH/Fan Fail/PWR Fail LED

Connect an LED cable to pins 7 and 8 of the Front Control Panel (JF1) to use UID/Overheat/
Fan Fail/Power Fail LED connections. The LED on pin 8 provides warnings of overheat, power
failure or fan failure. Refer to the table below for details.

Information LED-UID/OH/PWR Fail/Fan Fail LED

Pin Denitions (Pin 7 & Pin 8 of JF1)

Status Description

Solid red An overheat condition has occurred. (This may be caused by cable congestion).

Blinking red (1Hz) Fan failure: check for an inoperative fan.

Blinking red (0.25Hz) Power failure: check for a non-operational power supply

Solid blue Local UID is activated. Use this function to locate a unit in a rack mount

environment that might be in need of service.

Blinking blue (300 msec) Remote UID is on. Use this function to identify a unit from a remote location that

might be in need of service.

Power Fail LED

The Power Fail LED connection is located on pins 5 and 6 of JF1. Refer to the table below

for pin denitions.

Power Fail LED

Pin Denitions (JF1)

Pin# Denition

5 3.3V

6 PWR Supply Fail

1. NIC1 LED

Ground

Ground

Power Fail LED

OH/PWR Fail/Fan Fail LED

NIC2 Active LED

NIC1 Active LED

HDD LED

PWR LED

x

Ground

20

2. NIC2 LED

3. Front UID LED

5

4

2

1

4. OH/PWR Fail/Fan Fail LED

5. PWR Fail LED

Power Button

Reset Button

3.3V

UID LED

3

3.3V Stby

3.3V Stby

3.3V Stby

3.3V

NMI

x

19

47

Super X11DPX-T User's Manual

1 2

Reset Button

The Reset Button connection is located on pins 3 and 4 of JF1. Attach it to a hardware reset

switch on the computer case to reset the system. Refer to the table below for pin denitions.

Reset Button

Pin Denitions (JF1)

Pin# Denition

3 Reset

4 Ground

Power Button

The Power Button connection is located on pins 1 and 2 of JF1. Momentarily contacting both

pins will power on/o󰀨 the system. This button can also be congured to function as a suspend
button (with a setting in the BIOS - see Chapter 4). To turn o󰀨 the power in the suspend
mode, press the button for at least 4 seconds. Refer to the table below for pin denitions.

Power Button

2

Reset Button

1

3.3V Stby

3.3V Stby

3.3V Stby

3.3V

UID LED

3.3V

Pin# Denition

1 Signal

2 Ground

Ground

Ground

Power Fail LED

OH/PWR Fail/Fan Fail LED

NIC2 Active LED

NIC1 Active LED

HDD LED

PWR LED

Power Button

Pin Denitions (JF1)

1. Reset Button

2. Power Button

NMI

x

19

x

Ground

20

48

Chapter 2: Installation

COM1

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

I-SATA4~7I-SATA0~3

FANC FAND

CPU2

CPU1

BIOS
LICENSE

JBT1

M.2 CONNECTOR

SAN MAC
MAC CODE

JF1

BAR CODE

IPMI CODE

VGA

USB 2/3

BT1

JNVI2C2

JNVI2C1

PCH

FANA

FAN2

FAN5

FAN1

P2-DIMMC1

P2-DIMMB1

P2-DIMMA1

P2-DIMMA2

P2-DIMMD2

P2-DIMMD1

P2-DIMME1

P2-DIMMF1

FAN6

P1-DIMMA2

P1-DIMMA1

P1-DIMMB1

P1-DIMMC1

JPWR1

JPWR2

JPWR3

JPI2C1

FAN4

LEDBMC

S-UM12

S-SATA0

S-SATA1

FANB

FAN3

JNCSI1

S-SGPIO

JSTBY1

JWD1

JSEN1

COM2

P1-DIMMF1

P1-DIMME1

P1-DIMMD1

P1-DIMMD2

SP1

USB8 (3.0)

JTPM1

JPWR4

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

JUIDB1

(UID)

LED2

(UID-LED)

USB 6/7 (3.0)

JL1

LEDPWR

JSD1

JSD2

JIPMB1

JRK1

JPTG1

JPCIE11

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPME2

LAN 2 LAN 1

USB 0/1

IPMI_LAN

USB 4/5 (3.0)

BMC

JPCIE2

(CPU1 SLOT2 PCI-E 3.0 x16)

JPCIE1

(CPU1 SLOT1 PCI-E 3.0 x8)

JPCIE3

(CPU1 SLOT3 PCI-E 3.0 x8)

JPCIE6

(CPU2 SLOT6 PCI-E 3.0 x16)

JPCIE5

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

(CPU1 SLOT7 PCI-E 3.0 x8)

JPCIE8

(CPU2 SLOT8 PCI-E 3.0 x16)

JPCIE4

(CPU1 SLOT4 PCI-E 3.0 x16)

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

JPCIE10

(CPU2 SLOT10 PCI-E 3.0 x8)

2.7 Connectors

Power Connections

Main ATX Power Supply Connector

The primary power supply connector (JPWR1) meets the ATX SSI EPS 24-pin specication.

You must also connect the 8-pin (JPWR2/JPWR3) and 4-pin (JPWR4) CPU power connectors
to your power supply.

Warning: To provide adequate power to your system and to avoid damaging the power sup-
ply or the motherboard, be sure to connect all power connectors mentioned above to the
power supply. Failure in doing so may void the manufacturer warranty on your power supply
and motherboard.

ATX Power 24-pin Connector

Pin Denitions

Pin# Denition Pin# Denition

13 +3.3V 1 +3.3V

14 NC 2 +3.3V

15 Ground 3 Ground

16 PS_ON 4 +5V

17 Ground 5 Ground

18 Ground 6 +5V

19 Ground 7 Ground

20 Res (NC) 8 PWR_OK

21 +5V 9 5VSB

22 +5V 10 +12V

23 +5V 11 +12V

24 Ground 12 +3.3V

12V 8-pin PWR Connector

Pin Denitions

Pins Denition

1 through 4 Ground

5 through 8 +12V

12V 4-pin PWR Connector

Pin Denitions

Pins Denition

1-2 Ground

3-4 +12V

Required Connection

1. 24-pin ATX PWR (JPWR1)

(Required)

2. 8-pin Processor PWR

(JPWR2) (Required)

3. 8-pin Processor PWR

(JPWR3) (Required)

4. 4-pin Processor PWR

(JPWR4) (Required)

4

3
2

1

49

Super X11DPX-T User's Manual

COM1

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

I-SATA4~7I-SATA0~3

FANC FAND

CPU2

CPU1

BIOS
LICENSE

JBT1

M.2 CONNECTOR

SAN MAC
MAC CODE

JF1

BAR CODE

IPMI CODE

VGA

USB 2/3

BT1

JNVI2C2

JNVI2C1

PCH

FANA

FAN2

FAN5

FAN1

P2-DIMMC1

P2-DIMMB1

P2-DIMMA1

P2-DIMMA2

P2-DIMMD2

P2-DIMMD1

P2-DIMME1

P2-DIMMF1

FAN6

P1-DIMMA2

P1-DIMMA1

P1-DIMMB1

P1-DIMMC1

JPWR1

JPWR2

JPWR3

JPI2C1

FAN4

LEDBMC

S-UM12

S-SATA0

S-SATA1

FANB

FAN3

JNCSI1

S-SGPIO

JSTBY1

JWD1

JSEN1

COM2

P1-DIMMF1

P1-DIMME1

P1-DIMMD1

P1-DIMMD2

SP1

USB8 (3.0)

JTPM1

JPWR4

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

JUIDB1

(UID)

LED2

(UID-LED)

USB 6/7 (3.0)

JL1

LEDPWR

JSD1

JSD2

JIPMB1

JRK1

JPTG1

JPCIE11

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPME2

LAN 2 LAN 1

USB 0/1

IPMI_LAN

USB 4/5 (3.0)

BMC

JPCIE2

(CPU1 SLOT2 PCI-E 3.0 x16)

JPCIE1

(CPU1 SLOT1 PCI-E 3.0 x8)

JPCIE3

(CPU1 SLOT3 PCI-E 3.0 x8)

JPCIE6

(CPU2 SLOT6 PCI-E 3.0 x16)

JPCIE5

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

(CPU1 SLOT7 PCI-E 3.0 x8)

JPCIE8

(CPU2 SLOT8 PCI-E 3.0 x16)

JPCIE4

(CPU1 SLOT4 PCI-E 3.0 x16)

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

JPCIE10

(CPU2 SLOT10 PCI-E 3.0 x8)

Headers

Fan Headers

There are eight fan headers on the motherboard. These are 4-pin fan headers; pins 1-3 are
backward compatible with traditional 3-pin fans. The onboard fan speeds are controlled by
Thermal Management via the BMC (or by IPMI). Use 4-pin fan headers for fan speed control
support.

Fan Header

Pin Denitions

Pin# Denition

1 Ground (Black)

2 +12V (Red)

3 Tachometer

4 PWM Control

Internal Speaker/Buzzer

The Internal Speaker/Buzzer (SP1) is used to provide audible indications for various beep

codes. See the table below for pin denitions.

Internal Buzzer

Pin Denitions

Pin# Denition

1 Pos (+) Beep In

2 Neg (-) Alarm Speaker

1. FAN1

9

8

10

7

11

4

3

6

5

1

50

2

2. FAN2

3. FAN3

4. FAN4

5. FAN5

6. FAN6

7. FANA

8. FANB

9. FANC

10. FAND

11. Internal Speaker

Chapter 2: Installation

COM1

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

I-SATA4~7I-SATA0~3

FANC FAND

CPU2

CPU1

BIOS
LICENSE

JBT1

M.2 CONNECTOR

SAN MAC
MAC CODE

JF1

BAR CODE

IPMI CODE

VGA

USB 2/3

BT1

JNVI2C2

JNVI2C1

PCH

FANA

FAN2

FAN5

FAN1

P2-DIMMC1

P2-DIMMB1

P2-DIMMA1

P2-DIMMA2

P2-DIMMD2

P2-DIMMD1

P2-DIMME1

P2-DIMMF1

FAN6

P1-DIMMA2

P1-DIMMA1

P1-DIMMB1

P1-DIMMC1

JPWR1

JPWR2

JPWR3

JPI2C1

FAN4

LEDBMC

S-UM12

S-SATA0

S-SATA1

FANB

FAN3

JNCSI1

S-SGPIO

JSTBY1

JWD1

JSEN1

COM2

P1-DIMMF1

P1-DIMME1

P1-DIMMD1

P1-DIMMD2

SP1

USB8 (3.0)

JTPM1

JPWR4

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

JUIDB1

(UID)

LED2

(UID-LED)

USB 6/7 (3.0)

JL1

LEDPWR

JSD1

JSD2

JIPMB1

JRK1

JPTG1

JPCIE11

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPME2

LAN 2 LAN 1

USB 0/1

IPMI_LAN

USB 4/5 (3.0)

BMC

JPCIE2

(CPU1 SLOT2 PCI-E 3.0 x16)

JPCIE1

(CPU1 SLOT1 PCI-E 3.0 x8)

JPCIE3

(CPU1 SLOT3 PCI-E 3.0 x8)

JPCIE6

(CPU2 SLOT6 PCI-E 3.0 x16)

JPCIE5

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

(CPU1 SLOT7 PCI-E 3.0 x8)

JPCIE8

(CPU2 SLOT8 PCI-E 3.0 x16)

JPCIE4

(CPU1 SLOT4 PCI-E 3.0 x16)

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

JPCIE10

(CPU2 SLOT10 PCI-E 3.0 x8)

S-SGPIO Header

A Serial General Purpose Input/Output header (S-SGPIO) is located on the motherboard.
This header is used to communicate with the enclosure management chip on the backplane.

See the table below for pin denitions.

SGPIO Header

Pin Denitions

Pin# Denition Pin# Denition

1 NC 2 NC

3 Ground 4 DATA Out

5 Load 6 Ground

7 Clock 8 NC

NC = No Connection

Disk-On-Module Power Connector

The Disk-On-Module (DOM) power connectors at JSD1 and JSD2 provide 5V power to a
solid-state DOM storage devices connected to one of the SATA ports. See the table below

for pin denitions.

DOM Power

Pin Denitions

Pin# Denition

1 5V

2 Ground

3 Ground

1

3

2

1. S-SGPIO

2. JSD1

3. JSD2

51

Super X11DPX-T User's Manual

COM1

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

I-SATA4~7I-SATA0~3

FANC FAND

CPU2

CPU1

BIOS
LICENSE

JBT1

M.2 CONNECTOR

SAN MAC
MAC CODE

JF1

BAR CODE

IPMI CODE

VGA

USB 2/3

BT1

JNVI2C2

JNVI2C1

PCH

FANA

FAN2

FAN5

FAN1

P2-DIMMC1

P2-DIMMB1

P2-DIMMA1

P2-DIMMA2

P2-DIMMD2

P2-DIMMD1

P2-DIMME1

P2-DIMMF1

FAN6

P1-DIMMA2

P1-DIMMA1

P1-DIMMB1

P1-DIMMC1

JPWR1

JPWR2

JPWR3

JPI2C1

FAN4

LEDBMC

S-UM12

S-SATA0

S-SATA1

FANB

FAN3

JNCSI1

S-SGPIO

JSTBY1

JWD1

JSEN1

COM2

P1-DIMMF1

P1-DIMME1

P1-DIMMD1

P1-DIMMD2

SP1

USB8 (3.0)

JTPM1

JPWR4

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

JUIDB1

(UID)

LED2

(UID-LED)

USB 6/7 (3.0)

JL1

LEDPWR

JSD1

JSD2

JIPMB1

JRK1

JPTG1

JPCIE11

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPME2

LAN 2 LAN 1

USB 0/1

IPMI_LAN

USB 4/5 (3.0)

BMC

JPCIE2

(CPU1 SLOT2 PCI-E 3.0 x16)

JPCIE1

(CPU1 SLOT1 PCI-E 3.0 x8)

JPCIE3

(CPU1 SLOT3 PCI-E 3.0 x8)

JPCIE6

(CPU2 SLOT6 PCI-E 3.0 x16)

JPCIE5

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

(CPU1 SLOT7 PCI-E 3.0 x8)

JPCIE8

(CPU2 SLOT8 PCI-E 3.0 x16)

JPCIE4

(CPU1 SLOT4 PCI-E 3.0 x16)

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

JPCIE10

(CPU2 SLOT10 PCI-E 3.0 x8)

TPM Header

The JTPM1 header is used to connect a Trusted Platform Module (TPM)/Port 80, which is
available from SMCI (optional). A TPM/Port 80 connector is a security device that supports
encryption and authentication in hard drives. It allows the motherboard to deny access if the
TPM associated with the hard drive is not installed in the system. See the table below for

pin denitions.

Trusted Platform Module/Port 80 Header

Pin Denitions

Pin# Denition Pin# Denition

1 P3V3 2 SPI_TPM_CS_N

3 PCIE_RESET_N# 4 SPI_PCH_MISO

5 SPI_PCH_CLK# 6 Ground

7 SPI_PCH_MOSI 8 N/A

9 JTPM1_P3V3A 10 IRQ_TPM_SPIN_N

Chassis Intrusion

A Chassis Intrusion header is located at JL1 on the motherboard. Connect an appropriate
cable from JL1 to the chassis so that you can be informed of a chassis intrusion (via IPMI)

when the system case is opened. Refer to the table below for pin denitions.

Chassis Intrusion

Pin Denitions

Pins Denition

1 Intrusion Input

2 Ground

2

1

1. TPM/Port 80 Header

2. Chassis Intrusion

52

Chapter 2: Installation

COM1

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

I-SATA4~7I-SATA0~3

FANC FAND

CPU2

CPU1

BIOS
LICENSE

JBT1

M.2 CONNECTOR

SAN MAC
MAC CODE

JF1

BAR CODE

IPMI CODE

VGA

USB 2/3

BT1

JNVI2C2

JNVI2C1

PCH

FANA

FAN2

FAN5

FAN1

P2-DIMMC1

P2-DIMMB1

P2-DIMMA1

P2-DIMMA2

P2-DIMMD2

P2-DIMMD1

P2-DIMME1

P2-DIMMF1

FAN6

P1-DIMMA2

P1-DIMMA1

P1-DIMMB1

P1-DIMMC1

JPWR1

JPWR2

JPWR3

JPI2C1

FAN4

LEDBMC

S-UM12

S-SATA0

S-SATA1

FANB

FAN3

JNCSI1

S-SGPIO

JSTBY1

JWD1

JSEN1

COM2

P1-DIMMF1

P1-DIMME1

P1-DIMMD1

P1-DIMMD2

SP1

USB8 (3.0)

JTPM1

JPWR4

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

JUIDB1

(UID)

LED2

(UID-LED)

USB 6/7 (3.0)

JL1

LEDPWR

JSD1

JSD2

JIPMB1

JRK1

JPTG1

JPCIE11

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPME2

LAN 2 LAN 1

USB 0/1

IPMI_LAN

USB 4/5 (3.0)

BMC

JPCIE2

(CPU1 SLOT2 PCI-E 3.0 x16)

JPCIE1

(CPU1 SLOT1 PCI-E 3.0 x8)

JPCIE3

(CPU1 SLOT3 PCI-E 3.0 x8)

JPCIE6

(CPU2 SLOT6 PCI-E 3.0 x16)

JPCIE5

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

(CPU1 SLOT7 PCI-E 3.0 x8)

JPCIE8

(CPU2 SLOT8 PCI-E 3.0 x16)

JPCIE4

(CPU1 SLOT4 PCI-E 3.0 x16)

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

JPCIE10

(CPU2 SLOT10 PCI-E 3.0 x8)

4-pin BMC External I2C Header

A System Management Bus header for IPMI 2.0 is located at JIPMB1. Connect a cable to this
header to use the IPMB I2C connection on your system. See the table below for pin denitions.

External I2C Header

Pin Denitions

Pin# Denition

1 Data

2 Ground

3 Clock

4 No Connection

Power SMB (I2C) Header

Power System Management Bus (I2C) header at JPI2C1 monitors the power supply input/

output voltages, fans, temperatures, and status. Refer to the table below for pin denitions.

1

Power SMB Header

Pin Denitions

Pin# Denition

1 Clock

2 Data

3 Power Fail

4 Ground

5 +3.3V

1. BMC External I2C
Header

2. Power SMB Header

2

53

Super X11DPX-T User's Manual

COM1

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

I-SATA4~7I-SATA0~3

FANC FAND

CPU2

CPU1

BIOS
LICENSE

JBT1

M.2 CONNECTOR

SAN MAC
MAC CODE

JF1

BAR CODE

IPMI CODE

VGA

USB 2/3

BT1

JNVI2C2

JNVI2C1

PCH

FANA

FAN2

FAN5

FAN1

P2-DIMMC1

P2-DIMMB1

P2-DIMMA1

P2-DIMMA2

P2-DIMMD2

P2-DIMMD1

P2-DIMME1

P2-DIMMF1

FAN6

P1-DIMMA2

P1-DIMMA1

P1-DIMMB1

P1-DIMMC1

JPWR1

JPWR2

JPWR3

JPI2C1

FAN4

LEDBMC

S-UM12

S-SATA0

S-SATA1

FANB

FAN3

JNCSI1

S-SGPIO

JSTBY1

JWD1

JSEN1

COM2

P1-DIMMF1

P1-DIMME1

P1-DIMMD1

P1-DIMMD2

SP1

USB8 (3.0)

JTPM1

JPWR4

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

JUIDB1

(UID)

LED2

(UID-LED)

USB 6/7 (3.0)

JL1

LEDPWR

JSD1

JSD2

JIPMB1

JRK1

JPTG1

JPCIE11

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPME2

LAN 2 LAN 1

USB 0/1

IPMI_LAN

USB 4/5 (3.0)

BMC

JPCIE2

(CPU1 SLOT2 PCI-E 3.0 x16)

JPCIE1

(CPU1 SLOT1 PCI-E 3.0 x8)

JPCIE3

(CPU1 SLOT3 PCI-E 3.0 x8)

JPCIE6

(CPU2 SLOT6 PCI-E 3.0 x16)

JPCIE5

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

(CPU1 SLOT7 PCI-E 3.0 x8)

JPCIE8

(CPU2 SLOT8 PCI-E 3.0 x16)

JPCIE4

(CPU1 SLOT4 PCI-E 3.0 x16)

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

JPCIE10

(CPU2 SLOT10 PCI-E 3.0 x8)

I-SATA 3.0 and S-SATA 3.0 Ports

The X11DPX-T has eight I-SATA 3.0 ports (I-SATA0~3, I-SATA4~7), which are supported by
the Intel C621 chipset. In addition, it also has two S-SATA 3.0 ports (S-SATA0/S-SATA1) that
are supported by the Intel SCU. S-SATA0/S-SATA1 can be used with Supermicro SuperDOMs

which are yellow SATA DOM connectors with power pins built in, and do not require external

power cables. Supermicro SuperDOMs are backward-compatible with regular SATA HDDs or
SATA DOMs that need external power cables. All these SATA ports provide serial-link signal
connections, which are faster than the connections of Parallel ATA.

SATA 3.0 Port

Pin Denitions

Pin# Signal

1 Ground

2 SATA_TXP

3 SATA_TXN

4 Ground

5 SATA_RXN

6 SATA_RXP

7 Ground

4

3

2

1

1. I-SATA0~3

2. I-SATA4~7

3. S-SATA0

4. S-SATA1

54

Chapter 2: Installation

COM1

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

I-SATA4~7I-SATA0~3

FANC FAND

CPU2

CPU1

BIOS
LICENSE

JBT1

M.2 CONNECTOR

SAN MAC
MAC CODE

JF1

BAR CODE

IPMI CODE

VGA

USB 2/3

BT1

JNVI2C2

JNVI2C1

PCH

FANA

FAN2

FAN5

FAN1

P2-DIMMC1

P2-DIMMB1

P2-DIMMA1

P2-DIMMA2

P2-DIMMD2

P2-DIMMD1

P2-DIMME1

P2-DIMMF1

FAN6

P1-DIMMA2

P1-DIMMA1

P1-DIMMB1

P1-DIMMC1

JPWR1

JPWR2

JPWR3

JPI2C1

FAN4

LEDBMC

S-UM12

S-SATA0

S-SATA1

FANB

FAN3

JNCSI1

S-SGPIO

JSTBY1

JWD1

JSEN1

COM2

P1-DIMMF1

P1-DIMME1

P1-DIMMD1

P1-DIMMD2

SP1

USB8 (3.0)

JTPM1

JPWR4

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

JUIDB1

(UID)

LED2

(UID-LED)

USB 6/7 (3.0)

JL1

LEDPWR

JSD1

JSD2

JIPMB1

JRK1

JPTG1

JPCIE11

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPME2

LAN 2 LAN 1

USB 0/1

IPMI_LAN

USB 4/5 (3.0)

BMC

JPCIE2

(CPU1 SLOT2 PCI-E 3.0 x16)

JPCIE1

(CPU1 SLOT1 PCI-E 3.0 x8)

JPCIE3

(CPU1 SLOT3 PCI-E 3.0 x8)

JPCIE6

(CPU2 SLOT6 PCI-E 3.0 x16)

JPCIE5

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

(CPU1 SLOT7 PCI-E 3.0 x8)

JPCIE8

(CPU2 SLOT8 PCI-E 3.0 x16)

JPCIE4

(CPU1 SLOT4 PCI-E 3.0 x16)

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

JPCIE10

(CPU2 SLOT10 PCI-E 3.0 x8)

VROC RAID Key Header

A VROC RAID Key header is located at JRK1 on the motherboard. Install a VROC RAID
Key on JRK1 for NVMe RAID support as shown in the illustration below. Please refer to the
layout below for the location of JRK1.

Note: Enable the VROC Key is required when using the RAID function.

Intel VROC Key

Pin Denitions

Pin# Denition

1 Ground

2 3.3V Standby

3 Ground

4 PCH RAID Key

VROC Key

VROC Key Header (JRK1)

1

1. VROC RAID Key Header

55

Super X11DPX-T User's Manual

COM1

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

I-SATA4~7I-SATA0~3

FANC FAND

CPU2

CPU1

BIOS
LICENSE

JBT1

M.2 CONNECTOR

SAN MAC
MAC CODE

JF1

BAR CODE

IPMI CODE

VGA

USB 2/3

BT1

JNVI2C2

JNVI2C1

PCH

FANA

FAN2

FAN5

FAN1

P2-DIMMC1

P2-DIMMB1

P2-DIMMA1

P2-DIMMA2

P2-DIMMD2

P2-DIMMD1

P2-DIMME1

P2-DIMMF1

FAN6

P1-DIMMA2

P1-DIMMA1

P1-DIMMB1

P1-DIMMC1

JPWR1

JPWR2

JPWR3

JPI2C1

FAN4

LEDBMC

S-UM12

S-SATA0

S-SATA1

FANB

FAN3

JNCSI1

S-SGPIO

JSTBY1

JWD1

JSEN1

COM2

P1-DIMMF1

P1-DIMME1

P1-DIMMD1

P1-DIMMD2

SP1

USB8 (3.0)

JTPM1

JPWR4

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

JUIDB1

(UID)

LED2

(UID-LED)

USB 6/7 (3.0)

JL1

LEDPWR

JSD1

JSD2

JIPMB1

JRK1

JPTG1

JPCIE11

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPME2

LAN 2 LAN 1

USB 0/1

IPMI_LAN

USB 4/5 (3.0)

BMC

JPCIE2

(CPU1 SLOT2 PCI-E 3.0 x16)

JPCIE1

(CPU1 SLOT1 PCI-E 3.0 x8)

JPCIE3

(CPU1 SLOT3 PCI-E 3.0 x8)

JPCIE6

(CPU2 SLOT6 PCI-E 3.0 x16)

JPCIE5

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

(CPU1 SLOT7 PCI-E 3.0 x8)

JPCIE8

(CPU2 SLOT8 PCI-E 3.0 x16)

JPCIE4

(CPU1 SLOT4 PCI-E 3.0 x16)

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

JPCIE10

(CPU2 SLOT10 PCI-E 3.0 x8)

NVMe SMBus Headers

NVMe SMBus (I2C) headers (JNVI2C1/JNVI2C2), used for PCIe SMBus clock and data
connections, provide hot-plug support via a dedicated SMBus interface. This feature is only
available for a Supermicro complete system with an SMCI-proprietary NVMe add-on card
and cable installed. Also, JNVI2C1 and JNVI2C2 are VPP headers for NVMe add-on cards.

See the table below for pin denitions.

NVMe SMBus Header

Pin Denitions

Pin# Denition

1 Data

2 Ground

3 Clock

4 VCCIO

1

1

1. NVMe I2C Header

56

Chapter 2: Installation

COM1

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

I-SATA4~7I-SATA0~3

FANC FAND

CPU2

CPU1

BIOS
LICENSE

JBT1

M.2 CONNECTOR

SAN MAC
MAC CODE

JF1

BAR CODE

IPMI CODE

VGA

USB 2/3

BT1

JNVI2C2

JNVI2C1

PCH

FANA

FAN2

FAN5

FAN1

P2-DIMMC1

P2-DIMMB1

P2-DIMMA1

P2-DIMMA2

P2-DIMMD2

P2-DIMMD1

P2-DIMME1

P2-DIMMF1

FAN6

P1-DIMMA2

P1-DIMMA1

P1-DIMMB1

P1-DIMMC1

JPWR1

JPWR2

JPWR3

JPI2C1

FAN4

LEDBMC

S-UM12

S-SATA0

S-SATA1

FANB

FAN3

JNCSI1

S-SGPIO

JSTBY1

JWD1

JSEN1

COM2

P1-DIMMF1

P1-DIMME1

P1-DIMMD1

P1-DIMMD2

SP1

USB8 (3.0)

JTPM1

JPWR4

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

JUIDB1

(UID)

LED2

(UID-LED)

USB 6/7 (3.0)

JL1

LEDPWR

JSD1

JSD2

JIPMB1

JRK1

JPTG1

JPCIE11

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPME2

LAN 2 LAN 1

USB 0/1

IPMI_LAN

USB 4/5 (3.0)

BMC

JPCIE2

(CPU1 SLOT2 PCI-E 3.0 x16)

JPCIE1

(CPU1 SLOT1 PCI-E 3.0 x8)

JPCIE3

(CPU1 SLOT3 PCI-E 3.0 x8)

JPCIE6

(CPU2 SLOT6 PCI-E 3.0 x16)

JPCIE5

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

(CPU1 SLOT7 PCI-E 3.0 x8)

JPCIE8

(CPU2 SLOT8 PCI-E 3.0 x16)

JPCIE4

(CPU1 SLOT4 PCI-E 3.0 x16)

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

JPCIE10

(CPU2 SLOT10 PCI-E 3.0 x8)

Standby Power

The standby power header is located at JSTBY1 on the motherboard. Refer to the table

below for pin denitions.

Standby Power

Pin Denitions

Pin# Denition

1 +5V Standby

2 Ground

3 No Connection

PCIe M.2 Connector (M.2 CONNECTOR)

This motherboard has one PCIe M.2 connector (M.2 CONNECTOR). The M.2, formerly known
as "Next Generation Form Factor (NGFF)" replaces a mini PCIe slot. M.2 allows for a variety

of card sizes and o󰀨ers increased functionality and spatial e󰀩ciency. The M.2 socket on the

motherboard supports PCIe 3.0 x4 (32 Gb/s) SSD cards in the 2280 and 22110 form factors.

A Holder

C Card Holder Mount

Turn 90 degrees
to lock

1

Locked position

Locked position
with M.2 card

2

B Holder Mount

Turn 90 degrees
to lock

D Plastic screw

Locked position

STOP

57

Press in here

Rectangle hole
on MB

A

Hole Location on the M B 42

M.2 Card 60 A+B+C

M.2 Card 80 A+B+C

M.2 Card 110 A+B+D

A+B+C

B

C

A

Copyright © 2017 by Super Micro Computer, Inc. All rights reserved.

1. Standby Power

2. PCIe M.2 Connector

A+B+D

D

B

Super X11DPX-T User's Manual

COM1

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

I-SATA4~7I-SATA0~3

FANC FAND

CPU2

CPU1

BIOS
LICENSE

JBT1

M.2 CONNECTOR

SAN MAC
MAC CODE

JF1

BAR CODE

IPMI CODE

VGA

USB 2/3

BT1

JNVI2C2

JNVI2C1

PCH

FANA

FAN2

FAN5

FAN1

P2-DIMMC1

P2-DIMMB1

P2-DIMMA1

P2-DIMMA2

P2-DIMMD2

P2-DIMMD1

P2-DIMME1

P2-DIMMF1

FAN6

P1-DIMMA2

P1-DIMMA1

P1-DIMMB1

P1-DIMMC1

JPWR1

JPWR2

JPWR3

JPI2C1

FAN4

LEDBMC

S-UM12

S-SATA0

S-SATA1

FANB

FAN3

JNCSI1

S-SGPIO

JSTBY1

JWD1

JSEN1

COM2

P1-DIMMF1

P1-DIMME1

P1-DIMMD1

P1-DIMMD2

SP1

USB8 (3.0)

JTPM1

JPWR4

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

JUIDB1

(UID)

LED2

(UID-LED)

USB 6/7 (3.0)

JL1

LEDPWR

JSD1

JSD2

JIPMB1

JRK1

JPTG1

JPCIE11

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPME2

LAN 2 LAN 1

USB 0/1

IPMI_LAN

USB 4/5 (3.0)

BMC

JPCIE2

(CPU1 SLOT2 PCI-E 3.0 x16)

JPCIE1

(CPU1 SLOT1 PCI-E 3.0 x8)

JPCIE3

(CPU1 SLOT3 PCI-E 3.0 x8)

JPCIE6

(CPU2 SLOT6 PCI-E 3.0 x16)

JPCIE5

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

(CPU1 SLOT7 PCI-E 3.0 x8)

JPCIE8

(CPU2 SLOT8 PCI-E 3.0 x16)

JPCIE4

(CPU1 SLOT4 PCI-E 3.0 x16)

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

JPCIE10

(CPU2 SLOT10 PCI-E 3.0 x8)

NC-SI Header for IPMI Support

A Network-Controller Sideband Interface (NC-SI) header is located at JNCSI1 on the
motherboard. Connect an appropriate cable from this header to an add-on card to provide the
out-of-band (sideband) connection between the onboard Baseboard Management Controller
(BMC) and a Network Interface Controller (NIC) for remote management. For the network
sideband interface to work properly, you will need to use a NIC add-on card that supports
NC-SI and also need to have a special cable. Please contact Supermicro at www.supermicro.

com to purchase the cable for this header. Refer to the table below for pin denitions.

NC-SI Header for IPMI Support

Pin Denitions

Pin# Denition Pin# Denition

1 CLK_50MHz 2 Ground

3 NCSI_CRS_DV 4 Ground

5 NCSI_RXD0 6 Ground

7 NCSI_RXD1 8 Ground

9 NCSI_TXD0 10 Ground

11 NCSI_TXD1 12 Ground

13 NCSI_TX_EX 14 NCSI_PRESENT_N

15 NC 16 NC

17 5V STBY 18 5V STBY

19 5V STBY 20 5V STBY

21 5V STBY 22 NC

1. NC-SI Header for IPMI
Support (JNCSI1)

1

58

Chapter 2: Installation

COM1

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

I-SATA4~7I-SATA0~3

FANC FAND

CPU2

CPU1

BIOS
LICENSE

JBT1

M.2 CONNECTOR

SAN MAC
MAC CODE

JF1

BAR CODE

IPMI CODE

VGA

USB 2/3

BT1

JNVI2C2

JNVI2C1

PCH

FANA

FAN2

FAN5

FAN1

P2-DIMMC1

P2-DIMMB1

P2-DIMMA1

P2-DIMMA2

P2-DIMMD2

P2-DIMMD1

P2-DIMME1

P2-DIMMF1

FAN6

P1-DIMMA2

P1-DIMMA1

P1-DIMMB1

P1-DIMMC1

JPWR1

JPWR2

JPWR3

JPI2C1

FAN4

LEDBMC

S-UM12

S-SATA0

S-SATA1

FANB

FAN3

JNCSI1

S-SGPIO

JSTBY1

JWD1

JSEN1

COM2

P1-DIMMF1

P1-DIMME1

P1-DIMMD1

P1-DIMMD2

SP1

USB8 (3.0)

JTPM1

JPWR4

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

JUIDB1

(UID)

LED2

(UID-LED)

USB 6/7 (3.0)

JL1

LEDPWR

JSD1

JSD2

JIPMB1

JRK1

JPTG1

JPCIE11

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPME2

LAN 2 LAN 1

USB 0/1

IPMI_LAN

USB 4/5 (3.0)

BMC

JPCIE2

(CPU1 SLOT2 PCI-E 3.0 x16)

JPCIE1

(CPU1 SLOT1 PCI-E 3.0 x8)

JPCIE3

(CPU1 SLOT3 PCI-E 3.0 x8)

JPCIE6

(CPU2 SLOT6 PCI-E 3.0 x16)

JPCIE5

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

(CPU1 SLOT7 PCI-E 3.0 x8)

JPCIE8

(CPU2 SLOT8 PCI-E 3.0 x16)

JPCIE4

(CPU1 SLOT4 PCI-E 3.0 x16)

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

JPCIE10

(CPU2 SLOT10 PCI-E 3.0 x8)

Inlet Sensor Header

This header (JSEN1) allows BMC to monitor thermal inlet temperature. A special module is

required. Please contact Supermicro at www.supermicro.com to purchase the module for this
header. Refer to the table below for pin denitions.

Inlet Sensor Header

Pin Denitions

Pin# Denition

1 SMBDAT

2 Ground

3 SMBCLK

4 3.3V STBY

1

1. Inlet Sensor Header (JSEN1)

59

Super X11DPX-T User's Manual

2.8 Jumper Settings

How Jumpers Work

To modify the operation of the motherboard, jumpers can be used to choose between optional
settings. Jumpers create shorts between two pins to change the function of the connector.

Pin 1 is identied with a square solder pad on the printed circuit board. See the diagram

below for an example of jumping pins 1 and 2. Refer to the motherboard layout page for
jumper locations.

Note: On two-pin jumpers, "Closed" means the jumper is on and "Open" means the

jumper is o󰀨 the pins.

Connector

Pins

Jumper

Setting

3 2 1

3 2 1

CMOS Clear

JBT1 is used to clear CMOS, which will also clear any passwords. Instead of pins, this jumper
consists of contact pads to prevent accidentally clearing the contents of CMOS.

To Clear CMOS

1. First power down the system and unplug the power cord(s).

2. Remove the cover of the chassis to access the motherboard.

3. Remove the onboard battery from the motherboard.

4. Short the CMOS pads with a metal object such as a small screwdriver for at least four
seconds.

5. Remove the screwdriver (or shorting device).

6. Replace the cover, reconnect the power cord(s), and power on the system.

Note: Clearing CMOS will also clear all passwords.

Do not use the PW_ON connector to clear CMOS.

JBT1 contact pads

60

Chapter 2: Installation

COM1

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

I-SATA4~7I-SATA0~3

FANC FAND

CPU2

CPU1

BIOS
LICENSE

JBT1

M.2 CONNECTOR

SAN MAC
MAC CODE

JF1

BAR CODE

IPMI CODE

VGA

USB 2/3

BT1

JNVI2C2

JNVI2C1

PCH

FANA

FAN2

FAN5

FAN1

P2-DIMMC1

P2-DIMMB1

P2-DIMMA1

P2-DIMMA2

P2-DIMMD2

P2-DIMMD1

P2-DIMME1

P2-DIMMF1

FAN6

P1-DIMMA2

P1-DIMMA1

P1-DIMMB1

P1-DIMMC1

JPWR1

JPWR2

JPWR3

JPI2C1

FAN4

LEDBMC

S-UM12

S-SATA0

S-SATA1

FANB

FAN3

JNCSI1

S-SGPIO

JSTBY1

JWD1

JSEN1

COM2

P1-DIMMF1

P1-DIMME1

P1-DIMMD1

P1-DIMMD2

SP1

USB8 (3.0)

JTPM1

JPWR4

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

JUIDB1

(UID)

LED2

(UID-LED)

USB 6/7 (3.0)

JL1

LEDPWR

JSD1

JSD2

JIPMB1

JRK1

JPTG1

JPCIE11

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPME2

LAN 2 LAN 1

USB 0/1

IPMI_LAN

USB 4/5 (3.0)

BMC

JPCIE2

(CPU1 SLOT2 PCI-E 3.0 x16)

JPCIE1

(CPU1 SLOT1 PCI-E 3.0 x8)

JPCIE3

(CPU1 SLOT3 PCI-E 3.0 x8)

JPCIE6

(CPU2 SLOT6 PCI-E 3.0 x16)

JPCIE5

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

(CPU1 SLOT7 PCI-E 3.0 x8)

JPCIE8

(CPU2 SLOT8 PCI-E 3.0 x16)

JPCIE4

(CPU1 SLOT4 PCI-E 3.0 x16)

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

JPCIE10

(CPU2 SLOT10 PCI-E 3.0 x8)

Watch Dog

JWD1 controls the Watch Dog function. Watch Dog is a monitor that can reboot the system
when a software application hangs. Jumping pins 1-2 will cause Watch Dog to reset the
system if an application hangs. Jumping pins 2-3 will generate a non-maskable interrupt
signal for the application that hangs. Watch Dog must also be enabled in BIOS. The default
setting is Reset.

Note: When Watch Dog is enabled, the user needs to write their own application
software to disable it.

Watch Dog

Jumper Settings

Jumper Setting Denition

Pins 1-2 Reset

Pins 2-3 NMI

Open Disabled

1

2

1. Watch Dog

2. CMOS Clear

61

Super X11DPX-T User's Manual

COM1

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

I-SATA4~7I-SATA0~3

FANC FAND

CPU2

CPU1

BIOS
LICENSE

JBT1

M.2 CONNECTOR

SAN MAC
MAC CODE

JF1

BAR CODE

IPMI CODE

VGA

USB 2/3

BT1

JNVI2C2

JNVI2C1

PCH

FANA

FAN2

FAN5

FAN1

P2-DIMMC1

P2-DIMMB1

P2-DIMMA1

P2-DIMMA2

P2-DIMMD2

P2-DIMMD1

P2-DIMME1

P2-DIMMF1

FAN6

P1-DIMMA2

P1-DIMMA1

P1-DIMMB1

P1-DIMMC1

JPWR1

JPWR2

JPWR3

JPI2C1

FAN4

LEDBMC

S-UM12

S-SATA0

S-SATA1

FANB

FAN3

JNCSI1

S-SGPIO

JSTBY1

JWD1

JSEN1

COM2

P1-DIMMF1

P1-DIMME1

P1-DIMMD1

P1-DIMMD2

SP1

USB8 (3.0)

JTPM1

JPWR4

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

JUIDB1

(UID)

LED2

(UID-LED)

USB 6/7 (3.0)

JL1

LEDPWR

JSD1

JSD2

JIPMB1

JRK1

JPTG1

JPCIE11

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPME2

LAN 2 LAN 1

USB 0/1

IPMI_LAN

USB 4/5 (3.0)

BMC

JPCIE2

(CPU1 SLOT2 PCI-E 3.0 x16)

JPCIE1

(CPU1 SLOT1 PCI-E 3.0 x8)

JPCIE3

(CPU1 SLOT3 PCI-E 3.0 x8)

JPCIE6

(CPU2 SLOT6 PCI-E 3.0 x16)

JPCIE5

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

(CPU1 SLOT7 PCI-E 3.0 x8)

JPCIE8

(CPU2 SLOT8 PCI-E 3.0 x16)

JPCIE4

(CPU1 SLOT4 PCI-E 3.0 x16)

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

JPCIE10

(CPU2 SLOT10 PCI-E 3.0 x8)

Manufacturing Mode Select

Close JPME2 to bypass SPI ash security and force the system to use the Manufacturing
Mode, which will allow you to ash the system rmware from a host server to modify system

settings. See the table below for jumper settings.

Manufacturing Mode Select

Jumper Settings

Jumper Setting Denition

Pins 1-2 Normal (Default)

Pins 2-3 Manufacturing Mode

1

1. Manufacturing Mode Select

62

Chapter 2: Installation

COM1

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

I-SATA4~7I-SATA0~3

FANC FAND

CPU2

CPU1

BIOS
LICENSE

JBT1

M.2 CONNECTOR

SAN MAC
MAC CODE

JF1

BAR CODE

IPMI CODE

VGA

USB 2/3

BT1

JNVI2C2

JNVI2C1

PCH

FANA

FAN2

FAN5

FAN1

P2-DIMMC1

P2-DIMMB1

P2-DIMMA1

P2-DIMMA2

P2-DIMMD2

P2-DIMMD1

P2-DIMME1

P2-DIMMF1

FAN6

P1-DIMMA2

P1-DIMMA1

P1-DIMMB1

P1-DIMMC1

JPWR1

JPWR2

JPWR3

JPI2C1

FAN4

LEDBMC

S-UM12

S-SATA0

S-SATA1

FANB

FAN3

JNCSI1

S-SGPIO

JSTBY1

JWD1

JSEN1

COM2

P1-DIMMF1

P1-DIMME1

P1-DIMMD1

P1-DIMMD2

SP1

USB8 (3.0)

JTPM1

JPWR4

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

JUIDB1

(UID)

LED2

(UID-LED)

USB 6/7 (3.0)

JL1

LEDPWR

JSD1

JSD2

JIPMB1

JRK1

JPTG1

JPCIE11

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPME2

LAN 2 LAN 1

USB 0/1

IPMI_LAN

USB 4/5 (3.0)

BMC

JPCIE2

(CPU1 SLOT2 PCI-E 3.0 x16)

JPCIE1

(CPU1 SLOT1 PCI-E 3.0 x8)

JPCIE3

(CPU1 SLOT3 PCI-E 3.0 x8)

JPCIE6

(CPU2 SLOT6 PCI-E 3.0 x16)

JPCIE5

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

(CPU1 SLOT7 PCI-E 3.0 x8)

JPCIE8

(CPU2 SLOT8 PCI-E 3.0 x16)

JPCIE4

(CPU1 SLOT4 PCI-E 3.0 x16)

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

JPCIE10

(CPU2 SLOT10 PCI-E 3.0 x8)

10Gb LAN1/2 Enable/Disable

JPTG1 allows you to enable or disable the 10Gb LAN1/LAN2. The default setting is Enabled.

10Gb LAN Enable/Disable

Jumper Settings

Jumper Setting Denition

Pins 1-2 Enabled

Pins 2-3 Disabled

1

1. 10Gb LAN1/LAN2 Enable/
Disable

63

Super X11DPX-T User's Manual

COM1

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

I-SATA4~7I-SATA0~3

FANC FAND

CPU2

CPU1

BIOS
LICENSE

JBT1

M.2 CONNECTOR

SAN MAC
MAC CODE

JF1

BAR CODE

IPMI CODE

VGA

USB 2/3

BT1

JNVI2C2

JNVI2C1

PCH

FANA

FAN2

FAN5

FAN1

P2-DIMMC1

P2-DIMMB1

P2-DIMMA1

P2-DIMMA2

P2-DIMMD2

P2-DIMMD1

P2-DIMME1

P2-DIMMF1

FAN6

P1-DIMMA2

P1-DIMMA1

P1-DIMMB1

P1-DIMMC1

JPWR1

JPWR2

JPWR3

JPI2C1

FAN4

LEDBMC

S-UM12

S-SATA0

S-SATA1

FANB

FAN3

JNCSI1

S-SGPIO

JSTBY1

JWD1

JSEN1

COM2

P1-DIMMF1

P1-DIMME1

P1-DIMMD1

P1-DIMMD2

SP1

USB8 (3.0)

JTPM1

JPWR4

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

JUIDB1

(UID)

LED2

(UID-LED)

USB 6/7 (3.0)

JL1

LEDPWR

JSD1

JSD2

JIPMB1

JRK1

JPTG1

JPCIE11

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPME2

LAN 2 LAN 1

USB 0/1

IPMI_LAN

USB 4/5 (3.0)

BMC

JPCIE2

(CPU1 SLOT2 PCI-E 3.0 x16)

JPCIE1

(CPU1 SLOT1 PCI-E 3.0 x8)

JPCIE3

(CPU1 SLOT3 PCI-E 3.0 x8)

JPCIE6

(CPU2 SLOT6 PCI-E 3.0 x16)

JPCIE5

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

(CPU1 SLOT7 PCI-E 3.0 x8)

JPCIE8

(CPU2 SLOT8 PCI-E 3.0 x16)

JPCIE4

(CPU1 SLOT4 PCI-E 3.0 x16)

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

JPCIE10

(CPU2 SLOT10 PCI-E 3.0 x8)

LAN 1/LAN 2

IPMI LAN

(X8ST3-F)

2.9 LED Indicators

IPMI-Dedicated LAN LEDs

A dedicated IPMI LAN is also included on the motherboard. The amber LED on the right of
the IPMI LAN port indicates activity, while the green LED on the left indicates the speed of
the connection. See the table below for more information.

IPMI LAN LEDs

IPMI LAN

Activity LEDLink LED

LAN1/LAN2 LEDs

Two LAN ports (LAN1/LAN2) are located on the I/O back panel of the motherboard. Each
Ethernet LAN port has two LEDs. The green LED indicates activity, while the other Link LED

may be green, amber or o󰀨 to indicate the speed of the connections. See the tables below

for more information.

Color Status Denition

O󰀨 O󰀨

Green:

Solid

Amber

Blinking

Link/Speed

(Left)

Activity

(Right)

No

Connection

100 Mb/s

1Gb/s

Link LED

Rear View (when facing the

rear side of the chassis)

Activity LED

LAN1/LAN2 Activity LED (Right)

LED State

Color Status Denition

Green Flashing Active

64

10G LAN1/LAN2 Link LED (Left)

LED State

Color Denition

O󰀨

10 Mbps, 100 Mbps, No

Connection

Green 10 Gbps

Amber 1 Gbps

1

1. IPMI-Dedicated LAN LEDs

2. LAN1/LAN2 LEDs

1

2

Chapter 2: Installation

COM1

LAN
CTRL

DESIGNED IN USA

X11DPX-T

REV:1.01A

I-SATA4~7I-SATA0~3

FANC FAND

CPU2

CPU1

BIOS
LICENSE

JBT1

M.2 CONNECTOR

SAN MAC
MAC CODE

JF1

BAR CODE

IPMI CODE

VGA

USB 2/3

BT1

JNVI2C2

JNVI2C1

PCH

FANA

FAN2

FAN5

FAN1

P2-DIMMC1

P2-DIMMB1

P2-DIMMA1

P2-DIMMA2

P2-DIMMD2

P2-DIMMD1

P2-DIMME1

P2-DIMMF1

FAN6

P1-DIMMA2

P1-DIMMA1

P1-DIMMB1

P1-DIMMC1

JPWR1

JPWR2

JPWR3

JPI2C1

FAN4

LEDBMC

S-UM12

S-SATA0

S-SATA1

FANB

FAN3

JNCSI1

S-SGPIO

JSTBY1

JWD1

JSEN1

COM2

P1-DIMMF1

P1-DIMME1

P1-DIMMD1

P1-DIMMD2

SP1

USB8 (3.0)

JTPM1

JPWR4

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

ALWAYS POPULATE DIMMx1 FIRST

JUIDB1

(UID)

LED2

(UID-LED)

USB 6/7 (3.0)

JL1

LEDPWR

JSD1

JSD2

JIPMB1

JRK1

JPTG1

JPCIE11

(CPU2 SLOT11 PCI-E 3.0 x4 (IN x8))

JPME2

LAN 2 LAN 1

USB 0/1

IPMI_LAN

USB 4/5 (3.0)

BMC

JPCIE2

(CPU1 SLOT2 PCI-E 3.0 x16)

JPCIE1

(CPU1 SLOT1 PCI-E 3.0 x8)

JPCIE3

(CPU1 SLOT3 PCI-E 3.0 x8)

JPCIE6

(CPU2 SLOT6 PCI-E 3.0 x16)

JPCIE5

(CPU2 SLOT5 PCI-E 3.0 x8)

JPCIE7

(CPU1 SLOT7 PCI-E 3.0 x8)

JPCIE8

(CPU2 SLOT8 PCI-E 3.0 x16)

JPCIE4

(CPU1 SLOT4 PCI-E 3.0 x16)

JPCIE9

(CPU2 SLOT9 PCI-E 3.0 x8)

JPCIE10

(CPU2 SLOT10 PCI-E 3.0 x8)

Onboard Power LED

LEDPWR is an Onboard Power LED. When this LED is lit, it means that power is present

on the motherboard. In suspend mode, this LED will blink on and o󰀨. Be sure to turn o󰀨 the

system and unplug the power cord(s) before removing or installing components.

Onboard Power LED Indicator

LED Color Denition

System O󰀨

O󰀨

(power cable not

connected)

Green System On

BMC Heartbeat LED

LEDBMC is the BMC heartbeat LED. When the LED is blinking green, BMC is functioning
normally. See the table below for the LED status.

BMC Heartbeat LED Indicator

LED Color Denition

Green:

Blinking

BMC Normal

Unit ID LED

A rear UID LED indicator at LED2 is located near the UID switch on the I/O back panel. This

UID indicator provides easy identication of a system unit that may need service.

UID LED Indicator

LED Color Denition

Blue: On Unit Identied

2

3

1. Onboard Power LED

2. BMC Heartbeat LED

3. UID LED

1

65

Super X11DPX-T User's Manual

Chapter 3

Troubleshooting

3.1 Troubleshooting Procedures

Use the following procedures to troubleshoot your system. If you have followed all of the
procedures below and still need assistance, refer to the ‘Technical Support Procedures’ and/
or ‘Returning Merchandise for Service’ section(s) in this chapter. Always disconnect the AC
power cord before adding, changing or installing any non hot-swap hardware components.

Before Power On

1. Check that the power LED on the motherboard is on.

2. Make sure that the power connector is connected to your power supply.

3. Make sure that no short circuits exist between the motherboard and chassis.

4. Disconnect all cables from the motherboard, including those for the keyboard and
mouse.

5. Remove all add-on cards.

6. Install a CPU, a heatsink*, and connect the internal speaker and the power LED to the
motherboard. Check all jumper settings as well. (Make sure that the heatsink is fully
seated.)

7. Use the correct type of onboard CMOS battery (CR2032) as recommended by the
manufacturer. To avoid possible explosion, do not install the CMOS battery upside down.

No Power

1. Make sure that no short circuits exist between the motherboard and the chassis.

2. Verify that all jumpers are set to their default positions.

3. Check that the 115V/230V switch on the power supply is properly set.

4. Turn the power switch on and o󰀨 to test the system.

5. The battery on your motherboard may be old. Check to verify that it still supplies
~3VDC. If it does not, replace it with a new one.

66

Chapter 3: Troubleshooting

No Video

1. If the power is on but you have no video, remove all the add-on cards and cables.

2. Use the speaker to determine if any beep codes exist. Refer to Appendix A for details on
beep codes.

System Boot Failure

If the system does not display POST (Power-On-Self-Test) or does not respond after the
power is turned on, check the following:

1. Check for any error beep from the motherboard speaker.

• If there is no error beep, try to turn on the system without DIMM modules installed. If there

is still no error beep, replace the motherboard.

• If there are error beeps, clear the CMOS settings by unplugging the power cord and

contacting both pads on the CMOS Clear Jumper (JBT1). Refer to Chapter 2.

2. Remove all components from the motherboard, especially the DIMM modules. Make
sure that system power is on and that memory error beeps are activated.

3. Turn on the system with only one DIMM module installed. If the system boots, check for
bad DIMM modules or slots by following the Memory Errors Troubleshooting procedure
in this Chapter.

Memory Errors

1. Make sure that the DIMM modules are properly and fully installed.

2. Conrm that you are using the correct memory. Also, it is recommended that you use
the same memory type and speed for all DIMMs in the system. See Section 2.4 for
memory details.

3. Check for bad DIMM modules or slots by swapping modules between slots and noting
the results.

4. Check the power supply voltage 115V/230V switch.

67

Super X11DPX-T User's Manual

Losing the System's Setup Conguration

1. Make sure that you are using a high quality power supply. A poor quality power supply
may cause the system to lose the CMOS setup information. Refer to Section 1.5 for
details on recommended power supplies.

2. The battery on your motherboard may be old. Check to verify that it still supplies
~3VDC. If it does not, replace it with a new one.

3. If the above steps do not x the setup conguration problem, contact your vendor for
repairs.

When the System Becomes Unstable

A. If the system becomes unstable during or after OS installation, check the following:

1. CPU/BIOS support: Make sure that your CPU is supported and that you have the latest
BIOS installed in your system.

2. Memory support: Make sure that the memory modules are supported by testing the
modules using memtest86 or a similar utility.

Note: Refer to the product page on our website at http://www.supermicro.com for
memory and CPU support and updates.

3. HDD support: Make sure that all hard disk drives (HDDs) work properly. Replace the
bad HDDs with good ones.

4. System cooling: Check the system cooling to make sure that all heatsink fans and CPU/
system fans, etc., work properly. Check the hardware monitoring settings in the IPMI
to make sure that the CPU and system temperatures are within the normal range. Also
check the front panel Overheat LED and make sure that it is not on.

5. Adequate power supply: Make sure that the power supply provides adequate power to
the system. Make sure that all power connectors are connected. Please refer to our
website for more information on the minimum power requirements.

6. Proper software support: Make sure that the correct drivers are used.

B. If the system becomes unstable before or during OS installation, check the following:

1. Source of installation: Make sure that the devices used for installation are working
properly, including boot devices such as CD.

2. Cable connection: Check to make sure that all cables are connected and working
properly.

68

Chapter 3: Troubleshooting

3. Using the minimum conguration for troubleshooting: Remove all unnecessary
components (starting with add-on cards rst), and use the minimum conguration (but

with a CPU and a memory module installed) to identify the trouble areas. Refer to the
steps listed in Section A above for proper troubleshooting procedures.

4. Identifying bad components by isolating them: If necessary, remove a component in
question from the chassis, and test it in isolation to make sure that it works properly.
Replace a bad component with a good one.

5. Check and change one component at a time instead of changing several items at the
same time. This will help isolate and identify the problem.

6. To nd out if a component is good, swap this component with a new one to see if the
system will work properly. If so, then the old component is bad. You can also install the
component in question in another system. If the new system works, the component is
good and the old system has problems.

69

Super X11DPX-T User's Manual

3.2 Technical Support Procedures

Before contacting Technical Support, please take the following steps. Also, note that as a

motherboard manufacturer, we do not sell directly to end-users, so it is best to rst check with

your distributor or reseller for troubleshooting services. They should know of any possible

problem(s) with the specic system conguration that was sold to you.

1. Please review the ‘Troubleshooting Procedures’ and 'Frequently Asked Questions'
(FAQs) sections in this chapter or see the FAQs on our website before contacting
Technical Support.

2. BIOS upgrades can be downloaded from our website. Note: Not all BIOS can be

ashed depending on the modications to the boot block code.

3. If you still cannot resolve the problem, include the following information when contacting
us for technical support:

• Motherboard model and PCB revision number

• BIOS release date/version (this can be seen on the initial display when your system rst

boots up)

• System conguration

An example of a Technical Support form is posted on our website.

Distributors: For immediate assistance, please have your account number ready when
contacting our technical support department by e-mail.

70

Chapter 3: Troubleshooting

3.3 Battery Removal and Installation

Battery Removal

To remove the onboard battery, follow the steps below:

1. Power o󰀨 your system and unplug your power cable.

2. Locate the onboard battery as shown below.

3. Using a tool such as a pen or a small screwdriver, push the battery lock outwards to
unlock it. Once unlocked, the battery will pop out from the holder.

4. Remove the battery.

Proper Battery Disposal

Please handle used batteries carefully. Do not damage the battery in any way; a damaged
battery may release hazardous materials into the environment. Do not discard a used battery

in the garbage or a public landll. Please comply with the regulations set up by your local

hazardous waste management agency to dispose of your used battery properly.

Battery Installation

1. To install an onboard battery, follow the steps 1 & 2 above and continue below:

2. Identify the battery's polarity. The positive (+) side should be facing up.

3. Insert the battery into the battery holder and push it down until you hear a click to
ensure that the battery is securely locked.

Note: When replacing a battery, be sure to only replace it with the same type.

71

OR

Super X11DPX-T User's Manual

3.4 Frequently Asked Questions

Question: What type of memory does my motherboard support?

Answer: This motherboard supports up to 4TB of 3DS Load Reduced DIMM (3DS LRDIMM),

3DS Registered DIMM (3DS RDIMM), or up to 2TB of Load Registered DIMM (LRDIMM),
with speeds of 2933*/2666/2400/2133/1866/1600/1333 MHz modules in 16 memory slots.
See Section 2.4 for details on Memory Support and Installation.

Notes: 1. Support for 2933MHz memory is dependent on the CPU SKU. 2. The memory

capacity support will di󰀨er according to the processor SKUs.

Question: Why can't I turn o󰀨 the power using the momentary power on/o󰀨 switch?

Answer: The instant power o󰀨 function is controlled in the BIOS by the Power Button Mode
setting. When the On/O󰀨 feature is enabled, the motherboard will have instant o󰀨 capabilities

as long as the BIOS has control of the system. When the Standby or Suspend feature is

enabled or when the BIOS is not in control such as during memory count (the rst screen
that appears when the system is turned on), the momentary on/o󰀨 switch must be held for

more than four seconds to shut down the system. This feature is required to implement the
ACPI features on the motherboard.

Question: How do I update my BIOS?

Answer: It is recommended that you do not upgrade your BIOS if you are not experiencing

any problems with your system. Updated BIOS les are located on our website at http://

www.supermicro.com/ResourceApps/BIOS_IPMI_Intel.html. Please check our BIOS warning

message and the information on how to update your BIOS on our website. Select your

motherboard model and download the BIOS le to your computer. Also, check the current

BIOS revision to make sure that it is newer than your BIOS before downloading. Please refer
to the following section for the instructions on how to update your BIOS under UEFI Shell.

Note: The SPI BIOS chip used on this motherboard cannot be removed. Send your

motherboard back to our RMA Department at Supermicro for repair. For BIOS Recovery
instructions, please refer to the AMI BIOS Recovery Instructions posted at http://www.

supermicro.com/support/manuals/.

72

Chapter 3: Troubleshooting

Question: How do I update my BIOS under UEFI Shell?

Note: We do not recommend that you update your BIOS if you are not experiencing a

BIOS-related problem. If you need to update your BIOS, please follow the steps below
to properly update your BIOS under UEFI Shell.

1. Download and save the BIOS update package to your computer.

2. Extract the les from the UEFI folder of the BIOS package to a USB stick.

Note: The USB stick doesn't have to be bootable; however, it has to be formatted with

the FAT/FAT32 le system.

3. Insert the USB stick into a USB port, boot to the UEFI Built-In Shell, and enter the following
commands to start the BIOS update:

Shell> fs0:

fs0:\> cd UEFI

fs0:\UEFI> ash.nsh BIOSname#.###

4. The FLASH.NSH script will compare the Flash Descriptor Table (FDT) code in the new
BIOS with the existing one in the motherboard:

a. If a di󰀨erent FDT is found

• A new le, STARTUP.NSH, will be created, and the system will automatically reboot in 10

seconds without you pressing any key. BIOS will be updated after the system reboots.

• You can also press <Y> to force an immediate system reboot to shorten the process. Dur-

ing system reboot, press the <F11> key to invoke the boot menu and boot into the build-in
UEFI Shell. Your BIOS will be updated automatically.

b. If the FDT is the same

• BIOS update will be immediately performed without a system reboot initiated.

Warning: Do not shut down or reset the system while updating the BIOS to prevent possible
system boot failure!)

5. Perform an A/C power cycle after the message indicating the BIOS update has completed.

6. Go to the BIOS setup utility, and restore the BIOS settings.

73

Super X11DPX-T User's Manual

3.5 Returning Merchandise for Service

A receipt or copy of your invoice marked with the date of purchase is required before any
warranty service is rendered. You can obtain service by calling your vendor for a Returned
Merchandise Authorization (RMA) number. When returning to the manufacturer, the RMA
number should be prominently displayed on the outside of the shipping carton and mailed
prepaid or hand-carried. Shipping and handling charges will be applied for all orders that
must be mailed when service is complete.

For faster service, RMA authorizations may be requested online (http://www.supermicro.com/

support/rma/).

This warranty only covers normal consumer use and does not cover damages incurred in
shipping or from failure due to the alteration, misuse, abuse or improper maintenance of
products.

During the warranty period, contact your distributor rst for any product problems.

74

Chapter 4: UEFI BIOS

Chapter 4

UEFI BIOS

4.1 Introduction

This chapter describes the AMIBIOS™ Setup utility for the X11DPX-T motherboard. The BIOS

is stored on a chip and can be easily upgraded using a ash program.

Note: Due to periodic changes to the BIOS, some settings may have been added
or deleted and might not yet be recorded in this manual. Please refer to the Manual

Download area of our website for any changes to BIOS that may not be reected in

this manual.

Starting the Setup Utility

To enter the BIOS Setup Utility, hit the <Delete> key while the system is booting up. (In
most cases, the <Delete> key is used to invoke the BIOS setup screen. There are a few
cases when other keys are used, such as <F1>, <F2>, etc.) Each main BIOS menu option
is described in this manual.

The Main BIOS screen has two main frames. The left frame displays all the options that can

be congured. “Grayed-out” options cannot be congured. The right frame displays the key

legend. Above the key legend is an area reserved for a text message. When an option is
selected in the left frame, it is highlighted in white. Often a text message will accompany it.
(Note that the AMI BIOS has default text messages built in. We retain the option to include,
omit, or change any of these text messages.) Settings printed in Bold are the default values.

A " " indicates a submenu. Highlighting such an item and pressing the <Enter> key will
open the list of settings within that submenu.

The BIOS setup utility uses a key-based navigation system called hot keys. Most of these
hot keys (<F1>, <F2>, <F3>, <F4>, <Enter>, <ESC>, <Arrow> keys, etc.) can be used at
any time during the setup navigation process.

75

Super X11DPX-T User's Manual

4.2 Main Setup

When you rst enter the AMI BIOS setup utility, you will enter the Main setup screen. You can

always return to the Main setup screen by selecting the Main tab on the top of the screen. The
Main BIOS setup screen is shown below. The following Main menu items will be displayed:

System Date/System Time

Use this feature to change the system date and time. Highlight System Date or System Time
using the arrow keys. Enter new values using the keyboard. Press the <Tab> key or the arrow

keys to move between elds. The date must be entered in MM/DD/YYYY format. The time

is entered in HH:MM:SS format.

Note: The time is in the 24-hour format. For example, 5:30 P.M. appears as 17:30:00.
The date's default value is the BIOS build after RTC reset.

Supermicro X11DPX-T

BIOS Version

This feature displays the version of the BIOS ROM used in the system.

Build Date

This feature displays the date when the version of the BIOS ROM used in the system was built.

CPLD Version

This feature displays the version of the CPLD (Complex-Programmable Logical Device) used

in the system.

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Memory Information

Total Memory

This feature displays the total size of memory available in the system.

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4.3 Advanced Setup Congurations

Use the arrow keys to select Boot Setup and press <Enter> to access the submenu items.

Warning: Take caution when changing the Advanced settings. An incorrect value, an incorrect
DRAM frequency, or an incorrect BIOS timing setting may cause the system to malfunction.
When this occurs, restore the setting to the manufacture default setting.

Boot Feature

Quiet Boot

Use this feature to select the screen display between the POST messages and the OEM logo
upon bootup. Select Disabled to display the POST messages. Select Enabled to display the
OEM logo instead of the normal POST messages. The options are Disabled and Enabled.

Option ROM Messages

Use this feature to set the display mode for the Option ROM. Select Keep Current to display
the current AddOn ROM setting. Select Force BIOS to use the Option ROM display set by
the system BIOS. The options are Force BIOS and Keep Current.

Bootup NumLock State

Use this feature to set the Power-on state for the <Numlock> key. The options are On and O󰀨.

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Wait For "F1" If Error

Use this feature to force the system to wait until the 'F1' key is pressed if an error occurs.
The options are Disabled and Enabled.

INT19 (Interrupt 19) Trap Response

Interrupt 19 is the software interrupt that handles the boot disk function. When this feature
is set to Immediate, the ROM BIOS of the host adaptors will "capture" Interrupt 19 at bootup
immediately and allow the drives that are attached to these host adaptors to function as
bootable disks. If this feature is set to Postponed, the ROM BIOS of the host adaptors will not
capture Interrupt 19 immediately and allow the drives attached to these adaptors to function
as bootable devices at bootup. The options are Immediate and Postponed.

Re-try Boot

When EFI (Expansible Firmware Interface) Boot is selected, the system BIOS will automatically
reboot the system from an EFI boot device after an initial boot failure. Select Legacy Boot to
allow the BIOS to automatically reboot the system from a Legacy boot device after an initial
boot failure. The options are Disabled, Legacy Boot, and EFI Boot.

Install Windows 7 USB support

Enable this feature to use the USB keyboard and mouse during the Windows 7 installation,
since the native XHCI driver support is unavailable. Use a SATA optical drive as a USB drive.

USB CD/DVD drives are not supported. Disable this feature after the XHCI driver has been

installed in Windows. The options are Disabled and Enabled.

Port 61h Bit-4 Emulation

Select Enabled to support the emulation of Port 61h bit-4 toggling in SMM (System
Management Mode). The options are Disabled and Enabled.

Power Conguration

Watch Dog Function

If enabled, the Watch Dog Timer will allow the system to reset or generate NMI based on
jumper settings when it is expired for more than 5 minutes. The options are Disabled and
Enabled.

Restore on AC Power Loss

Use this feature to set the power state after a power outage. Select Stay-Off for

the system power to remain o󰀨 after a power loss. Select Power-On for the system

power to be turned on after a power loss. Select Last State to allow the system to
resume its last power state before a power loss. The options are Stay O󰀨, Power On,
and Last State.

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Power Button Function

This feature controls how the system shuts down when the power button is pressed. Select 4

Seconds Override for the user to power o󰀨 the system after pressing and holding the power
button for 4 seconds or longer. Select Instant O󰀨 to instantly power o󰀨 the system as soon

as the user presses the power button. The options are Instant O󰀨 and 4 Seconds Override.

Throttle on Power Fail

Throttling improves reliability and reduces power consumption in the processor via automatic
voltage control during processor idle states. Select Enabled to decrease the system power
by throttling CPU frequency when one power supply is failed. The options are Disabled and
Enabled.

CPU Conguration

This submenu displays the information of the CPU as detected by the BIOS. It also allows

the user to conguration CPU settings:

• Processor BSP Revision

• Processor Socket

• Processor ID

• Processor Frequency

• Processor Max Ration

• Processor Min Ration

• Microcode Revision

• L1 Cache RAM

• L2 Cache RAM

• L3 Cache RAM

• Processor 0 Version

• Processor 1 Version

Hyper-Threading [All] (Available when supported by the CPU)

Select Enabled to support Intel Hyper-threading Technology to enhance CPU performance.
The options are Disable and Enable.

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Execute Disable Bit (Available if supported by the OS & the CPU)

Select Enable to enable the Execute-Disable Bit which will allow the processor to designate
areas in the system memory where an application code can execute and where it cannot,

thus preventing a worm or a virus from ooding illegal codes to overwhelm the processor or

damage the system during an attack. (Please refer to Intel's website for more information.)
The options are Disable and Enable.

Intel Virtualization Technology (Available when supported by the CPU)

Select Enable to use Intel Virtualization Technology which will allow multiple workloads to

share the same set of common resources. On shared virtualized hardware, various workloads
(or tasks) can co-exist, sharing the same resources, while functioning in full independence
from each other, and migrating freely across multi-level infrastructures and scale as needed.
The options are Disable and Enable.

Note: If a change is made to this setting, you will need to reboot the system for the

change to take e󰀨ect. Refer to Intel’s website for detailed information.

PPIN Control

Select Unlock/Enable to use the Protected-Processor Inventory Number (PPIN) in the system.
The options are Unlock/Disable and Unlock/Enable.

Hardware Prefetcher (Available when supported by the CPU)

If this feature is set to Enable, the hardware prefetcher will prefetch streams of data and
instructions from the main memory to the L2 cache to improve CPU performance. The options
are Enable and Disable.

Adjacent Cache Prefetch (Available when supported by the CPU)

The CPU prefetches the cache line for 64 bytes if this feature is set to Disable. The CPU
prefetches both cache lines for 128 bytes as comprised if this feature is set to Enable. The
options are Enable and Disable.

DCU Streamer Prefetcher (Available when supported by the CPU)

Select Enabled to enable Intel CPU Advanced Encryption Standard (AES) Instructions for
CPU to enhance data integrity. The options are Enable and Disable.

DCU IP Prefetcher (Available when supported by the CPU)

If this feature is set to Enable, the DCU (Data Cache Unit) IP prefetcher will prefetch IP
addresses in advance to improve network connectivity and system performance. The options
are Enable and Disable.

LLC Prefetch

Select Enable to support the LLC prefetch on all threads. The options are Disable and Enable.

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Extended APIC (Extended Advanced Programmable Interrupt Controller)

Select Enable to use the extended APIC (Advanced Programmable Interrupt Control) support
to enhance power management. The options are Disable and Enable.

AES-NI

Select Enable to use the Intel Advanced Encryption Standard (AES) New Instructions (NI) to
ensure data security. The options are Disable and Enable.

Advanced Power Management Conguration

CPU P State Control

SpeedStep (Pstates)

EIST (Enhanced Intel SpeedStep™ Technology) allows the system to automatically adjust
processor voltage and core frequency to reduce power consumption and heat dissipation.
The options are Disable and Enable.

Activate PBF (Available when SpeedStep is set to Enable)

Select Enable to enable Prioritized Base Frequency (PBF) feature support which will
enhance CPU performance. The options are Disable and Enable.

Congure PBF (Available when Activate PBF is set to Enable)

Select Enable to allow the BIOS to congure high priority CPU cores as Prioritized Base
Frequency (PBF) so that software programs do not have to congure the PBF (Prioritized

Base Frequency) settings. The options are Enable and Disable.

EIST PSD Function

This feature allows the user to change the P-State (Power-Performance State) coordina­tion type. P-State is also known as "SpeedStep" for Intel processors. Select HW_ALL to
change the P-State coordination type for all hardware components only. Select SW_ALL
to change the P-State coordination type for all software installed in the system. Select

SW_ANY to change the P-State coordination type for a particular software program
specied by the user in the system. The options are HW_ALL, SW_ALL, and SW_ANY.

Turbo Mode (Available when Intel® EIST Technology is enabled)

Select Enable to use the Turbo Mode to boost system performance. The options are
Disable and Enable.

Hardware PM State Control

Hardware P-States

This feature enables the hardware P-States support. The options are Disable, Native
Mode, Out of Band Mode, and Native Mode with No Legacy Support.

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CPU C State Control

Autonomous Core C-State
Use this feature to enable the autonomous core C-State control. The options are Dis-

able and Enable.

CPU C6 report

Select Enable to allow the BIOS to report the CPU C6 State (ACPI C3) to the operating
system. During the CPU C6 State, the power to all cache is turned o󰀨. The options are

Disable, Enable, and Auto.

Enhanced Halt State (C1E)

Select Enable to use Enhanced Halt-State technology, which will signicantly reduce

the CPU's power consumption by reducing the CPU's clock cycle and voltage during a
Halt-state. The options are Disable and Enable.

Package C State Control

Package C State

This feature allows the user to set the limit on the C-State package register. The options

are C0/C1 state, C2 state, C6 (non Retention) state, C6 (Retention) state, No Limit, and

Auto.

CPU T State Control

Software Controlled T-States

This feature enables the software controlled T-States support. The options are Disable
and Enable

Chipset Conguration

Warning: Setting the wrong values in the following features may cause the system to malfunc­tion.

North Bridge

This feature allows the user to congure the following North Bridge settings.

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UPI Conguration

UPI Conguration

The following information will be displayed:

• Number of CPU

• Number of IIO

• Current UPI Link Speed

• Current UPI Link Frequency

• UPI Global MMIO Low Base/Limit

• UPI Global MMIO High Base/Limit

• UPI Pci-e Conguration Base/Size

Degrade Precedence

Select Topology Precedence to degrade features if system options are in conict. Select
Feature Precedence to degrade topology if system options are in conict. The options

are Topology Precedence and Feature Precedence.

Link L0p Enable

Select Enable for the QPI to enter the L0p state for power saving. The options are Dis­able, Enable, and Auto.

Link L1 Enable

Select Enable for the QPI to enter the L1 state for power saving. The options are Dis­able, Enable, and Auto.

IO Directory Cache (IODC)

Use this feature to enable the IO Directory Cache (IODC) support. The options are Dis­able, Auto, Enable for Remote InvItoM Hybrid Push, InvItoM AllocFlow, Enable for Re-

mote InvItoM Hybrid AllocNonAlloc, and Enable for Remote InvItoM and Remote WViLF.

Isoc Mode

Select Enable to enable Isochronous support to meet QoS (Quality of Service) require-

ments. This feature is especially important for Virtualization Technology. The options are

Disable, Enable, and Auto.

Memory Conguration

Integrated Memory Controller (iMC)

Enforce POR

Select Enable to enforce POR restrictions on DDR4 frequency and voltage programming.
The options are POR and Disable.

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PPR Type

Post Package Repair (PPR) is a new feature available for the DDR4 Technology. PPR
provides additional spare capacity within a DDR4 DRAM module that is used to replace

faulty cell areas detected during system boot. PPR o󰀨ers two types of memory repairs.
Soft Post Package Repair (sPPR) provides a quick, temporary x on a raw element in a

bank group of a DDR4 DRAM device, while hard Post Package Repair (hPPR) will take
a longer time to provide permanent repair on a raw element. The options are Auto, Hard
PPR, Soft PPR, and PPR Disabled.

Memory Frequency

Use this feature to set the maximum memory frequency for onboard memory modules.
The options are Auto, 1866, 2000, 2133, 2400, 2666, and 2933. (Note: 2933 MHz mem-

ory is supported by 2nd Gen Intel Xeon Scalable-SP (82xx/62xx series) processors only.)

Data Scrambling for NVMDIMM

Select Enable to enable data scrambling to enhance system performance and data in­tegrity. The options are Auto, Disable, and Enable.

Data Scrambling for DDR4

Use this feature to enable data scrambling for DDR4. The options are Auto, Disable,
and Enable.

Enable ADR

Select Enable for ADR (Automatic Diagnostic Repository) support to enhance memory
performance. The options are Disable and Enable.

Refresh Options

Use this feature to select the self refresh mode. The options are Accelerated Self Refresh
and 2x Refresh.

Memory Topology

The following information will be displayed: P1 DIMMA1/P1 DIMMB1/P1 DIMMC1/P1
DIMMD1/P1 DIMME1/P1 DIMMF1

Memory RAS (Reliability_Availability_Serviceability) Conguration

Memory RAS Conguration Setup

Use this submenu to congure the following Memory RAS settings.

Static Virtual Lockstep Mode

Select Enable to support the static virtual lockstep mode. The options are Disable
and Enable.

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Mirror Mode

Use this feature to select the mirror mode. The options are Disable, Mirror Mode 1LM,
and Mirror Mode 2LM. If this feature is set to Mirror Mode 1LM or Mirror Mode 2LM,

the available memory capacity will be reduced by 50 percent.

UEFI ARM Mirror

Select Enable to support the UEFI-based address range mirroring with setup option.
The options are Disable and Enable.

Memory Rank Sparing

Select Enable to enable memory-sparing support for memory ranks to improve memory
performance. The options are Disable and Enable.

*If the feature, Memory Rank Sparing, is set to Enable, the following features
will become available for user's conguration:

Multi Rank Sparing

Use this feature to set the multiple rank sparing number. The default setting and the
maximum is two ranks per channel. The options are One Rank and Two Rank.

Correctable Error Threshold

Use this feature to enter the threshold value for correctable memory errors. The default
setting is 10.

SDDC Plus One

Single Device Data Correction (SDDC) allows data to be reconstructed when one of
the memory devices fails on a DIMM. Use this feature to enable the SDDC support.

The options are Disable and Enable.

ADDDC Sparing

Adaptive Double Device Data Correction (ADDDC) Sparing detects the predetermined
threshold for correctable errors, copying the contents of the failing DIMM to spare
memory. The failing DIMM or memory rank will then be disabled. The options are Dis-

able and Enable.

Patrol Scrub

Patrol Scrubbing is a process that allows the CPU to correct correctable memory errors
detected on a memory module and send the correction to the requestor (the original
source). When this feature is set to Enable, read-and-write will be performed every
16K cycles per cache line if there is no delay caused by internal processing. The op­tions are Disable and Enable.

Patrol Scrub Interval

This feature allows you to decide how many hours the system should wait before the
next complete patrol scrub is performed. Use the keyboard to enter a value from 0-24.
The Default setting is 24.

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IIO Conguration

IIO Conguration

EV DFX Features

When this feature is set to Enable, the EV_DFX Lock Bits that are located on a proces­sor will always remain clear during electric tuning. The options are Disable and Enable.

CPU1 Conguration

IOU0 (IIO PCIe Br1)

This feature congures the PCIe port Bifurcation setting for a PCIe port specied by

the user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

IOU1 (IIO PCIe Br2)

This feature congures the PCIe port Bifurcation setting for a PCIe port specied by

the user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

IOU2 (IIO PCIe Br3)

This feature congures the PCIe port Bifurcation setting for a PCIe port specied by

the user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

CPU1 SLOT2 PCI-E 3.0 x16

Link Speed

Use this feature to select the link speed for the PCIe port. The options are Auto,

Gen 1 (2.5 GT/s), Gen 2 (5 GT/s), and Gen 3 (8 GT/s).

PCI-E Port Link Status

PCI-E Port Link Max

PCI-E Port Link Speed

PCI-E Port Clocking

The options are Distinct and Common. If this item is set to Distinct, this component
and the component at the opposite end of the Link are operating with separate refer­ence clock sources. If this item is set to Common, this component and the component
at the opposite end of the Link are operating with a common clock source.

PCI-E Port Max Payload Size

Select Auto for the system BIOS to automatically set the maximum payload value
for a PCIe device to enhance system performance. The options are 128B, 256B,
and Auto.

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CPU1 SLOT4 PCI-E 3.0 x16

Link Speed

Use this feature to select the link speed for the PCIe port. The options are Auto,

Gen 1 (2.5 GT/s), Gen 2 (5 GT/s), and Gen 3 (8 GT/s).

PCI-E Port Link Status

PCI-E Port Link Max

PCI-E Port Link Speed

PCI-E Port Clocking

The options are Distinct and Common. If this item is set to Distinct, this component
and the component at the opposite end of the Link are operating with separate refer­ence clock sources. If this item is set to Common, this component and the component
at the opposite end of the Link are operating with a common clock source.

PCI-E Port Max Payload Size

Select Auto for the system BIOS to automatically set the maximum payload value
for a PCIe device to enhance system performance. The options are 128B, 256B,
and Auto.

CPU1 SLOT9 PCI-E 3.0 x16

Link Speed

Use this feature to select the link speed for the PCIe port. The options are Auto,

Gen 1 (2.5 GT/s), Gen 2 (5 GT/s), and Gen 3 (8 GT/s).

PCI-E Port Link Status

PCI-E Port Link Max

PCI-E Port Link Speed

PCI-E Port Clocking

The options are Distinct and Common. If this item is set to Distinct, this component
and the component at the opposite end of the Link are operating with separate refer­ence clock sources. If this item is set to Common, this component and the component
at the opposite end of the Link are operating with a common clock source.

PCI-E Port Max Payload Size

Select Auto for the system BIOS to automatically set the maximum payload value
for a PCIe device to enhance system performance. The options are 128B, 256B,
and Auto.

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CPU2 Conguration

IOU0 (IIO PCIe Br1)

This feature congures the PCIe port Bifurcation setting for a PCIe port specied by

the user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

IOU1 (IIO PCIe Br2)

This feature congures the PCIe port Bifurcation setting for a PCIe port specied by

the user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

IOU2 (IIO PCIe Br3)

This feature congures the PCIe port Bifurcation setting for a PCIe port specied by

the user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

CPU2 SLOT6 PCI-E 3.0 x16

Link Speed

Use this feature to select the link speed for the PCIe port. The options are Auto,

Gen 1 (2.5 GT/s), Gen 2 (5 GT/s), and Gen 3 (8 GT/s).

PCI-E Port Link Status

PCI-E Port Link Max

PCI-E Port Link Speed

PCI-E Port Clocking

The options are Distinct and Common. If this item is set to Distinct, this component
and the component at the opposite end of the Link are operating with separate refer­ence clock sources. If this item is set to Common, this component and the component
at the opposite end of the Link are operating with a common clock source.

PCI-E Port Max Payload Size

Select Auto for the system BIOS to automatically set the maximum payload value
for a PCIe device to enhance system performance. The options are 128B, 256B,
and Auto.

CPU2 SLOT8 PCI-E 3.0 x16

Link Speed

Use this feature to select the link speed for the PCIe port. The options are Auto,

Gen 1 (2.5 GT/s), Gen 2 (5 GT/s), and Gen 3 (8 GT/s).

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PCI-E Port Link Status

PCI-E Port Link Max

PCI-E Port Link Speed

PCI-E Port Clocking

The options are Distinct and Common. If this item is set to Distinct, this component
and the component at the opposite end of the Link are operating with separate refer­ence clock sources. If this item is set to Common, this component and the component
at the opposite end of the Link are operating with a common clock source.

PCI-E Port Max Payload Size

Select Auto for the system BIOS to automatically set the maximum payload value
for a PCIe device to enhance system performance. The options are 128B, 256B,
and Auto.

CPU2 SLOT10 PCI-E 3.0 x16

Link Speed

Use this feature to select the link speed for the PCIe port. The options are Auto,

Gen 1 (2.5 GT/s), Gen 2 (5 GT/s), and Gen 3 (8 GT/s).

PCI-E Port Link Status

PCI-E Port Link Max

PCI-E Port Link Speed

PCI-E Port Clocking

The options are Distinct and Common. If this item is set to Distinct, this component
and the component at the opposite end of the Link are operating with separate refer­ence clock sources. If this item is set to Common, this component and the component
at the opposite end of the Link are operating with a common clock source.

PCI-E Port Max Payload Size

Select Auto for the system BIOS to automatically set the maximum payload value
for a PCIe device to enhance system performance. The options are 128B, 256B,
and Auto.

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IOAT (Intel® IO Acceleration) Conguration

Disable TPH

Select Yes to deactivate TLP Processing Hint support. The options are No and Yes.

Prioritize TPH

Use this feature to enable the prioritize TPH support. The options are Enable and

Disable.

Relaxed Ordering

Select Enable to enable Relaxed Ordering support which will allow certain transactions
to violate the strict-ordering rules of PCI bus for a transaction to be completed prior
to other transactions that have already been enqueued. The options are Disable and
Enable.

Intel® VT for Directed I/O (VT-d)

Intel® VT for Directed I/O (VT-d)

Select Enable to use Intel Virtualization Technology support for Direct I/O VT-d support
by reporting the I/O device assignments to the VMM (Virtual Machine Monitor) through
the DMAR ACPI Tables. This feature o󰀨ers fully-protected I/O resource sharing across

Intel platforms, providing greater reliability, security and availability in networking and
data-sharing. The options are Enable and Disable.

*If the feature above is set to Enable, the following features will be available:

Interrupt Remapping

Select Enable for Interrupt Remapping support to enhance system performance. The
options are Enable and Disable.

PassThrough DMA

Select Enable to use the Non-Isoch VT_D engine pass through DMA support. The
options are Enable and Disable.

ATS

Select Enable to use the Non-Isoch VT_D engine ATS support. The options are En­able and Disable.

Posted Interrupt

Use this feature to enable VT_D posted interrupt. The options are Enable and Disable.

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Coherency Support (Non-Isoch)

Select Enable for the Non-Iscoh VT-d engine to pass through DMA (Direct Memory

Access) to enhance system performance. The options are Enable and Disable.

Intel® VMD technology

This section describes the conguration settings for the Intel Volume Management
Device (VMD) Technology.

Note: After you’ve enabled VMD on a PCIe slot of your choice, this PCIe slot will

be dedicated for VMD use only, and it will no longer support any PCIe device. To
re-activate this slot for PCIe use, please disable VMD.

Intel® VMD for Volume Management Device on CPU1

VMD Cong for PStack0

Intel® VMD for Volume Management Device

Select Enable to use the Intel Volume Management Device Technology for this stack.

The options are Disable and Enable.

*If the feature "Intel VMD for Volume Management Device" is set to Enable,
the following features will be available:

CPU1 SLOT2 PCI-E 3.0 x16 VMD (Available when the device is detected by
the system)

Select Enable to use the Intel Volume Management Device Technology for this de­vice. The options are Disable and Enable.

Hot Plug Capable (Available when the device is detected by the system)

Use this feature to enable the hot plug support for PCIe root ports 1A~1D. The op­tions are Disable and Enable.

VMD Cong for PStack1

Intel® VMD for Volume Management Device

Select Enable to use the Intel Volume Management Device Technology for this stack.

The options are Disable and Enable.

*If the feature "Intel VMD for Volume Management Device" is set to Enable,
the following features will be available:

CPU1 SLOT4 PCI-E 3.0 x16 VMD (Available when the device is detected by
the system)

Select Enable to use the Intel Volume Management Device Technology for this de­vice. The options are Disable and Enable.

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Hot Plug Capable (Available when the device is detected by the system)

Use this feature to enable the hot plug support for PCIe root ports 2A~2D. The op­tions are Disable and Enable.

VMD Cong for PStack2

Intel® VMD for Volume Management Device

Select Enable to use the Intel Volume Management Device Technology for this stack.

The options are Disable and Enable.

*If the feature "Intel VMD for Volume Management Device" is set to Enable,
the following features will be available:

CPU1 SLOT9 PCI-E 3.0 x16 VMD (Available when the device is detected by
the system)

Select Enable to use the Intel Volume Management Device Technology for this de­vice. The options are Disable and Enable.

Hot Plug Capable (Available when the device is detected by the system)

Use this feature to enable the hot plug support for PCIe root ports 3A~3D. The op­tions are Disable and Enable.

Intel® VMD for Volume Management Device on CPU2

VMD Cong for PStack0

Intel® VMD for Volume Management Device

Select Enable to use the Intel Volume Management Device Technology for this stack.

The options are Disable and Enable.

*If the feature "Intel VMD for Volume Management Device" is set to Enable,
the following features will be available:

CPU2 SLOT6 PCI-E 3.0 x16 VMD (Available when the device is detected by
the system)

Select Enable to use the Intel Volume Management Device Technology for this de­vice. The options are Disable and Enable.

Hot Plug Capable (Available when the device is detected by the system)

Use this feature to enable the hot plug support for PCIe root ports 1A~1D. The op­tions are Disable and Enable.

VMD Cong for PStack1

Intel® VMD for Volume Management Device

Select Enable to use the Intel Volume Management Device Technology for this stack.

The options are Disable and Enable.

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*If the feature "Intel VMD for Volume Management Device" is set to Enable,
the following features will be available:

CPU2 SLOT8 PCI-E 3.0 x16 VMD (Available when the device is detected by
the system)

Select Enable to use the Intel Volume Management Device Technology for this de­vice. The options are Disable and Enable.

Hot Plug Capable (Available when the device is detected by the system)

Use this feature to enable the hot plug support for PCIe root ports 2A~2D. The op­tions are Disable and Enable.

VMD Cong for PStack2

Intel® VMD for Volume Management Device

Select Enable to use the Intel Volume Management Device Technology for this stack.

The options are Disable and Enable.

*If the feature "Intel VMD for Volume Management Device" is set to Enable,
the following features will be available:

CPU2 SLOT10 PCI-E 3.0 x16 VMD (Available when the device is detected by
the system)

Select Enable to use the Intel Volume Management Device Technology for this de­vice. The options are Disable and Enable.

Hot Plug Capable (Available when the device is detected by the system)

Use this feature to enable the hot plug support for PCIe root ports 3A~3D. The op­tions are Disable and Enable.

IIO-PCIE Express Global Options

PCI-E Completion Timeout Disable

Use this feature for PCIe Completion Timeout support for electric tuning. The options
are Yes, No, and Per-Port.

South Bridge

The following South Bridge information will be displayed:

• USB Module Version

• USB Devices

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Chapter 4: UEFI BIOS

Legacy USB Support

Select Enabled to support onboard legacy USB devices. Select Auto to disable legacy
support if there are no legacy USB devices present. Select Disable to have all USB devices
available for EFI applications only. The options are Enabled, Disabled, and Auto.

XHCI Hand-o󰀨

This is a work-around solution for operating systems that do not support XHCI (Extensible

Host Controller Interface) hand-o󰀨. The XHCI ownership change should be claimed by the

XHCI driver. The options are Enabled and Disabled.

Port 60/64 Emulation

Select Enabled for I/O port 60h/64h emulation support, which will provide complete legacy

USB keyboard support for the operating systems that do not support legacy USB devices.
The options are Disabled and Enabled..

Server ME Conguration

This feature displays the following system ME conguration settings.

• Operational Firmware Version

• Backup Firmware Version

• Recovery Firmware Version

• ME Firmware Status #1

• ME Firmware Status #2

• Current State

• Error Code

PCH SATA Conguration

SATA Controller

This feature enables or disables the onboard SATA controller supported by the Intel PCH
chip. The options are Disable and Enable.

Congure SATA as

Select AHCI to congure a SATA drive specied by the user as an AHCI drive. Select RAID
to congure a SATA drive specied by the user as a RAID drive. The options are AHCI and

RAID.

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Super X11DPX-T User's Manual

SATA HDD Unlock

Select Enable to unlock the HDD password. The options are Disable and Enable.

Aggressive Link Power Management

When this feature is set to Enable, the SATA AHCI controller manages the power usage of

the SATA link. The controller will put the link to a low power state when the I/O is inactive for
an extended period of time, and the power state will return to normal when the I/O becomes

active. The options are Disable and Enable.

*If the feature, Congure SATA as, is set to AHCI, the following features will become
available for user's conguration:

SATA Port 0~ Port 7

This feature displays the information detected on the installed SATA drive on the particular
SATA port.

• Model number of drive and capacity

• Software Preserve Support

Hot Plug (SATA Port 0~ Port 7)

Select Enabled to enable a SATA port specied by the user. The options are Disable and
Enable.

Spin Up Device (SATA Port 0~ Port 7)

On an edge detect from 0 to 1, set this feature to allow the PCH to initialize the device.
The options are Disable and Enable.

SATA Device Type (SATA Port 0~ Port 7)

Use this feature to specify if the SATA port specied by the user should be connected to a

Solid State drive or a Hard Disk Drive. The options are Hard Disk Drive and Solid State
Drive.

*If the feature, Congure SATA as, is set to RAID, the following features will become
available for user's conguration:

SATA RSTe Boot Info

Select Enable to provide the full int13h support for SATA controller attached devices. The
options are Disable and Enable.

Aggressive Link Power Management

When this feature is set to Enable, the SATA AHCI controller manages the power usage of

the SATA link. The controller will put the link to a low power state when the I/O is inactive for
an extended period of time, and the power state will return to normal when the I/O becomes

active. The options are Disable and Enable.

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Chapter 4: UEFI BIOS

SATA RAID Option ROM/UEFI Driver

Select EFI to load the EFI driver for system boot. Select Legacy to load a legacy driver for
system boot. The options are Disable, EFI, and Legacy.

SATA Port 0~ Port 7

This feature displays the information detected on the installed SATA drive on the particular
SATA port.

• Model number of drive and capacity

• Software Preserve Support

Hot Plug (SATA Port 0~ Port 7)

Select Enabled to enable a SATA port specied by the user. The options are Disable and
Enable.

Spin Up Device (SATA Port 0~ Port 7)

On an edge detect from 0 to 1, set this feature to allow the PCH to initialize the device.
The options are Disable and Enable.

SATA Device Type (SATA Port 0~ Port 7)

Use this feature to specify if the SATA port specied by the user should be connected to a

Solid State drive or a Hard Disk Drive. The options are Hard Disk Drive and Solid State
Drive.

PCH sSATA Conguration

sSATA Controller

This feature enables or disables the onboard SATA controller supported by the Intel PCH
chip. The options are Enable and Disable.

Congure sSATA as

Select AHCI to congure a SATA drive specied by the user as an AHCI drive. Select RAID
to congure a SATA drive specied by the user as a RAID drive. The options are AHCI and

RAID.

SATA HDD Unlock

Select Enable to unlock the HDD password. The options are Disable and Enable.

Aggressive Link Power Management

When this feature is set to Enable, the SATA AHCI controller manages the power usage of

the SATA link. The controller will put the link to a low power state when the I/O is inactive for
an extended period of time, and the power state will return to normal when the I/O becomes

active. The options are Disable and Enable.

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Super X11DPX-T User's Manual

*If the feature, Congure sSATA as, is set to AHCI, the following features will become
available for user's conguration:

sSATA Port 0~ Port 5

This feature displays the information detected on the installed SATA drive on the particular
SATA port.

• Model number of drive and capacity

• Software Preserve Support

Hot Plug (sSATA Port 0~ Port 5)

Select Enabled to enable a SATA port specied by the user. The options are Disable and
Enable.

Spin Up Device (sSATA Port 0~ Port 5)

On an edge detect from 0 to 1, set this feature to allow the PCH to initialize the device.
The options are Disable and Enable.

sSATA Device Type (sSATA Port 0~ Port 5)

Use this feature to specify if the SATA port specied by the user should be connected to a

Solid State drive or a Hard Disk Drive. The options are Hard Disk Drive and Solid State
Drive.

*If the feature, Congure SATA as, is set to RAID, the following features will become
available for user's conguration:

sSATA RSTe Boot Info

Select Enable to provide the full int13h support for SATA controller attached devices. The
options are Disable and Enable.

sSATA RAID Option ROM/UEFI Driver

Select EFI to load the EFI driver for system boot. Select Legacy to load a legacy driver for
system boot. The options are Disable, EFI, and Legacy.

sSATA Port 0~ Port 5

This feature displays the information detected on the installed SATA drive on the particular
SATA port.

• Model number of drive and capacity

• Software Preserve Support

Hot Plug (sSATA Port 0~ Port 5)

Select Enabled to enable a SATA port specied by the user. The options are Disable and
Enable.

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Chapter 4: UEFI BIOS

Spin Up Device (sSATA Port 0~ Port 5)

On an edge detect from 0 to 1, set this feature to allow the PCH to initialize the device.
The options are Disable and Enable.

sSATA Device Type (sSATA Port 0~ Port 5)

Use this feature to specify if the SATA port specied by the user should be connected to a

Solid State drive or a Hard Disk Drive. The options are Hard Disk Drive and Solid State
Drive.

PCIe/PCI/PnP Conguration

The following information will be displayed:

• PCI Bus Driver Version

PCI Devices Common Settings:

Above 4G Decoding (Available if the system supports 64-bit PCI decoding)

Select Enabled to decode a PCI device that supports 64-bit in the space above 4G Address.

The options are Disabled and Enabled.

SR-IOV Support

Use this feature to enable or disable Single Root IO Virtualization support. The options are

Disabled and Enabled.

MMIO High Base

Use this feature to select the base memory size according to memory-address mapping for
the IO hub. The options are 56T, 40T, 24T, 16T, 4T, and 1T.

MMIO High Granularity Size

Use this feature to select the high memory size according to memory-address mapping for

the IO hub. The options are 1G, 4G, 16G, 64G, 256G, and 1024G.

PCI PERR/SERR Support

Select Enabled to activate PCI Error and System Error report handling. The options are
Disabled and Enabled.

Maximum Read Request

Select Auto to allow the system BIOS to automatically set the maximum read request size
for a PCIe device to enhance system performance. The options are Auto, 128 Bytes, 256
Bytes, 512 Bytes, 1024 Bytes, 2048 Bytes, and 4096 Bytes.

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Super X11DPX-T User's Manual

MMCFG Base

Use this feature to select the default value for the PCI MMIO (Memory-Mapped IO) base

address. The options are 1G, 1.5G, 1.75G, 2G, 2.25G, and 3G.

NVMe Firmware Source

Use this feature to select the NVMe rmware to support booting. The options are Vendor

Dened Firmware and AMI Native Support. The default option, Vendor Dened Firmware,
is pre-installed on the drive and may resolve errata or enable innovative functions for the

drive. The other option, AMI Native Support, is o󰀨ered by the BIOS with a generic method.

VGA Priority

Use this feature to select the graphics device to be used as the primary video display for
system boot. The options are Onboard and O󰀨board.

RSC-UMR-8 SLOT1 PCI-E x8 OPROM

RSC-UMR-8 M.2_PCIe OPROM

Select Disabled to deactivate the selected slot, Legacy to activate the slot in legacy mode,
and EFI to activate the slot in EFI mode. The options are Disabled, Legacy, and EFI.

Onboard LAN Option ROM Type

Select an option to enable Option ROM support to boot the computer using a device specied

by the user. The options are Legacy and EFI.

Onboard LAN1 Option ROM

Onboard LAN2 Option ROM

Use the above two features to select the type of device installed in a LAN port specied by

the user for system boot. The default setting for Onboard LAN1 Option ROM is PXE, and the
default setting for Onboard LAN2 Option ROM is Disabled.

Onboard NVMe1 Option ROM

Onboard NVMe2 Option ROM

Onboard NVMe3 Option ROM

Onboard NVMe4 Option ROM

Use the above four features to select the type of the device installed on an NVMe port specied

by the user for system boot. The options are Disabled, Legacy, and EFI.

Onboard Video Option ROM

Select Legacy to boot the system using a legacy video device installed on the motherboard.
The options are Disabled, Legacy, and EFI.

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