Supermicro X11DDW-L/NT User Manual

X11DDW-L/NT

USER’S MANUAL

Revision 1.0a

The information in this User’s Manual has been carefully reviewed and is believed to be accurate. The vendor assumes
no responsibility for any inaccuracies that may be contained in this document, and makes no commitment to update
or to keep current the information in this manual, or to notify any person or organization of the updates. Please Note:

For the most up-to-date version of this manual, please see our website at www.supermicro.com.

Super Micro Computer, Inc. ("Supermicro") reserves the right to make changes to the product described in this manual
at any time and without notice. This product, including software and documentation, is the property of Supermicro and/
or its licensors, and is supplied only under a license. Any use or reproduction of this product is not allowed, except
as expressly permitted by the terms of said license.

IN NO EVENT WILL Super Micro Computer, Inc. BE LIABLE FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL,
SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR INABILITY TO USE THIS PRODUCT
OR DOCUMENTATION, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN PARTICULAR, SUPER
MICRO COMPUTER, INC. SHALL NOT HAVE LIABILITY FOR ANY HARDWARE, SOFTWARE, OR DATA STORED
OR USED WITH THE PRODUCT, INCLUDING THE COSTS OF REPAIRING, REPLACING, INTEGRATING,
INSTALLING OR RECOVERING SUCH HARDWARE, SOFTWARE, OR DATA.

Any disputes arising between manufacturer and customer shall be governed by the laws of Santa Clara County in the
State of California, USA. The State of California, County of Santa Clara shall be the exclusive venue for the resolution
of any such disputes. Supermicro's total liability for all claims will not exceed the price paid for the hardware product.

FCC Statement: This equipment has been tested and found to comply with the limits for a Class A digital device
pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful
interference when the equipment is operated in a commercial environment. This equipment generates, uses, and can
radiate radio frequency energy and, if not installed and used in accordance with the manufacturer’s instruction manual,
may cause harmful interference with radio communications. Operation of this equipment in a residential area is likely
to cause harmful interference, in which case you will be required to correct the interference at your own expense.

California Best Management Practices Regulations for Perchlorate Materials: This Perchlorate warning applies only
to products containing CR (Manganese Dioxide) Lithium coin cells. “Perchlorate Material-special handling may apply.
See www.dtsc.ca.gov/hazardouswaste/perchlorate”.

WARNING: Handling of lead solder materials used in this product may expose you to lead, a
chemical known to the State of California to cause birth defects and other reproductive harm.

The products sold by Supermicro are not intended for and will not be used in life support systems, medical equipment,
nuclear facilities or systems, aircraft, aircraft devices, aircraft/emergency communication devices or other critical

systems whose failure to perform be reasonably expected to result in signicant injury or loss of life or catastrophic

property damage. Accordingly, Supermicro disclaims any and all liability, and should buyer use or sell such products
for use in such ultra-hazardous applications, it does so entirely at its own risk. Furthermore, buyer agrees to fully
indemnify, defend and hold Supermicro harmless for and against any and all claims, demands, actions, litigation, and
proceedings of any kind arising out of or related to such ultra-hazardous use or sale.

Manual Revision 1.0a

Release Date: August 14, 2017

Unless you request and receive written permission from Super Micro Computer, Inc., you may not copy any part of this

document. Information in this document is subject to change without notice. Other products and companies referred

to herein are trademarks or registered trademarks of their respective companies or mark holders.

Copyright © 2017 by Super Micro Computer, Inc.
All rights reserved.

Printed in the United States of America

Preface

Preface

About This Manual

This manual is written for system integrators, IT technicians, and knowledgeable end users.
It provides information for the installation and use of the X11DDW-L/NT motherboard.

About This Motherboard

The Super X11DDW-L/NT motherboard supports dual Intel Xeon 81xx/61xx/51xx/41xx/31xx
series processors (Socket P -F) with a TDP (Thermal Design Power) of up to 205W and a
QPI (QuickPath Interconnect) of up to 10.4GT/s. Built with the Intel® C621/C622 PCH, this

motherboard supports 1536GB Registered ECC DDR4 in 12 memory slots. It o󰀨ers support for

Intel Intelligent Power Node Manager, Active Management Technology, and vPro technology.
The X11DDW-L/NT includes four NVMe connectors, slots for riser card support, fourteen
SATA 3.0 ports, and dual LAN and USB 3.0 ports. The X11DDW-L/NT provides maximum
performance, system cooling, and PCI-E capacity. This motherboard is optimized for PCI-

Express expansion with exible IO support, and is ideal for general-purpose server platforms.

Please note that this motherboard is intended to be installed and serviced by professional
technicians only. For processor/memory updates, please refer to our website at http://www.
supermicro.com/products/.

Manual organization

Chapter 1 describes the features, specications and performance of the motherboard, and

provides detailed information on the Intel C621/C622 chipsets.

Chapter 2 provides hardware installation instructions. Read this chapter when installing the
processor, memory modules and other hardware components into the system.

If you encounter any problems, see Chapter 3, which describes troubleshooting procedures
for video, memory and system setup stored in the CMOS.

Chapter 4 includes an introduction to the BIOS, and provides detailed information on running
the CMOS Setup utility.

Appendix A provides BIOS Error Beep Codes.

Appendix B lists software program installation instructions.

Appendix C lists standardized warning statements in various languages.

Appendix D contains UEFI BIOS Recovery instructions.

3

X11DDW-L/NT User's Manual

Contacting Supermicro

Headquarters

Address: Super Micro Computer, Inc.

980 Rock Ave.

San Jose, CA 95131 U.S.A.

Tel: [phone]

Fax: [phone]

Email: [e-mail] (General Information)

[e-mail] (Technical Support)

Website: www.supermicro.com

Europe

Address: Super Micro Computer B.V.

Het Sterrenbeeld 28, 5215 ML

's-Hertogenbosch, The Netherlands

Tel: [phone]

Fax: [phone]

Email: [e-mail] (General Information)

[e-mail] (Technical Support)

[e-mail] (Customer Support)

Website: www.supermicro.nl

Asia-Pacic

Address: Super Micro Computer, Inc.

3F, No. 150, Jian 1st Rd.

Zhonghe Dist., New Taipei City 235

Taiwan (R.O.C)

Tel: [phone]

Fax: [phone]

Email: [e-mail]

Website: www.supermicro.com.tw

4

Preface

Table of Contents

Chapter 1 Introduction

1.1 Checklist ...............................................................................................................................8

Quick Reference ...............................................................................................................11

Quick Reference Table ......................................................................................................12

Motherboard Features .......................................................................................................14

1.2 Processor and Chipset Overview .......................................................................................18

1.3 Special Features ................................................................................................................18

Recovery from AC Power Loss .........................................................................................18

1.4 System Health Monitoring ..................................................................................................19

Onboard Voltage Monitors ................................................................................................19

Fan Status Monitor with Firmware Control .......................................................................19

Environmental Temperature Control .................................................................................19

System Resource Alert......................................................................................................19

1.5 ACPI Features ....................................................................................................................20

1.6 Power Supply .....................................................................................................................20

1.7 Super I/O ............................................................................................................................20

1.8 Advanced Power Management ..........................................................................................21

Intel® Intelligent Power Node Manager (IPNM).................................................................21

Management Engine (ME) ................................................................................................21

Chapter 2 Installation

2.1 Static-Sensitive Devices .....................................................................................................22

Precautions .......................................................................................................................22

Unpacking .........................................................................................................................22

2.2 Motherboard Installation .....................................................................................................23

Tools Needed ....................................................................................................................23

Location of Mounting Holes ..............................................................................................23

Installing the Motherboard.................................................................................................24

2.3 Processor and Heatsink Installation ....................................................................................25

The Processor ...................................................................................................................25

Overview of the Processor Socket Assembly ...................................................................26

Overview of the Processor Heatsink Module ....................................................................27

5

X11DDW-L/NT User's Manual

Preparing the CPU Socket for Installation ........................................................................28

Removing the Dust Cover from the CPU Socket .............................................................28

Attaching the Processor to the CPU/Heatsink Carrier ......................................................29

Attaching the CPU/Carrier Assembly to the Passive Heatsink to Form the Processor

Heatsink Module (PHM) ....................................................................................................30

Installing the Processor Heatsink Module (PHM) ............................................................31

Removing the Processor Heatsink Module (PHM) ...........................................................32

2.4 Memory Support and Installation .......................................................................................33

Memory Support ................................................................................................................33

DIMM Population Requirements .......................................................................................34

DIMM Installation ..............................................................................................................37

DIMM Removal .................................................................................................................37

2.5 Rear I/O Ports ....................................................................................................................38

2.6 Front Control Panel ............................................................................................................42

2.7 Connectors .........................................................................................................................47

Power Connector ..............................................................................................................47

Headers .............................................................................................................................49

2.8 Jumper Settings .................................................................................................................57

How Jumpers Work ...........................................................................................................57

2.9 LED Indicators ....................................................................................................................62

2.10 PCI-E 3.0 Slots .................................................................................................................65

Chapter 3 Troubleshooting

3.1 Troubleshooting Procedures ..............................................................................................66

Before Power On ..............................................................................................................66

No Power ..........................................................................................................................66

No Video ...........................................................................................................................67

System Boot Failure .......................................................................................................67

Memory Errors ..................................................................................................................67

Losing the System's Setup Conguration .........................................................................68

When the System Becomes Unstable ..............................................................................68

3.2 Technical Support Procedures ...........................................................................................70

3.3 Frequently Asked Questions ..............................................................................................71

3.4 Battery Removal and Installation .......................................................................................72

6

Battery Removal ................................................................................................................72

Proper Battery Disposal ....................................................................................................72

Battery Installation .............................................................................................................72

3.5 Returning Merchandise for Service ....................................................................................73

Chapter 4 BIOS

4.1 Introduction .........................................................................................................................74

4.2 Main Setup .........................................................................................................................75

4.3 Advanced Setup Congurations .........................................................................................77

4.4 Event Logs ........................................................................................................................105

4.5 IPMI ...................................................................................................................................107

4.6 Security ...........................................................................................................................110

4.7 Boot .................................................................................................................................114

4.8 Save & Exit .......................................................................................................................116

Appendix A BIOS Codes

Appendix B Software Installation

B.1 Installing Software Programs ...........................................................................................120

B.2 SuperDoctor® 5 .................................................................................................................121

Appendix C Standardized Warnings

Battery Handling ..............................................................................................................122

Product Disposal .............................................................................................................124

Appendix D UEFI BIOS Recovery

7

X11DDW-L/NT User's Manual

Chapter 1

Introduction

Congratulations on purchasing your computer motherboard from an industry leader.
Supermicro motherboards are designed to provide you with the highest standards in quality
and performance.

In addition to the motherboard, several important parts that are included with your shipment
are listed below. If anything listed is damaged or missing, please contact your retailer.

1.1 Checklist

Main Parts List

Description Part Number Quantity

Supermicro Motherboard X11DDW-L/NT 1

SATA Cables CBL-0044L 2

Quick Reference Guide MNL-1907-QRG 1

Important Links

For your system to work properly, please follow the links below to download all necessary
drivers/utilities and the user’s manual for your server.

• Supermicro product manuals: http://www.supermicro.com/support/manuals/

• Product drivers and utilities: ftp://ftp.supermicro.com

• Product safety info: http://www.supermicro.com/about/policies/safety_information.cfm

• If you have any questions, please contact our support team at: [e-mail]

This manual may be periodically updated without notice. Please check the Supermicro website

for possible updates to the manual revision level.

8

Figure 1-1. Motherboard Image

Chapter 1: Introduction

Lorem ipsum

Note: All graphics shown in this manual were based upon the latest PCB revision
available at the time of publication of the manual. The motherboard you received may
or may not look exactly the same as the graphics shown in this manual.

9

X11DDW-L/NT User's Manual

Figure 1-2. X11DDW-L Motherboard Layout

(not drawn to scale)

LE1

C

A

JUIDB1

JPME1

JPME2

USB2/3

JSXB1_1

LAN2

JM2_1

LE3

CPU2_PORT3

LAN1

(3.0)

IPMI_LAN
USB0/1(3.0)

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

BMC

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

S-SGPIO2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

P2_NVME1

JRK1

JL1

JP3

JNVI2C2

P2 DIMM

F1

E1

CPU2

D1

P2_NVME0

JSXB1_3

P2 DIMM

A1

BIOS LICENSE

B1

SRW1

X11DDW-L

REV:1.02
DESIGNED IN USA

CPU2

C1

S-SATA 0~3

MAC CODE

P1 DIMM

F1

E1

I-SATA 4~7

I-SATA 0~3

BAR CODE

BT1

CPU1

D1

JBT1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

X NMIPWR

NIC HDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

VGA

10G PHY

LEDM1

CPU1

P1 DIMM

A1

JP2

JAOM

B1

C1

JIPMB1

LE2

S-SATA5

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JF1

JPL1

JWD1

JPG1

JBR1

FAN5FAN6

Di󰀨erences between X11DDW-L/NT

X11DDW-L X11DDW-NT
10G No Yes

NVME No Yes

FAN4

FAN3

JPWR3

FAN2

JPI2C1

JPWR1

JPWR2

FAN1

Note: Components not documented are for internal testing only.

10

Quick Reference

JPG1

JBR1

Chapter 1: Introduction

CPU2 PCI-E 3.0 X16

P1_NVME1 (-NT)

CPU1+CPU2 PCI-E 3.0 X16

JRK1

JL1

JP3

JNVI2C2
P2_NVME1 (-NT)
P2_NVME0 (-NT)

JSXB1_1

JM2_1

LE3

I-SATA4~7

I-SATA0~3

S-SATA0~3

JNVI2C2

S-SGPIO2

SRW1

JSXB1_3

JRK1

JL1

JNVI2C2

P2 DIMM

F1

E1

JP3

D1

CPU2

P2_NVME1

P2_NVME0

LE1

JUIDB1

JPME1

JPME2

LE1

C

A

JUIDB1

JPME1

JPME2

JSXB1_1

JM2_1

LE3

CPU2_PORT3

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

S-SGPIO2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

JSXB1_3

P2 DIMM

A1

SRW1

BIOS LICENSE

B1

C1

CPU2

S-SATA 0~3

MAC CODE

X11DDW-L

REV:1.02
DESIGNED IN USA

P1 DIMM

F1

E1

D1

CPU1

C621

I-SATA 0~3

LAN2

LAN2

I-SATA 4~7

BAR CODE

BT1

LAN1

LAN1

+

USB2/3

JBT1

JNVI2C1

P1_NVME1

P1_NVME0

PWRRST
ON

USB2/3
(3.0)

JSDCARD1

NICHDD

NIC

UID

LED

2 1

LEDPSFAIL

LED

IPMI LAN

USB0/1

IPMI_LAN
USB0/1(3.0)

10G PHY

BMC

LEDM1

X NMIPWR

VGA

CPU1

P1 DIMM
A1

VGA

JIPMB1

S-SATA5

S-SATA4

JSTBY1

USB4/5(3.0)

JPL1

JWD1

S-SATA5

JIPMB1
JPG1

JPL1

JBR1

JWD1

S-SATA4

JSTBY1

USB4/5

JTPM1

1

JBMC_DEBUG

JF1

JBT1

LEDM1

JVRM2

JVRM1

JTPM1

JD1

JBMC DEBUG

JF1

LE2

JVRM1JVRM2

JD1

JP2

JAOM

LE2

JP2

C1

B1

JSDCARD1

P1_NVME0 (-NT)

BT1

JPI2C1

JPI2C1

JPWR3

JPWR3

JPWR1

JPWR1

JPWR2

JPWR2

FAN4

FAN6

FAN5FAN6

FAN5 FAN4 FAN3 FAN2 FAN1

FAN3

CPU1CPU2

FAN1

FAN2

Notes:

• See Chapter 2 for detailed information on jumpers, I/O ports, and JF1 front panel con-

nections.

• " " indicates the location of Pin 1.

• Jumpers/LED indicators not indicated are used for internal testing only.

• Use only the correct type of onboard CMOS battery as specied by the manufacturer. Do

not install the onboard battery upside down to avoid possible explosion.

11

X11DDW-L/NT User's Manual

Quick Reference Table

Jumper Description Default Setting

JBT1 Clear CMOS Open (Normal)

JPG1 VGA Enable Pins 1-2 (Enabled)

JPL1 LAN1/LAN2 Enable Pins 1-2 (Enabled)

JPME1 ME Recovery Pins 1-2 (Normal)

JPME2 Manufacturing (ME) Mode Select Pins 1-2 (Normal)

JVRM1 VRM SMB Clock (to BMC or PCH) Pins 1-2 (BMC, Normal)

JVRM2 VRM SMB Data (to BMC or PCH) Pins 1-2 (BMC, Normal)

JWD1 Watch Dog Timer Enable Pins 1-2 (Normal)

Connector Description

Battery (BT1) Onboard CMOS battery

FAN1~6 System cooling fan headers

IPMI_LAN Dedicated IPMI LAN port

JAOM PCI-E 3.0 x16 SAS3 AOM controller slot

JD1 Power LED/Speaker header (Pins 1-3: Power LED, Pins 4-7: Speaker)

JF1 Front control panel header

JIPMB1 4-pin external BMC I2C header (for an IPMI card)

JL1 Chassis intrusion header

JM2_1 M.2 slot supported by PCH

JNVI2C1/JNVI2C2 NVMe I2C headers

JPI2C1 Power Supply SMBbus I2C header

JPWR1/JPWR2 12V 8-pin power supply connectors

JPWR3 24-pin ATX main power supply connector

JRK1 RAID Key for onboard SATA devices

JSDCARD1 Micro SD Card slot

JSTBY1 Standby power header

JTPM1 Trusted Platform Module (TPM)/Port 80 connector

JUIDB1 Unit Identier (UID) switch

LAN1/LAN2 Gigabit LAN (GLAN) Ethernet ports on the back panel

P1_NVME0/P1_NVME1 (-NT) NVM Express PCI-E 3.0 x4 ports (from CPU1)

P2_NVME0/P2_NVME1 (-NT) NVM Express PCI-E 3.0 x4 ports (from CPU2)

(I-)SATA0~3, 4~7 I- SATA 3.0 connectors supported by the Intel PCH

(S-)SATA0~3 S-SATA 3.0 connectors supported by the Intel SCU

(S-)SATA4/S-SATA5

SXB1 PCI-E 3.0 (x16 + x16) Left Riser Card slot supported by CPU1 and CPU2

S-SATA connectors with built-in power pins and support of Supermicro SuperDOM (Disk-on

Module) devices

Note: Table is continued on the next page.

12

Chapter 1: Introduction

Connector Description

SXB2 PCI-E 3.0 x16 Right Riser Card slot supported by CPU2

S-SGPIO2 Serial General Purpose I/O port

USB0/1 Back panel USB 3.0 ports

USB2/3 Back panel USB 3.0 ports

USB4/5 USB 3.0 headers

VGA Back panel VGA port

LED Description Status

LE1 UID (Unit Identier) LED Solid Blue: Unit Identied

LE2 Onboard Power LED On: Onboard Power On

LE3 M.2 LED Blinking Green: Device Working

LEDM1 BMC Heartbeat LED Blinking Green: BMC Normal

13

X11DDW-L/NT User's Manual

Motherboard Features

Motherboard Features

CPU

• Dual Intel Xeon 81xx/61xx/51xx/41xx/31xx series processors (Socket P)

Note: Both CPUs need to be installed for full access to the PCI-E slots, DIMM slots, and onboard controllers. Refer

to the block diagram on page 16 to determine which slots or devices may be a󰀨ected.

Memory

• Integrated memory controller supports up to 1536GB of ECC Load Reduced DIMM (LRDIMM), Registered DIMM (RDIMM),

and Non-Volatile DIMM (NV-DIMM) DDR4 (288-pin) 2666MT/s modules in 12 slots

DIMM Size

• Up to 128GB at 1.2V

Note 1: Memory speed support depends on the processors used in the system.

Note 2: For the latest CPU/memory updates, please refer to our website at http://www.supermicro.com/products/

motherboard.

Chipset

• Intel C621 (-L)

• Intel C622 (NT)

Expansion Slots

• One (1) PCI-Express 3.0 (x16 + x16) slot supported by CPU1 and CPU2 for Left Riser Card (SXB1)

• One (1) PCI-Express 3.0 x16 slot supported by CPU2 for Right Riser Card (SXB2)

• One (1) PCI-Express 3.0 x16 slot supported by CPU1 for SAS3 AOM controller (JAOM)

BaseBoard Management Controller (BMC)

• ASpeed AST 2500 Baseboard Controller (BMC) supports IPMI 2.0

• One (1) dedicated IPMI LAN located on the rear IO backpanel

Graphics

• Graphics controller via AST 2500 BMC (BaseBoard Management Controller)

I/O Devices

Fourteen (14) SATA ports

• SATA 3.0

• I-SATA0~3, I-SATA4~7

• S-SATA0~3

• S-SATA4,S-SATA5 (SuperDOM support)

• RAID (PCH) • RAID 0, 1, 10

Note: The table above is continued on the next page.

14

Chapter 1: Introduction

Motherboard Features

Peripheral Devices

• Two (2) USB 3.0 ports on the rear I/O panel (USB 0/1)

• Two (2) USB 3.0 ports on the rear I/O panel (USB 2/3)

• Two (2) USB 3.0 front accessible header (USB 4/5)

BIOS

• 256MB Aten BIOS

• ACPI 3.0 or later, SPI dual/quad speed support, and SMBIOS 2.7 or later

Power Management

• ACPI power management

• Power button override mechanism

• Wake-On-LAN

• Power-on mode for AC power recovery

• Intel® Intelligent Power Node Manager 3.0 (available when the Supermicro Power Manager [SPM] is installed and a

special power supply is used. See the note on page 20.)

• Management Engine (ME)

System Health Monitoring

• Onboard voltage monitoring for +1.8V, +3.3V, +5V, +/-12V, +3.3V standby, +5V standby, VBAT, HT, memory, PCH

temperature, system temperature, and memory temperature

• CPU 5-phase switching voltage regulator

• CPU thermal trip support

• Status monitor for speed control

• Status monitor for on/o󰀨 control

• CPU Thermal Design Power (TDP) support of up to 145W (See Note 1 on next page.)

Fan Control

• Five 4-pin fan headers

• Fan status monitoring via IPMI connections

• Low-noise fan speed control

System Management

• Trusted Platform Module (TPM) support

• PECI (Platform Environment Control Interface) 2.0 support

• Power supply monitoring

• SuperDoctor® 5, Watch Dog, Non-maskable interrupt (NMI), RoHS

• Chassis intrusion detection

LED Indicators

• CPU/Overheating

• Power/Suspend-state indicator

• Fan failure

• UID/remote UID

• HDD activity

• LAN activity.

Note: The table above is continued on the next page.

15

X11DDW-L/NT User's Manual

Dimensions

• 12" (L) x 13" (W) (30.48 mm x 33.02 mm)

Note 1: The CPU maximum thermal design power (TDP) is subject to chassis and

heatsink cooling restrictions. For proper thermal management, please check the chas-

sis and heatsink specications for proper CPU TDP sizing.

Note 2: For IPMI conguration instructions, please refer to the Embedded IPMI Con­guration User's Guide available at http://www.supermicro.com/support/manuals/.

Note 3: It is strongly recommended that you change BMC log-in information upon initial
system power-on. The manufacture default username is ADMIN and the password is

ADMIN. For proper BMC conguration, please refer to http://www.supermicro.com/
products/info/les/IPMI/Best_Practices_BMC_Security.pdf

Motherboard Features

16

Figure 1-3.

System Block Diagram

Chapter 1: Introduction

RJ45

DDR4

BMC Boot Flash

BIOS

(OPTION)

VGA CONN

LUIO

PCI-E X16 G3

JAOM

2 x NVME

RJ45

10G/1G

RJ45

10G/1G

LAN3

RTL8211E-VB-CG

SPI

SPI

VCCP0 12v

VR13

5+1 PHASE

205W

VCCP0-(F)

CPU1 CPU2

SOCKET ID : 0

#3

#2

UPI

10.4/11.2G

P1

P0

UPI

P1

PECI : 30 PECI : 31

DMI3

#1B#1A

UPI

P0

P2P2

#1A

PCI-E X8 G3

#1B #2 #3

#E-0

#D-0

#C-0

#B-0

#A-0

DDRIV

2133/2666

PCI-E X16 G3

#F-0

(LANE REVERSE)

(LANE REVERSE)

PCI-E X4 + X4 G3

LAN 10G/1G

X557-AT2/88E1512

RGRMII

BMC

AST2500

RMII/NCSI

PCI-E X1 G2

USB 2.0

ESPI

ESPI
Header

DMI3

KR/KX

INTEL

PCH

X8 UPLINK NO QAT (~15W)
X8 UPLINK NO QAT (~17W)

#5

#12

USB2.0

TPM HEADER

Debug Card

PCI-E X4 + X4 G3

6.0 Gb/S

USB 2.0

USB 3.0

SPI

BIOS

SYSTEM POWER

Temp Sensor

EMC1402-1 *2 at diff SMBUS

FRONT PANEL

FAN SPEED

CTRL

Note: ports available on the (-NT) model only.

4 x NVME (2+2)

VCCP1 12v

VR13

5+1 PHASE

205W

VCCP1

SOCKET ID : 1

PCI-E X8 G3

#1

#0

#M-0

#L-0

#K-0

#J-0

#H-0

#G-0

DMI3

DDRIV

2133/2666

(LANE REVERSE)PCI-E X16 G3

(LANE REVERSE)PCI-E X16 G3

RUIO

LUIO

NA

2 x NVME

#12

#11

#10

Rear x4
Header x2

iPass 4x3
SuperDOM x2

#13

SATA

#9

#8

#7

#6

#5

#4

#3

#2

SATA

USB

USB

Note: This is a general block diagram and may not exactly represent the features on

your motherboard. See the previous pages for the actual specications of your moth­erboard.

17

X11DDW-L/NT User's Manual

1.2 Processor and Chipset Overview

Built upon the functionality and capability of the Dual Intel Xeon 81xx/61xx/51xx/41xx/31xx
series processors (Socket P) and the Intel C621/C622 chipsets, the X11DDW-L/NT

motherboard provides system performance, power e󰀩ciency, and feature sets to address

the needs of next-generation computer users. With features like a 6-channel DDR4 memory
controller and up to 28 cores with Hyper-Threading technology, the X11DDW-L/NT provides
maximum performance, system cooling, and PCI-E capacity. This motherboard is optimized
for general purpose server platforms.

The Intel Xeon 81xx/61xx/51xx/41xx/31xx series processor and the Intel C621/C622 PCH
support the following features:

• Intel® AVX-512 support with memory bandwidth increase to 6 channels (x1.5 from the

previous generation)

• High availability interconnect between multiple nodes

• Rich set of available IOs, full exibility in usage model, and software stack

• Dedicated subsystems for customer innovation

• Increased platform security with Intel® Boot Guard for hardware-based boot integrity pro-

tection; prevention of bu󰀨er overow class security threads

• Integrated solution for real-time compression, streaming write & read performance in-

creases from gen-to-gen

• Hot plug and enclosure management with Intel Volume Management Device (Intel VMD)

• Single standard server development (Accelerate NFV transition) consolidating application,

control, and data plane workloads, reducing total platform investment needs

1.3 Special Features

This section describes the health monitoring features of the motherboard. The motherboard
has an onboard ASpeed 2500 Baseboard Management Controller (BMC) that supports system
health monitoring.

Recovery from AC Power Loss

The Basic I/O System (BIOS) provides a setting that determines how the system will respond
when AC power is lost and then restored to the system. You can choose for the system to

remain powered o󰀨 (in which case you must press the power switch to turn it back on), or

18

Chapter 1: Introduction

for it to automatically return to the power-on state. See the Advanced BIOS Setup section
for this setting. The default setting is Last State.

1.4 System Health Monitoring

This section describes the health monitoring features of the X11DDW-L/NT motherboard. The
motherboard has an onboard Baseboard Management Controller (BMC) chip that supports
system health monitoring. Once a voltage becomes unstable, a warning is given or an error

message is sent to the screen. The user can adjust the voltage thresholds to dene the

sensitivity of the voltage monitor.

Onboard Voltage Monitors

The onboard voltage monitor will continuously scan crucial voltage levels. Once a voltage
becomes unstable, it will give a warning or send an error message to the screen. The user

can adjust the voltage thresholds to dene the sensitivity of the voltage monitor. Real time

readings of these voltage levels are all displayed in BIOS.

Fan Status Monitor with Firmware Control

The system health monitor embedded in the BMC chip can check the RPM status of the
cooling fans. The CPU and chassis fans are controlled via lPMI.

Environmental Temperature Control

System Health sensors in the BMC monitor the temperatures and voltage settings of onboard
processors and the system in real time via the IPMI interface. Whenever the temperature of

the CPU or the system exceeds a user-dened threshold, system/CPU cooling fans will be

turned on to prevent the CPU or the system from overheating.

Note: To avoid possible system overheating, please be sure to provide adequate air-

ow to your system.

System Resource Alert

This feature is available when used with SuperDoctor 5®. SuperDoctor 5 is used to notify the

user of certain system events. For example, you can congure SuperDoctor 5 to provide you

with warnings when the system temperature, CPU temperatures, voltages and fan speeds

go beyond a predened range.

19

X11DDW-L/NT User's Manual

1.5 ACPI Features

ACPI stands for Advanced Conguration and Power Interface. The ACPI specication denes
a exible and abstract hardware interface that provides a standard way to integrate power

management features throughout a computer system including its hardware, operating system

and application software. This enables the system to automatically turn on and o󰀨 peripherals

such as network cards, hard disk drives and printers.

In addition to enabling operating system-directed power management, ACPI also provides a
generic system event mechanism for Plug and Play and an operating system-independent

interface for conguration control. ACPI leverages the Plug and Play BIOS data structures

while providing a processor architecture-independent implementation that is compatible with
Windows 8, Windows 10, and Windows 2012 operating systems.

1.6 Power Supply

As with all computer products, a stable power source is necessary for proper and reliable
operation. It is even more important for processors that have high CPU clock rates. In areas

where noisy power transmission is present, you may choose to install a line lter to shield

the computer from noise. It is recommended that you also install a power surge protector to
help avoid problems caused by power surges.

1.7 Super I/O

The Super I/O (ASpeed AST2500 chip) provides a high-speed, 16550 compatible serial
communication port (UART), which supports serial infrared communication. The UART
includes send/receive FIFO, a programmable baud rate generator, complete modem control
capability, and a processor interrupt system. The UART provides legacy speed with baud
rate of up to 115.2 Kbps as well as an advanced speed with baud rates of 250 K, 500 K, or
1 Mb/s, supporting higher speed modems.

The Super I/O provides functions that comply with ACPI (Advanced Conguration and Power

Interface), which includes support of legacy and ACPI power management through a SMI
or SCI function pin. It also features auto power management to reduce power consumption.

20

Chapter 1: Introduction

1.8 Advanced Power Management

The following new advanced power management features are supported by the motherboard.

Intel® Intelligent Power Node Manager (IPNM)

Available when the Supermicro Power Manager (SPM) is installed, Intel's Intelligent Power
Node Manager (IPNM) provides your system with real-time thermal control and power

management for maximum energy e󰀩ciency. Although IPNM Specication Version 2.0/3.0

is supported by the BMC (Baseboard Management Controller), your system must also have

IPNM-compatible Management Engine (ME) rmware installed to use this feature.

Note: Support for IPNM 2.0/3.0 support is dependent on the power supply used in
the system.

Management Engine (ME)

The Management Engine, which is an ARC controller embedded in the IOH (I/O Hub), provides

Server Platform Services (SPS) to your system. The services provided by SPS are di󰀨erent

from those provided by the ME on client platforms.

21

X11DDW-L/NT User's Manual

Chapter 2

Installation

2.1 Static-Sensitive Devices

Electrostatic Discharge (ESD) can damage electronic com ponents. To avoid damaging
your motherboard and your system, it is important to handle it very carefully. The following

measures are generally su󰀩cient to protect your equipment from ESD.

Precautions

• Use a grounded wrist strap designed to prevent static discharge.

• Touch a grounded metal object before removing the board from the antistatic bag.

• Handle the board by its edges only; do not touch its components, peripheral chips, memory

modules or gold contacts.

• When handling chips or modules, avoid touching their pins.

• Put the motherboard and peripherals back into their antistatic bags when not in use.

• For grounding purposes, make sure that your chassis provides excellent conductivity be-

tween the power supply, the case, the mounting fasteners and the motherboard.

• Use only the correct type of CMOS onboard battery as specied by the manufacturer. Do

not install the CMOS battery upside down, which may result in a possible explosion.

Unpacking

The motherboard is shipped in antistatic packaging to avoid static damage. When unpacking
the motherboard, make sure that the person handling it is static protected.

22

Chapter 2: Installation

2.2 Motherboard Installation

All motherboards have standard mounting holes to t di󰀨erent types of chassis. Make sure

that the locations of all the mounting holes for both the motherboard and the chassis match.
Although a chassis may have both plastic and metal mounting fasteners, metal ones are
highly recommended because they ground the motherboard to the chassis. Make sure that

the metal stando󰀨s click in or are screwed in tightly.

Phillips
Screwdriver
(1)

Tools Needed

JRK1

JL1

JNVI2C2

CPU2

P2 DIMM

F1

E1

JP3

D1

P2_NVME1

P2_NVME0

Phillips
Screws (7)

LE1

C

A

JUIDB1

JPME1

JPME2

JSXB1_1

JM2_1

LE3

CPU2_PORT3

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

S-SGPIO2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

JSXB1_3

P2 DIMM

A1

BIOS LICENSE

B1

C1

SRW1

CPU2

S-SATA 0~3

MAC CODE

X11DDW-L

REV:1.02
DESIGNED IN USA

P1 DIMM

F1

E1

Stando󰀨s (7)

Only if Needed

VGA

S-SATA5

10G PHY

LEDM1

CPU1

P1 DIMM
A1

JIPMB1

JPL1

JPG1

JWD1

JBR1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JP2

JAOM

JF1

LE2

C1

B1

JPI2C1

USB2/3

LAN2

(3.0)

LAN1

IPMI_LAN
USB0/1(3.0)

C621

BMC

JBT1

I-SATA 4~7

I-SATA 0~3

BAR CODE

BT1

CPU1

D1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

X NMIPWR

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

Location of Mounting Holes

Notes: 1) To avoid damaging the motherboard and its components, please do not use

a force greater than 8 lb/inch on each mounting screw during motherboard installation.

2) Some components are very close to the mounting holes. Please take precautionary
measures to avoid damaging these components when installing the motherboard to
the chassis.

JPWR3

JPWR1

JPWR2

FAN4

FAN5FAN6

FAN3

FAN1

FAN2

23

X11DDW-L/NT User's Manual

Installing the Motherboard

1. Install the I/O shield into the back of the chassis.

2. Locate the mounting holes on the motherboard. See the previous page for the location.

3. Locate the matching mounting holes on the chassis. Align the mounting holes on the
motherboard against the mounting holes on the chassis.

4. Install stando󰀨s in the chassis as needed.

5. Install the motherboard into the chassis carefully to avoid damaging other motherboard
components.

6. Using the Phillips screwdriver, insert a Phillips head #6 screw into a mounting hole on
the motherboard and its matching mounting hole on the chassis.

7. Repeat Step 5 to insert #6 screws into all mounting holes.

8. Make sure that the motherboard is securely placed in the chassis.

Note: Images displayed in this manual are for illustration only. Your chassis or

components might look di󰀨erent from those shown in this manual.

24

Chapter 2: Installation

2.3 Processor and Heatsink Installation

Warning: When handling the processor package, avoid placing direct pressure on the label

area of the fan. Also, improper CPU installation or socket misalignment can cause serious
damage to the CPU or the motherboard that will require RMA repairs. Please read and follow
all instructions thoroughly before installing your CPU and heatsink.

Notes:

• Always connect the power cord last, and always remove it before adding, removing or

changing any hardware components. Make sure that you install the processor into the
CPU socket before you install the CPU heatsink.

• If you buy a CPU separately, make sure that you use an Intel-certied multi-directional

heatsink only.

• Make sure to install the motherboard into the chassis before you install the CPU heatsink.

• When receiving a motherboard without a processor pre-installed, make sure that the plastic

CPU socket cap is in place and none of the socket pins are bent; otherwise, contact your
retailer immediately.

• Refer to the Supermicro website for updates on CPU support.

The Processor

Note: All graphics, drawings and pictures shown in this manual are for illustration only.

The components that came with your machine may or may not look exactly the same
as those shown in this manual.

(The 81xx/61xx/51xx/41xx/31xx Processor)

25

X11DDW-L/NT User's Manual

Overview of the Processor Socket Assembly

The processor socket assembly contains 1) the 81/xx/61xx/51xx/41xx/31xx processor, 2)
CPU/heatsink carrier, 3) dust cover, and 4) CPU socket.

1. The 81xx/61xx/51xx/41xx/31xx Processor

2. CPU/Heatsink Carrier

3. Dust Cover

4. CPU Socket

WARNING!

CPU Socket Assembly

Note: Be sure to cover the CPU socket with the dust cover when the CPU is not in-

stalled.

26

Chapter 2: Installation

Overview of the Processor Heatsink Module

The processor heatsink module (PHM) contains 1) a passive heatsink, 2) a CPU/heatsink
carrier, and 3) the 81/xx/61xx/51xx/41xx/31xx processor.

1. Passive Heatsink

2. CPU/Heatsink Carrier

3. 81/xx/61xx/51xx/41xx/31xx processor

Processor Heatsink Module

(Bottom View)

27

X11DDW-L/NT User's Manual

Preparing the CPU Socket for Installation

This motherboard comes with the CPU socket pre-assembled in the factory. The CPU socket
contains 1) a dust cover, 2) a socket bracket, 3) the CPU (LGA3647) socket, and 4) a back
plate. These components are pre-installed on the motherboard before shipping.

Processor Socket Assembly

Removing the Dust Cover from the CPU Socket

Remove the dust cover from the CPU socket, exposing the LGA3647 socket and socket pins
as shown on the illustration below.

Note: Do not touch the socket pins to avoid damaging them, causing the CPU to
malfunction.

WARNING!

Socket Cover

Socket Pins

LGA3647 Socket

28

Chapter 2: Installation

Attaching the Processor to the CPU/Heatsink Carrier

To properly install the CPU onto the CPU/heatsink carrier, please follow the steps below.

1. Locate Pin 1 (Notch A), Notch B, and Notch C on the CPU and locate Pin 1 (Notch A),
Notch B, and Notch C on the CPU/heatsink carrier.

2. Align Pin 1 (Notch A), Notch B, and Notch C on the CPU with the corresponding
notches on the carrier. Once they are aligned, carefully insert the CPU into the carrier
until you hear a click. Once the CPU is properly mounted onto the carrier, the CPU/
carrier assembly is made.

Pin 1

CPU
(Upside Down)

Align CPU Notch C
and Clip C

A

A

B

Align CPU Pin 1

Align CPU Notch B
and Clip B

C

A

B

C

Allow Clip B to
Latch on to CPU

Package Carrier
(Upside Down)

B

C

CPU Mounted on

Allow Clip C to
Latch on to CPU

Package Carrier
(Upside Down)

CPU Mounted on
Package Carrier
(Rightside Up)

29

X11DDW-L/NT User's Manual

Attaching the CPU/Carrier Assembly to the Passive Heatsink to

Form the Processor Heatsink Module (PHM)

After you have made a CPU/carrier assembly, please follow the steps below to mount the
assembly onto the heatsink to create the Processor Heatsink Module (PHM).

1. Place the heatsink upside down with the thermal grease facing up. Locate two larger

mounting holes (A, B) at the diagonal corners of the heatsink, and two smaller mounting
holes (C, D) on the heatsink.

2. Hold the CPU/carrier at the center edge, and turn it upside down with the CPU pins

facing up. Locate the two larger holes (1, 2) at the diagonal corners of the carrier and
the smaller holes of the same size (3, 4) on the carrier. Please note the mounting clips
located next to every mounting hole on the carrier.

3. Align the larger holes (1, 2) on the

carrier against the larger mounting holes
(A, B) on the heatsink and smaller holes
(3, 4) on the carrier against the smaller
mounting holes (C, D) on the heatsink.
Insert the mounting clips next to the
larger hole on the carrier into the larger
mounting hole on the heatsink (1 A,
2 B) and snap the mounting clips next
to the smaller holes on the carrier onto
the edges of the heatsink next to the
smaller holes (3 C, 4 D) making sure
that the mounting clips snap into place,
and that the CPU/carrier assembly is
properly mounted onto the heatsink. By
mounting the CPU/carrier assembly to
the heatsink, the Processor Heatsink
Module (PHM) is assembled.

CPU and Carrier Package

(Upside Down)

Mounting
Clips

CPU and Carrier Package

(Upside Down)

4

D

Heatsink

(Upside Down)

D

Mounting
Clips

2

1

B

A

B

CPU and Carrier Package

(Rightside Up)

Mounting
Clips

3

c

Thermal paste

On Locations (C, D), the
clips snap onto
the heatsink’s sides

c

30

On Locations of (A, B), the
clips snap through the heatsink’s
mounting holes

A

Make sure Mounting
Clips snap into place

Chapter 2: Installation

Installing the Processor Heatsink Module (PHM)

1. Once you have assembled the processor heatsink module (PHM) by following the

instructions listed on the previous page, align the processor heatsink module with the
CPU socket on the motherboard.

2. Align the large hole on the heatsink against the large notch on the CPU socket, the

small hole on the heatsink against the small notch on the socket. Carefully insert the

PHM into the socket, making sure that the large and small notches t through the
corresponding mounting holes on the socket. The PHM will only t one way. If it does
not t correctly, remove it and try again.

3. Using a T30-size star driver bit, tighten four screws into the mounting holes on the

socket to securely install the PHM into the motherboard, starting with the mounting hole
marked #1 (in the sequence of 1, 2, 3, and 4).

Note: Do not use excessive force when tightening the screws to avoid damaging the
CPU and the socket.

#2

#4

Tighten the
screws in the
sequence of 1, 2,
3, 4.

#4

#1

#2

#3

#3

#1

Small Hole

Small

Notch

Use a torque of 8 lbf

Processor Heatsink

Module (Bottom View)

Large

Hole

#3

#1

Large
Notch

#3

#1

31

X11DDW-L/NT User's Manual

Removing the Processor Heatsink Module (PHM)

Before starting to remove the processor heatsink module (PHM), unplug power cord from
the power outlet.

1. Using a T30-size star driver, turn the screws on the PHM counterclockwise to loosen it
from the socket, starting with screw marked #4 (in the sequence of 4, 3, 2, 1).

2. After all four screws are removed, wiggle the PHM gently and pull up to remove it from
the socket.

Note: To properly remove the processor heatsink module, be sure to loosen and re­move the screws on the PHM in the sequence of 4, 3, 2, 1 as shown below.

#2

#4

Removing the
screws in the
sequence of 4, 3,
2, 1.

#4

#1

#2

#3

#3

#1

#4

#1

Starting from here

#2

#3

#2

#4

#3

32

Chapter 2: Installation

2.4 Memory Support and Installation

Note: Check the Supermicro website for recommended memory modules.

Important: Exercise extreme care when installing or removing DIMM modules to pre-

vent any damage.

Memory Support

The X11DDW-L/NT supports up to 1536GB of Load Reduced DIMM (LRDIMM), Registered
DIMM (RDIMM), and Non-Volatile DIMM (NV-DIMM) DDR4 (288-pin) ECC 2666MT/s modules
in 12 slots. Populating these DIMM modules with a pair of memory modules of the same type
and size will result in interleaved memory, which will improve memory performance.

Notes: 1. Be sure to use memory modules of the same type and speed on the moth-

erboard. Mixing of memory modules of di󰀨erent types and speeds is not allowed.

2. When installing memory modules, be sure to populate the rst DIMM module on
the blue memory slot, which is the rst memory slot of a memory channel, and then
populate the second DIMM in the black slot if 2DPC memory conguration is used.

3. Using unbalanced memory topology by populating two DIMMs in one channel while
populating one DIMM in another channel will result in reduced memory performance.

DDR4 Memory Support for the Intel Xeon 81/xx/61xx/51xx/41xx/31xx Processor Platform

Ranks

Type

RDIMM SRx4 8 GB 16 GB 2666 2666

RDIMM SRx8 4 GB 8 GB 2666 2666

RDIMM DRx8 8 GB 16 GB 2666 2666

RDIMM DRx4 16 GB 32 GB 2666 2666

RDIMM 3Ds

LRDIMM QRx4 32 GB 64 GB 2666 2666

LRDIMM 3Ds

Per

DIMM

and Data

Width

QRX4 N/A 2H-64GB 2666 2666

8RX4 N/A 4H-128GB 2666 2666

QRX4 N/A 2H-64GB 2666 2666

8Rx4 N/A 4H-128 GB 2666 2666

DIMM Capacity

(GB)

4 Gb 8 Gb 1.2 V 1.2 V

Speed (MT/s); Voltage (V); Slots per Channel (SPC) and DIMMs per Channel (DPC)

2 Slots per Channel

1DPC (1-DIMM per Channel) 2DPC (2-DIMM per Channel)

DDR4 Memory Support for the Intel Xeon 81/xx/61xx/51xx/41xx/31xx Processor Platform

Ranks

Type

RDIMM SRx4 8 GB 16 GB 2666

RDIMM SRx8 4 GB 8 GB 2666

RDIMM DRx8 8 GB 16 GB 2666

RDIMM DRx4 16 GB 32 GB 2666

RDIMM 3Ds

LRDIMM QRx4 32 GB 64 GB 2666

LRDIMM 3Ds

Per

DIMM

and Data

Width

QRX4 N/A 2H-64GB 2666

8RX4 N/A 4H-128GB 2666

QRX4 N/A 2H-64GB 2666

8Rx4 N/A 4H-128 GB 2666

DIMM Capacity

(GB)

4 Gb 8 Gb 1.2 V

Speed (MT/s); Voltage (V); Slots per Channel (SPC) and DIMMs per Channel (DPC)

1 Slot per Channel

1DPC (1-DIMM per Channel)

33

X11DDW-L/NT User's Manual

DIMM Population Requirements

For optimal memory performance, follow the tables below when populating memory modules.

Key Parameters for DIMM Congurations

Parameters Possible Values

Number of Channels 1, 2, 3, 4, 5, or 6

Number of DIMMs per Channel 1DPC (1 DIMM Per Channel) or 2DPC (2 DIMMs Per Channel)

DIMM Type RDIMM (w/ECC), LRDIMM, 3DS-LRDIMM

DIMM Construction • non-3DS RDIMM Raw Cards: A/B (2RX4), C (1RX4),

D (1RX8), E (2RX8)

• 3DS RDIMM Raw Cards: A/B (4RX4)

• non-3DS LRDIMM Raw Cards: D/E (4RX4)

• 3DS LRDIMM Raw Cards: A/B (8RX4)

General Population Requirements

DIMM Mixing Rules

• All DIMMs must be DDR4 DIMMs only.

• X4 and X8 DIMMs can be mixed in the same channel.

• Mixing of LRDIMMs and RDIMMs is not allowed in the same channel, across di󰀨erent channels, and across

di󰀨erent sockets.

• Mixing of non-3DS and 3DS LRDIMM is not allowed in the same channel, across di󰀨erent channels, and across

di󰀨erent sockets.

Mixing of DIMM Types within a Channel

DIMM Types RDIMM LRDIMM 3DS LRDIMM

RDIMM Allowed Not Allowed Not Allowed

LRDIMM Not Allowed Allowed Not Allowed

3DS LRDIMM Not Allowed NotAllowed Allowed

34

DDR4 Only Socket Level Population Requirements

DDR4 Socket Level Minimum Population Requirements

• There should be at least one DDR4 DIMM per socket.

• If only one DIMM is populated in a channel, then populate it in the slot furthest away from CPU.

• Always populate DIMMs with a higher electrical loading in DIMM0 followed by DIMM1.

DDR4 Only Memory Populations with Possible Mixes

DDR4 RDIMM DIMM0/DIMM1

Within

IMC

DIMM

Popula-

tion

DDR0 x8, None, x8, x8 x4, None, x4, x4 x8, x4, or x4, x8 Single Rank, None

DDR1 None or same as

DDR2 None or same as

Cong. Set A

DDR0

DDR1 (excludes

DIMM 1 in 5DIMM

congurations)

DDR4 Only Memory Populations with Possible Mixes

3DS LRDIMM or 3DS RDIMM DIMM0/DIMM1 Cong. Set A Possible Mixes

Within IMC

DIMM Popu-

lation

DDR0 x4, None, x4, x4 Quad Rank, None

DDR1 None or same as DDR0

DDR2 None or same as DDR1

DIMM0/DIMM1

Cong. Set B

None or same as

DDR0

None or same as

DDR1 (excludes

DIMM 1 in 5DIMM

congurations)

DIMM0/DIMM1 Con-

g. Set C

None or same as

DDR0

None or same as

DDR1 (excludes DIMM

1 in 5DIMM congura-

tions)

DIMM0/DIMM1

Quad Rank, Quad Rank

Cannot mix 3DS LRDIMM and RDIMM

Single Rank, Single Rank

Dual Rank, Single Rank,

Dual Rank, Dual Rank,

Single Rank, Single Rank

Chapter 2: Installation

Possible Mixes

DIMM0/DIMM1

Dual Rank, None

LRDIMMs DIMM0/DIMM1 Possible Mixes

Within IMC

DIMM Popu-

lation

DIMM Population

within an IMC

(Note: Uniformly
populate with x8
DRAMs DIMMs)

DIMM Population

within an IMC

(Note: Non-equal

in rank pair of x8

DIMMs)

DDR4 Only Memory Populations with Possible Mixes

DIMM0/DIMM1

DDR0 x4, None, x4, x4 Quad Rank, None

DDR1 None or same as DDR0

DDR2 None or same as DDR1

Quad Rank, Quad Rank

Note: Requirements
*Match DIMM types installed across DDR

channels within an IMC

*Always populate iMC0 rst

Purley DDR4 Only 2SPC Memory Conguration with x8 DIMMs

Total # of

DIMMs

1 x8 DIMM Must be installed on iMC0 DDR Channel 0 1 N/A

2 x8 DIMMs DDR0: Populate with 1 DIMM

3 x8 DIMMs DDR0: Populate with 1 DIMM

4 x8 DIMMs DDR0: Populate with 2 DIMMs

5 x8 DIMMs DDR Channel 0, 1, 2: DIMM0 is populated with identi-

DDR Channel 0, 1: DIMM1 is populated with identical

6 x8 DIMMs Populate 2 DIMMs per DDR channel x SVLS

1 pair of

DIMMs

2 pairs of

DIMMs

3 pairs of

DIMMs

2 pairs+1
(5DIMMs)

DDR1: Populate the second DIMM (for best perfor-

DDR0: Populate with 1 pair of non-equal rank DIMMs

DDR0: Populate with 1 pair of non-equal rank DIMMs

DDR0: Populate with 1 pair of non-equal rank DIMMs

DDR1: Populate with identical DIMMs as DDR0

DDR2: DIMM0 is populated with identical DIMM as

DDR Channel Number

DDR1: Populate identically as DDR0

DDR1: Populate identically as DDR0
DDR2: Populate identically as DDR1

DDR1: Populate identically as DDR0

cal DIMMs,

DIMMs

DDR0: Populate with 1 DIMM

mance)

DDR1: Populate identically as DDR0

DDR1: Populate identically as DDR0
DDR2: Populate identically as DDR1

DDR1

of Ranks

>1 SVLS

1 N/A

>1 SVLS

1 N/A

>1 SVLS

x SVLS

>1 SVLS

1 N/A

>1 SVLS

1 N/A

>1 SVLS

x SVLS

>1 SVLS

Virtual

Lock Step

35

X11DDW-L/NT User's Manual

Purley DDR4 Only 2SPC Memory Conguration with x4 DIMMs

Total # of

DIMMs

DIMM Popula­tion within an

IMC

Note: Uniformly

populate with x4
DRAMs/DIMMs

1 x4 DIMM Must be installed on iMC0 DDR Channel 0 1 Y, only Bank VLS

2 x4 DIMMs DDR0: Populate with 1 DIMM

3 x4 DIMMs DDR0: Populate with 1 DIMM

4 x4 DIMMs DDR0: Populate with 2 DIMMs

5 x4 DIMMs DDR Channel 0, 1, 2: DIMM0 is populated with identi-

DDR Channel 0, 1: DIMM1 is populated with identical

6 x4 DIMMs Populate 2 DIMMs per DDR channel x Y

DDR Channel Number

DDR1: Populate identically as DDR0

DDR1: Populate identically as DDR0
DDR2: Populate identically as DDR1

DDR1: Populate identically as DDR0

cal DIMMs,

DIMMs

of Ranks

Adaptive Virtual

Lock Step

>1 Y

1 Y, only Bank VLS

>1 Y

1 Y, only Bank VLS

>1 Y

x Y

>1 Y

DIMM Popula­tion within an

IMC

Note: Non-

equal in rank

pair of x4

DIMMs)

1 pair of

DIMMs

2 pairs of

DIMMs

3 pairs of

DIMMs

2 pairs+1

(5DIMMs)

DDR0: Populate with 1 DIMM

DDR1: Populate the second DIMM (for best perfor-

DDR0: Populate with 1 pair of non-equal rank DIMMs

DDR1: Populate identically as DDR0

DDR0: Populate with 1 pair of non-equal rank DIMMs

DDR1: Populate identically as DDR0
DDR2: Populate identically as DDR1

DDR0: Populate with 1 pair of non-equal rank DIMMs

DDR1: Populate with identical DIMMs as DDR0

DDR2: DIMM0 is populated with identical DIMM as

mance)

DDR1

>1 Y

>1 Y

x Y

>1 Y

Purley DDR4 Only 2SPC Memory Conguration with x8/x4 DIMMs Mixed

DDR4 RDIMM Total # of DIMMs DDR Channel ADDC/SDDC

DIMM Popula­tion within an

IMC

1 pair of x8, x4 DDR0: Populate with 1 DIMM

2 pairs of x8, x4 Populate with 1 pair of DIMMs on DDR0,

3 pairs of x8, x4 A pair of DIMMs on DDR0, and identical pair on

DDR1: Populate the second DIMM (for best perfor-

mance)

and identical pair on DDR1

DDR1, and DDR2

Features

No

No

No

36

JBMC_DEBUG

SRW1

JSDCARD1

JM2_1

JUIDB1

JP3

FAN5FAN6

FAN4

FAN3

FAN2

FAN1

JBT1

LE3

LE1

C

A

LEDM1

LE2

JNVI2C1

JIPMB1

JNVI2C2

JPME2

JPME1

JPL1

JPG1

S-SGPIO2

BT1

+

JSTBY1

JD1

1

JVRM1JVRM2

JL1

JP2

JF1

JPWR1

JPWR2

JPI2C1

JPWR3

JTPM1

JRK1

JSXB1_2

JAOM

JSXB1_1

JSXB1_3

BAR CODE

X11DDW-L

REV:1.02

MAC CODE

DESIGNED IN USA

BIOS LICENSE

I-SATA 4~7

I-SATA 0~3

S-SATA 0~3

P1_NVME1

P1_NVME0

P2_NVME1

P2_NVME0

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

CPU2_PORT3

SXB2:CPU2 PCI-E 3.0 X16

USB4/5(3.0)

USB0/1(3.0)

USB2/3
(3.0)

S-SATA5

S-SATA4

VGA

LAN1

LAN2

XNMIPWR

LED

NICHDD

LED

NIC
2 1

UID
LEDPSFAIL

PWRRST
ON

IPMI_LAN

F1

P1 DIMM

E1

D1

CPU1

JWD1

JBR1

CPU1

P1 DIMM

B1

A1

C1

A1

P2 DIMM

B1

C1

CPU2

F1

P2 DIMM

E1

D1

CPU2

C621

10G PHY

BMC

DIMM Installation

1. Insert DIMM modules in the following
order: For CPU1, begin with P1-DIMMC1,
P1-DIMMB1, P1-DIMMA1 then P1­DIMMF1, P1-DIMME1, P1-DIMMD1.
For CPU2, begin with P2-DIMMC1, P2­DIMMB1, P2-DIMMA1 then P2-DIMMF1,
P2-DIMME1, P2-DIMMD1. For the system
to work properly, please use memory
modules of the same type and speed on
the motherboard.

2. Push the release tabs outwards on both
ends of the DIMM slot to unlock it.

3. Align the key of the DIMM module with the
receptive point on the memory slot.

Chapter 2: Installation

4. Align the notches on both ends of the

Notches

module against the receptive points on the
ends of the slot.

5. Use two thumbs together to press the
notches on both ends of the module
straight down into the slot until the module
snaps into place.

Release Tabs

6. Press the release tabs to the lock positions
to secure the DIMM module into the slot.

Press both notches

straight down into

DIMM Removal

the memory slot.

Reverse the steps above to remove the DIMM
modules from the motherboard.

37

X11DDW-L/NT User's Manual

JPG1

JBR1

2.5 Rear I/O Ports

See the gure below for the locations and descriptions of the various I/O ports on the rear

of the motherboard.

LE1

C

A

JUIDB1

JPME1

JSXB1_1

JPME2

LAN2

JM2_1

LE3

CPU2_PORT3

USB2/3
(3.0)

LAN1

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

P2_NVME1

E1

JNVI2C2

P2_NVME0

CPU2

D1

JRK1

JL1

P2 DIMM

F1

JP3

S-SGPIO2

JSXB1_3

P2 DIMM

A1

BIOS LICENSE

B1

C1

SRW1

X11DDW-L

REV:1.02
DESIGNED IN USA

P1 DIMM

CPU2

S-SATA 0~3

MAC CODE

F1

E1

I-SATA 0~3

CPU1

D1

BAR CODE

BT1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

JBT1

I-SATA 4~7

XNMIPWR

IPMI_LAN
USB0/1(3.0)

BMC

10G PHY

LEDM1

CPU1

VGA

P1 DIMM

A1

S-SATA5

JIPMB1

JPL1

JWD1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JP2

JAOM

JF1

LE2

C1

B1

JPI2C1

JPWR3

JPWR1

JPWR2

FAN4

FAN5FAN6

FAN3

FAN2

Back panel I/O Port Locations and Denitions

2

1

6

4

5

3

8

7

Back Panel I/O Ports

FAN1

9

No. Description No. Description

1. VGA port 6. USB3 (3.0)

2. Dedicated IPMI LAN 7. LAN2

3. USB0 (3.0) 8. LAN1

4. USB1 (3.0) 9. Unit Identier Switch

5. USB2 (3.0)

38

Chapter 2: Installation

JP3

JPG1

JBR1

VGA Port

The onboard VGA port is located next to IPMI LAN port on the I/O back panel. Use this
connection for VGA display.

Unit Identier Switch/UID LED Indicator

A Unit Identier (UID) switch (UID) and a UID LED Indicator (LE1) are located on the I/O

back panel. When you press the UID switch, the UID LED indicator will be turned on. Press

the UID switch again to turn o󰀨 the LED. The UID Indicator provides easy identication of a

system unit that may be in need of service.

Note: UID can also be triggered via IPMI on the motherboard. For more information
on IPMI, please refer to the IPMI User's Guide posted on our website at http://www.
supermicro.com.

UID Switch

Pin Denitions

Pin# Denition

1 Ground

Color Status

Blue: On Unit Identied

UID LED

Pin Denitions

2 Ground

3 Button In

4 Button In

IPMI_LAN
USB0/1(3.0)

BMC

10G PHY

LEDM1

CPU1

P1 DIMM

1

VGA

S-SATA5

JIPMB1

JPL1

JWD1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JP2

JAOM

JF1

LE2

A1

C1

B1

1. VGA Port

2. UID Switch

3. UID LED

2 3

LE1

C

A

JUIDB1

JPME1

JPME2

JSXB1_1

JM2_1

LE3

CPU2_PORT3

LAN2

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

P2_NVME1

JRK1

JL1

JNVI2C2

P2 DIMM

F1

E1

P2_NVME0

CPU2

D1

S-SGPIO2

JSXB1_3

P2 DIMM

A1

BIOS LICENSE

B1

C1

SRW1

X11DDW-L

REV:1.02
DESIGNED IN USA

P1 DIMM
F1

CPU2

S-SATA 0~3

MAC CODE

E1

D1

CPU1

I-SATA 0~3

I-SATA 4~7

BAR CODE

BT1

USB2/3
(3.0)

LAN1

JBT1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

X NMIPWR

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

FAN5FAN6

JPI2C1

JPWR3

JPWR1

JPWR2

FAN4

FAN3

FAN1

FAN2

39

X11DDW-L/NT User's Manual

JP3

JPG1

JBR1

Universal Serial Bus (USB) Ports

There are two USB 3.0 ports (USB0/1) and two USB 3.0 ports (USB2/3) on the I/O back
panel. There is one USB 3.0 header (USB4/5) on the motherboard to provide front access
USB connection.

Front Panel USB 4/5 (3.0/2.0)

Pin Denitions

Pin# Denition Pin# Denition

1 VBUS 11 IntA_P2_D+

2 IntA_P1_SSRX- 12 IntA_P2_D-

3 IntA_P1_SSRX+ 13 GND

4 GND 14 IntA_P2_SSTX+

5 IntA_P1_SSTX- 15 IntA_P2_SSTX-

6 IntA_P1_SSTX+ 16 GND

7 GND 17 IntA_P2_SSRX+

8 IntA_P1_D- 18 IntA_P2_SSRX-

9 IntA_P1_D+ 19 VBus

ID

10

LE1

C

A

JUIDB1

JPME1

JPME2

JSXB1_1

JM2_1

LE3

CPU2_PORT3

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

S-SGPIO2

SRW1

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

BIOS LICENSE

JSXB1_3

X11DDW-L

P2 DIMM

A1

B1

C1

REV:1.02
DESIGNED IN USA

CPU2

P2_NVME1

JNVI2C2

E1

P2_NVME0

CPU2

D1

JRK1

JL1

P2 DIMM

F1

S-SATA 0~3

MAC CODE

P1 DIMM
F1

E1

LAN2

LAN1

C621

JBT1

I-SATA 4~7

I-SATA 0~3

P1_NVME1

BAR CODE

P1_NVME0

+

BT1

CPU1

D1

Back Panel USB (3.0)

Pin Denitions

Pin# Denition Pin# Denition

1 VBUS 10 Power

2 D- 11 USB 2.0 Di󰀨erential Pair

3 D+ 12

4 Ground 13 Ground of PWR Return

5 StdA_SSRX- 14 SuperSpeed Receiver

6 StdA_SSRX+ 15 Di󰀨erential Pair

7 GND_DRAIN 16 Ground for Signal Return

8 StdA_SSTX- 17 SuperSpeed Transmitter

9 StdA_SSTX+ 18 Di󰀨erential Pair

1

2

VGA

S-SATA5

10G PHY

LEDM1

CPU1

P1 DIMM

A1

JIPMB1

JPL1

JWD1

S-SATA4

JSTBY1

USB4/5(3.0)

3

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JP2

JAOM

JF1

LE2

C1

B1

USB2/3
(3.0)

IPMI_LAN
USB0/1(3.0)

BMC

JNVI2C1

JSDCARD1

XNMIPWR

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

1. USB0/1

2. USB2/3

3. USB4/5

FAN5FAN6

JPI2C1

JPWR3

JPWR1

JPWR2

FAN4

FAN3

FAN1

FAN2

40

Chapter 2: Installation

Ethernet Ports

Two LAN ports (LAN1/LAN2) and a dedicated IPMI LAN are located on the I/O back panel.
These LAN ports are supported by the onboard AST 2500 BMC and accepts an RJ45 type
cable. Refer to the LED Indicator Section for LAN LED information.

LAN Ports

Pin Denition

Pin# Denition Pin# Denition

1 10 sgnd

2 TD0+ 11 Act LED

3 TD0- 12 P3V3SB

TD1+

4

TD1-

5

6 TD2+ 15 Ground

7 TD2- 16 Ground

8 TD3+ 17 Ground

9 TD3- 18 Ground

13

14

Link 100 LED

(Yellow, +3V3SB)

Link 1000 LED

(Yellow, +3V3SB)

LE1

2 1 3

C

A

JUIDB1

JPME1

JSXB1_1

JPME2

LAN2

JM2_1

LE3

CPU2_PORT3

USB2/3
(3.0)

LAN1

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

P2_NVME1

JNVI2C2

D1

P2_NVME0

CPU2

JRK1

JL1

P2 DIMM

F1

E1

JP3

S-SGPIO2

JSXB1_3

P2 DIMM

A1

BIOS LICENSE

B1

C1

SRW1

CPU2

S-SATA 0~3

MAC CODE

X11DDW-L

REV:1.02

DESIGNED IN USA

P1 DIMM

F1

E1

I-SATA 0~3

BAR CODE

CPU1

D1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

BT1

X NMIPWR

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

JBT1

I-SATA 4~7

IPMI_LAN
USB0/1(3.0)

BMC

10G PHY

LEDM1

CPU1

VGA

JP2

P1 DIMM

A1

S-SATA5

JIPMB1

JPL1

JPG1

JWD1

JBR1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JAOM

JF1

LE2

C1

B1

JPI2C1

JPWR3

JPWR1

JPWR2

1. LAN1

2. LAN2

3. IPMI LAN

FAN5FAN6

FAN4

FAN3

FAN1

FAN2

41

X11DDW-L/NT User's Manual

JP3

JPG1

JBR1

2.6 Front Control Panel

JF1 contains header pins for various buttons and indicators that are normally located on a

control panel at the front of the chassis. These connectors are designed specically for use
with Supermicro chassis. See the gure below for the descriptions of the front control panel

buttons and LED indicators.

LE1

C

A

JUIDB1

JPME1

JSXB1_1

JPME2

LAN2

JM2_1

LE3

CPU2_PORT3

USB2/3
(3.0)

LAN1

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

P2_NVME1

JNVI2C2

E1

P2_NVME0

CPU2

D1

JRK1

JL1

P2 DIMM
F1

S-SGPIO2

JSXB1_3

P2 DIMM
A1

BIOS LICENSE

B1

C1

SRW1

X11DDW-L

REV:1.02
DESIGNED IN USA

CPU2

S-SATA 0~3

P1 DIMM

F1

MAC CODE

CPU1

E1

D1

I-SATA 0~3

I-SATA 4~7

BAR CODE

BT1

JBT1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

XNMIPWR

IPMI_LAN
USB0/1(3.0)

BMC

10G PHY

LEDM1

CPU1

VGA

JP2

P1 DIMM
A1

S-SATA5

JIPMB1

JPL1

JWD1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JAOM

JF1

LE2

C1

B1

FAN5FAN6

Figure 2-3. JF1 Header Pins

Power Button

Reset Button

Power Fail

NIC2 Activity LED

NIC1 Activity LED

HDD LED

PWR

Reset

UID LED

JPI2C1

JPWR3

JPWR1

JPWR2

FAN4

FAN3

2

1

FAN1

FAN2

Ground

Ground

3.3V

OH/Fan Fail LED

3.3V Stby

3.3V Stby

3.3V Stby

Power LED

NMI

X

3.3V

X

Ground

19 20

42

Chapter 2: Installation

Power Button

The Power Button connection is located on pins 1 and 2 of JF1. Momentarily contacting both

pins will power on/o󰀨 the system. This button can also be congured to function as a suspend
button (with a setting in the BIOS - see Chapter 4). To turn o󰀨 the power when the system

is in suspend mode, press the button for 4 seconds or longer. Refer to the table below for

pin denitions.

Power Button

Pin Denitions (JF1)

Pins Denition

1 Signal

2 Ground

Reset Button

The Reset Button connection is located on pins 3 and 4 of JF1. Attach it to a hardware reset

switch on the computer case to reset the system. Refer to the table below for pin denitions.

Power Button

1

Reset Button

2

NIC2 Activity LED

NIC1 Activity LED

PWR

Reset

Power Fail

UID LED

HDD LED

Reset Button

Pin Denitions (JF1)

Pins Denition

3 Reset

4 Ground

2

1

Ground

Ground

3.3V

OH/Fan Fail LED

3.3V Stby

3.3V Stby

3.3V Stby

1. PWR Button

2. Reset Button

Power LED

X

NMI

19 20

3.3V

X

Ground

43

X11DDW-L/NT User's Manual

Power Fail LED

The Power Fail LED connection is located on pins 5 and 6 of JF1. Refer to the table below

for pin denitions.

Power Fail LED

Pin Denitions (JF1)

Pin# Denition

5 3.3V

6 PWR Supply Fail

Fan Fail and UID LED

Connect an LED cable to pins 7 and 8 of the front control panel to use the Overheat/Fan
Fail LED connections. The LED on pin 8 provides warnings of overheat or fan failure. Refer

to the tables below for pin denitions.

OH/Fan Fail Indicator

State Denition

O󰀨 Normal

On Overheat

Flashing Fan Fail

Power Button

Reset Button

Power Fail

1

2

NIC2 Activity LED

NIC1 Activity LED

Status

PWR

Reset

UID LED

OH/Fan Fail LED

Pin Denitions (JF1)

Pin# Denition

7 Blue LED

8 OH/Fan Fail LED

2

1

Ground

Ground

3.3V

OH/Fan Fail LED

3.3V Stby

3.3V Stby

3

1. Power Fail LED

2. UID LED

3. OH/Fan Fail LED

HDD LED

Power LED

X

NMI

19 20

3.3V Stby

3.3V

X

Ground

44

Chapter 2: Installation

NIC1/NIC2 (LAN1/LAN2)

The NIC (Network Interface Controller) LED connection for LAN port 1 is located on pins
11 and 12 of JF1, and LAN port 2 is on pins 9 and 10. Attach the NIC LED cables here to

display network activity. Refer to the table below for pin denitions.

LAN1/LAN2 LED

Pin Denitions (JF1)

Pin# Denition

9 NIC 2 Activity LED

11 NIC 1 Activity LED

HDD LED

The HDD LED connection is located on pins 13 and 14 of JF1. Attach a cable to pin 14 to

show hard drive activity status. Refer to the table below for pin denitions.

Power Button

Reset Button

Power Fail

NIC2 Activity LED

1

2

NIC1 Activity LED

PWR

Reset

UID LED

HDD LED

Pin Denitions (JF1)

Pins Denition

13 3.3V Stdby

14 HDD Active

2

1

Ground

Ground

3.3V

OH/Fan Fail LED

3.3V Stby

3.3V Stby

1. NIC2 LED

2. NIC1 LED

3. HDD LED

HDD LED

3

Power LED

X

NMI

19 20

3.3V Stby

3.3V

X

Ground

45

X11DDW-L/NT User's Manual

Power LED

The Power LED connection is located on pins 15 and 16 of JF1. Refer to the table below

for pin denitions.

Power LED

Pin Denitions (JF1)

Pins Denition

15 3.3V

16 PWR LED

NMI Button

The non-maskable interrupt (NMI) button header is located on pins 19 and 20 of JF1. Refer

to the table below for pin denitions.

NMI Button

Pin Denitions (JF1)

Pins Denition

19 Control

20 Ground

1

Power Button

Reset Button

NIC2 Activity LED

NIC1 Activity LED

1

PWR

Reset

Power Fail

UID LED

HDD LED

Power LED

NMI

2

X

19 20

2

Ground

Ground

3.3V

OH/Fan Fail LED

3.3V Stby

3.3V Stby

3.3V Stby

3.3V

X

Ground

1. Power LED

2. NMI

46

Chapter 2: Installation

2.7 Connectors

Power Connector

ATX and CPU Power Connectors

JPWR3 is the 24-pin ATX main power supply connector. This primary power supply connector

meets the ATX SSI EPS 24-pin specication. You must also connect the 8-pin (JPWR1/

JPWR2) CPU power connectors to your power supply.

ATX Power 24-pin Connector

Pin Denitions

Pin# Denition Pin# Denition

13 +3.3V 1 +3.3V

14 NC 2 +3.3V

15 Ground 3 Ground

16 PS_ON 4 +5V

17 Ground 5 Ground

18 Ground 6 +5V

19 Ground 7 Ground

20 Res (NC) 8 PWR_OK

21 +5V 9 5VSB

22 +5V 10 +12V

23 +5V 11 +12V

24 Ground 12 +3.3V

LE1

C

A

JUIDB1

JPME1

JSXB1_1

JPME2

JM2_1

LE3

CPU2_PORT3

USB2/3
(3.0)

LAN2

LAN1

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

P2_NVME1

JNVI2C2

E1

P2_NVME0

CPU2

D1

JRK1

JL1

P2 DIMM

F1

JP3

S-SGPIO2

JSXB1_3

P2 DIMM
A1

BIOS LICENSE

B1

C1

SRW1

X11DDW-L

REV:1.02
DESIGNED IN USA

CPU2

S-SATA 0~3

MAC CODE

P1 DIMM

F1

E1

I-SATA 0~3

CPU1

D1

BAR CODE

BT1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

JBT1

I-SATA 4~7

XNMIPWR

IPMI_LAN

USB0/1(3.0)

BMC

10G PHY

LEDM1

CPU1

VGA

P1 DIMM
A1

S-SATA5

JIPMB1

JPL1

JPG1

JWD1

JBR1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JP2

JAOM

JF1

LE2

C1

B1

JPI2C1

JPWR3

1. ATX Power Supply

1

JPWR1

JPWR2

FAN4

FAN5FAN6

FAN3

FAN1

FAN2

47

X11DDW-L/NT User's Manual

JPG1

JBR1

12V 8-pin CPU Power Connectors

JPWR1 and JPWR2 are the 8-pin 12V DC power input for the CPU or alternative single
power source for a special enclosure when the 24-pin ATX power is not in use. Refer to the

table below for pin denitions.

12V 8-pin Power

Pin Denitions

Pin# Denition

1 - 4 Ground

5 - 8 +12V

LE1

C

A

JUIDB1

JPME1

JSXB1_1

JPME2

LAN2

JM2_1

LE3

CPU2_PORT3

USB2/3
(3.0)

LAN1

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

JSXB1_3

P2_NVME1

JNVI2C2

D1

P2_NVME0

CPU2

JRK1

JL1

P2 DIMM

F1

E1

JP3

S-SGPIO2

P2 DIMM

A1

BIOS LICENSE

B1

C1

SRW1

S-SATA 0~3

MAC CODE

X11DDW-L

REV:1.02
DESIGNED IN USA

P1 DIMM

F1

E1

CPU2

I-SATA 0~3

BAR CODE

CPU1

D1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

BT1

X NMIPWR

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

JBT1

I-SATA 4~7

IPMI_LAN
USB0/1(3.0)

BMC

10G PHY

LEDM1

CPU1

P1 DIMM

A1

VGA

S-SATA5

JIPMB1

JPL1

JWD1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JP2

JAOM

JF1

LE2

C1

B1

JPI2C1

JPWR3

JPWR1

1

JPWR2

1. JPWR1

2. JPWR2

2

FAN4

FAN5FAN6

FAN3

FAN1

FAN2

48

Chapter 2: Installation

JPG1

JBR1

Headers

Onboard Fan Header

This motherboard has six fan headers (FAN1~6) on the motherboard. This is a 4-pin fan
header, which is backward compatible with a traditional 3-pin fan. The onboard fan speed
is controlled by Thermal Management (via Hardware Monitoring) in the BIOS. When using
Thermal Management setting, please use all 3-pin fans or all 4-pin fans.

Fan Header

Pin Denitions

Pin# Denition

1 Ground (Black)

2 +12V (Red)

3 Tachometer

4 PWM Control

LE1

C

A

JUIDB1

JPME1

JSXB1_1

JPME2

LAN2

JM2_1

LE3

CPU2_PORT3

USB2/3
(3.0)

LAN1

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

P2_NVME1

JNVI2C2

D1

P2_NVME0

CPU2

JRK1

JL1

P2 DIMM

F1

E1

JP3

S-SGPIO2

JSXB1_3

P2 DIMM

A1

BIOS LICENSE

B1

SRW1

C1

S-SATA 0~3

MAC CODE

X11DDW-L

REV:1.02
DESIGNED IN USA

P1 DIMM

F1

E1

CPU2

I-SATA 0~3

BAR CODE

CPU1

D1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

BT1

X NMIPWR

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

JBT1

I-SATA 4~7

IPMI_LAN
USB0/1(3.0)

BMC

10G PHY

LEDM1

CPU1

VGA

JP2

P1 DIMM
A1

S-SATA5

JIPMB1

JPL1

JWD1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JAOM

JF1

LE2

C1

B1

JPI2C1

JPWR3

JPWR1

JPWR2

1. FAN1

2. FAN2

3. FAN3

4. FAN4

5. FAN5

6. FAN6

FAN5FAN6

6

5

FAN4

FAN3

34 2

FAN1

FAN2

1

49

X11DDW-L/NT User's Manual

JPG1

JBR1

TPM Header

The JTPM1 header is used to connect a Trusted Platform Module (TPM)/Port 80, which is
available from a third-party vendor. A TPM/Port 80 connector is a security device that supports
encryption and authentication in hard drives. It allows the motherboard to deny access if the
TPM associated with the hard drive is not installed in the system. See the table below for

pin denitions.

Trusted Platform Module/Port 80 Header

Pin Denitions

Pin# Denition Pin# Denition

1 +3.3V 2 SPI_CS#

3 RESET# 4 SPI_MISO

5 SPI_CLK 6 GND

7 SPI_MOSI 8

9 +3.3V Stdby 10 SPI_IRQ#

LE1

C

A

JUIDB1

JPME1

JSXB1_1

JPME2

LAN2

JM2_1

LE3

CPU2_PORT3

USB2/3
(3.0)

LAN1

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

P2_NVME1

JRK1

JL1

JNVI2C2

P2 DIMM

F1

E1

JP3

P2_NVME0

CPU2

D1

S-SGPIO2

JSXB1_3

P2 DIMM

A1

BIOS LICENSE

B1

C1

SRW1

S-SATA 0~3

MAC CODE

X11DDW-L

REV:1.02
DESIGNED IN USA

P1 DIMM

F1

E1

CPU2

I-SATA 0~3

BAR CODE

CPU1

D1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

BT1

X NMIPWR

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

JBT1

I-SATA 4~7

IPMI_LAN
USB0/1(3.0)

BMC

10G PHY

LEDM1

CPU1

VGA

JP2

P1 DIMM
A1

S-SATA5

JIPMB1

JPL1

JWD1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

1

JBMC_DEBUG

JD1

JAOM

JF1

LE2

C1

B1

JPI2C1

1. TPM/Port 80 Header

FAN5FAN6

JPWR3

JPWR1

JPWR2

FAN4

FAN3

FAN1

FAN2

50

Chapter 2: Installation

RAID Key Header

A RAID Key header is located at JRK1 on the motherboard. The RAID key is used to support
onboard S-SATA connections.

Intel RAID Key

Pin Denitions

Pins Denition

1 GND

2 PU 3.3V Stdby

3 GND

4 PCH RAID KEY

SGPIO Header

The T-SGPIO3 (Serial General Purpose Input/Output) header is used to communicate with
the enclosure management chip on the back panel.

SGPIO Header

Pin Denitions

Pin# Denition Pin# Denition

1 NC 2 NC

3 Ground 4 DATA Out

5 Load 6 Ground

7 Clock 8 NC

NC = No Connection

LE1

C

A

JUIDB1

JPME1

JSXB1_1

JPME2

LAN2

JM2_1

LE3

CPU2_PORT3

USB2/3
(3.0)

LAN1

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

1

P2_NVME1

JNVI2C2

D1

P2_NVME0

CPU2

JRK1

JL1

P2 DIMM

F1

E1

JP3

S-SGPIO2

JSXB1_3

P2 DIMM
A1

BIOS LICENSE

B1

SRW1

C1

S-SATA 0~3

2

X11DDW-L

REV:1.02
DESIGNED IN USA

P1 DIMM

F1

CPU2

MAC CODE

CPU1

E1

D1

I-SATA 0~3

I-SATA 4~7

BAR CODE

BT1

JBT1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

X NMIPWR

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

IPMI_LAN
USB0/1(3.0)

BMC

10G PHY

LEDM1

CPU1

VGA

JP2

P1 DIMM
A1

S-SATA5

JIPMB1

JPL1

JPG1

JWD1

JBR1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JAOM

JF1

LE2

C1

B1

JPI2C1

JPWR3

JPWR1

JPWR2

1. RAID Key

2. T-SGPIO3

FAN5FAN6

FAN4

FAN3

FAN1

FAN2

51

X11DDW-L/NT User's Manual

JP3

Standby Power

The Standby Power header is located at JSTBY1 on the motherboard. You must have a card
with a Standby Power connector and a cable to use this feature. Refer to the table below

for pin denitions.

Standby Power

Pin Denitions

Pin# Denition

1 +5V Standby

2 Ground

3 No Connection

Power SMB (I2C) Header

The Power System Management Bus (I2C) connector (JPI2C1) monitors the power supply,

fan, and system temperatures. Refer to the table below for pin denitions.

Power SMB Header

Pin Denitions

Pin# Denition

1 Clock

2 Data

3 PMBUS_Alert

4 Ground

5 +3.3V

LE1

C

A

JUIDB1

JPME1

JSXB1_1

JPME2

LAN2

JM2_1

LE3

CPU2_PORT3

USB2/3
(3.0)

LAN1

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

P2_NVME1

JNVI2C2

D1

P2_NVME0

CPU2

JRK1

JL1

P2 DIMM

F1

E1

S-SGPIO2

JSXB1_3

P2 DIMM

A1

BIOS LICENSE

B1

SRW1

C1

S-SATA 0~3

X11DDW-L

REV:1.02
DESIGNED IN USA

P1 DIMM
F1

CPU2

MAC CODE

CPU1

E1

D1

I-SATA 0~3

I-SATA 4~7

BAR CODE

BT1

JBT1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

IPMI_LAN
USB0/1(3.0)

X NMIPWR

BMC

10G PHY

LEDM1

CPU1

VGA

P1 DIMM

A1

S-SATA5

JIPMB1

JPL1

JPG1

JWD1

JBR1

S-SATA4

JSTBY1

1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JP2

JAOM

JF1

LE2

C1

B1

JPI2C1

1. Standby Power

2. Power SMB Header

2

JPWR3

FAN4

FAN5FAN6

FAN3

JPWR1

JPWR2

FAN1

FAN2

52

Chapter 2: Installation

4-pin BMC External I2C Header

A System Management Bus header for IPMI 2.0 is located at JIPMB1. Connect the appropriate
cable here to use the IPMB I2C connection on your system. Refer to the table below for pin

denitions.

External I2C Header

Pin Denitions

Pin# Denition

1 Data

2 Ground

3 Clock

4 No Connection

Chassis Intrusion

A Chassis Intrusion header is located at JL1 on the motherboard. Attach the appropriate cable
from the chassis to inform you of a chassis intrusion when the chassis is opened. Refer to

the table below for pin denitions.

Chassis Intrusion

Pin Denitions

Pin# Denition

1 Intrusion Input

2 Ground

LE1

C

A

JUIDB1

JPME1

JSXB1_1

JPME2

LAN2

JM2_1

LE3

CPU2_PORT3

USB2/3
(3.0)

LAN1

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

P2_NVME1

JNVI2C2

D1

P2_NVME0

CPU2

JRK1

JL1

2

P2 DIMM

F1

E1

JP3

S-SGPIO2

JSXB1_3

P2 DIMM
A1

BIOS LICENSE

B1

SRW1

C1

S-SATA 0~3

X11DDW-L

REV:1.02
DESIGNED IN USA

P1 DIMM

F1

CPU2

MAC CODE

CPU1

E1

D1

I-SATA 0~3

I-SATA 4~7

BAR CODE

BT1

JBT1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

X NMIPWR

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

IPMI_LAN
USB0/1(3.0)

BMC

10G PHY

LEDM1

CPU1

VGA

1

JP2

P1 DIMM
A1

S-SATA5

JIPMB1

JPL1

JPG1

JWD1

JBR1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JAOM

JF1

LE2

C1

B1

JPI2C1

1. SMBus

2. Chassis Intrusion

FAN5FAN6

JPWR3

JPWR1

JPWR2

FAN4

FAN3

FAN1

FAN2

53

X11DDW-L/NT User's Manual

JP3

NVMe I2C Header

Connector JNVI2C1 and JNVI2C2 are a management headers for the Supermicro AOC NVMe
PCI-E peripheral cards. Please connect the I2C cables to these connectors.

NVMe Slots

Use the four NVMe slots (P1_NVME0, P1_NVEM1, P2_NVEM0, and P2_NVME1) to attach
high-speed PCI-E storage devices. These slots are available on the (-NT) model only.

M.2 Slot

The X11DDW-L/NT motherboard has one M.2 slot located at JM2_1. M.2 was formerly Next
Generation Form Factor (NGFF) and serves to replace mini PCI-E. M.2 allows for a variety of

card sizes, increased functionality, and spatial e󰀩ciency. The M.2 socket on the motherboard

supports PCI-E 3.0 X4 (32 Gb/s) SSD cards in the 2242, 2260, 2280, and 22110 (bracket
required) form factors.

LE1

C

A

JUIDB1

JPME1

JSXB1_1

JPME2

LAN2

7

JM2_1

LE3

CPU2_PORT3

USB2/3
(3.0)

LAN1

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

2

P2_NVME1

JNVI2C2

P2_NVME0

CPU2

D1

JRK1

JL1

P2 DIMM

F1

E1

S-SGPIO2

JSXB1_3

P2 DIMM

A1

BIOS LICENSE

B1

C1

SRW1

S-SATA 0~3

X11DDW-L

REV:1.02
DESIGNED IN USA

P1 DIMM

F1

CPU2

MAC CODE

CPU1

E1

D1

I-SATA 0~3

BAR CODE

BT1

I-SATA 4~7

+

JBT1

P1_NVME1

P1_NVME0

PWRRST
ON

JNVI2C1

JSDCARD1

NICHDD

NIC

UID

2 1

LEDPSFAIL

1

4

3

X NMIPWR

LED

LED

6 5

FAN4

FAN5FAN6

FAN3

IPMI_LAN
USB0/1(3.0)

BMC

10G PHY

LEDM1

CPU1

VGA

JP2

P1 DIMM
A1

S-SATA5

JIPMB1

JPL1

JPG1

JWD1

JBR1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JAOM

JF1

LE2

C1

B1

JPI2C1

JPWR3

JPWR1

JPWR2

FAN1

FAN2

1. NVMe I2C1 Header

2. NVMe I2C2 Heade

3. P1_NVME0 Slot

4. P1_NVME1 Slot

5. P2_NVME0 Slot

6. P2_NVME1 Slot

7. M.2 Slot

= Available on (-NT) model only.

54

Chapter 2: Installation

JPG1

JBR1

I-SATA 3.0 and S-SATA 3.0 Ports

The X11DDW-L/NT has eight I-SATA 3.0 ports (I-SATA0~3, I-SATA4~7) and six S-SATA
(S-SATA0~3, S-SATA4, S-SATA5) on the motherboard. These SATA ports are supported
by the Intel C620 chipset. S-SATA4/S-SATA5 can be used with Supermicro SuperDOMs
which are yellow SATA DOM connectors with power pins built in, and do not require external
power cables. Supermicro SuperDOMs are backward-compatible with regular SATA HDDs or
SATA DOMs that need external power cables. All these SATA ports provide serial-link signal
connections, which are faster than the connections of Parallel ATA.

SATA 3.0 Port

Pin Denitions

Pin# Signal

1 Ground

2 SATA_TXP

3 SATA_TXN

4 Ground

5 SATA_RXN

6 SATA_RXP

7 Ground

LE1

C

A

JUIDB1

JPME1

JSXB1_1

JPME2

LAN2

JM2_1

LE3

CPU2_PORT3

USB2/3
(3.0)

LAN1

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

S-SGPIO2

SRW1

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

BIOS LICENSE

P2_NVME1

JNVI2C2

P2_NVME0

CPU2

D1

FAN5FAN6

JRK1

JL1

P2 DIMM
F1

E1

JP3

JSXB1_3

P2 DIMM

A1

CPU2

B1

C1

3

S-SATA 0~3

MAC CODE

X11DDW-L

REV:1.02
DESIGNED IN USA

P1 DIMM

F1

E1

D1

I-SATA 0~3

CPU1

1 2

I-SATA 4~7

BAR CODE

BT1

JBT1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

FAN4

FAN3

XNMIPWR

IPMI_LAN
USB0/1(3.0)

BMC

10G PHY

LEDM1

CPU1

VGA

JP2

P1 DIMM

A1

S-SATA5

JIPMB1

5

JPL1

JWD1

S-SATA4

4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JAOM

JF1

LE2

C1

B1

JPI2C1

JPWR3

JPWR1

JPWR2

FAN1

FAN2

1. I-SATA0-3

2. I-SATA4-7

3. S-SATA0-3

4. S-SATA4

5. S-SATA5

55

X11DDW-L/NT User's Manual

Power LED/Speaker

On the JD1 header, pins 1-3 are for the power LED and pins 4-7 are for the internal speaker.
If you wish to use an external speaker, connect its cable to pins 1-4.

Speaker Connector

Pin Denitions

Pin Setting Denition

Pins 1-3 Power LED

Pins 4-7 Speaker

Micro SD Card

There is one Micro SD memory card slot located at JSDCARD1 on the motherboard.

LE1

C

A

JUIDB1

JPME1

JSXB1_1

JPME2

LAN2

JM2_1

LE3

CPU2_PORT3

USB2/3
(3.0)

LAN1

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

P2_NVME1

JNVI2C2

P2_NVME0

CPU2

D1

FAN5FAN6

JRK1

JL1

P2 DIMM

F1

E1

JP3

S-SGPIO2

JSXB1_3

P2 DIMM

A1

BIOS LICENSE

B1

C1

SRW1

S-SATA 0~3

X11DDW-L

REV:1.02
DESIGNED IN USA

P1 DIMM

F1

CPU2

MAC CODE

CPU1

E1

D1

I-SATA 0~3

BAR CODE

BT1

I-SATA 4~7

+

JBT1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

X NMIPWR

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

FAN4

FAN3

IPMI_LAN
USB0/1(3.0)

BMC

10G PHY

LEDM1

CPU1

P1 DIMM

VGA

S-SATA5

JIPMB1

JPL1

JPG1

JWD1

JBR1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

1

JBMC_DEBUG

JD1

JP2

2

JAOM

JF1

LE2

A1

C1

B1

JPI2C1

JPWR3

JPWR1

JPWR2

FAN1

FAN2

1. Power LED/Speaker

56

Chapter 2: Installation

2.8 Jumper Settings

How Jumpers Work

To modify the operation of the motherboard, jumpers can be used to choose between optional

settings. Jumpers create shorts between two pins to change the function of the connector.

Pin 1 is identied with a square solder pad on the printed circuit board. See the diagram
at right for an example of jumping pins 1 and 2. Refer to the motherboard layout page for
jumper locations.

Note: On two-pin jumpers, "Closed" means the jumper is on and "Open" means the
jumper is o󰀨 the pins.

Connector

Pins

Jumper

Setting

3 2 1

3 2 1

CMOS Clear

JBT1 is used to clear CMOS, which will also clear any passwords. Instead of pins, this jumper

consists of contact pads to prevent accidentally clearing the contents of CMOS.

To Clear CMOS

1. First power down the system and unplug the power cord(s).

2. Remove the cover of the chassis to access the motherboard.

3. Remove the onboard battery from the motherboard.

4. Short the CMOS pads with a metal object such as a small screwdriver for at least four
seconds.

5. Remove the screwdriver (or shorting device).

6. Replace the cover, reconnect the power cord(s), and power on the system.

Note: Clearing CMOS will also clear all passwords.

Do not use the PW_ON connector to clear CMOS.

JBT1 contact pads

57

X11DDW-L/NT User's Manual

JPG1

JBR1

VGA Enable/Disable

JPG1 allows you to enable or disable the VGA port using the onboard graphics controller.
The default setting is Enabled.

VGA Enable/Disable

Jumper Settings

Jumper Setting Denition

Pins 1-2 Enabled

Pins 2-3 Disabled

LAN Port Enable/Disable

Change the setting of jumper JPL1 to enable or disable LAN ports 1 and 2. The default

setting is Enabled.

LAN Port Enable/Disable

Jumper Settings

Jumper Setting Denition

Pins 1-2 Enabled

Pins 2-3 Disabled

LE1

C

A

JUIDB1

JPME1

JSXB1_1

JPME2

LAN2

JM2_1

LE3

CPU2_PORT3

USB2/3
(3.0)

LAN1

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

P2_NVME1

JRK1

JL1

JNVI2C2

P2 DIMM

F1

E1

JP3

P2_NVME0

CPU2

D1

FAN5FAN6

S-SGPIO2

JSXB1_3

P2 DIMM

A1

BIOS LICENSE

B1

C1

SRW1

S-SATA 0~3

X11DDW-L

REV:1.02

DESIGNED IN USA

P1 DIMM

F1

CPU2

MAC CODE

CPU1

E1

D1

I-SATA 0~3

I-SATA 4~7

BAR CODE

BT1

JBT1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

FAN4

X NMIPWR

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

FAN3

IPMI_LAN
USB0/1(3.0)

BMC

10G PHY

LEDM1

CPU1

VGA

JP2

P1 DIMM
A1

S-SATA5

JIPMB1

JPL1

JPWR3

JPWR1

JPWR2

FAN2

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

1

JBMC_DEBUG

JD1

JF1

JPI2C1

FAN1

JTPM1

1

JWD1

2

JAOM

LE2

C1

B1

1. VGA Enable/Disable

2. LAN Enable/Disable

58

Chapter 2: Installation

JP3

Management Engine (ME) Recovery

Use jumper JPME1 to select ME Firmware Recovery mode, which will limit resource

allocation for essential system operation only in order to maintain normal power operation
and management. In the single operation mode, online upgrade will be available via Recovery

mode. See the table below for jumper settings.

ME Recovery Mode

Jumper Settings

Jumper Setting Denition

Pins 1-2 Normal

Pins 2-3 ME Recovery

Manufacturing Mode

Close JPME2 to bypass SPI ash security and force the system to use the Manufacturing
Mode, which will allow you to ash the system rmware from a host server to modify system
settings. See the table below for jumper settings.

Manufacturing Mode Select

Jumper Settings

Jumper Setting Denition

Pins 1-2 Normal (Default)

Pins 2-3 Manufacturing Mode

LE1

C

A

JUIDB1

JPME1

JPME2

21

USB2/3

I-SATA 4~7

(3.0)

LAN1

JBT1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

X NMIPWR

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

JSXB1_1

JM2_1

LE3

CPU2_PORT3

LAN2

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

P2_NVME1

JNVI2C2

P2_NVME0

CPU2

D1

JRK1

JL1

P2 DIMM

F1

E1

S-SGPIO2

JSXB1_3

P2 DIMM
A1

BIOS LICENSE

B1

C1

SRW1

X11DDW-L

REV:1.02
DESIGNED IN USA

CPU2

S-SATA 0~3

P1 DIMM

F1

MAC CODE

CPU1

E1

D1

I-SATA 0~3

BAR CODE

BT1

IPMI_LAN
USB0/1(3.0)

BMC

10G PHY

LEDM1

CPU1

VGA

JP2

P1 DIMM
A1

S-SATA5

JIPMB1

JPL1

JPG1

JWD1

JBR1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JAOM

JF1

LE2

C1

B1

JPI2C1

1. ME Recovery

2. Manufacturing Mode

FAN5FAN6

JPWR3

JPWR1

JPWR2

FAN4

FAN3

FAN1

FAN2

59

X11DDW-L/NT User's Manual

JP3

Watch Dog

JWD1 controls the Watch Dog function. Watch Dog is a monitor that can reboot the system
when a software application hangs. Jumping pins 1-2 will cause Watch Dog to reset the
system if an application hangs. Jumping pins 2-3 will generate a non-maskable interrupt
signal for the application that hangs. Watch Dog must also be enabled in BIOS. The default
setting is Reset.

Note: When Watch Dog is enabled, the user needs to write their own application
software to disable it.

Watch Dog

Jumper Settings

Jumper Setting Denition

Pins 1-2 Reset

Pins 2-3 NMI

Open Disabled

LE1

C

A

JUIDB1

JPME1

JSXB1_1

JPME2

LAN2

JM2_1

LE3

CPU2_PORT3

USB2/3
(3.0)

LAN1

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

P2_NVME1

JNVI2C2

P2_NVME0

CPU2

D1

FAN5FAN6

JRK1

JL1

P2 DIMM

F1

E1

S-SGPIO2

JSXB1_3

P2 DIMM

A1

BIOS LICENSE

B1

C1

SRW1

S-SATA 0~3

MAC CODE

X11DDW-L

REV:1.02
DESIGNED IN USA

P1 DIMM
F1

E1

CPU2

I-SATA 0~3

BAR CODE

CPU1

D1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

BT1

FAN4

X NMIPWR

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

FAN3

JBT1

I-SATA 4~7

IPMI_LAN
USB0/1(3.0)

BMC

10G PHY

LEDM1

CPU1

VGA

P1 DIMM

A1

S-SATA5

JIPMB1

JPL1

JPG1

JWD1

JBR1

1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JP2

JAOM

JF1

LE2

C1

B1

JPI2C1

JPWR3

JPWR1

JPWR2

FAN1

FAN2

1. Watch Dog

60

Chapter 2: Installation

JPG1

JBR1

I2C Bus for VRM

Jumpers JVRM1 and JVRM2 allow the BMC or the PCH to access CPU and memory VRM

controllers. See the table below for jumper settings.

VRM

Jumper Settings

Jumper Setting Denition

Pins 1-2 BMC (Normal)

Pins 2-3 PCH

LE1

C

A

JUIDB1

JPME1

JSXB1_1

JPME2

LAN2

JM2_1

LE3

CPU2_PORT3

USB2/3
(3.0)

LAN1

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

P2_NVME1

JRK1

JL1

JNVI2C2

P2 DIMM

F1

E1

JP3

P2_NVME0

CPU2

D1

FAN5FAN6

S-SGPIO2

JSXB1_3

P2 DIMM

A1

BIOS LICENSE

B1

C1

SRW1

S-SATA 0~3

X11DDW-L

REV:1.02
DESIGNED IN USA

P1 DIMM

F1

CPU2

MAC CODE

CPU1

E1

D1

I-SATA 0~3

I-SATA 4~7

BAR CODE

BT1

JBT1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

FAN4

X NMIPWR

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

FAN3

IPMI_LAN

USB0/1(3.0)

BMC

10G PHY

LEDM1

CPU1

P1 DIMM

VGA

S-SATA5

JIPMB1

JPL1

JWD1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

1

JTPM1

2

1

JBMC_DEBUG

JD1

JP2

JAOM

JF1

LE2

A1

C1

B1

JPI2C1

JPWR3

JPWR1

JPWR2

FAN1

FAN2

1. JVRM1

2. JVRM2

61

X11DDW-L/NT User's Manual

JP3

2.9 LED Indicators

IPMI LAN LEDs

A dedicated IPMI LAN, located on the back panel, has two LED indicators. The amber LED
on the right of the IPMI LAN port indicates activity, while the LED on the left indicates the
speed of the connection. See the table below for more information.

IPMI LAN

Activity LEDLink LED

IPMI LAN LEDs

Color/State Denition

Link (left)

Green: Solid

Amber: Solid

Activity (Right) Amber: Blinking Active

100 Mbps

1Gbps

1

LE1

C

A

JUIDB1

JPME1

JSXB1_1

JPME2

LAN2

JM2_1

LE3

CPU2_PORT3

USB2/3
(3.0)

LAN1

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

P2_NVME1

JRK1

JL1

JNVI2C2

P2 DIMM

F1

E1

P2_NVME0

CPU2

D1

S-SGPIO2

JSXB1_3

P2 DIMM

A1

BIOS LICENSE

B1

C1

SRW1

S-SATA 0~3

X11DDW-L

REV:1.02
DESIGNED IN USA

P1 DIMM

F1

CPU2

MAC CODE

CPU1

E1

D1

I-SATA 0~3

I-SATA 4~7

BAR CODE

BT1

JBT1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

X NMIPWR

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

IPMI_LAN
USB0/1(3.0)

BMC

10G PHY

LEDM1

CPU1

VGA

JP2

P1 DIMM
A1

S-SATA5

JIPMB1

JPL1

JPG1

JWD1

JBR1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JAOM

JF1

LE2

C1

B1

JPI2C1

JPWR3

JPWR1

JPWR2

1. IPMI LAN LED

FAN5FAN6

FAN4

FAN3

FAN1

FAN2

62

Chapter 2: Installation

JP3

BMC Heartbeat LED

LEDM1 is the BMC heartbeat LED. When the LED is blinking green, BMC is functioning
normally. See the table below for the LED status.

Onboard Power LED Indicator

LED Color Denition

Green:

Blinking

BMC Normal

Onboard Power LED

The Onboard Power LED is located at LE2 on the motherboard. When this LED is on, the

system is on. Be sure to turn o󰀨 the system and unplug the power cord before removing or

installing components. Refer to the table below for more information.

Onboard Power LED Indicator

LED Color Denition

System O󰀨

O󰀨

Green System On

(power cable not

connected)

LE1

C

A

JUIDB1

JPME1

JSXB1_1

JPME2

LAN2

JM2_1

LE3

CPU2_PORT3

USB2/3
(3.0)

LAN1

C621

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

P2_NVME1

JRK1

JL1

JNVI2C2

P2 DIMM

F1

E1

P2_NVME0

CPU2

D1

S-SGPIO2

JSXB1_3

P2 DIMM

A1

BIOS LICENSE

B1

C1

SRW1

S-SATA 0~3

X11DDW-L

REV:1.02
DESIGNED IN USA

P1 DIMM

F1

CPU2

MAC CODE

CPU1

E1

D1

I-SATA 0~3

I-SATA 4~7

BAR CODE

BT1

JBT1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

X NMIPWR

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

IPMI_LAN
USB0/1(3.0)

BMC

1

10G PHY

LEDM1

2

CPU1

VGA

JP2

P1 DIMM
A1

S-SATA5

JIPMB1

JPL1

JPG1

JWD1

JBR1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JAOM

JF1

LE2

C1

B1

JPI2C1

JPWR3

JPWR1

JPWR2

1. BMC Heartbeat LED

2. Onboard Power LED

FAN5FAN6

FAN4

FAN3

FAN1

FAN2

63

X11DDW-L/NT User's Manual

JP3

Unit ID LED

A rear UID LED indicator at LE1 is located near the UID switch on the back panel. This UID

indicator provides easy identication of a system.unit that may need service.

UID LED

LED Indicator

LED Color Denition

Blue: On Unit Identied

M.2 LED

An M.2 LED is located at LE3 on the motherboard. When LE3 is blinking, M.2 functions
normally. Refer to the table below for more information.

M.2 LED State

LED Color Denition

Green: Blinking Device Working

1

LE1

C

A

JUIDB1

JPME1

JPME2

JSXB1_1

JM2_1

LE3

CPU2_PORT3

2

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

P2_NVME1

JRK1

JL1

JNVI2C2

P2 DIMM

F1

E1

P2_NVME0

CPU2

D1

S-SGPIO2

JSXB1_3

P2 DIMM

A1

BIOS LICENSE

B1

C1

SRW1

X11DDW-L

REV:1.02
DESIGNED IN USA

P1 DIMM

CPU2

S-SATA 0~3

F1

MAC CODE

CPU1

E1

D1

I-SATA 0~3

C621

BAR CODE

LAN2

BT1

I-SATA 4~7

USB2/3
(3.0)

LAN1

JBT1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

X NMIPWR

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

IPMI_LAN
USB0/1(3.0)

BMC

10G PHY

LEDM1

CPU1

VGA

JP2

P1 DIMM
A1

S-SATA5

JIPMB1

JPL1

JPG1

JWD1

JBR1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JAOM

JF1

LE2

C1

B1

JPI2C1

1. UID LED

2. M.2 LED

FAN5FAN6

JPWR3

JPWR1

JPWR2

FAN4

FAN3

FAN1

FAN2

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Chapter 2: Installation

JP3

2.10 PCI-E 3.0 Slots

PCI-E 3.0 Slots

There are several PCI-E slots located on the motherboard. Refer to the layout below for their
locations.

1. PCI-E 3.0 (x16 + x16) Left Riser Card (SXB1)

2. PCI-E 3.0 x16 Right Riser Card (SXB2)

3. PCI-E 3.0 x16 SAS3 AOM Controller (JAOM)

LE1

C

A

JUIDB1

JPME1

JPME2

JSXB1_1

JM2_1

LE3

CPU2_PORT3

2

SXB1B:CPU1 PCI-E 3.0 X16 + CPU2 PCI-E 3.0 X16

JSXB1_2

CPU2_PORT2ACPU2_PORT2BCPU2_PORT2CCPU2_PORT2DCPU1_PORT3CCPU1_PORT3DCPU1_PORT3CCPU1_PORT3D

SXB2:CPU2 PCI-E 3.0 X16

CPU1_PORT3BCPU1_PORT3ACPU1_PORT3BCPU1_PORT3A

S-SGPIO2

BIOS LICENSE

JSXB1_3

P2 DIMM

A1

B1

SRW1

X11DDW-L

REV:1.02
DESIGNED IN USA

CPU2

C1

S-SATA 0~3

MAC CODE

P1 DIMM

F1

E1

1

P2_NVME1

JRK1

JL1

JNVI2C2

P2 DIMM

F1

E1

D1

P2_NVME0

CPU2

LAN2

C621

I-SATA 4~7

I-SATA 0~3

BAR CODE

BT1

CPU1

D1

USB2/3
(3.0)

LAN1

JBT1

JNVI2C1

P1_NVME1

JSDCARD1

P1_NVME0

+

X NMIPWR

NICHDD

NIC

UID

PWRRST
ON

LED

LED

2 1

LEDPSFAIL

IPMI_LAN
USB0/1(3.0)

BMC

10G PHY

LEDM1

3

CPU1

P1 DIMM

A1

VGA

S-SATA5

JIPMB1

JPL1

JPG1

JWD1

JBR1

S-SATA4

JSTBY1

USB4/5(3.0)

JVRM1JVRM2

JTPM1

1

JBMC_DEBUG

JD1

JP2

JAOM

JF1

LE2

C1

B1

JPI2C1

JPWR3

JPWR1

JPWR2

FAN4

FAN5FAN6

FAN3

FAN1

FAN2

65

X11DDW-L/NT User's Manual

Chapter 3

Troubleshooting

3.1 Troubleshooting Procedures

Use the following procedures to troubleshoot your system. If you have followed all of the
procedures below and still need assistance, refer to the ‘Technical Support Procedures’ and/
or ‘Returning Merchandise for Service’ section(s) in this chapter. Always disconnect the AC
power cord before adding, changing or installing any non hot-swap hardware components.

Before Power On

1. Check that the power LED on the motherboard is on.

2. Make sure that the power connector is connected to your power supply.

3. Make sure that no short circuits exist between the motherboard and chassis.

4. Disconnect all cables from the motherboard, including those for the keyboard and
mouse.

5. Remove all add-on cards.

6. Install a CPU, a heatsink*, and connect the internal speaker and the power LED to the

motherboard. Check all jumper settings as well. (Make sure that the heatsink is fully

seated.)

7. Use the correct type of onboard CMOS battery (CR2032) as recommended by the
manufacturer. To avoid possible explosion, do not install the CMOS battery upside down.

No Power

1. Make sure that no short circuits exist between the motherboard and the chassis.

2. Verify that all jumpers are set to their default positions.

3. Check that the 115V/230V switch on the power supply is properly set.

4. Turn the power switch on and o󰀨 to test the system.

5. The battery on your motherboard may be old. Check to verify that it still supplies
~3VDC. If it does not, replace it with a new one.

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Chapter 3: Troubleshooting

No Video

1. If the power is on but you have no video, remove all the add-on cards and cables.

2. Use the speaker to determine if any beep codes exist. Refer to Appendix A for details on
beep codes.

System Boot Failure

If the system does not display POST (Power-On-Self-Test) or does not respond after the
power is turned on, check the following:

1. Check for any error beep from the motherboard speaker.

• If there is no error beep, try to turn on the system without DIMM modules installed. If there

is still no error beep, replace the motherboard.

• If there are error beeps, clear the CMOS settings by unplugging the power cord and

contacting both pads on the CMOS Clear Jumper (JBT1). Refer to chapter 2.

2. Remove all components from the motherboard, especially the DIMM modules. Make
sure that system power is on and that memory error beeps are activated.

3. Turn on the system with only one DIMM module installed. If the system boots, check for
bad DIMM modules or slots by following the Memory Errors Troubleshooting procedure
in this Chapter.

Memory Errors

1. Make sure that the DIMM modules are properly and fully installed.

2. Conrm that you are using the correct memory. Also, it is recommended that you use
the same memory type and speed for all DIMMs in the system. See Section 2.4 for
memory details.

3. Check for bad DIMM modules or slots by swapping modules between slots and noting
the results.

4. Check the power supply voltage 115V/230V switch.

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X11DDW-L/NT User's Manual

Losing the System's Setup Conguration

1. Make sure that you are using a high quality power supply. A poor quality power supply
may cause the system to lose the CMOS setup information. Refer to Section 1.6 for
details on recommended power supplies.

2. The battery on your motherboard may be old. Check to verify that it still supplies
~3VDC. If it does not, replace it with a new one.

3. If the above steps do not x the setup conguration problem, contact your vendor for
repairs.

When the System Becomes Unstable

A. If the system becomes unstable during or after OS installation, check the following:

1. CPU/BIOS support: Make sure that your CPU is supported and that you have the latest
BIOS installed in your system.

2. Memory support: Make sure that the memory modules are supported by testing the
modules using memtest86 or a similar utility.

Note: Refer to the product page on our website at http:\\www.supermicro.com for
memory and CPU support and updates.

3. HDD support: Make sure that all hard disk drives (HDDs) work properly. Replace the
bad HDDs with good ones.

4. System cooling: Check the system cooling to make sure that all heatsink fans and CPU/
system fans, etc., work properly. Check the hardware monitoring settings in the IPMI
to make sure that the CPU and system temperatures are within the normal range. Also
check the front panel Overheat LED and make sure that it is not on.

5. Adequate power supply: Make sure that the power supply provides adequate power to
the system. Make sure that all power connectors are connected. Please refer to our
website for more information on the minimum power requirements.

6. Proper software support: Make sure that the correct drivers are used.

B. If the system becomes unstable before or during OS installation, check the following:

1. Source of installation: Make sure that the devices used for installation are working
properly, including boot devices such as CD.

2. Cable connection: Check to make sure that all cables are connected and working
properly.

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Chapter 3: Troubleshooting

3. Using the minimum conguration for troubleshooting: Remove all unnecessary
components (starting with add-on cards rst), and use the minimum conguration (but

with a CPU and a memory module installed) to identify the trouble areas. Refer to the
steps listed in Section A above for proper troubleshooting procedures.

4. Identifying bad components by isolating them: If necessary, remove a component in
question from the chassis, and test it in isolation to make sure that it works properly.
Replace a bad component with a good one.

5. Check and change one component at a time instead of changing several items at the
same time. This will help isolate and identify the problem.

6. To nd out if a component is good, swap this component with a new one to see if the
system will work properly. If so, then the old component is bad. You can also install the
component in question in another system. If the new system works, the component is
good and the old system has problems.

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X11DDW-L/NT User's Manual

3.2 Technical Support Procedures

Before contacting Technical Support, please take the following steps. Also, note that as a

motherboard manufacturer, we do not sell directly to end-users, so it is best to rst check with

your distributor or reseller for troubleshooting services. They should know of any possible

problem(s) with the specic system conguration that was sold to you.

1. Please review the ‘Troubleshooting Procedures’ and 'Frequently Asked Questions'
(FAQs) sections in this chapter or see the FAQs on our website before contacting
Technical Support.

2. BIOS upgrades can be downloaded from our website. Note: Not all BIOS can be

ashed depending on the modications to the boot block code.

3. If you still cannot resolve the problem, include the following information when contacting
us for technical support:

• Motherboard model and PCB revision number

• BIOS release date/version (this can be seen on the initial display when your system rst

boots up)

• System conguration

An example of a Technical Support form is posted on our website.

Distributors: For immediate assistance, please have your account number ready when
contacting our technical support department by e-mail.

70

Chapter 3: Troubleshooting

3.3 Frequently Asked Questions

Question: What type of memory does my motherboard support?

Answer: The X11DDW-L/NT motherboard supports up to 1536GB of DDR4 ECC LRDIMM/

RDIMM/NVDIMM memory at 2666 MT/s in 12 slots. See Section 2.4 for details on installing
memory.

Question: How do I update my BIOS?

Answer: It is recommended that you do not upgrade your BIOS if you are not experiencing

any problems with your system. Updated BIOS les are located on our website at http://www.

supermicro.com. Please check our BIOS warning message and the information on how to

update your BIOS on our website. Select your motherboard model and download the BIOS

le to your computer. Also, check the current BIOS revision to make sure that it is newer
than your BIOS before downloading. You can choose from the zip le and the .exe le. If
you choose the zip BIOS le, please unzip the BIOS le onto a bootable USB device. Run
the batch le using the format FLASH.BAT lename.rom from your bootable USB device to
ash the BIOS. Then, your system will automatically reboot.

Question: Why can't I turn o󰀨 the power using the momentary power on/o󰀨 switch?

Answer: The instant power o󰀨 function is controlled in BIOS by the Power Button Mode
setting. When the On/O󰀨 feature is enabled, the motherboard will have instant o󰀨 capabilities

as long as the BIOS has control of the system. When the Standby or Suspend feature is

enabled or when the BIOS is not in control such as during memory count (the rst screen
that appears when the system is turned on), the momentary on/o󰀨 switch must be held for

more than four seconds to shut down the system. This feature is required to implement the
ACPI features on the motherboard.

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X11DDW-L/NT User's Manual

3.4 Battery Removal and Installation

Battery Removal

To remove the onboard battery, follow the steps below:

1. Power o󰀨 your system and unplug your power cable.

2. Locate the onboard battery as shown below.

3. Using a tool such as a pen or a small screwdriver, push the battery lock outwards to
unlock it. Once unlocked, the battery will pop out from the holder.

4. Remove the battery.

Proper Battery Disposal

Please handle used batteries carefully. Do not damage the battery in any way; a damaged
battery may release hazardous materials into the environment. Do not discard a used battery

in the garbage or a public landll. Please comply with the regulations set up by your local

hazardous waste management agency to dispose of your used battery properly.

Battery Installation

1. To install an onboard battery, follow the steps 1 & 2 above and continue below:

2. Identify the battery's polarity. The positive (+) side should be facing up.

3. Insert the battery into the battery holder and push it down until you hear a click to
ensure that the battery is securely locked.

Important: When replacing a battery, be sure to only replace it with the same type.

OR

72

Chapter 3: Troubleshooting

3.5 Returning Merchandise for Service

A receipt or copy of your invoice marked with the date of purchase is required before any
warranty service will be rendered. You can obtain service by calling your vendor for a Returned
Merchandise Authorization (RMA) number. When returning to the manufacturer, the RMA
number should be prominently displayed on the outside of the shipping carton and mailed
prepaid or hand-carried. Shipping and handling charges will be applied for all orders that
must be mailed when service is complete.

For faster service, RMA authorizations may be requested online (http://www.supermicro.com/

support/rma/).

This warranty only covers normal consumer use and does not cover damages incurred in
shipping or from failure due to the alteration, misuse, abuse or improper maintenance of
products.

During the warranty period, contact your distributor rst for any product problems.

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X11DDW-L/NT User's Manual

Chapter 4

BIOS

4.1 Introduction

This chapter describes the AMIBIOS™ Setup utility for the motherboard. The BIOS is stored

on a chip and can be easily upgraded using a ash program.

Note: Due to periodic changes to the BIOS, some settings may have been added
or deleted and might not yet be recorded in this manual. Please refer to the Manual

Download area of our website for any changes to BIOS that may not be reected in

this manual.

Starting the Setup Utility

To enter the BIOS Setup Utility, hit the <Delete> key while the system is booting-up. (In
most cases, the <Delete> key is used to invoke the BIOS setup screen. There are a few
cases when other keys are used, such as <F1>, <F2>, etc.) Each main BIOS menu option
is described in this manual.

The Main BIOS screen has two main frames. The left frame displays all the options that can

be congured. “Grayed-out” options cannot be congured. The right frame displays the key

legend. Above the key legend is an area reserved for a text message. When an option is
selected in the left frame, it is highlighted in white. Often a text message will accompany it.
(Note that BIOS has default text messages built in. We retain the option to include, omit, or
change any of these text messages.) Settings printed in Bold are the default values.

A " " indicates a submenu. Highlighting such an item and pressing the <Enter> key will
open the list of settings within that submenu.

The BIOS setup utility uses a key-based navigation system called hot keys. Most of these
hot keys (<F1>, <F2>, <F3>, <Enter>, <ESC>, <Arrow> keys, etc.) can be used at any time
during the setup navigation process.

74

Chapter 4: BIOS

4.2 Main Setup

When you rst enter the AMI BIOS setup utility, you will enter the Main setup screen. You can

always return to the Main setup screen by selecting the Main tab on the top of the screen.
The Main BIOS setup screen is shown below.The following Main menu items will be displayed:

System Date/System Time

Use this option to change the system date and time. Highlight System Date or System Time
using the arrow keys. Enter new values using the keyboard. Press the <Tab> key or the arrow

keys to move between elds. The date must be entered in MM/DD/YYYY format. The time

is entered in HH:MM:SS format.

Note: The time is in the 24-hour format. For example, 5:30 P.M. appears as 17:30:00.
The date's default value is 01/01/2015 after RTC reset.

Supermicro X11DDW-L

BIOS Version

This item displays the version of the BIOS ROM used in the system.

Build Date

This item displays the date when the version of the BIOS ROM used in the system was built.

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X11DDW-L/NT User's Manual

Memory Information

Total Memory

This item displays the total size of memory available in the system.

76

Chapter 4: BIOS

4.3 Advanced Setup Congurations

Use the arrow keys to select Boot Setup and press <Enter> to access the submenu items.

Warning: Take caution when changing the Advanced settings. An incorrect value, a very high
DRAM frequency, or an incorrect DRAM timing setting may make the system unstable. When
this occurs, revert to the default to the manufacture default settings.

Boot Feature

Quiet Boot

Use this feature to select the screen display between the POST messages and the OEM logo
upon bootup. Select Disabled to display the POST messages. Select Enabled to display the
OEM logo instead of the normal POST messages. The options are Disabled and Enabled.

Option ROM Messages

Use this feature to set the display mode for the Option ROM. Select Keep Current to display
the current AddOn ROM setting. Select Force BIOS to use the Option ROM display set by
the system BIOS. The options are Force BIOS and Keep Current.

Bootup NumLock State

Use this feature to set the Power-on state for the <Numlock> key. The options are On and O󰀨.

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X11DDW-L/NT User's Manual

Wait For "F1" If Error

Use this feature to force the system to wait until the 'F1' key is pressed if an error occurs.
The options are Disabled and Enabled.

INT19 (Interrupt 19) Trap Response

Interrupt 19 is the software interrupt that handles the boot disk function. When this item is
set to Immediate, the ROM BIOS of the host adaptors will "capture" Interrupt 19 at bootup
immediately and allow the drives that are attached to these host adaptors to function as
bootable disks. If this item is set to Postponed, the ROM BIOS of the host adaptors will not
capture Interrupt 19 immediately and allow the drives attached to these adaptors to function
as bootable devices at bootup. The options are Immediate and Postponed.

Re-try Boot

If this item is enabled, the BIOS will automatically reboot the system from a specied boot

device after its initial boot failure. The options are Disabled, Legacy Boot, and EFI Boot.

Install Windows 7 USB Support

Enable this feature to use the USB keyboard and mouse during the Windows 7 installation
since the native XHCI driver support is unavailable. Use a SATA optical drive as a USB drive,
and USB CD/DVD drives are not supported. Disable this feature after the XHCI driver has
been installed in Windows. The options are Disabled and Enabled.

Port 61h Bit-4 Emulation

Select Enabled to enable the emulation of Port 61h bit-4 toggling in SMM (System Management
Mode). The options are Disabled and Enabled.

Power Conguration

Watch Dog Function

If enabled, the Watch Dog Timer will allow the system to reset or generate NMI based on
jumper settings when it is expired for more than ve minutes. The options are Disabled and
Enabled.

Restore on AC Power Loss

Use this feature to set the power state after a power outage. Select Stay Off for

the system power to remain o󰀨 after a power loss. Select Power On for the system

power to be turned on after a power loss. Select Last State to allow the system to
resume its last power state before a power loss. The options are Stay O󰀨, Power On,
and Last State.

78

Chapter 4: BIOS

Power Button Function

This feature controls how the system shuts down when the power button is pressed. Select 4

Seconds Override for the user to power o󰀨 the system after pressing and holding the power
button for 4 seconds or longer. Select Instant O󰀨 to instantly power o󰀨 the system as soon

as the user presses the power button. The options are Instant O󰀨 and 4 Seconds Override.

Throttle on Power Fail

Use this feature to decrease system power by throttling CPU frequency when one power
supply has failed. The options are Disabled and Enabled.

CPU Conguration

Processor Conguration

The following CPU information will display:

• Processor BSP Revision

• Processor Socket

• Processor ID

• Processor Frequency

• Processor Max Ratio

• Processor Min Ratio

• Microcode Revision

• L1 Cache RAM

• L2 Cache RAM

• L3 Cache RAM

• Processor 0 Version

• Processor 1 Version

Hyper-Threading (ALL) (Available when supported by the CPU)

Select Enable to support Intel Hyper-threading Technology to enhance CPU performance.
The options are Disable and Enable.

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X11DDW-L/NT User's Manual

Execute Disable Bit (Available if supported by the OS & the CPU)

Select Enabled to enable the Execute-Disable Bit which will allow the processor to designate
areas in the system memory where an application code can execute and where it cannot,

thus preventing a worm or a virus from ooding illegal codes to overwhelm the processor

or damage the system during an attack. The default is Enable. (Refer to the Intel® and
Microsoft® websites for more information.)

Intel Virtualization Technology

Use feature to enable the Vanderpool Technology. This technology allows the system to run
several operating systems simultaneously. The options are Disable and Enable.

PPIN Control

Select Unlock/Enable to use the Protected-Processor Inventory Number (PPIN) in the system.
The options are Unlock/Disable and Unlock/EnablE

Hardware Prefetcher (Available when supported by the CPU)

If set to Enabled, the hardware prefetcher will prefetch streams of data and instructions from
the main memory to the L2 cache to improve CPU performance. The options are Disable
and Enable.

Adjacent Cache Prefetch (Available when supported by the CPU)

The CPU prefetches the cache line for 64 bytes if this feature is set to Disabled. The CPU
prefetches both cache lines for 128 bytes as comprised if this feature is set to Enable.

DCU Streamer Prefetcher (Available when supported by the CPU)

Select Enabled to enable the DCU (Data Cache Unit) Streamer Prefetcher which will stream
and prefetch data and send it to the Level 1 data cache to improve data processing and
system performance. The options are Disable and Enable.

DCU IP Prefetcher (Available when supported by the CPU)

Select Enabled for DCU (Data Cache Unit) IP Prefetcher support, which will prefetch IP
addresses to improve network connectivity and system performance. The options are Enable
and Disable.

LLC Prefetch

If set to Enabled, the hardware prefetcher will prefetch streams of data and instructions from
the main memory to the L3 cache to improve CPU performance. The options are Disable
and Enable.

Extended APIC

Select Enable to activate APIC (Advanced Programmable Interrupt Controller) support. The
options are Disable and Enable.

80

Chapter 4: BIOS

AES-NI

Select Enable to use the Intel Advanced Encryption Standard (AES) New Instructions (NI) to
ensure data security. The options are Disable and Enable.

Advanced Power Management Conguration

CPU P State Control

This feature allows the user to congure the following CPU power settings

Speedstep (Pstates)

Intel SpeedStep Technology allows the system to automatically adjust processor voltage

and core frequency to reduce power consumption and heat dissipation. The options are
Disabled and Enabled.

EIST PSD Funtion

This feature allows the user to choose between Hardware and Software to control the
processor's frequency and performance (P-state). In HW_ALL mode, the processor hard­ware is responsible for coordinating the P-state, and the OS is responsible for keeping the
P-state request up to date on all Logical Processors. In SW_ALL mode, the OS Power
Manager is responsible for coordinating the P-state, and must initiate the transition on
all Logical Processors. In SW_ANY mode, the OS Power Manager is responsible for
coordinating the P-state and may initiate the transition on any Logical Processors. The
options are HW_ALL, SW_ALL, and SW_ANY.

Turbo Mode

This feature will enable dynamic control of the processor, allowing it to run above stock
frequency.

Hardware PM State Control

Hardware P-States

This setting allows the user to select between OS and hardware-controlled P-states.
Selecting Native Mode allows the OS to choose a P-state. Selecting Out of Band Mode
allows the hardware to autonomously choose a P-state without OS guidance. Selecting
Native Mode with No Legacy Support functions as Native Mode with no support for older
hardware.

CPU C State Control

Autonomous Core C-State

Enabling this setting allows the hardware to autonomously choose to enter a C-state
based on power consumption and clock speed. The options are Disable and Enable.

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X11DDW-L/NT User's Manual

CPU C6 Report

Select Enabled to allow the BIOS to report the CPU C6 State (ACPI C3) to the operating

system. During the CPU C6 State, the power to all cache is turned o󰀨. The options are

Disable and Enable.

Enhanced Halt State (C1E)

Select Enabled to use Enhanced Halt-State technology, which will signicantly reduce

the CPU's power consumption by reducing the CPU's clock cycle and voltage during a
Halt-state. The options are Disable and Enable.

Package C State Control

Package C State

This feature allows the user to set the limit on the C State package register. The options
are C0/C1 State, C2 State, C6 (Non Retention) State, C6 (Retention) state, No Limit,
and Auto.

CPU T State Control

Software Controlled T-States

Enabling this feature allows the OS to choose a T-State. The options are Enable and

Disable.

Chipset Conguration

Warning: Setting the wrong values in the following features may cause the system to malfunc-

tion.

North Bridge

This feature allows the user to congure the following North Bridge settings.

UPI Conguration

UPI General Conguration

UPI Status

The following UPI information will display:

• Number of CPU

• Number of IIO

• Current UPI Link Speed

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Chapter 4: BIOS

• Current UPI Link Frequency

• UPI Global MMIO Low Base / Limit

• UPI Global MMIO High Base / Limit

• UPI Pci-e Congguration Base / Size

Degrade Precedence

Use this feature to set degrade precedence when system settings are in conict. Select

Topology Precedence to degrade Features. Select Feature Precedence to degrade
Topology. The options are Topology Precedence and Feature Precedence.

Link L0p Enable

Select Enable for Link L0p support. The options are Enable and Disable.

Link L1 Enable

Select Enable for Link L1 support. The options are Enable and Disable.

IO Directory Cache (IODC)

IO Directory Cache is an 8-entry cache that stores the directory state of remote IIO writes
and memory lookups, and saves directory updates. Use this feature to lower cache to cache
(C2C) transfer latencies. The options are Disable, Auto, Enable for Remote InvItoM Hybrid
Push, InvItoM AllocFlow, Enable for Remote InvItoM Hybrid AllocNonAlloc, and Enable for
Remote InvItoM and Remote WViLF.

Isoc Mode

Select Enabled for Isochronous support to meet QoS (Quality of Service) requirements.
This feature is especially important for Virtualization Technology. The options are Enable
and Disable.

Memory Conguration

Enforce POR

Select Enable to enforce POR restrictions on DDR4 frequency and voltage programming.
The options are Enabled and Disable.

Memory Frequency

Use this feature to set the maximum memory frequency for onboard memory modules.
The options are Auto, 1333, 1400, 1600, 1800, 1867, 2000, 2133, 2200, and 2400.

Data Scrambling for NVDIMM

Use this festure to enable or disable data scrambling for non-volatile DIMM (NVDIMM)
memory. The options are Auto, Disable, and Enable.

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Data Scrambling for DDR4

Use this feature to enable or disable data scrambling for DDR4 memory. The options
are Auto, Disable, and Enable.

tCCD_L Relaxation

If this feature is set to Enable, SPD (Serial Presence Detect) will override tCCD_L ("Col­umn to Column Delay-Long", or “Command to Command Delay-Long” on the column
side.) If this feature is set to Disable, tCCD_L will be enforced based on the memory
frequency. The options are Enable and Disable.

Enable ADR

Select Enable for ADR (Automatic Diagnostic Repository) support to enhance memory
performance. The options are Enable and Disable.

2X REFRESH

This option allows the user to select 2X refresh mode. The options are Auto, Enabled,
and Disabled.

Memory Topology

This feature displays DIMM population information.

Memory RAS Conguration

Static Virtual Lockstep Mode

Select Enable to run the system's memory channels in lockstep mode to minimize memory
access latency. The options are Disable and Enable.

Mirror Mode

This feature allows memory to be mirrored between two channels, providing 100% re­dundancy. The options are Disable, Mirror Mode 1LM, and Mirror Mode 2LM.

UEFI ARM Mirror

This options allows the system to imitate the behavior of the UEFI based Address Range
Mirror with setup option. The options are Disable and Enable.

Memory Rank Sparing

Select Enable to enable memory-sparing support for memory ranks to improve memory
performance. The options are Disable and Enable.

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Correctable Error Threshold

Use this item to specify the threshold value for correctable memory-error logging, which
sets a limit on the maximum number of events that can be logged in the memory-error
log at a given time. The default setting is 10.

SDDC Plus One

Single Device Data Correction (SDDC) organizes data in a single bundle (x4/x8 DRAM).
If any or all the bits become corrupted, corrections occur. The x4 condition is corrected
on all cases. The x8 condition is corrected only if the system is in Lockstep Mode. The
options are Disable and Enable.

ADDDC Sparing

Adaptive Double Device Data Correction (ADDDC) Sparing detects when the prede­termined threshold for correctable errors is reached, copying the contents of the failing
DIMM to spare memory. The failing DIMM or memory rank will then be disabled. The
options are Disable and Enable.

Patrol Scrub

Patrol Scrubbing is a process that allows the CPU to correct correctable memory errors
detected on a memory module and send the correction to the requestor (the original
source). When this item is set to Enable, the IO hub will read and write back one cache
line every 16K cycles, if there is no delay caused by internal processing. By using this
method, roughly 64 GB of memory behind the IO hub will be scrubbed every day. The
options are Disable and Enable.

Patrol Scrub Interval

This feature allows you to decide how many hours the system should wait before the
next complete patrol scrub is performed. Use the keyboard to enter a value from 0-24.
The default setting is 24.

IIO Conguration

EV DFX Features

CPU1 Conguration

IOU0 (II0 PCIe Br1)

This item congures the PCI-E port Bifuraction setting for a PCI-E port specied by the

user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

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IOU1 (II0 PCIe Br2)

This item congures the PCI-E port Bifuraction setting for a PCI-E port specied by the

user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

IOU2 (II0 PCIe Br3)

This item congures the PCI-E port Bifuraction setting for a PCI-E port specied by the

user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

MCP0 (II0 PCIe Br4)

This item congures the PCI-E port Bifuraction setting for a PCI-E port specied by the

user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

MCP1 (II0 PCIe Br5)

This item congures the PCI-E port Bifuraction setting for a PCI-E port specied by the

user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

CPU1 PcieBr1D00F0 - Port 1A/PcieBr1D01F0 - Port 1B/PcieBr2D00F0 - Port 2A

RSC-R1UW-2E16 SLOT2

Link Speed

Use this item to select the link speed for the PCI-E port specied by the user. The op­tions are Auto, Gen 1 (2.5 GT/s), Gen 2 (5 GT/s), and Gen 3 (8 GT/s).

PCI-E Port Max Payload Size

Selecting Auto for this feature will enable the motherboard to automatically detect the
maximum Transaction Layer Packet (TLP) size for the connected PCI-E device, allowing

for maximum I/O e󰀩ciency. Selecting 128B or 256B will designate maximum packet size

of 128 or 256. Options are Auto, 128, and 256. Auto is enabled by default.

CPU2 Conguration

IOU0 (II0 PCIe Br1)

This item congures the PCI-E port Bifuraction setting for a PCI-E port specied by the

user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

IOU1 (II0 PCIe Br2)

This item congures the PCI-E port Bifuraction setting for a PCI-E port specied by the

user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

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IOU2 (II0 PCIe Br3)

This item congures the PCI-E port Bifuraction setting for a PCI-E port specied by the

user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

MCP0 (II0 PCIe Br4)

This item congures the PCI-E port Bifuraction setting for a PCI-E port specied by the

user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

MCP1 (II0 PCIe Br5)

This item congures the PCI-E port Bifuraction setting for a PCI-E port specied by the

user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.

CPU2 PcieBr1D00F0 - Port 1A/PcieBr1D01F0 - Port 1B/RSC-R1UW-2E16
SLOT1/RSC-R1UW-E8R SLOT1

Link Speed

Use this item to select the link speed for the PCI-E port specied by the user. The op­tions are Auto, Gen 1 (2.5 GT/s), Gen 2 (5 GT/s), and Gen 3 (8 GT/s).

PCI-E Port Max Payload Size

Selecting Auto for this feature will enable the motherboard to automatically detect the
maximum Transaction Layer Packet (TLP) size for the connected PCI-E device, allowing

for maximum I/O e󰀩ciency. Selecting 128B or 256B will designate maximum packet size

of 128 or 256. Options are Auto, 128, and 256. Auto is enabled by default.

IOAT Conguration

Disable TPH

Transparent Hugepages is a Linux memory management system that enables commu­nication in larger blocks (pages). Enabling this feature will increase performance. The
options are No and Yes.

Prioritize TPH

Use this feature to enable Prioritize TPH support. The options are Enable and Disable.

Relaxed Ordering

Select Enable to enable Relaxed Ordering support which will allow certain transactions to
violate the strict-ordering rules of PCI bus for a transaction to be completed prior to other
transactions that have already been enqueued. The options are Disable and Enable.

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Intel® VT for Directed I/O (VT-d)

Intel® VT for Directed I/O (VT-d)

Select Enable to use Intel Virtualization Technology for Direct I/O VT-d support by report­ing the I/O device assignments to the VMM (Virtual Machine Monitor) through the DMAR

ACPI tables. This feature o󰀨ers fully-protected I/O resource sharing across Intel platforms,

providing greater reliability, security and availability in networking and data-sharing. The
options are Disabled and Enabled.

Interrupt Remapping

Select Enable for Interrupt Remapping support to enhance system performance. The
options are Enable and Disable.

PassThrough DMA

Use this feature to allow devices such as network cards to access the system memory
without using a processor. Select Enable to use the Non-Isoch VT_D Engine Pass
Through Direct Memory Access (DMA) support. The options are Enable and Disable.

ATS

Use this feature to enable Non-Isoch VT-d Engine Address Translation Services (ATS)
support. ATS translates virtual addresses to physical addresses. The options are Enable
and Disable.

Posted Interrupt

Use this feature to enable VT_D Posted Interrupt. The options are Enable and Disable.

Coherency Support (Non-Isoch)

Use this feature to maintain setting coherency between processors or other devices.
Select Enable for the Non-Iscoh VT-d engine to pass through DMA to enhance system
performance. The options are Enable and Disable.

Intel® VMD Technology

Intel® VMD for Volume Management Device on CPU1

VMD Cong for PStack0

Intel® VMD for Volume Management Device

Select Enable to use the Intel Volume Management Device Technology for this stack.
The options are Disable and Enable.

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Chapter 4: BIOS

*If the item "Intel VMD for Volume Management Device" above is set to Enable,
the following items will be dislayed:

VMD port 1A~VMD port 1D (Available when the device is detected by the
system)

Select Enable to use the Intel Volume Management Device Technology for this spe-

cic root port. The options are Disable and Enable.

Hot Plug Capable (Available when the device is detected by the system)

Use this feature to enable hot plug support for PCIe root ports 1A~1D. The options
are Disable and Enable.

VMD Cong for PStack1

Intel® VMD for Volume Management Device

Select Enable to use the Intel Volume Management Device Technology for this stack.
The options are Disable and Enable.

*If the item "Intel VMD for Volume Management Device" above is set to Enable,
the following items will be dislayed:

VMD port 2A~VMD port 2D (Available when the device is detected by the
system)

Select Enable to use the Intel Volume Management Device Technology for this spe-

cic root port. The options are Disable and Enable.

Hot Plug Capable (Available when the device is detected by the system)

Use this feature to enable hot plug support for PCIe root ports 2A~2D. The options
are Disable and Enable.

VMD Cong for PStack2

Intel® VMD for Volume Management Device

Select Enable to use the Intel Volume Management Device Technology for this stack.
The options are Disable and Enable.

*If the item "Intel VMD for Volume Management Device" above is set to Enable,
the following items will be dislayed:

VMD port 3A~VMD port 3D (Available when the device is detected by the
system)

Select Enable to use the Intel Volume Management Device Technology for this spe­cic root port. The options are Disable and Enable.

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Hot Plug Capable (Available when the device is detected by the system)

Use this feature to enable hot plug support for PCIe root ports 3A~3D. The options
are Disable and Enable.

Intel® VMD for Volume Management Device on CPU2

VMD Cong for PStack0

Intel® VMD for Volume Management Device

Select Enable to use the Intel Volume Management Device Technology for this stack.
The options are Disable and Enable.

*If the item "Intel VMD for Volume Management Device" above is set to Enable,
the following items will be dislayed:

VMD port 1A~VMD port 1D (Available when the device is detected by the
system)

Select Enable to use the Intel Volume Management Device Technology for this spe-

cic root port. The options are Disable and Enable.

Hot Plug Capable (Available when the device is detected by the system)

Use this feature to enable hot plug support for PCIe root ports 1A~1D. The options
are Disable and Enable.

VMD Cong for PStack1

Intel® VMD for Volume Management Device

Select Enable to use the Intel Volume Management Device Technology for this stack.
The options are Disable and Enable.

*If the item "Intel VMD for Volume Management Device" above is set to Enable,
the following items will be dislayed:

VMD port 2A~VMD port 2D (Available when the device is detected by the
system)

Select Enable to use the Intel Volume Management Device Technology for this spe-

cic root port. The options are Disable and Enable.

Hot Plug Capable (Available when the device is detected by the system)

Use this feature to enable hot plug support for PCIe root ports 2A~2D. The options
are Disable and Enable.

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Chapter 4: BIOS

VMD Cong for PStack2

Intel® VMD for Volume Management Device

Select Enable to use the Intel Volume Management Device Technology for this stack.
The options are Disable and Enable.

*If the item "Intel VMD for Volume Management Device" above is set to Enable,
the following items will be dislayed:

VMD port 3A~VMD port 3D (Available when the device is detected by the
system)

Select Enable to use the Intel Volume Management Device Technology for this spe-

cic root port. The options are Disable and Enable.

Hot Plug Capable (Available when the device is detected by the system)

Use this feature to enable hot plug support for PCIe root ports 3A~3D. The options
are Disable and Enable.

PCI-E Completion Timeout Disable

Use this feature to enable PCI-E Completion Timeout support for electric tuning. The
options are Yes, No, and Per-Port.

South Bridge

Legacy USB Support

This feature enables support for USB 2.0 and older. The options are Enabled and Dis­abled. Default setting is Enabled.

XHCI Hand-o󰀨

When disabled, the motherboard will not support USB 3.0. Options are Enabled and
Disabled. Default setting is Disabled.

Port 60/64 Emulation

This feature allows legacy I/O support for USB devices like mice and keyboards. The
options are Enabled and disabled. Default setting is Enabled.

Server ME (Management Engine) Conguration

This feature displays the following system ME conguration settings.

• Operational Firmware Version

• Backup Firmware Version

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• Recovery Firmware Version

• ME Firmware Status #1

• ME Firmware Status #2

• Current State

• Error Code

PCH SATA Conguration

When this submenu is selected, the AMI BIOS automatically detects the presence of the
SATA devices that are supported by the Intel PCH chip and displays the following items:

SATA Controller

This item enables or disables the onboard SATA controller supported by the Intel PCH
chip. The options are Disable and Enable.

Congure SATA as

Select IDE to congure a SATA drive specied by the user as an IDE drive. Select AHCI to
congure a SATA drive specied by the user as an AHCI drive. Select RAID to congure a
SATA drive specied by the user as a RAID drive. The options are IDE, AHCI, and RAID.

SATA HDD Unlock

This feature allows the user to remove any password-protected SATA disk drives.

Aggressive Link Power Management

When this item is set to Enabled, the SATA AHCI controller manages the power usage of
the SATA link. The controller will put the link in a low power mode during extended periods
of I/O inactivity, and will return the link to an active state when I/O activity resumes. The
options are Disabled and Enabled.

*If the item above "Congure SATA as" is set to RAID, the following items will

display:

SATA Port 0 ~ Port 7

This item displays the information detected on the installed SATA drive on the particular
SATA port.

• Model number of drive and capacity

• Software Preserve Support

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Chapter 4: BIOS

Port 0 ~ Port 7 Hot Plug

Set this item to Enabled for hot-plugging support, which will allow the user to replace a
SATA drive without shutting down the system. The options are Disabled and Enabled.

Port 0 ~ Port 6 Spin Up Device

On an edge detect from 0 to 1, set this item to allow the PCH to initialize the device. The
options are Disabled and Enabled.

Port 0 ~ Port 6 SATA Device Type

Use this item to specify if the SATA port specied by the user should be connected to

a Solid State drive or a Hard Disk Drive. The options are Hard Disk Drive and Solid
State Drive.

PCH sSATA Conguration

When this submenu is selected, the AMI BIOS automatically detects the presence of the
SATA devices that are supported by the Intel PCH chip and displays the following items:

sSATA Controller

This item enables or disables the onboard sSATA controller supported by the Intel PCH
chip. The options are Disable and Enable.

Congure sSATA as

Select AHCI to congure an sSATA drive specied by the user as an AHCI drive. Select
RAID to congure an sSATA drive specied by the user as a RAID drive. The options

are AHCI, and RAID.

SATA HDD Unlock

This feature allows the user to remove any password-protected SATA disk drives.

Aggressive Link Power Management

When this item is set to Enabled, the SATA AHCI controller manages the power usage of
the SATA link. The controller will put the link in a low power mode during extended periods
of I/O inactivity, and will return the link to an active state when I/O activity resumes. The
options are Disabled and Enabled.

*If the item above "Congure SATA as" is set to RAID, the following items will

display:

sSATA Port 0 ~ Port 2

This item displays the information detected on the installed sSATA drive on the particular
sSATA port.

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X11DDW-L/NT User's Manual

• Model number of drive and capacity

• Software Preserve Support

Port 0 ~ Port 2 Hot Plug

Set this item to Enabled for hot-plugging support, which will allow the user to replace a
SATA drive without shutting down the system. The options are Disabled and Enabled.

Port 0 ~ Port 2 Spin Up Device

On an edge detect from 0 to 1, set this item to allow the PCH to initialize the device. The
options are Disabled and Enabled.

Port 0 ~ Port 2 SsATA Device Type

Use this item to specify if the SATA port specied by the user should be connected to

a Solid State drive or a Hard Disk Drive. The options are Hard Disk Drive and Solid
State Drive.

PCIe/PCI/PnP Conguration

The following information will display:

• PCI Bus Driver Version

• PCI Devices Common Settings:

Above 4G Decoding (Available if the system supports 64-bit PCI decoding)

Select Enabled to decode a PCI device that supports 64-bit in the space above 4G Address.
The options are Disabled and Enabled.

SR-IOV Support

Use this feature to enable or disable Single Root IO Virtualization Support. The options are

Disabled and Enabled.

MMIO High Base

Use this item to select the base memory size according to memory-address mapping for the
IO hub. The options are 56 TB, 40 TB, 24 TB, 3 TB, 2 TB, and 1 TB.

MMIO High Granularity Size

Use this item to select the high memory size according to memory-address mapping for the
IO hub. The options are 256 GB, 128 GB, 512 GB, and 1024 GB.

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Chapter 4: BIOS

PCI PERR/SERR Support

Select Enabled to allow a PCI device to generate a PERR/SERR number for a PCI Bus Signal
Error Event. The options are Enabled and Disabled.

Maximum Read Request

Select Auto for the system BIOS to automatically set the maximum size for a read request
for a PCI-E device to enhance system performance. The options are Auto, 128 Bytes, 256
Bytes, 512 Bytes, 1024 Bytes, 2048 Bytes, and 4096 Bytes.

MMCFG Base

Use this item to select the low base address for PCIE adapters to increase base memory.
The options are 1G, 1.5G, 1.75G, 2G, 2.25G. and 3G.

NVMe Firmware Source

Use this item to select the NVMe rmware to support booting. The options are Vendor

Dened Firmware and AMI Native Support. The default option, Vendor Dened Firmware,

is pre-installed on the drive and may resolve errata or enable innovative functions for the

drive. The other option, AMI Native Support, is o󰀨ered by the BIOS with a generic method.

VGA Priority

Use this item to select the graphics device to be used as the primary video display for system
boot. The options are Onboard and O󰀨board.

M.2 PCI-E 3.0 X4 OPROM

Use this feature to select which rmware type to be loaded for the add-on card in this slot.

The options are Disabled, Legacy, and EFI.

CPU1 AOM PCI-E 3.0 x16 OPROM

Use this feature to select which rmware type to be loaded for the add-on card in this slot.

The options are Disabled, Legacy, and EFI.

RSC-R1UW-2E16 SLOT1 PCI-E x16 OPROM

Use this feature to select which rmware type to be loaded for the add-on card in this slot.

The options are Disabled, Legacy, and EFI.

RSC-R1UW-2E16 SLOT2 PCI-E x16 OPROM

Use this feature to select which rmware type to be loaded for the add-on card in this slot.

The options are Disabled, Legacy, and EFI.

RSC-R1UW-E8R SLOT1 PCI-E x8 OPROM

Use this feature to select which rmware type to be loaded for the add-on card in this slot.

The options are Disabled, Legacy, and EFI.

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X11DDW-L/NT User's Manual

Onboard LAN Device

Select Enabled to enable the Onboard LAN device. The options are Enabled and Disabled.

Onboard LAN1 Option ROM

Use this feature to select which rmware function to be loaded for LAN Port1 used for system

boot. The options are Disabled, Legacy, and EFI.

Onboard LAN2 Option ROM

Use this feature to select which rmware function to be loaded for LAN Port2 used for system

boot. The options are Disabled, Legacy, and EFI.

Onboard Video Option ROM

Use this item to select the Onboard Video Option ROM type. The options are Disabled,
Legacy, and EFI.

Network Stack Conguration

Network Stack

Select Enabled to enable PXE (Preboot Execution Environment) or UEFI (Unied Extensible

Firmware Interface) for network stack support. The options are Enabled and Disabled.

*If "Network Stack" is set to Enabled, the following items will display:

Ipv4 PXE Support

Use this feature to enable Ipv4 PXE Boot Support. If this feature is disabled, it will not create
the Ipv4 PXE Boot option. The options are Disabled and Enabled.

Ipv4 HTTP Support

Use this feature to enable Ipv4 HTTP Boot Support. If this feature is disabled, it will not create
the Ipv4 HTTP Boot option. The options are Disabled and Enabled.

Ipv6 PXE Support

Use this feature to enable Ipv6 PXE Boot Support. If this feature is disabled, it will not create
the Ipv6 PXE Boot option. The options are Disabled and Enabled.

Ipv6 HTTP Support

Use this feature to enable Ipv6 HTTP Boot Support. If this feature is disabled, it will not create
the Ipv6 HTTP Boot option. The options are Disabled and Enabled.

PXE Boot Wait Time

Use this feature to select the wait time to press the ESC key to abort the PXE boot. The
default is 0.

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Chapter 4: BIOS

Media Detect Count

Use this feature to select the wait time in seconds to detect LAN media. The default is 1.

Super IO Conguration

The following Super IO information will display:

• Super IO Chip AST2500

Serial Port 1 Conguration

Serial Port 1

Select Enabled to enable the onboard serial port specied by the user. The options are

Enabled and Disabled.

Device Settings

This item displays the base I/O port address and the Interrupt Request address of a serial

port specied by the user.

Note: This item is hidden when Serial Port 1 is set to Disabled.

Change Port 1 Settings

This feature species the base I/O port address and the Interrupt Request address of Serial

Port 1. Select Auto for the BIOS to automatically assign the base I/O and IRQ address to

a serial port specied.

The options for Serial Port 2 are Auto, (IO=3F8h; IRQ=4), (IO=3F8h; IRQ=3, 4, 5, 6, 7, 9,
10, 11, 12), (IO=2F8h; IRQ=3, 4, 5, 6, 7, 9, 10, 11, 12); (IO=3E8h; IRQ=3, 4, 5, 6, 7, 9, 10,
11, 12), and (IO=2E8h; IRQ=3, 4, 5, 6, 7, 9, 10, 11, 12).

Serial Port 2 Conguration

Serial Port 2

Select Enabled to enable the onboard serial port specied by the user. The options are

Enabled and Disabled.

Device Settings

This item displays the base I/O port address and the Interrupt Request address of a serial

port specied by the user.

Note: This item is hidden when Serial Port 2 is set to Disabled.

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X11DDW-L/NT User's Manual

Change Port 2 Settings

This feature species the base I/O port address and the Interrupt Request address of Serial

Port 2. Select Auto for the BIOS to automatically assign the base I/O and IRQ address to

a serial port specied.

The options for Serial Port 2 are Auto, (IO=3F8h; IRQ=4), (IO=3F8h; IRQ=3, 4, 5, 6, 7, 9,
10, 11, 12), (IO=2F8h; IRQ=3, 4, 5, 6, 7, 9, 10, 11, 12); (IO=3E8h; IRQ=3, 4, 5, 6, 7, 9, 10,
11, 12), and (IO=2E8h; IRQ=3, 4, 5, 6, 7, 9, 10, 11, 12).

Serial Port 2 Attribute

Select SOL to use COM Port 2 as a Serial_Over_LAN (SOL) port for console redirectoin.
The options are COM and SOL.

Serial Port Console Redirection

COM0 Console Redirection

Select Enabled to enable console redirection support for a serial port specied by the user.

The options are Enabled and Disabled.

*If the item above set to Enabled, the following items will become available for user's

conguration:

COM2/SOL Console Redirection Settings

This feature allows the user to specify how the host computer will exchange data with the
client computer, which is the remote computer used by the user.

Terminal Type

This feature allows the user to select the target terminal emulation type for Console
Redirection. Select VT100 to use the ASCII Character set. Select VT100+ to add color and
function key support. Select ANSI to use the Extended ASCII Character Set. Select VT-UTF8
to use UTF8 encoding to map Unicode characters into one or more bytes. The options are
VT100, VT100+, VT-UTF8, and ANSI.

Bits per second

Use this feature to set the transmission speed for a serial port used in Console Redirection.
Make sure that the same speed is used in the host computer and the client computer. A lower
transmission speed may be required for long and busy lines. The options are 9600, 19200,
38400, 57600 and 115200 (bits per second).

Data Bits

Use this feature to set the data transmission size for Console Redirection. The options are
7 Bits and 8 Bits.

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Chapter 4: BIOS

Parity

A parity bit can be sent along with regular data bits to detect data transmission errors. Select
Even if the parity bit is set to 0, and the number of 1's in data bits is even. Select Odd if the
parity bit is set to 0, and the number of 1's in data bits is odd. Select None if you do not want
to send a parity bit with your data bits in transmission. Select Mark to add a mark as a parity
bit to be sent along with the data bits. Select Space to add a Space as a parity bit to be sent
with your data bits. The options are None, Even, Odd, Mark, and Space.

Stop Bits

A stop bit indicates the end of a serial data packet. Select 1 Stop Bit for standard serial data
communication. Select 2 Stop Bits if slower devices are used. The options are 1 and 2.

Flow Control

Use this feature to set the ow control for Console Redirection to prevent data loss caused
by bu󰀨er overow. Send a "Stop" signal to stop sending data when the receiving bu󰀨er is full.
Send a "Start" signal to start sending data when the receiving bu󰀨er is empty. The options

are None and Hardware RTS/CTS.

VT-UTF8 Combo Key Support

Select Enabled to enable VT-UTF8 Combination Key support for ANSI/VT100 terminals. The
options are Disabled and Enabled.

Recorder Mode

Select Enabled to capture the data displayed on a terminal and send it as text messages to
a remote server. The options are Disabled and Enabled.

Resolution 100x31

Select Enabled for extended-terminal resolution support. The options are Disabled and

Enabled.

Legacy OS Redirection Resolution

Use this feature to select the number of rows and columns used in Console Redirection for
legacy OS support. The options are 80x24 and 80x25.

Putty KeyPad

This feature selects the settings for Function Keys and KeyPad used for Putty, which is a
terminal emulator designed for the Windows OS. The options are VT100, LINUX, XTERMR6,
SC0, ESCN, and VT400.

Redirection After BIOS POST

Use this feature to enable or disable legacy console redirection after BIOS POST. When set to
Bootloader, legacy console redirection is disabled before booting the OS. When set to Always

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X11DDW-L/NT User's Manual

Enable, legacy console redirection remains enabled when booting the OS. The options are
Always Enable and Bootloader.

Legacy Console Redirection Settings

Legacy Serial Redirection Port

Use this feature to select a COM port to display redirection of Legacy OS and Legacy OPROM
messages. The options are COM1 and SOL/COM2.

EMS Console Redirection Settings

EMS Console Redirection

This feature allows the user to specify how the host computer will exchange data with the
client computer, which is the remote computer used by the user.

*If the item above set to Enabled, the following items will become available for user's

conguration:

Terminal Type

Use this feature to select the target terminal emulation type for Console Redirection. Select
VT100 to use the ASCII character set. Select VT100+ to add color and function key support.
Select ANSI to use the extended ASCII character set. Select VT-UTF8 to use UTF8 encoding
to map Unicode characters into one or more bytes. The options are VT100, VT100+, VT-

UTF8, and ANSI.

Bits Per Second

This item sets the transmission speed for a serial port used in Console Redirection. Make
sure that the same speed is used in the host computer and the client computer. A lower
transmission speed may be required for long and busy lines. The options are 9600, 19200,
57600, and 115200 (bits per second).

Flow Control

Use this item to set the ow control for Console Redirection to prevent data loss caused by
bu󰀨er overow. Send a "Stop" signal to stop sending data when the receiving bu󰀨er is full.
Send a "Start" signal to start sending data when the receiving bu󰀨er is empty. The options

are None, Hardware RTS/CTS, and Software Xon/Xo󰀨.

Data Bits

Use this feature to set the data transmission size for Console Redirection. The options are
7 Bits and 8 Bits.

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