The information in this User’s Manual has been carefully reviewed and is believed to be accurate.
The vendor assumes no responsibility for any inaccuracies that may be contained in this document,
makes no commitment to update or to keep current the information in this manual, or to notify any
person or organization of the updates. Please Note: For the most up-to-date version of this
manual, please see our web site at www.supermicro.com.
Super Micro Computer, Inc. ("Supermicro") reserves the right to make changes to the product
described in this manual at any time and without notice. This product, including software and documentation, is the property of Supermicro and/or its licensors, and is supplied only under a license.
Any use or reproduction of this product is not allowed, except as expressly permitted by the terms
of said license.
IN NO EVENT WILL SUPERMICRO BE LIABLE FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL,
SPECULATIVE OR CONSEQUENTIAL DAMAGES ARISING FROM THE USE OR INABILITY TO
USE THIS PRODUCT OR DOCUMENTATION, EVEN IF ADVISED OF THE POSSIBILITY OF
SUCH DAMAGES. IN PARTICULAR, SUPERMICRO SHALL NOT HAVE LIABILITY FOR ANY
HARDWARE, SOFTWARE, OR DATA STORED OR USED WITH THE PRODUCT, INCLUDING THE
COSTS OF REPAIRING, REPLACING, INTEGRATING, INSTALLING OR RECOVERING SUCH
HARDWARE, SOFTWARE, OR DATA.
Any disputes arising between manufacturer and customer shall be governed by the laws of Santa
Clara County in the State of California, USA. The State of California, County of Santa Clara shall
be the exclusive venue for the resolution of any such disputes. Super Micro's total liability for all
claims will not exceed the price paid for the hardware product.
FCC Statement: This equipment has been tested and found to comply with the limits for a class B
digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable
protection against harmful interference in a residential installation. This equipment generates, uses,
and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that
interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on,
the user is encouraged to try to correct the interference by one or more of the following measures:
• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and receiver.
• Connect the equipment to an outlet on a circuit different from that to which the receiver
is connected.
• Consult the authorized dealer or an experienced radio/TV technician for help.
California Best Management Practices Regulations for Perchlorate Materials: This Perchlorate warning applies only to products containing CR (Manganese Dioxide) Lithium coin cells. “Perchlorate
Material-special handling may apply. See www.dtsc.ca.gov/hazardouswaste/perchlorate”
WARNING: Handling of lead solder materials used in this
product may expose you to lead, a chemical known to the
State of California to cause birth defects and other reproductive harm.
De uiteindelijke verwijdering van dit product dient te geschieden in overeenstemming
met alle nationale wetten en reglementen.
2-2 Static-Sensitive Devices
Electrostatic-Discharge (ESD) can damage electronic com ponents. To avoid dam-
aging your system board, it is important to handle it very carefully. The following
measures are generally sufcient to protect your equipment from ESD.
Precautions
• Use a grounded wrist strap designed to prevent static discharge.
• Touch a grounded metal object before removing the board from the antistatic
bag.
• Handle the board by its edges only; do not touch its components, peripheral
chips, memory modules or gold contacts.
• When handling chips or modules, avoid touching their pins.
• Put the motherboard and peripherals back into their antistatic bags when not in
use.
• For grounding purposes, make sure your computer chassis provides excellent
conductivity between the power supply, the case, the mounting fasteners and
the motherboard.
• Use only the correct type of onboard CMOS battery. Do not install the onboard
battery upside down to avoid possible explosion.
Unpacking
The motherboard is shipped in antistatic packaging to avoid static damage. When
unpacking the board, make sure that the person handling it is static protected.
2-4
Page 31
Chapter 2: Installation
2-3 Motherboard Installation
All motherboards have standard mounting holes to t different types of chassis.
Make sure that the locations of all the mounting holes for both motherboard and
chassis match. Although a chassis may have both plastic and metal mounting fas-
teners, metal ones are highly recommended because they ground the motherboard
to the chassis. Make sure that the metal standoffs click in or are screwed in tightly.
Then use a screwdriver to secure the motherboard onto the motherboard tray.
Tools Needed
Philips Screwdriver
(1)
Philips Screws (7)
Standoffs (7)
Only if Needed
Location of Mounting Holes
UID
LE1
SATA4
JP4
MAC CODE
BAR CODE
IPMI CODE
I-SATA1
I-SATA0
JSD2
FAN7
JUIDB1
SXB1_1
SXB1_2
SXB1_3
I-SATA3
I-SATA2
JSD1
SATA5
JL1
FAN5
FAN6
VGA
BIOS
LICENSE
JBRSET1
SXB2
2-3:DISABLE
LAN1
1-2:ENABLE
JPL2
JPL3
LAN2
2-3:DISABLE
1-2:ENABLE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
2-3:BIOS RECOVERY
1-2:NORMAL
DM1
JPME2
JWD1
JBR1
2-3:NMI
JWD:Watch Dog
1-2:RST
JBR1
JBT1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
DIMMD1
DIMMD2
DIMMC1
DIMMC2
FAN4
LAN2
LEDM1
X10SRW-F
REV:1.01
DESIGNED IN USA
1
LGA2011-3
FAN3
USB0/1(3.0)
LAN1
USB2/3
IPMI_LAN
DM2
JPG1
BT1
JPF1
JPG1:VGA
ON:POWER FORCE ON
1-2:ENABLE
JI2C1/2:
I2C BUS FOR PCI-E SLOT
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
INTRUSIONJL1:
CHASSIS
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
CPU
1
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
FAN2
Caution: 1) To avoid damaging the motherboard and its components, please do
not use a force greater than 8 lb/inch on each mounting screw during motherboard
installation. 2) Some components are very close to the mounting holes. Please take
precautionary measures to avoid damaging these components when installing the
motherboard to the chassis.
JIPMB1
COM1
123
IPMI
4
COM2
JF1
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
JPL1
TPM/PORT80
JI2C2J29
JTPM1
JI2C1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
USB4/5
J30
111
USB6/7
SP1
JPF2
JPF1
USB8(3.0)
J23
T-SGPIO3
1
T-SGPIO2
USB9/10
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JOH1
JF1
JPI2C1
JSTBY1
JPWR1
J24
FAN1
2-5
Page 32
X10SRW-F User’s Manual
Installing the Motherboard
1. Install the I/O shield into the back of the chassis.
2. Locate the mounting holes on the motherboard. (See the previous page.)
3. Locate the matching mounting holes on the chassis. Align the mounting holes
on the motherboard against the mounting holes on the chassis.
4. Install standoffs in the chassis as needed.
5. Install the motherboard into the chassis carefully to avoid damaging other
motherboard components.
6. Using the Phillips screwdriver, insert a Phillips head #6 screw into a mounting
hole on the motherboard and its matching mounting hole on the chassis.
7. Repeat Step 5 to insert #6 screws into all mounting holes.
8. Make sure that the motherboard is securely placed in the chassis.
Note: Images displayed are for illustration only. Your chassis or compo-
nents might look different from those shown in this manual.
2-6
Page 33
Chapter 2: Installation
2-4 Processor and Heatsink Installation
Warning: When handling the processor package, avoid placing direct pressure on the
label area of the fan.
Notes:
• Always connect the power cord last, and always remove it before adding, re-
moving or changing any hardware components. Make sure that you install the
processor into the CPU socket before you install the CPU heatsink.
• If you buy a CPU separately, make sure that you use an Intel-certied multi-
directional heatsink only.
• Make sure to install the system board into the chassis before you install the
CPU heatsink.
• When receiving a server board without a processor pre-installed, make sure that
the plastic CPU socket cap is in place and none of the socket pins are bent;
otherwise, contact your retailer immediately.
• Refer to the Supermicro website for updates on CPU support.
Installing the LGA2011 Processor
1. There are two load levers on the LGA2011 socket. To open the socket cover,
rst press and release the load lever labeled 'Open 1st'.
1
OPEN 1st
Press down
on
labeled 'Open 1st'.
2
OPEN 1st
Load Lever
2-7
Page 34
X10SRW-F User’s Manual
2. Press the second load lever labeled 'Close 1st' to release the load plate that
covers the CPU socket from its locking position.
1
3. With the 'Close 1st' lever fully retracted, gently push down on the 'Open 1st'
lever to open the load plate. Lift the load plate to open it completely.
Press down on
Lever 'Close 1st'
OPEN 1st
1
OPEN 1st
Load
Gently push
down to pop the
load plate open.
Pull lever away from
2
the socket
OPEN 1st
2
2-8
Page 35
Chapter 2: Installation
4. Using your thumb and the index nger, loosen the CPU lever and open the
load plate.
5. Use your thumb and index nger to hold the CPU on its edges. Align the CPU
keys, which are semi-circle cutouts, against the socket keys.
Socket Keys
CPU Keys
6. Once they are aligned, carefully lower the CPU straight down into the socket.
(Do not drop the CPU on the socket. Do not move the CPU horizontally or
vertically. Do not rub the CPU against the surface or against any pins of the
socket to avoid damaging the CPU or the socket.)
Warning: You can only install the
CPU inside the socket in one direc-
tion. Make sure that it is properly
inserted into the CPU socket before
closing the load plate. If it doesn't
close properly, do not force it as it
may damage your CPU. Instead,
open the load plate again and dou-
ble-check that the CPU is aligned
properly.
2-9
Page 36
X10SRW-F User’s Manual
7. With the CPU inside the socket, inspect the four corners of the CPU to make
sure that the CPU is properly installed.
8. Close the load plate with the CPU inside the socket. Lock the lever labelled
'Close 1st' rst, then lock the lever labelled 'Open 1st' second. Using your
thumb gently push the load levers down to the lever locks.
Gently close
12
the load plate.
3
Lever Lock
OPEN 1st
Push down and
lock the lever
labelled 'Open
1st'.
Push down and lock the
lever labelled 'Close 1st'.
OPEN 1st
4
OPEN 1st
2-10
Lever Lock
Page 37
Chapter 2: Installation
Installing a Passive CPU Heatsink
1. Do not apply any thermal grease to the heatsink or the CPU die -- the re-
quired amount has already been applied.
2. Place the heatsink on top of the CPU so that the four mounting holes are
aligned with those on the Motherboard's and the Heatsink Bracket under-
neath.
3. Screw in two diagonal screws (i.e., the #1 and the #2 screws) until just snug
(-do not over-tighten the screws to avoid possible damage to the CPU.)
4. Finish the installation by fully tightening all four screws.
Screw#1
Motherboard
Note: For optimized airow, please follow your chassis airow direction
to install the correct CPU heatsink direction. Graphic drawings included
in this manual are for reference only. They might look different from the
components installed in your system
Screw#2
OPEN 1st
Mounting Holes
2-11
Page 38
X10SRW-F User’s Manual
Removing the Heatsink
Warning: We do not recommend that the CPU or the heatsink be removed. However,
if you do need to uninstall the heatsink, please follow the instructions below to prevent
damage to the CPU or the CPU socket.
1. Unscrew the heatsink screws from the motherboard in the sequence as
shown in the illustration below.
2. Gently wriggle the heatsink to loosen it from the CPU. (Do not use excessive
force when wriggling the heatsink!)
3. Once the heatsink is loosened, remove the heatsink from the CPU socket.
4. Remove the used thermal grease and clean the surface of the CPU and the
heatsink. Reapply the proper amount of thermal grease on the surface before
reinstalling the heatsink.
Loosen screws
in sequence as
shown.
Screw#4
Screw#1
Motherboard
Screw#2
Screw#3
2-12
Page 39
FAN1
T-SGPIO3
USB6/7
2-5 Installing DDR4 Memory
Note: Check the Supermicro website for recommended memory mod-
ules.
CAUTION
Exercise extreme care when installing or removing DIMM
modules to prevent any possible damage.
Chapter 2: Installation
DIMM Installation
1. Insert the desired number of DIMMs
into the memory slots, starting with
DIMMA1 (Channel A, Slot 1, see
the next page for the location). For
the system to work properly, please
use the memory modules of the
same type and speed in the same
motherboard.
2. Push the release tabs outwards on
both ends of the DIMM slot to unlock
it.
3. Align the key of the DIMM mod-
ule with the receptive point on the
memory slot.
4. Align the notches on both ends of
the module against the receptive
points on the ends of the slot.
5. Use two thumbs together to press
the notches on both ends of the
module straight down into the slot
until the module snaps into place.
6. Press the release tabs to the lock
positions to secure the DIMM module
into the slot.
UID
LE1
JUIDB1
VGA
DM1
BIOS
MAC CODE
LICENSE
JBRSET1
SXB1_1
SXB2
BAR CODE
2-3:DISABLE
LAN1
1-2:ENABLE
JPL2
JPL3
LAN2
2-3:DISABLE
1-2:ENABLE
IPMI CODE
JSD2
SATA4
JP4
JPME2
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
2-3:NMI
JWD:Watch Dog
1-2:RST
2-3:BIOS RECOVERY
1-2:NORMAL
JBR1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
I-SATA1
SXB1_2
SXB1_3
I-SATA0
I-SATA3
I-SATA2
JSD1
SATA5
DIMMC1
DIMMC2
JL1
FAN5
FAN6
FAN7
FAN4
USB0/1(3.0)
LAN2
LAN1
LEDM1
JPG1
JPF1
JPG1:VGA
JWD1
JBR1
DIMMD1
DIMMD2
ON:POWER FORCE ON
1-2:ENABLE
JI2C1/2:
I2C BUS FOR PCI-E SLOT
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
JBT1
CHASSIS
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
X10SRW-F
REV:1.01
DESIGNED IN USA
CPU
1
LGA2011-3
1
FAN3
Notches
Release Tabs
Press both notches
straight down into the
memory slot.
JIPMB1
COM1
123
IPMI
4
COM2
JF1
ON
USB2/3
IPMI_LAN
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
JPL1
TPM/PORT80
JI2C2 J29
JTPM1
JI2C1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
DM2
USB4/5
J30
BT1
111
SP1
JPF2
JPF1
USB8(3.0)
J23
INTRUSIONJL1:
DIMMB2
DIMMB1
DIMMA2
JVR1
1
T-SGPIO2
USB9/10
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JOH1
JF1
JPI2C1
JSTBY1
JPWR1
J24
DIMMA1
FAN2
2-13
Page 40
X10SRW-F User’s Manual
Removing Memory Modules
Reverse the steps above to remove the DIMM modules from the motherboard.
Memory Support
DIMMB2
DIMMB1
DIMMA2
DIMMA1
Edge of the motherboard
1
1
DIMMD2
DIMMD1
DIMMC2
DIMMC1
The X10SRW-F supports eight ECC DDR4 RDIMM/LRDIMM/UDIMM at 2400 MHz
(max.) memory (1 DPC) up to 256GB RDIMM, 512GB LRDIMM, or 64GB UDIMM.
Populating these DIMM modules with a pair of memory modules of the same
type and same size will result in interleaved memory, which will improve memory
performance. Please refer to the tables on the next page.
2-14
Page 41
Chapter 2: Installation
Ranks Per
and
Speed (MT/s); Voltage
(DPC)
LRDIMM
3DS
Ranks Per
and
Speed (MT/s); Voltage (V);
Channel (DPC)
Memory Population Guidelines
Please follow the tables below when populating the X10SRW-F.
Populating RDIMM/LRDIMM DDR4 Memory Modules for the E52600v3-based Motherboard
(V);
Slot Per Channel (SPC)
DIMM Capacity
DIMM
Type
Data
Width
RDIMM SRx4 8GB 16GB
RDIMM SRx8 4GB 8GB
RDIMM DRx8 8GB 16GB
RDIMM DRx4 16GB 32GB
LRDIMM QRx4 32GB 64GB
8Rx4 64GB 128GB
†
(GB)
4Gb 8Gb
Populating RDIMM/LRDIMM DDR4 Memory Modules for the E52600v4-based Motherboard
and DIMM Per Channel
1 Slot Per
Channel
1DPC 1DPC 2DPC
1.2V 1.2V 1.2V
2133 2133 1866
2133 2133 1866
2133 2133 1866
2133 2133 1866
2133 2133 2133
2133 2133 2133
2 Slots Per Channel
Slot Per Channel (SPC) and DIMM Per
DIMM Capacity
DIMM
Type
Data
Width
RDIMM SRx48GB 16GB
RDIMM SRx84GB8GB
RDIMM DRx88GB 16GB
RDIMM DRx416GB 32GB
LRDIMM QRx432GB 64GB
LRDIMM
8Rx464GB 128GB
3DS
(GB)
4Gb8Gb
1 Slot Per
Channel
1DPC1DPC2DPC
1.2V1.2V1.2V
240024002133
240024002133
240024002133
240024002133
240024002400
240024002400
2 Slots Per Channel
2-15
Page 42
X10SRW-F User’s Manual
Notes:
• Be sure to use memory modules of the same type, speed, and frequency
on the same motherboard. Mixing of memory modules of different types
and speeds is not allowed.
• Due to memory allocation to system devices, the amount of memory that
remains available for operational use will be reduced when 4 GB of RAM
is used. The reduction in memory availability is disproportional. See the
following table for details.
Possible System Memory Allocation & Availability
System DeviceSizePhysical Memory
Firmware Hub ash memory (System BIOS)1 MB3.99
Local APIC4 KB3.99
Area Reserved for the chipset2 MB3.99
I/O APIC (4 Kbytes)4 KB3.99
PCI Enumeration Area 1256 MB3.76
PCI Express (256 MB)256 MB3.51
PCI Enumeration Area 2 (if needed) -Aligned on 256-MB
boundary-
VGA Memory16 MB2.85
TSEG1 MB2.84
Memory available to OS and other applications 2.84
512 MB3.01
Remaining (-Available)
(4 GB Total System
Memory)
2-16
Page 43
Chapter 2: Installation
USB6/7
F
2-6 Connectors/IO Ports
The I/O ports are color coded in conformance with the industry standards. See the
gure below for the colors and locations of the various I/O ports.
Backplane I/O Panel
SATA4
JP4
MAC CODE
BAR CODE
IPMI CODE
I-SATA1
I-SATA0
JSD2
FAN7
UID
LE1
JUIDB1
VGA
BIOS
LICENSE
SXB1_1
SXB2
2-3:DISABLE
LAN1
1-2:ENABLE
LAN2
2-3:DISABLE
1-2:ENABLE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
SXB1_2
SXB1_3
I-SATA3
I-SATA2
JSD1
SATA5
JL1
FAN5
FAN6
DM1
JBRSET1
JPL2
JPL3
JPME2
JWD1
JBR1
2-3:NMI
JWD:Watch Dog
1-2:RST
2-3:BIOS RECOVERY
1-2:NORMAL
JBT1
JBR1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
DIMMD1
DIMMD2
DIMMC1
DIMMC2
FAN4
LAN2
LEDM1
X10SRW-F
REV:1.01
DESIGNED IN USA
1
LGA2011-3
FAN3
USB0/1(3.0)
LAN1
USB2/3
IPMI_LAN
DM2
JPG1
BT1
JPF1
JPG1:VGA
ON:POWER FORCE ON
1-2:ENABLE
JI2C1/2:
I2C BUS FOR PCI-E SLOT
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
INTRUSIONJL1:
CHASSIS
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
CPU
1
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
FAN2
JIPMB1
COM1
123
IPMI
4
COM2
JF1
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
JPL1
TPM/PORT80
JI2C2J29
JTPM1
JI2C1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
USB4/5
J30
111
SP1
JPF2
JPF1
USB8(3.0)
J23
T-SGPIO3
1
T-SGPIO2
USB9/10
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JOH1
JF1
JPI2C1
JSTBY1
JPWR1
J24
FAN1
B
E
A
C
GH
I
J
D
Backplane I/O Panel
A. COM1F. USB Port 4 (3.0)
B. IPMI LANG. LAN1
C. USB Port 0 (2.0)H. LAN2
D. USB Port 1 (2.0)I. VGA Port
E. USB Port 3 (3.0)J. UID Switch
2-17
Page 44
X10SRW-F User’s Manual
T-SGPIO3
USB6/7
USB4/5
F
Universal Serial Bus (USB)
Four Universal Serial Bus ports (USB 3.0 ports 0/1 and USB 2.0 ports 2/3) are
located on the I/O back panel. In addition, three USB 2.0 headers (USB 4/5, 6/7,
9/10), and two USB 3.0 headers (USB 8 (Type A), USB 11/12) are also located on
the motherboard to provide USB 3.0 support using USB cables (not included). See
the tables below for pin denitions.
Front Panel USB (2.0) 2/3
Pin Denitions
Pin # DenitionPin # Denition
1+5V2+5V
3USB_PN24USB_PN3
5USB_PP26USB_PP3
7Ground8Ground
9Key10Ground
UID
LE1
MAC CODE
BAR CODE
IPMI CODE
JSD2
SATA4
JUIDB1
SXB1_1
I-SATA1
SXB1_2
SXB1_3
I-SATA0
I-SATA3
I-SATA2
JSD1
SATA5
VGA
BIOS
LICENSE
JBRSET1
SXB2
2-3:DISABLE
LAN1
1-2:ENABLE
JPL2
JPL3
LAN2
2-3:DISABLE
1-2:ENABLE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
2-3:NMI
2-3:BIOS RECOVERY
1-2:NORMAL
JBR1
DM1
LAN2
LAN1
LEDM1
JPG1
JBT1
X10SRW-F
REV:1.01
DESIGNED IN USA
1
JPG1:VGA
1-2:ENABLE
2-3:DISABLE
CPU
JPME2
JWD1
JBR1
JWD:Watch Dog
1-2:RST
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
A
USB0/1(3.0)
2-3:DISABLE
1-2:ENABLE
I2C BUS FOR PCI-E SLOT
B
USB2/3
IPMI_LAN
JPL1
DM2
BT1
JPF1
ON:POWER FORCE ON
JI2C1/2:
INTRUSIONJL1:
CHASSIS
USB9/10
JOH1
A. Backpanel USB 3.0 #0/1
B. Backpanel USB 2.0 #2/3
C. Front Panel USB 2.0 #4/5
D. Front Panel USB 2.0 #6/7
E. Front Panel USB 3.0 #8 (Type A)
F. Front Panel USB 2.0 #9/10
G. Front Panel USB 3.0 #11/12
JIPMB1
COM1
123
IPMI
4
COM2
JF1
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
TPM/PORT80
JI2C2J29
JTPM1
JI2C1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
J30
C
111
SP1
JPF2
JPF1
USB8(3.0)
D
J23
1
E
T-SGPIO2
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
G
LE2
JF1
JPI2C1
JSTBY1
LGA2011-3
1
DIMMD1
DIMMD2
DIMMC1
JL1
JP4
FAN5
FAN6
FAN7
DIMMC2
FAN4
FAN3
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
JPWR1
J24
FAN2
FAN1
2-18
Page 45
Chapter 2: Installation
T-SGPIO3
USB6/7
SATA4
Ethernet Ports
Two Gigabit Ethernet ports (LAN1/LAN2)
and an IPMI_LAN port are located on
the I/O Backpanel to provide network
connections. These ports accept RJ45
type cables.
Note: Please refer to the LED
Indicator Section for LAN LED
information.
Serial Ports (COM1/COM2)
Serial port COM1 is located next to USB
0/1 on the I/O backplane. Another Serial
port header (COM2) is located next to
IPMI_LAN on the motherboard. See the
table on the right for pin denitions.
D
C
A
USB0/1(3.0)
LAN1
USB2/3
IPMI_LAN
DM2
JPG1
BT1
JPF1
JPG1:VGA
ON:POWER FORCE ON
1-2:ENABLE
JI2C1/2:
I2C BUS FOR PCI-E SLOT
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
INTRUSIONJL1:
CHASSIS
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
CPU
JIPMB1
COM1
IPMI
COM2
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
JPL1
TPM/PORT80
JI2C2J29
JTPM1
JI2C1
J30
111
SP1
JPF2
JPF1
USB8(3.0)
J23
T-SGPIO2
USB9/10
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JOH1
JF1
JPI2C1
JSTBY1
MAC CODE
BAR CODE
IPMI CODE
JSD2
B
UID
LE1
JUIDB1
VGA
BIOS
LICENSE
SXB1_1
SXB2
2-3:DISABLE
LAN1
1-2:ENABLE
LAN2
2-3:DISABLE
1-2:ENABLE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
2-3:BIOS RECOVERY
I-SATA1
SXB1_2
SXB1_3
I-SATA0
I-SATA3
I-SATA2
JSD1
SATA5
DM1
LAN2
JBRSET1
JPL2
JPL3
2-3:NMI
JWD:Watch Dog
1-2:RST
1-2:NORMAL
JBR1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
LEDM1
JPME2
JWD1
JBR1
JBT1
X10SRW-F
REV:1.01
DESIGNED IN USA
1
LAN Ports
Pin Denition
Pin# Denition
1SGND9TD0+
2TD0+10TD0-
3TD3+11Link 1000 LED
4TD3-12Link 1000 LED
(Green, +3V3SB
(Yellow, +3V3SB)
5TD2+13Act LED
6TD2-14
7TD1+15SGND
8TD1-16SGND
(NC: No Connection)
Serial Ports
Pin Denitions
Pin # DenitionPin # Denition
1DCD6DSR
2RXD7RTS
3TXD8CTS
4DTR9RI
5SGND10SGND
123
4
JF1
ON
E
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
USB4/5
1
A. LAN1
B. LAN2
C. IPIMI_LAN
D. COM1
E. COM2
LGA2011-3
1
JL1
JP4
FAN5
FAN6
FAN7
DIMMD1
DIMMD2
DIMMC1
DIMMC2
FAN4
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
FAN3
JPWR1
J24
FAN2
FAN1
2-19
Page 46
X10SRW-F User’s Manual
T-SGPIO3
USB6/7
USB4/5
Unit Identier Switch/UID LED Indicator
A Unit Identier (UID) switch and an LED
Indicator are located on the motherboard.
The UID switch is located next to the VGA
port on the backplane. The UID LED (LE1)
is located next to the UID switch. When you
press the UID switch, the UID LED will be
turned on. Press the UID switch again to
turn off the LED indicator. The UID Indicator
provides easy identication of a system unit
that may be in need of service.
Note: UID can also be triggered
via IPMI on the motherboard. For
more information on IPMI, please
refer to the IPMI User's Guide
posted on our website @ http://
www.supermicro.com.
VGA Port
The onboard VGA port is located next to
LAN Ports 1/2 on the I/O backpanel. Use
the connection for VGA display.
B
A
UID
LE1
JUIDB1
VGA
DM1
BIOS
LICENSE
JBRSET1
SXB1_1
SXB2
2-3:DISABLE
LAN1
1-2:ENABLE
JPL2
JPL3
LAN2
2-3:DISABLE
1-2:ENABLE
JPME2
JWD1
JBR1
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
2-3:NMI
JWD:Watch Dog
1-2:RST
2-3:BIOS RECOVERY
1-2:NORMAL
JBR1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
SXB1_2
SXB1_3
I-SATA3
I-SATA2
SATA5
USB0/1(3.0)
LAN2
LAN1
USB2/3
IPMI_LAN
LEDM1
JBT1
X10SRW-F
REV:1.01
DESIGNED IN USA
1
DM2
JPG1
BT1
JPF1
JPG1:VGA
ON:POWER FORCE ON
1-2:ENABLE
JI2C1/2:
I2C BUS FOR PCI-E SLOT
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
INTRUSIONJL1:
CHASSIS
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
CPU
JIPMB1
COM1
123
IPMI
4
COM2
JF1
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
JPL1
TPM/PORT80
JI2C2J29
JTPM1
JI2C1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
J30
111
SP1
JPF2
JPF1
USB8(3.0)
J23
1
T-SGPIO2
USB9/10
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JOH1
JF1
JPI2C1
JSTBY1
SATA4
C
MAC CODE
BAR CODE
IPMI CODE
JSD2
I-SATA1
I-SATA0
JSD1
UID Switch
Pin# Denition
1Ground
2Ground
3Button In
4Button In
UID LED
Status
Color/State Status
Blue: On Unit Identied
A. VGA
B. UID Switch
C. UID LED
LGA2011-3
1
DIMMD1
DIMMD2
DIMMC1
JL1
JP4
FAN6
FAN7
DIMMC2
FAN5
FAN4
DIMMB2
DIMMB1
JVR1
FAN3
JPWR1
J24
DIMMA2
DIMMA1
FAN2
FAN1
2-20
Page 47
Chapter 2: Installation
FAN1
1920
Front Control Panel
JF1 contains header pins for various buttons and indicators that are normally located
on a control panel at the front of the chassis. These connectors are designed spe-
cically for use with Supermicro chassis. See the gure below for the descriptions
of the front control panel buttons and LED indicators. Refer to the following section
for descriptions and pin denitions.
OH/Fan Fail LED
UID
LE1
JUIDB1
BIOS
MAC CODE
LICENSE
JBRSET1
SXB1_1
SXB2
BAR CODE
2-3:DISABLE
LAN1
1-2:ENABLE
JPL2
JPL3
LAN2
2-3:DISABLE
1-2:ENABLE
IPMI CODE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
2-3:NMI
JWD:Watch Dog
1-2:RST
2-3:BIOS RECOVERY
1-2:NORMAL
JBR1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA1
S-SATA0
I-SATA1
SXB1_2
SXB1_3
I-SATA0
I-SATA3
I-SATA2
JSD1
JSD2
SATA5
SATA4
JL1
JP4
FAN5
FAN6
FAN7
Ground
Power LED
HDD LED
NIC1 LED
NIC2 LED
PWR Fail LED
Ground
Ground
VGA
DM1
LAN2
LAN1
LEDM1
JPG1
JPME2
S-SATA3
S-SATA2
JPG1:VGA
JWD1
JBR1
1-2:ENABLE
2-3:DISABLE
JBT1
X10SRW-F
REV:1.01
DESIGNED IN USA
CPU
1
LGA2011-3
DIMMD1
DIMMD2
DIMMC1
DIMMC2
FAN4
FAN3
JF1 Header Pins
X
2
1
USB0/1(3.0)
2-3:DISABLE
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
1
JPF1
ON:POWER FORCE ON
JI2C1/2:
I2C BUS FOR PCI-E SLOT
1-2:ENABLE
CHASSIS
DIMMB2
DIMMB1
Reset
PWR
COM1
USB2/3
IPMI_LAN
JPL1
JI2C1
DM2
J30
BT1
JPF2
JPF1
INTRUSIONJL1:
USB9/10
JD1
JOH1
DIMMA2
DIMMA1
JVR1
FAN2
NMI
X
P3V3
UID SW
P3V3_STB
P3V3_STB
UID LED
P3V3
Reset Button
Power Button
JIPMB1
123
IPMI
4
COM2
JF1
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
TPM/PORT80
JI2C2J29
JTPM1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
USB4/5
111
USB6/7
SP1
USB8(3.0)
J23
T-SGPIO3
1
T-SGPIO2
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
LE2
JF1
JPI2C1
JSTBY1
JPWR1
J24
2-21
Page 48
X10SRW-F User’s Manual
1
2
1920
Front Control Panel Pin Denitions
NMI Button
The non-maskable interrupt button
header is located on pins 19 and 20
of JF1. Refer to the table on the right
for pin denitions.
NMI Button
Pin Denitions (JF1)
Pin# Denition
19Control
20Ground
Power LED
The Power LED connection is located
on pins 15 and 16 of JF1. Refer to the
table on the right for pin denitions.
UID
LE1
SATA4
MAC CODE
BAR CODE
IPMI CODE
I-SATA1
I-SATA0
JSD2
JP4
FAN7
JUIDB1
VGA
BIOS
LICENSE
SXB1_1
SXB2
2-3:DISABLE
LAN1
1-2:ENABLE
LAN2
2-3:DISABLE
1-2:ENABLE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
2-3:BIOS RECOVERY
SXB1_2
SXB1_3
I-SATA3
I-SATA2
JSD1
SATA5
DM1
JBRSET1
JPL2
JPL3
JPME2
JWD1
JBR1
2-3:NMI
JWD:Watch Dog
1-2:RST
JBT1
1-2:NORMAL
JBR1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
LAN2
LEDM1
X10SRW-F
REV:1.01
DESIGNED IN USA
CPU
1
USB0/1(3.0)
LAN1
JPG1
JPG1:VGA
1-2:ENABLE
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
LGA2011-3
1
DIMMD1
DIMMD2
DIMMC1
JL1
FAN6
DIMMC2
FAN5
FAN4
FAN3
COM1
COM2
USB2/3
IPMI_LAN
JPL1
JI2C1
DM2
J30
BT1
JPF1
ON:POWER FORCE ON
JI2C1/2:
I2C BUS FOR PCI-E SLOT
JPF2
JPF1
INTRUSIONJL1:
CHASSIS
USB9/10
SPEAKER-PIN 4-7
JD1
JOH1
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
FAN2
Power LED
Pin Denitions (JF1)
Pin# Denition
153.3V
16PWR LED
JIPMB1
123
IPMI
4
JF1
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
TPM/PORT80
JI2C2J29
JTPM1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
USB4/5
111
USB6/7
SP1
USB8(3.0)
J23
T-SGPIO3
1
T-SGPIO2
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
PWR LED-PIN 1-3
LE2
JF1
JPI2C1
JSTBY1
JPWR1
J24
FAN1
A. NMI
B. PWR LED
Ground
Power LED
B
HDD LED
NIC1 LED
NIC2 LED
OH/Fan Fail LED
PWR Fail LED
X
Ground
Ground
NMI
X
P3V3
UID SW
P3V3_STB
P3V3_STB
UID LED
P3V3
Reset
PWR
A
Reset Button
Power Button
2-22
Page 49
Chapter 2: Installation
T-SGPIO3
USB6/7
SATA4
1
2
1920
HDD LED
The HDD LED connection is located
on pins 13 and 14 of JF1. Attach a
cable here to indicate HDD activ-
ity. See the table on the right for pin
HDD LED
Pin Denitions (JF1)
Pin# Denition
13P3V3_STB
14HD Active
denitions.
NIC1/NIC2 LEDs
The NIC (Network Interface Control-
ler) LED connection for GLAN Port 1
is located on pins 11 and 12 of JF1,
and the LED connection for GLAN
Port 2 is on pins 9 and 10. Attach the
NIC LED cables to the LED indicators
mentioned above to display network
GLAN1/2 LED
Pin Denitions (JF1)
Pin# Denition
9P3V3_STB
10NIC 2 Link/Acitivty
LED
11P3V3_STB
12NIC 1 Link/Acitivty
LED
activity. Refer to the layout below for
the locations of NIC LED indicators.
UID
LE1
JUIDB1
VGA
BIOS
MAC CODE
LICENSE
SXB1_1
SXB2
BAR CODE
2-3:DISABLE
LAN1
1-2:ENABLE
LAN2
2-3:DISABLE
1-2:ENABLE
IPMI CODE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
2-3:BIOS RECOVERY
I-SATA1
SXB1_2
SXB1_3
I-SATA0
I-SATA3
I-SATA2
JSD1
JSD2
SATA5
JL1
JP4
FAN5
FAN6
FAN7
DM1
JBRSET1
JPL2
JPL3
JPME2
JWD1
JBR1
2-3:NMI
JWD:Watch Dog
1-2:RST
JBT1
1-2:NORMAL
JBR1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
DIMMD1
DIMMD2
DIMMC1
DIMMC2
FAN4
LAN2
LEDM1
X10SRW-F
REV:1.01
DESIGNED IN USA
1
LGA2011-3
FAN3
USB0/1(3.0)
LAN1
USB2/3
IPMI_LAN
DM2
JPG1
BT1
JPF1
JPG1:VGA
ON:POWER FORCE ON
1-2:ENABLE
JI2C1/2:
I2C BUS FOR PCI-E SLOT
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
INTRUSIONJL1:
CHASSIS
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
CPU
1
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
FAN2
JIPMB1
COM1
123
IPMI
4
COM2
JF1
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
JPL1
TPM/PORT80
JI2C2J29
JTPM1
JI2C1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
USB4/5
J30
111
SP1
JPF2
JPF1
USB8(3.0)
J23
1
T-SGPIO2
USB9/10
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JOH1
JF1
JPI2C1
JSTBY1
JPWR1
J24
FAN1
A. HDD LED
B. NIC1 LED
C. NIC2 LED
Ground
Power LED
HDD LED
A
NIC1 LED
B
NIC2 LED
C
OH/Fan Fail LED
PWR Fail LED
Ground
Ground
NMI
X
X
P3V3
UID SW
P3V3_STB
P3V3_STB
UID LED
P3V3
Reset
Reset Button
Power Button
PWR
2-23
Page 50
X10SRW-F User’s Manual
1
2
1920
FAN1
T-SGPIO3
USB6/7
USB4/5
Overheat (OH)/Fan Fail/PWR Fail/
UID LED
Connect an LED cable to pins 7 and
8 of Front Control Panel to use the
Overheat, Fan Fail, and Power Fail
connections. Refer to the table on the
right for pin denitions.
Power Fail LED
The Power Fail LED connection is
located on pins 5 and 6 of JF1. Re-
fer to the table on the right for pin
denitions.
UID
LE1
SATA4
JP4
MAC CODE
BAR CODE
IPMI CODE
I-SATA1
I-SATA0
JSD2
JUIDB1
VGA
BIOS
LICENSE
SXB1_1
SXB2
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
1-2:ENABLE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
SXB1_2
SXB1_3
I-SATA3
I-SATA2
JSD1
SATA5
JL1
FAN5
FAN6
FAN7
DM1
JBRSET1
LAN1
JPL2
JPL3
LAN2
JPME2
JWD1
JBR1
2-3:NMI
JWD:Watch Dog
1-2:RST
2-3:BIOS RECOVERY
JBT1
1-2:NORMAL
JBR1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
DIMMD1
DIMMD2
DIMMC1
DIMMC2
FAN4
LAN2
LEDM1
X10SRW-F
REV:1.01
DESIGNED IN USA
1
LGA2011-3
FAN3
USB0/1(3.0)
LAN1
JPG1
JPG1:VGA
1-2:ENABLE
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
CPU
1
COM1
COM2
USB2/3
IPMI_LAN
JPL1
JI2C2J29
JI2C1
DM2
J30
BT1
JPF1
ON:POWER FORCE ON
JI2C1/2:
I2C BUS FOR PCI-E SLOT
111
JPF2
JPF1
J23
INTRUSIONJL1:
CHASSIS
USB9/10
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
JOH1
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
FAN2
OH/Fan Fail/ PWR Fail/Blue_UID
LED Pin Denitions (JF1)
Pin# Denition
7 P5V_STB
8 Red_LED-Cathode/OH/Fan Fail/
Power Fail
OH/Fan Fail/PWR Fail
LED Status (Red LED)
State Denition
OffNormal
OnOverheat
Flashing
1 Hz
Flashing
1/4 Hz
Pin Denitions (JF1)
Fan Fail
Redundant
Power
Supply Fail
PWR Fail LED
Pin# Denition
53.3V
6PWR LED Status
JIPMB1
123
IPMI
4
JF1
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
TPM/PORT80
JTPM1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
SP1
USB8(3.0)
1
T-SGPIO2
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
LE2
JF1
JPI2C1
JSTBY1
JPWR1
J24
A.OH/Fan Fail/PWR Fail/UID LED
B. PWR Fail LED
A
OH/Fan Fail LED
PWR Fail LED
B
Ground
X
Power LED
HDD LED
NIC1 LED
NIC2 LED
Ground
Ground
NMI
X
P3V3
UID SW
P3V3_STB
P3V3_STB
UID LED
P3V3
Reset
PWR
Reset Button
Power Button
2-24
Page 51
Chapter 2: Installation
1920
T-SGPIO3
USB6/7
USB4/5
SATA4
Reset Button
The Reset Button connection is located
on pins 3 and 4 of JF1. Attach it to a
hardware reset switch on the computer
case. Refer to the table on the right for
Reset Button
Pin Denitions (JF1)
Pin# Denition
3Reset
4Ground
pin denitions.
Power Button
The Power Button connection is located
on pins 1 and 2 of JF1. Momentarily
contacting both pins will power on/off
the system. This button can also be con-
Power Button
Pin Denitions (JF1)
Pin# Denition
1Signal
2Ground
gured to function as a suspend button
(with a setting in the BIOS - See Chapter
4). To turn off the power when the system
is in suspend mode, press the button for
4 seconds or longer. Refer to the table on
the right for pin denitions.
UID
LE1
JUIDB1
VGA
BIOS
MAC CODE
LICENSE
SXB1_1
SXB2
BAR CODE
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
1-2:ENABLE
IPMI CODE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
I-SATA1
SXB1_2
SXB1_3
I-SATA0
I-SATA3
I-SATA2
JSD1
JSD2
SATA5
JL1
JP4
FAN5
FAN6
FAN7
DM1
JBRSET1
LAN1
JPL2
JPL3
LAN2
JPME2
JWD1
JBR1
2-3:NMI
JWD:Watch Dog
1-2:RST
2-3:BIOS RECOVERY
JBT1
1-2:NORMAL
JBR1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
DIMMD1
DIMMD2
DIMMC1
DIMMC2
FAN4
LAN2
LEDM1
X10SRW-F
REV:1.01
DESIGNED IN USA
1
LGA2011-3
FAN3
USB0/1(3.0)
LAN1
USB2/3
IPMI_LAN
DM2
JPG1
BT1
JPF1
JPG1:VGA
ON:POWER FORCE ON
1-2:ENABLE
JI2C1/2:
I2C BUS FOR PCI-E SLOT
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
INTRUSIONJL1:
CHASSIS
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
CPU
1
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
FAN2
JIPMB1
COM1
123
IPMI
4
COM2
JF1
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
JPL1
TPM/PORT80
JI2C2J29
JTPM1
JI2C1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
J30
111
SP1
JPF2
JPF1
USB8(3.0)
J23
1
T-SGPIO2
USB9/10
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JOH1
JF1
JPI2C1
JSTBY1
Power LED
HDD LED
NIC1 LED
NIC2 LED
OH/Fan Fail LED
PWR Fail LED
JPWR1
J24
FAN1
Ground
X
Ground
Ground
A. Reset Button
B. PWR Button
NMI
X
P3V3
UID SW
P3V3_STB
P3V3_STB
UID LED
P3V3
Reset
Reset Button
Power Button
PWR
2
1
A
B
2-25
Page 52
X10SRW-F User’s Manual
FAN1
2-7 Connecting Cables
This section provides brief descriptions and pin-out denitions for onboard headers
and connectors. Be sure to use the correct cable for each header or connector.
For information on Backpanel USB and Front Panel USB ports, refer to page 2-17.
ATX Main PWR & CPU PWR
Connectors (J24 & JPWR1)
The 24-pin main power connector
(J24) is used to provide power to the
motherboard. The 8-pin CPU PWR
connector (JPWR1) is also required
for the processor. These power
connectors meet the SSI EPS 12V
specication. See the table on the
right for pin denitions.
24-Pin Main PWR
UID
LE1
IPMI CODE
JSD2
SATA4
MAC CODE
BAR CODE
I-SATA1
I-SATA0
JUIDB1
VGA
DM1
BIOS
LICENSE
JBRSET1
SXB1_1
SXB2
2-3:DISABLE
LAN1
1-2:ENABLE
JPL2
JPL3
LAN2
2-3:DISABLE
1-2:ENABLE
JPME2
JWD1
JBR1
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
2-3:NMI
JWD:Watch Dog
1-2:RST
JBT1
2-3:BIOS RECOVERY
1-2:NORMAL
JBR1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
SXB1_2
SXB1_3
I-SATA3
I-SATA2
JSD1
SATA5
LAN2
LEDM1
X10SRW-F
REV:1.01
DESIGNED IN USA
CPU
1
USB0/1(3.0)
LAN1
JPG1
JPG1:VGA
1-2:ENABLE
2-3:DISABLE
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
COM1
IPMI
COM2
USB2/3
IPMI_LAN
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
JPL1
TPM/PORT80
JI2C2J29
JTPM1
JI2C1
DM2
J30
BT1
JPF1
ON:POWER FORCE ON
JI2C1/2:
I2C BUS FOR PCI-E SLOT
2-3:DISABLE
1-2:ENABLE
111
SP1
JPF2
JPF1
USB8(3.0)
J23
INTRUSIONJL1:
CHASSIS
T-SGPIO2
USB9/10
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JOH1
JF1
JPI2C1
JSTBY1
ATX Power 24-pin Connector
Pin Denitions (JPW1)
Pin# Denition Pin # Denition
13+3.3V1+3.3V
14-12V2+3.3V
15GND3GND
16PS_ON4+5V
17GND5GND
18GND6+5V
19GND7GND
20Res (NC)8PWR_OK
21+5V95VSB
22+5V10+12V
23+5V11+12V
24GND12+3.3V
12V 8-pin Power Connec-
tor Pin Denitions
JIPMB1
123
4
JF1
ON
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
USB4/5
USB6/7
T-SGPIO3
1
Pins Denition
1 through 4Ground
5 through 8+12V
(Required)
A. 24-Pin ATX Main PWR
B. 8-Pin PWR
LGA2011-3
1
DIMMD1
DIMMD2
DIMMC1
JL1
JP4
FAN6
FAN7
DIMMC2
FAN5
FAN4
DIMMB2
DIMMB1
DIMMA2
JVR1
FAN3
JPWR1
B
J24
DIMMA1
A
FAN2
2-26
Page 53
Chapter 2: Installation
F
Fan Headers (Fan 1-2, Fan 4-7)
The X10SRW-F has six fan headers (Fan 1-2,
Fan 4-7). These fans are 4-pin fan headers.
Although pins 1-3 of the onboard fan headers
are backward compatible with the traditional
3-pin fans, we recommend that you use 4-pin
fans to take advantage of the fan speed control
via IPMI interface. This allows the fan speeds
to be automatically adjusted based on the moth-
erboard temperature. Refer to the table on the
right for pin denitions.
Chassis Intrusion (JL1)
A Chassis Intrusion header is located at JL1 on
the motherboard. Attach the appropriate cable
from the chassis to inform you of a chassis intru-
sion when the chassis is opened.
JIPMB1
COM1
123
IPMI
4
COM2
JF1
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
JPL1
TPM/PORT80
JI2C2J29
JTPM1
JI2C1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
USB4/5
J30
111
USB6/7
SP1
JPF2
JPF1
USB8(3.0)
J23
T-SGPIO3
1
T-SGPIO2
USB9/10
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JOH1
JF1
JPI2C1
JSTBY1
MAC CODE
BAR CODE
IPMI CODE
JSD2
SATA4
UID
LE1
JUIDB1
SXB1_1
I-SATA1
SXB1_2
SXB1_3
I-SATA0
I-SATA3
I-SATA2
JSD1
SATA5
VGA
BIOS
LICENSE
JBRSET1
SXB2
2-3:DISABLE
LAN1
1-2:ENABLE
JPL2
JPL3
LAN2
2-3:DISABLE
1-2:ENABLE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
2-3:NMI
2-3:BIOS RECOVERY
1-2:NORMAL
JBR1
DM1
JPME2
JWD1
JBR1
JWD:Watch Dog
1-2:RST
JBT1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
LAN2
LEDM1
X10SRW-F
REV:1.01
DESIGNED IN USA
CPU
1
USB0/1(3.0)
LAN1
USB2/3
IPMI_LAN
DM2
JPG1
BT1
JPF1
JPG1:VGA
ON:POWER FORCE ON
1-2:ENABLE
JI2C1/2:
I2C BUS FOR PCI-E SLOT
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
INTRUSIONJL1:
CHASSIS
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
Fan Header
Pin Denitions
Pin# Denition
1Ground (Black)
22.5A/+12V
(Red)
3Tachometer
4PWM_Control
Chassis Intrusion
Pin Denitions (JL1)
Pin# Denition
1Intrusion Input
2Ground
A. Fan 1
B. Fan 2
C. Fan 4
D. Fan 5
E. Fan 6
F. Fan 7
G. Chassis Intrusion
LGA2011-3
1
G
JL1
JP4
FAN5
FAN6
FAN7
E
D
DIMMD1
DIMMD2
DIMMC1
DIMMC2
FAN4
FAN3
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
C
JPWR1
J24
FAN2
FAN1
B
A
2-27
Page 54
X10SRW-F User’s Manual
T-SGPIO3
USB6/7
Internal Speaker/Buzzer (SP1)
The Internal Speaker/Buzzer (SP1) is
used to provide audible indications for
various beep codes. See the table on
the right for pin denitions.
UID
LE1
MAC CODE
BAR CODE
IPMI CODE
I-SATA1
I-SATA0
JSD2
SATA4
JUIDB1
BIOS
LICENSE
SXB1_1
SXB2
2-3:DISABLE
LAN1
1-2:ENABLE
LAN2
2-3:DISABLE
1-2:ENABLE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
SXB1_2
SXB1_3
I-SATA3
I-SATA2
JSD1
SATA5
JBRSET1
JPL2
JPL3
2-3:BIOS RECOVERY
1-2:NORMAL
VGA
DM1
LAN1
JPG1
JPG1:VGA
1-2:ENABLE
2-3:DISABLE
X10SRW-F
REV: 1.01
DESIGNED IN USA
CPU
USB0/1(3.0)
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
2-3:DISABLE
JI2C1/2:
I2C BUS FOR PCI-E SLOT
1-2:ENABLE
JPF1
ON:POWER FORCE ON
CHASSIS
LAN2
LEDM1
JPME2
JWD1
JBR1
2-3:NMI
JWD:Watch Dog
1-2:RST
JBR1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
JBT1
1
Internal Buzzer
Pin Denition
Pin# Denitions
Pin 1Pos. (+) Beep In
Pin 2Neg. (-)Alarm
JIPMB1
COM1
123
IPMI
4
COM2
JF1
USB2/3
IPMI_LAN
JPL1
DM2
BT1
A
INTRUSIONJL1:
USB9/10
JOH1
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
TPM/PORT80
JI2C2J29
JTPM1
JI2C1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
USB4/5
J30
111
SP1
JPF2
JPF1
USB8(3.0)
J23
1
T-SGPIO2
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JF1
JPI2C1
JSTBY1
Speaker
A. Internal Buzzer
LGA2011-3
DIMMD1
DIMMD2
DIMMC1
DIMMC2
JL1
JP4
FAN5
FAN6
FAN7
FAN4
1
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
FAN3
FAN2
JPWR1
J24
FAN1
2-28
Page 55
Chapter 2: Installation
T-SGPIO3
USB6/7
DOM PWR Connector (JSD1)
The Disk-On-Module (DOM) power
connectors, located at JSD1 and
JSD2, provide 5V power to a solid
state DOM storage device connected
to one of the SATA ports. See the table
on the right for pin denitions.
Standby Power
The Standby Power header is located
at JSTBY1 on the motherboard. See
the layout below for the location.
UID
LE1
JUIDB1
MAC CODE
SXB1_1
BAR CODE
IPMI CODE
I-SATA1
SXB1_2
SXB1_3
I-SATA0
I-SATA3
I-SATA2
JSD1
JSD2
B
SATA5
SATA4
VGA
BIOS
LICENSE
JBRSET1
SXB2
2-3:DISABLE
LAN1
1-2:ENABLE
JPL2
JPL3
LAN2
2-3:DISABLE
1-2:ENABLE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
2-3:NMI
2-3:BIOS RECOVERY
1-2:NORMAL
JBR1
DM1
JPME2
JWD1
JBR1
JWD:Watch Dog
1-2:RST
JBT1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
A
LAN2
LEDM1
X10SRW-F
REV:1.01
DESIGNED IN USA
CPU
1
USB0/1(3.0)
LAN1
JPG1
JPF1
JPG1:VGA
ON:POWER FORCE ON
1-2:ENABLE
JI2C1/2:
I2C BUS FOR PCI-E SLOT
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
CHASSIS
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
DOM PWR
Pin Denitions
Pin# Denition
15V
2Ground
3Ground
Standby Power
Pin Denitions
Pin# Denition
1+5V Standby
2Ground
3No Connection
JIPMB1
COM1
123
IPMI
4
COM2
JF1
USB2/3
IPMI_LAN
DM2
BT1
INTRUSIONJL1:
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
JPL1
TPM/PORT80
JI2C2J29
JTPM1
JI2C1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
USB4/5
J30
111
SP1
JPF2
JPF1
USB8(3.0)
J23
1
T-SGPIO2
USB9/10
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JOH1
JF1
JPI2C1
JSTBY1
C
A. DOM PWR 1
B. DOM PWR 2
C. Standby PWR
LGA2011-3
1
DIMMD1
DIMMD2
DIMMC1
JL1
JP4
FAN5
FAN6
FAN7
DIMMC2
FAN4
FAN3
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
JPWR1
J24
FAN2
FAN1
2-29
Page 56
X10SRW-F User’s Manual
T-SGPIO 1/2/3 Headers
Three Serial-Link General Purpose Input/
Output headers (T-SGPIO 1/2/3) are
located on the motherboard. T-SGPIO
1/2/3 support onboard SATA interface.
See the table on the right for pin deni-
tions.
Power SMB (I2C) Connector
Power System Management Bus (I2C)
Connector (JPI2C1) monitors power sup-
ply, fan and system temperatures. See
the table on the right for pin denitions.
UID
LE1
MAC CODE
BAR CODE
IPMI CODE
JSD2
SATA4
JUIDB1
SXB1_1
I-SATA1
SXB1_2
SXB1_3
I-SATA0
I-SATA3
I-SATA2
JSD1
SATA5
VGA
BIOS
LICENSE
JBRSET1
SXB2
2-3:DISABLE
LAN1
1-2:ENABLE
JPL2
JPL3
LAN2
2-3:DISABLE
1-2:ENABLE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
2-3:NMI
2-3:BIOS RECOVERY
1-2:NORMAL
JBR1
DM1
JPME2
JWD1
JBR1
JWD:Watch Dog
1-2:RST
JBT1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
LAN2
LEDM1
X10SRW-F
REV:1.01
DESIGNED IN USA
CPU
1
USB0/1(3.0)
LAN1
JPG1
JPG1:VGA
1-2:ENABLE
JI2C1/2:
I2C BUS FOR PCI-E SLOT
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
COM1
USB2/3
IPMI_LAN
JPL1
JI2C1
DM2
J30
BT1
JPF1
ON:POWER FORCE ON
JPF2
JPF1
INTRUSIONJL1:
CHASSIS
USB9/10
JD1
JOH1
T-SGPIO/6-SGPIO
Pin Denitions
Pin# Denition Pin# Denition
2NC1NC
4Data3Ground
6Ground5Load
8NC7Clock
Note: NC= No Connection
Pin# Denition
1Clock
2Data
3PWR Fail
4Ground
5+3.3V
JIPMB1
123
IPMI
4
COM2
JF1
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
TPM/PORT80
JI2C2J29
JTPM1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
USB4/5
111
USB6/7
SP1
USB8(3.0)
J23
T-SGPIO3
1
C
T-SGPIO2
B
T-SGPIO1
JUSB3-1A
A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
LE2
JF1
JPI2C1
JSTBY1
D
PWR SMB
Pin Denitions
A. T-SGPIO 1
B. T-SGPIO 2
C. T-SGPIO 3
D. SMB Connector
LGA2011-3
1
DIMMD1
DIMMD2
DIMMC1
JL1
JP4
FAN5
FAN6
FAN7
DIMMC2
FAN4
FAN3
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
JPWR1
J24
FAN2
FAN1
2-30
Page 57
Chapter 2: Installation
T-SGPIO3
USB6/7
USB4/5
TPM Header/Port 80 Header
A Trusted Platform Module/Port 80
header is located at JTPM1 to provide
TPM support and Port 80 connection.
Use this header to enhance system
performance and data security. See
the table on the right for pin deni-
tions.
UID
LE1
MAC CODE
BAR CODE
IPMI CODE
JSD2
SATA4
JUIDB1
SXB1_1
I-SATA1
SXB1_2
SXB1_3
I-SATA0
I-SATA3
I-SATA2
JSD1
SATA5
VGA
BIOS
LICENSE
JBRSET1
SXB2
2-3:DISABLE
LAN1
1-2:ENABLE
JPL2
JPL3
LAN2
2-3:DISABLE
1-2:ENABLE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
2-3:NMI
2-3:BIOS RECOVERY
1-2:NORMAL
JBR1
DM1
JPME2
JWD1
JBR1
JWD:Watch Dog
1-2:RST
JBT1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
LAN2
LEDM1
X10SRW-F
REV:1.01
DESIGNED IN USA
CPU
1
USB0/1(3.0)
LAN1
USB2/3
IPMI_LAN
DM2
JPG1
BT1
JPF1
JPG1:VGA
ON:POWER FORCE ON
1-2:ENABLE
JI2C1/2:
I2C BUS FOR PCI-E SLOT
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
INTRUSIONJL1:
CHASSIS
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
TPM/Port 80 Header
Pin Denitions
Pin # DenitionPin # Denition
1LCLK2GND
3LFRAME#4<(KEY)>
5LRESET#6+5V (X)
7LAD 38LAD 2
9+3.3V10LAD1
11LAD012GND
13SMB_CLK414SMB_DAT
15+3V_STB16SERIRQ
17GND18CLKRUN#
19LPCPD#20LDRQ# (X)
JIPMB1
COM1
123
IPMI
4
COM2
JF1
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
JPL1
TPM/PORT80
JI2C2J29
JTPM1
JI2C1
LEDLED12LEDFAIL
A
NMIXPWRHDDNICNICUIDPSRSTPWR
J30
111
SP1
JPF2
JPF1
USB8(3.0)
J23
1
T-SGPIO2
USB9/10
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JOH1
JF1
JPI2C1
JSTBY1
A. TPM/Port 80
LGA2011-3
1
DIMMD1
DIMMD2
DIMMC1
JL1
JP4
FAN5
FAN6
FAN7
DIMMC2
FAN4
FAN3
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
JPWR1
J24
FAN2
FAN1
2-31
Page 58
X10SRW-F User’s Manual
FAN1
T-SGPIO3
USB6/7
USB4/5
2-8 Jumper Settings
Explanation of Jumpers
To modify the operation of the mother-
board, jumpers can be used to choose
between optional settings. Jumpers create
shorts between two pins to change the
function of the connector. Pin 1 is identied
with a square solder pad on the printed
circuit board.
Note: On two-pin jumpers,
"Closed" means the jumper is on,
and "Open" means the jumper is
off the pins.
LAN1/LAN2 Enable/Disable
Jumpers JPL1/JPL2 enable or disable
LAN ports 1/2 on the motherboard. See
the table on the right for jumper settings.
The default setting is enabled.
JIPMB1
COM1
123
IPMI
4
COM2
JF1
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
JPL1
TPM/PORT80
JI2C2J29
JTPM1
JI2C1
LEDLED12LEDFAIL
A
NMIXPWRHDDNICNICUIDPSRSTPWR
J30
111
SP1
JPF2
JPF1
USB8(3.0)
J23
1
T-SGPIO2
USB9/10
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JOH1
JF1
JPI2C1
JSTBY1
JPWR1
J24
FAN2
SATA4
MAC CODE
IPMI CODE
JSD2
JP4
BAR CODE
I-SATA1
UID
LE1
JUIDB1
VGA
DM1
BIOS
LICENSE
JBRSET1
SXB1_1
SXB2
2-3:DISABLE
LAN1
1-2:ENABLE
JPL2
B
JPL3
LAN2
2-3:DISABLE
1-2:ENABLE
JPME2
JWD1
JBR1
C
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
2-3:NMI
JWD:Watch Dog
1-2:RST
JBT1
2-3:BIOS RECOVERY
1-2:NORMAL
JBR1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
SXB1_2
SXB1_3
I-SATA0
I-SATA3
I-SATA2
JSD1
SATA5
DIMMD1
DIMMD2
DIMMC1
JL1
FAN6
FAN7
DIMMC2
FAN5
FAN4
LAN2
LEDM1
X10SRW-F
REV:1.01
DESIGNED IN USA
1
LGA2011-3
FAN3
USB0/1(3.0)
LAN1
USB2/3
IPMI_LAN
DM2
JPG1
BT1
JPF1
JPG1:VGA
ON:POWER FORCE ON
1-2:ENABLE
JI2C1/2:
I2C BUS FOR PCI-E SLOT
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
INTRUSIONJL1:
CHASSIS
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
CPU
1
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
GLAN Enable
Jumper Settings
Pin# Denition
1-2Enabled (default)
2-3Disabled
A. JPL1: LAN Enable
B. JPL2: LAN1 Enable
C. JPL3: LAN2 Enable
2-32
Page 59
Chapter 2: Installation
T-SGPIO3
USB6/7
USB4/5
CMOS Clear (JBT1)
JBT1 is used to clear the saved system setup conguration stored in the CMOS
chip. To clear the contents of the CMOS, completely shut down the system, remove
the AC power cord and then short JBT1 with a jumper. Remove the jumper before
powering on the system again. This will erase all user settings and revert everything
to their factory-set defaults.
PCI-E Slot SMB Enable (I2C1/I2C2)
Use Jumpers I2C1/I2C2 to enable PCI-E
SMB (System Management Bus) support
to improve system management for the
PCI-E slots. See the table on the right
for jumper settings.
UID
LE1
MAC CODE
BAR CODE
IPMI CODE
JSD2
SATA4
JUIDB1
SXB1_1
I-SATA1
SXB1_2
SXB1_3
I-SATA0
I-SATA3
I-SATA2
JSD1
SATA5
VGA
BIOS
LICENSE
JBRSET1
SXB2
2-3:DISABLE
LAN1
1-2:ENABLE
JPL2
JPL3
LAN2
2-3:DISABLE
1-2:ENABLE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
2-3:NMI
2-3:BIOS RECOVERY
1-2:NORMAL
JBR1
DM1
JPME2
JWD1
JBR1
JWD:Watch Dog
1-2:RST
JBT1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
LAN2
LEDM1
A
X10SRW-F
REV:1.01
DESIGNED IN USA
CPU
1
USB0/1(3.0)
LAN1
USB2/3
IPMI_LAN
B
JPL1
DM2
JPG1
BT1
JPF1
JPG1:VGA
ON:POWER FORCE ON
1-2:ENABLE
JI2C1/2:
I2C BUS FOR PCI-E SLOT
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
INTRUSIONJL1:
CHASSIS
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
USB9/10
JOH1
PCI-E Slot_SMB Enable
Jumper Settings
Jumper Setting Denition
1-2Enabled
2-3Disabled
JIPMB1
COM1
123
IPMI
4
COM2
JF1
ON
C
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
TPM/PORT80
JI2C2J29
JTPM1
JI2C1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
J30
111
SP1
JPF2
JPF1
USB8(3.0)
J23
1
T-SGPIO2
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JF1
JPI2C1
JSTBY1
(Default)
A. Clear CMOS
2
B. JI
C1
2
C. JI
C2
LGA2011-3
1
DIMMD1
DIMMD2
DIMMC1
JL1
JP4
FAN5
FAN6
FAN7
DIMMC2
FAN4
FAN3
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
JPWR1
J24
FAN2
FAN1
2-33
Page 60
X10SRW-F User’s Manual
VGA Enable
Jumper JPG1 allows the user to enable
the onboard VGA connector. The default
setting is 1-2 to enable the connection.
See the table on the right for jumper
settings.
UID
LE1
MAC CODE
BAR CODE
IPMI CODE
JSD2
SATA4
JUIDB1
SXB1_1
I-SATA1
SXB1_2
SXB1_3
I-SATA0
I-SATA3
I-SATA2
JSD1
SATA5
VGA
BIOS
LICENSE
JBRSET1
SXB2
2-3:DISABLE
LAN1
1-2:ENABLE
JPL2
JPL3
LAN2
2-3:DISABLE
1-2:ENABLE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
2-3:BIOS RECOVERY
1-2:NORMAL
DM1
JPME2
JWD1
JBR1
2-3:NMI
JWD:Watch Dog
1-2:RST
JBR1
JBT1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
LAN2
A
LEDM1
X10SRW-F
REV:1.01
DESIGNED IN USA
CPU
1
USB0/1(3.0)
LAN1
USB2/3
IPMI_LAN
DM2
JPG1
BT1
JPF1
JPG1:VGA
ON:POWER FORCE ON
1-2:ENABLE
JI2C1/2:
I2C BUS FOR PCI-E SLOT
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
INTRUSIONJL1:
CHASSIS
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
USB9/10
VGA Enable
Jumper Settings
Jumper Setting Denition
1-2Enabled (Default)
2-3Disabled
JIPMB1
COM1
123
IPMI
4
COM2
JF1
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
JPL1
TPM/PORT80
JI2C2J29
JTPM1
JI2C1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
USB4/5
J30
111
USB6/7
SP1
JPF2
JPF1
USB8(3.0)
J23
T-SGPIO3
1
T-SGPIO2
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JOH1
JF1
JPI2C1
JSTBY1
A. VGA Enable
LGA2011-3
1
DIMMD1
DIMMD2
DIMMC1
JL1
JP4
FAN5
FAN6
FAN7
DIMMC2
FAN4
FAN3
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
JPWR1
J24
FAN2
FAN1
2-34
Page 61
Chapter 2: Installation
USB6/7
Watch Dog Enable/Disable
Watch Dog (JWD1) is a system moni-
tor that can reboot the system when a
software application hangs. Close pins
1-2 to reset the system if an applica-
tion hangs. Close pins 2-3 to generate a
non-maskable interrupt signal for the ap-
plication that hangs. See the table on the
right for jumper settings. Watch Dog must
also be enabled in the BIOS.
UID
LE1
MAC CODE
BAR CODE
IPMI CODE
JSD2
SATA4
JUIDB1
BIOS
LICENSE
SXB1_1
SXB2
2-3:DISABLE
LAN1
1-2:ENABLE
LAN2
2-3:DISABLE
1-2:ENABLE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
I-SATA1
SXB1_2
SXB1_3
I-SATA0
I-SATA3
I-SATA2
JSD1
SATA5
JBRSET1
JPL2
JPL3
2-3:BIOS RECOVERY
1-2:NORMAL
VGA
DM1
LAN1
JPG1
JPG1:VGA
1-2:ENABLE
2-3:DISABLE
X10SRW-F
REV: 1.01
DESIGNED IN USA
CPU
USB0/1(3.0)
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
2-3:DISABLE
1-2:ENABLE
JI2C1/2:
I2C BUS FOR PCI-E SLOT
JPF1
ON:POWER FORCE ON
CHASSIS
USB2/3
IPMI_LAN
DM2
BT1
INTRUSIONJL1:
LAN2
LEDM1
A
JPME2
JWD1
JBR1
2-3:NMI
JWD:Watch Dog
1-2:RST
JBR1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
JBT1
1
Watch Dog
Jumper Settings
Jumper Setting Denition
Pins 1-2Reset (default)
Pins 2-3NMI
OpenDisabled
A. Watch Dog Enable
JIPMB1
COM1
123
IPMI
4
COM2
JF1
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
JPL1
TPM/PORT80
JI2C2J29
JTPM1
JI2C1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
USB4/5
J30
111
SP1
JPF2
JPF1
USB8(3.0)
J23
T-SGPIO3
1
T-SGPIO2
USB9/10
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JOH1
JF1
JPI2C1
JSTBY1
LGA2011-3
DIMMD1
DIMMD2
DIMMC1
DIMMC2
JL1
JP4
FAN5
FAN6
FAN7
FAN4
1
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
FAN3
FAN2
JPWR1
J24
FAN1
2-35
Page 62
X10SRW-F User’s Manual
FAN1
T-SGPIO3
USB6/7
USB4/5
LAN 1/LAN 2
2-9 Onboard Indicators
LAN 1/LAN 2 LEDs
Two LAN ports (LAN 1/LAN 2) are located
on the I/O backplane of the motherboard.
Each Ethernet LAN port has two LEDs.
The yellow LED indicates activity, while the
Link LED may be green, amber, or off to
indicate the speed of the connections. See
the tables on the right for more information.
IPMI Dedicated LAN LEDs
In addition to the Gigabit Ethernet ports,
an IPMI Dedicated LAN is also located
above the Backplane USB ports 0/1 on the
motherboard. The yellow LED on the right
indicates activity, while the green/amber
LED on the left indicates the speed of the
connection. See the table on the right for
more information.
B
USB0/1(3.0)
LAN1
JPG1
JPG1:VGA
1-2:ENABLE
2-3:DISABLE
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
CPU
COM1
USB2/3
IPMI_LAN
JPL1
DM2
BT1
JPF1
ON:POWER FORCE ON
JI2C1/2:
I2C BUS FOR PCI-E SLOT
2-3:DISABLE
1-2:ENABLE
JPF2
INTRUSIONJL1:
CHASSIS
USB9/10
JOH1
SATA4
MAC CODE
BAR CODE
IPMI CODE
JSD2
A
UID
LE1
JUIDB1
VGA
DM1
BIOS
LICENSE
JBRSET1
SXB1_1
SXB2
2-3:DISABLE
LAN1
1-2:ENABLE
JPL2
JPL3
LAN2
2-3:DISABLE
1-2:ENABLE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
2-3:NMI
JWD:Watch Dog
1-2:RST
2-3:BIOS RECOVERY
1-2:NORMAL
JBR1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
I-SATA1
SXB1_2
SXB1_3
I-SATA0
I-SATA3
I-SATA2
JSD1
SATA5
LAN2
LEDM1
JPME2
JWD1
JBR1
JBT1
X10SRW-F
REV:1.01
DESIGNED IN USA
1
LAN1/LAN2
Link LED
GLAN 1/2 Activity Indicator
LED Settings
Activity LED
Color Status Denition
YellowFlashingActive
GLAN Ports 1/2 Link Indicator
LED Settings
LED Color Denition
OffNo Connection/10 Mbps/
Green100 Mbps
Amber1 Gbps
IPMI LAN
Link LED
IPMI LAN Link LED (Left) &
Activity LED (Right)
Activity LED
Color/State Denition
Link (Left)Amber: Solid1 Gbps
Green: Solid100 Mbps
Activity (Right) Yellow: Blinking Active
JIPMB1
123
IPMI
4
COM2
JF1
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
TPM/PORT80
JI2C2J29
JTPM1
JI2C1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
J30
111
SP1
JPF1
USB8(3.0)
J23
1
T-SGPIO2
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JF1
JPI2C1
JSTBY1
A. LAN 1/2 LEDs
B. IPMI_LAN LED
LGA2011-3
1
DIMMD1
DIMMD2
DIMMC1
JL1
JP4
FAN6
FAN7
DIMMC2
FAN5
FAN4
DIMMB2
DIMMB1
DIMMA2
JVR1
FAN3
JPWR1
J24
DIMMA1
FAN2
2-36
Page 63
Chapter 2: Installation
FAN1
T-SGPIO3
USB6/7
BMC Heartbeat LED (LEDM1)
A BMC Hear tbeat LED is located at
LEDM1 on the X10SRW-F. See the table
on the right for more information.
Unit Identication LED (LE1)
A rear UID LED indicator (LE1) is located
next to the I/O backplane. This UID Indicator
provides easy identication of a system unit
that may be in need of service.
Note: UID can also be triggered via
IPMI on the motherboard. For more
information on IPMI, please refer to
the IPMI User's Guide posted on
our website @ http://www.super-
micro.com.
B
UID
LE1
SATA4
MAC CODE
BAR CODE
IPMI CODE
JSD2
JUIDB1
SXB1_1
I-SATA1
SXB1_2
SXB1_3
I-SATA0
I-SATA3
I-SATA2
JSD1
SATA5
VGA
BIOS
LICENSE
JBRSET1
SXB2
2-3:DISABLE
LAN1
1-2:ENABLE
JPL2
JPL3
LAN2
2-3:DISABLE
1-2:ENABLE
1-2:NORMAL
JPME2:
2-3:ME MANUFACTURE MODE
2-3:BIOS RECOVERY
1-2:NORMAL
JBR1
DM1
JPME2
JWD1
JBR1
2-3:NMI
JWD:Watch Dog
1-2:RST
JBT1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA3
S-SATA1
S-SATA2
S-SATA0
LAN2
A
LEDM1
X10SRW-F
REV:1.01
DESIGNED IN USA
CPU
1
USB0/1(3.0)
LAN1
JPG1
JPG1:VGA
1-2:ENABLE
JI2C1/2:
I2C BUS FOR PCI-E SLOT
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
COM1
COM2
USB2/3
IPMI_LAN
DM2
BT1
JPF1
ON:POWER FORCE ON
INTRUSIONJL1:
CHASSIS
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
JPL1
TPM/PORT80
JI2C2J29
JI2C1
J30
111
SP1
JPF2
JPF1
USB8(3.0)
J23
T-SGPIO2
USB9/10
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JOH1
JF1
JSTBY1
BMC Heartbeat LED
Status
Color/State Denition
Green:
Blinking
BMC: Normal
UID LED Status
Color/State OS Status
Blue: On Windows OS Unit Identied
JIPMB1
123
IPMI
4
JF1
ON
JTPM1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
USB4/5
1
JPI2C1
A. BMC Heartbeat LED
B. UID LED
LGA2011-3
1
DIMMD1
DIMMD2
DIMMC1
JL1
JP4
FAN5
FAN6
FAN7
DIMMC2
FAN4
FAN3
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
JPWR1
J24
FAN2
2-37
Page 64
X10SRW-F User’s Manual
FAN1
Onboard Power LED (LE2)
An Onboard Power LED is located
at LE2 on the motherboard. When
LE2 is on, the AC power cable is
connected. Make sure to disconnect
the power cable before removing or
installing any component. See the
layout below for the LED location.
UID
LE1
MAC CODE
BAR CODE
IPMI CODE
JSD2
SATA4
JUIDB1
SXB1_1
SXB2
1-2:NORMAL
2-3:ME MANUFACTURE MODE
I-SATA1
SXB1_2
SXB1_3
I-SATA0
I-SATA3
I-SATA2
JSD1
SATA5
2-3:DISABLE
2-3:DISABLE
JPME2:
BIOS
LICENSE
1-2:ENABLE
LAN2
1-2:ENABLE
LAN1
2-3:BIOS RECOVERY
JBRSET1
JPL2
JPL3
2-3:NMI
1-2:NORMAL
JBR1
VGA
DM1
JPME2
JWD1
JBR1
JWD:Watch Dog
1-2:RST
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA1
S-SATA0
JBT1
S-SATA3
S-SATA2
LAN2
LEDM1
X10SRW-F
REV:1.01
DESIGNED IN USA
CPU
1
USB0/1(3.0)
LAN1
JPG1
JPF1
JPG1:VGA
ON:POWER FORCE ON
1-2:ENABLE
JI2C1/2:
I2C BUS FOR PCI-E SLOT
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
INTRUSIONJL1:
CHASSIS
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
Onboard PWR LED Indicator
LED Status
Color/Status Denition
OffSystem Off
Grenn: OnSystem on
A. Onboard Power LED
JIPMB1
COM1
123
IPMI
4
COM2
JF1
USB2/3
IPMI_LAN
DM2
BT1
USB9/10
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
JPL1
TPM/PORT80
JI2C2J29
JTPM1
JI2C1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
USB4/5
J30
111
USB6/7
SP1
JPF2
JPF1
USB8(3.0)
J23
T-SGPIO3
1
T-SGPIO2
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JOH1
JF1
A
JPI2C1
JSTBY1
LGA2011-3
DIMMD1
DIMMD2
DIMMC1
DIMMC2
JL1
JP4
FAN5
FAN6
FAN7
FAN4
1
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
FAN3
JPWR1
J24
FAN2
2-38
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SATA4
2-10 SATA Connections
F
Chapter 2: Installation
SATA/SAS Connections
Ten SATA 3.0 connectors (I-SATA 0-5) and (S-
SATA 0-3) are located on the board. I-SATA 0-5
are supported by the AHCI controller and are
compatible with RAID 0, 1, 5, 10. S-SATA 0-3
are supported by the sSATA controller and are
compatible with RAID 0, 1, 10. These Serial Link
connections provide faster data transmission than
legacy Parallel ATA. See the table on the right for
pin denitions.
UID
LE1
JUIDB1
MAC CODE
SXB1_1
SXB2
BAR CODE
IPMI CODE
1-2:NORMAL
2-3:ME MANUFACTURE MODE
I-SATA1
A
B
C
E
SXB1_2
SXB1_3
I-SATA0
I-SATA3
I-SATA2
JSD1
JSD2
SATA5
2-3:DISABLE
2-3:DISABLE
JPME2:
D
BIOS
LICENSE
LAN1
1-2:ENABLE
LAN2
1-2:ENABLE
JBRSET1
JPL2
JPL3
2-3:BIOS RECOVERY
1-2:NORMAL
VGA
DM1
JPME2
JWD1
JBR1
2-3:NMI
JWD:Watch Dog
1-2:RST
JBR1
JPB1
1-2:ENABLE
JPB1:BMC
2-3:DISABLE
S-SATA1
S-SATA0
JBT1
S-SATA3
J
H
S-SATA2
G
I
LAN2
LEDM1
X10SRW-F
REV:1.01
DESIGNED IN USA
CPU
1
USB0/1(3.0)
LAN1
JPG1
USB2/3
IPMI_LAN
JPL1
DM2
BT1
JPF1
JPG1:VGA
ON:POWER FORCE ON
1-2:ENABLE
JI2C1/2:
I2C BUS FOR PCI-E SLOT
2-3:DISABLE
1-2:ENABLE
2-3:DISABLE
INTRUSIONJL1:
CHASSIS
T-SGPIO3
(SATA SGPIO2)
T-SGPIO2
(SATA SGPIO1)
T-SGPIO1
(SATA SGPIO0)
USB9/10
JOH1
SATA/SAS Connectors
Pin Denitions
Pin# Signal
1Ground
2SATA_TXP
3SATA_TXN
4Ground
5SATA_RXN
6SATA_RXP
7Ground
JIPMB1
COM1
123
IPMI
4
COM2
JF1
ON
JPL1/LAN
1-2:ENABLE
2-3:DISABLE
TPM/PORT80
JI2C2J29
JTPM1
JI2C1
LEDLED12LEDFAIL
NMIXPWRHDDNICNICUIDPSRSTPWR
USB4/5
J30
111
USB6/7
SP1
JPF2
JPF1
USB8(3.0)
J23
T-SGPIO3
1
T-SGPIO2
T-SGPIO1
JUSB3-1A
USB11/12(3.0)
JD1:
SPEAKER-PIN 4-7
PWR LED-PIN 1-3
JD1
LE2
JF1
JPI2C1
JSTBY1
A. I-SATA 0
B. I-SATA 1
C. I-SATA 2
D. I-SATA 3
E. I-SATA 4
F. I-SATA 5
G. S-SATA 0
H. S-SATA 1
I. S-SATA 2
J. S-SATA 3
LGA2011-3
DIMMD1
DIMMD2
DIMMC1
DIMMC2
JL1
JP4
FAN5
FAN6
FAN7
FAN4
1
DIMMB2
DIMMB1
DIMMA2
DIMMA1
JVR1
FAN3
JPWR1
J24
FAN2
FAN1
2-39
L
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X10SRW-F User’s Manual
Notes
2-40
Page 67
Chapter 3: Troubleshooting
Chapter 3
Troubleshooting
3-1 Troubleshooting Procedures
Use the following procedures to troubleshoot your system. If you have followed all
of the procedures below and still need assistance, refer to the ‘Technical Support
Procedures’ and/or ‘Returning Merchandise for Service’ section(s) in this chapter.
Always disconnect the AC power cord before adding, changing or installing any
hardware components.
Before Power On
1. Make sure that the Standby PWR LED is not on. (Note: If it is on, the
onboard power is on. Be sure to unplug the power cable before installing or
removing the components.)
2. Make sure that there are no short circuits between the motherboard and
chassis.
3. Disconnect all ribbon/wire cables from the motherboard, including those for
the keyboard and mouse. Also, be sure to remove all add-on cards.
4. Install a CPU and heatsink (-be sure that it is fully seated) and then connect
the chassis speaker and the power LED to the motherboard. Check all jumper
settings as well.
No Power
1. Make sure that there are no short circuits between the motherboard and
chassis.
2. Make sure that all jumpers are set to their default positions.
3. Check if the 115V/230V switch on the power supply is properly set.
4. Turn the power switch on and off to test the system.
5. The battery on your motherboard may be old. Check to make sure that it still
supplies ~3VDC. If it does not, replace it with a new one.
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X10SRW-F User’s Manual
No Video
1. If the power is on, but you have no video--in this case, you will need to re-
move all the add-on cards and cables rst.
2. Use the speaker to determine if any beep codes exist. (Refer to Appendix A
for details on beep codes.)
3. Remove all memory modules and turn on the system. (If the alarm is on,
check the specications of memory modules, reset the memory or try a differ-
ent one.)
Memory Errors
1. Make sure that the DIMM modules are properly installed and fully seated in
the slots.
2. You should be using ECC DDR4 2400 MHz (max.) memory recommended by
the manufacturer. Also, it is recommended that you use the memory modules
of the same type and speed for all DIMMs in the system. Do not use memory
modules of different sizes, different speeds and different types on the same
motherboard.
3. Check for bad DIMM modules or slots by swapping modules between slots to
see if you can locate the faulty ones.
4. Check the switch of 115V/230V power supply.
Losing the System’s Setup Conguration
1. Please be sure to use a high quality power supply. A poor quality power sup-
ply may cause the system to lose CMOS setup information. Refer to Section
1-6 for details on recommended power supplies.
2. The battery on your motherboard may be old. Check to verify that it still sup-
plies ~3VDC. If it does not, replace it with a new one.
3. If the above steps do not x the Setup Conguration problem, contact your
vendor for repairs.
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Chapter 3: Troubleshooting
3-2 Technical Support Procedures
Before contacting Technical Support, please make sure that you have followed all
the steps listed below. Also, Note that as a motherboard manufacturer, Supermicro
does not sell directly to end users, so it is best to rst check with your distributor or
reseller for troubleshooting services. They should know of any possible problem(s)
with the specic system conguration that was sold to you.
1. Please go through the ‘Troubleshooting Procedures’ and 'Frequently Asked
Question' (FAQ) sections in this chapter or see the FAQs on our website
(http://www.supermicro.com/support/faqs/) before contacting Technical Sup-
port.
2. BIOS upgrades can be downloaded from our website at (http://www.supermi-
cro.com/support/bios/).
Note: Not all BIOS can be ashed. Some cannot be ashed; it depends
on the boot block code of the BIOS.
3. If you've followed the instructions above to troubleshoot your system, and still
cannot resolve the problem, then contact Supermicro's technical support and
provide them with the following information:
• Motherboard model and PCB revision number
• BIOS release date/version (this can be seen on the initial display when your
system rst boots up)
• System conguration
• An example of a Technical Support form is on our website at (http://www.su-
permicro.com/support/contact.cfm).
4. Distributors: For immediate assistance, please have your account number
ready when placing a call to our technical support department. We can be
reached by e-mail at support@supermicro.com, by phone at: (408) 503-
8000, option 2, or by fax at (408)503-8019.
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X10SRW-F User’s Manual
3-3 Frequently Asked Questions
Question: What type of memory does my motherboard support?
Answer: The X10SRW-F supports up to 256GB of RDIMM and 512Gb of LRDIMM
DDR4 2400 MHz (max.) in eight memory slots. See Section 2-5 for details on
installing memory.
Question: How do I update my BIOS?
Answer: We do NOT recommend that you upgrade your BIOS if you are not ex-
periencing any problems with your system. Updated BIOS les are located on our
website at http://www.supermicro.com/support/bios/. Please check our BIOS warn-
ing message and the information on how to update your BIOS on our web site.
Select your motherboard model and download the BIOS ROM le to your computer.
Also, check the current BIOS revision to make sure that it is newer than your BIOS
before downloading. You may choose the zip le. If you choose the zipped BIOS
le, please unzip the BIOS le onto a bootable device or a USB pen/thumb drive.
To ash the BIOS, run the batch le named "ami.bat" with the new BIOS ROM
le from your bootable device or USB pen/thumb drive. Use the following format:
F:\> ami.bat BIOS-ROM-lename.xxx <Enter>
Note: Always use the le named “ami.bat ” to update the BIOS, and insert
a space between "ami.bat" and the lename. The BIOS-ROM-lename
will bear the motherboard name (i.e., X10SRW-F) and build version as
the extension. For example, "X10SRW-F.115".
When the BIOS ashing screen is completed, power off to reboot the
system. Power on and at this point, you will need to load the BIOS de-
faults. Press <Del> to go to the BIOS setup screen, and select "Restore
Defaults" to load the default settings. Next, press <F4> to save and exit.
Then reboot the system.
Warning: Do not shut down or reset the system while updating the BIOS to prevent
possible system boot failure!
Note: The SPI BIOS chip installed on this motherboard is not removable.
To repair or replace a damaged BIOS chip, please send your motherboard
to RMA at Supermicro for service.
Question: I think my BIOS is corrupted. How can I recover my BIOS?
Answer: Please see Appendix C-BIOS Recovery for detailed instructions.
Question: What is the heatsink part number for my X10SRW-F motherboard?
Answer: For the 1U passive heatsink, use SNK-P0047PS (back plate is included).
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Chapter 3: Troubleshooting
3-4 Battery Removal and Installation
Battery Removal
To remove the onboard battery, follow the steps below:
1. Power off your system and unplug your power cable.
2. Locate the onboard battery as shown below.
3. Using a tool such as a pen or a small screwdriver, push the battery lock out-
wards to unlock it. Once unlocked, the battery will pop out from the holder.
4. Remove the battery.
Proper Battery Disposal
Warning: Please handle used batteries carefully. Do not damage the battery in any
way; a damaged battery may release hazardous materials into the environment. Do
not discard a used battery in the garbage or a public landll. Please comply with the
regulations set up by your local hazardous waste management agency to dispose of
your used battery properly.
Battery Installation
1. To install an onboard battery, follow the steps 1 & 2 above and continue
below:
2. Identify the battery's polarity. The positive (+) side should be facing up.
3. Insert the battery into the battery holder and push it down until you hear a
click to ensure that the battery is securely locked.
Warning: When replacing a battery, be sure to only replace it with the same type.
OR
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X10SRW-F User’s Manual
3-5 Returning Merchandise for Service
A receipt or copy of your invoice marked with the date of purchase is required
before any warranty service will be rendered. You can obtain service by calling
your vendor for a Returned Merchandise Authorization (RMA) number. For faster
service, you may also obtain RMA authorizations online (http://www.supermicro.
com/RmaForm/). When you return the motherboard to the manufacturer, the RMA
number should be prominently displayed on the outside of the shipping carton, and
mailed prepaid or hand-carried. Shipping and handling charges will be applied for
all orders that must be mailed when service is complete.
This warranty only covers normal consumer use and does not cover damages
incurred in shipping or from failure due to the alteration, misuse, abuse or improper
maintenance of products.
During the warranty period, contact your distributor rst for any product prob-
lems.
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Chapter 4: AMI BIOS
Chapter 4
BIOS
4-1 Introduction
This chapter describes the AMI BIOS setup utility for the X10SRW-F. The ROM BIOS
is stored in a Flash EEPROM and can be easily updated. This chapter describes
the basic navigation of the AMI BIOS setup utility screens.
Note: For AMI BIOS recovery, please refer to the UEFI BIOS Recovery
Instructions in Appendix C.
Starting BIOS Setup Utility
To enter the AMI BIOS setup utility screens, press the <Delete> key while the
system is booting up.
Note: In most cases, the <Delete> key is used to invoke the AMI BIOS
setup screen. There are a few cases when other keys are used, such as
<F1>, <F2>, etc.
Each main BIOS menu option is described in this manual. The AMI BIOS setup
menu screen has two main frames. The left frame displays all the options that can
be congured. Grayed-out options cannot be congured. Options in blue can be
congured by the user. The right frame displays the key legend. Above the key
legend is an area reserved for a text message. When an option is selected in the
left frame, it is highlighted in white. Often a text message will accompany it.
Note: the AMI BIOS has default text messages built in. Supermicro retains
the option to include, omit, or change any of these text messages.
The AMI BIOS setup utility uses a key-based navigation system called "hot keys."
Most of the AMI BIOS setup utility "hot keys" can be used at any time during the
setup navigation process. These keys include <F1>, <F4>, <Enter>, <Esc>, arrow
keys, etc.
Note: Options printed in Bold are default settings.
How To Change the Conguration Data
The conguration data that determines the system parameters may be changed by
entering the AMI BIOS setup utility. This setup utility can be accessed by pressing
<Del> at the appropriate time during system boot.
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X10SRW-F User’s Manual
How to Start the Setup Utility
Normally, the only visible Power-On Self-Test (POST) routine is the memory test.
As the memory is being tested, press the <Delete> key to enter the main menu of
the AMI BIOS setup utility. From the main menu, you can access the other setup
screens. An AMI BIOS identication string is displayed at the left bottom corner of
the screen, below the copyright message.
Warning: Do not upgrade the BIOS unless your system has a BIOS-related issue.
Flashing the wrong BIOS can cause irreparable damage to the system. In no event
shall Supermicro be liable for direct, indirect, special, incidental, or consequential dam-
ages arising from a BIOS update. If you have to update the BIOS, do not shut down
or reset the system while the BIOS is updating. This is to avoid possible boot failure.
4-2 Main Setup
When you rst enter the AMI BIOS setup utility, you will enter the Main setup screen.
You can always return to the Main setup screen by selecting the Main tab on the
top of the screen. The Main BIOS setup screen is shown below.
The following Main menu items will be displayed:
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Chapter 4: AMI BIOS
System Date/System Time
Use this option to change the system date and time. Highlight System Date or
System Time using the arrow keys. Enter new values using the keyboard. Press the
<Tab> key or the arrow keys to move between elds. The date must be entered in
Day MM/DD/YYYY format. The time is entered in HH:MM:SS format.
Note: The time is in the 24-hour format. For example, 5:30 P.M. appears
as 17:30:00.
Supermicro X10SRW-F
BIOS Version: This item displays the version of the BIOS ROM used in the
system.
Build Date: This item displays the date when the version of the BIOS ROM
used in the system was built.
Memory Information
Total Memory: This item displays the total size of memory available in the
system.
Memory Speed: This item displays the default speed of the memory modules
installed in the system..
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X10SRW-F User’s Manual
4-3 Advanced Setup Congurations
Use the arrow keys to select Advanced setup and press <Enter> to access the
submenu items:
Warning: Take Caution when changing the Advanced settings. An incorrect value, a
very high DRAM frequency or an incorrect BIOS timing setting may cause the system
to malfunction. When this occurs, restore the setting to the manufacture default setting.
Boot Feature
Quiet Boot
Use this feature to select the screen between displaying POST messages or the
OEM logo at bootup. Select Disabled to display the POST messages. Select En-
abled to display the OEM logo instead of the normal POST messages. The options
are Enabled and Disabled.
AddOn ROM Display Mode
Use this item to set the display mode for the Option ROM. Select Keep Current to
use the current AddOn ROM display setting. Select Force BIOS to use the Option
ROM display mode set by the system BIOS. The options are Force BIOS and
Keep Current.
Bootup Num-Lock
Use this feature to set the Power-on state for the Numlock key. The options are
Off and On.
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Chapter 4: AMI BIOS
Wait For 'F1' If Error
Select Enabled to force the system to wait until the 'F1' key is pressed if an error
occurs. The options are Disabled and Enabled.
INT19 (Interrupt 19) Trap Response
Interrupt 19 is the software interrupt that handles the boot disk function. When this
item is set to Immediate, the ROM BIOS of the host adaptors will "capture" Inter-
rupt 19 at bootup immediately and allow the drives that are attached to these host
adaptors to function as bootable disks. If this item is set to Postponed, the ROM
BIOS of the host adaptors will not capture Interrupt 19 immediately and allow the
drives attached to these adaptors to function as bootable devices at bootup. The
options are Immediate and Postponed.
Re-try Boot
When EFI Boot is selected, the system BIOS will automatically reboot the system
from an EFI boot device after its initial boot failure. Select Legacy Boot, to allow
the BIOS to automatically reboot the system from a Legacy boot device after its
initial boot failure. The options are Disabled, Legacy Boot, and EFI Boot.
Power Conguration
DeepSx Power Policies
Use this item to congure the Advanced Conguration and Power Interface (ACPI)
settings for the system. Enable S3 to use Standby Mode (Suspend-to- RAM) and
maintain power supply to the system RAM when the system is in the sleep mode.
Enable S4 to use Hibernation mode (Suspend to Disk) so that all data stored in of
the main memory can be saved in a non-volatile memory area such as in a hard
drive and then power down the system. Enable S5 to power off the whole system
except the power supply unit (PSU) and keep the power button "alive" so that the
user can "wake-up" the system by using an USB keyboard or mouse. The options
are Disabled, Enabled in S5, Enabled in S4-S5, and Enabled in S3-S4-S5,
Watch Dog Function
Select Enabled to allow the Watch Dog timer to reboot the system when it is inac-
tive for more than 5 minutes. The options are Enabled and Disabled.
Power Button Function
This feature controls how the system shuts down when the power button is pressed.
Select 4 Seconds Override for the user to power off the system after pressing and
holding the power button for 4 seconds or longer. Select Instant Off to instantly
power off the system as soon as the user presses the power button. The options
are 4 Seconds Override and Instant Off.
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X10SRW-F User’s Manual
Restore on AC Power Loss
Use this feature to set the power state after a power outage. Select Power-Off for
the system power to remain off after a power loss. Select Power-On for the system
power to be turned on after a power loss. Select Last State to allow the system
to resume its last power state before a power loss. The options are Power-On,
Stay-Off and Last State.
Chipset Conguration
Warning! Setting the wrong values in the following sections may cause the system
to malfunction.
CPU Conguration
The following CPU information will be displayed:
• Processor Socket
• Processor ID
• Processor Frequency
• Max (Maximum) CPU Speed
• Min (Minimum) CPU Speed
• Processor Max Ratio
• Processor Min Ratio
• Microcode Revision
• L1 Cache RAM
• L2 Cache RAM
• L3 Cache RAM
• CPU1 Version
Clock Spread Spectrum
Select Enable for Clock Spectrum support, which will allow the BIOS to monitor
and attempt to reduce the level of Electromagnetic Interference caused by the
components whenever needed. Select Disabled to enhance system stability. The
options are Disabled and Enabled.
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Chapter 4: AMI BIOS
Hyper-Threading
Select Enable to use Intel Hyper-Threading Technology to enhance CPU perfor-
mance. The options are Enable and Disable.
Performance/Watt
Select Power Optimized to use Intel Turbo Boost Technology to maximize system
performance (with maximum cooling) when performance state P0 lasts more than
two seconds. If Traditional is selected, Intel Turbo Boost Technology will be acti-
vated even when performance state P0 lasts less than two seconds. The options
are Traditional and Power Optimized.
Execute Disable Bit (Available if supported by the OS & the CPU)
Set to Enabled for Execute Disable Bit support which will allow the processor to
designate areas in the system memory where an application code can execute and
where it cannot, thus preventing a worm or a virus from ooding illegal codes to over-
whelm the processor or damaging the system during a virus attack. The options are
Enable and Disable. (Refer to Intel and Microsoft websites for more information.)
PPIN Control
Select Unlock/Enable to use the Protected-Processor Inventory Number (PPIN) in
the system. The options are Unlock/Enable and Unlock/Disable.
Hardware Prefetcher (Available when supported by the CPU)
If this item is set to Enable, the hardware prefetcher will prefetch streams of data
and instructions from the main memory to the Level 2 (L2) cache to improve CPU
performance. The options are Disable and Enable.
Adjacent Cache Line Prefetch (Available when supported by the CPU)
Select Enable for the CPU to prefetch both cache lines for 128 bytes as comprised.
Select Disable for the CPU to prefetch both cache lines for 64 bytes. The options
are Disable and Enable.
Note: If there is any change to this setting, you will need to power off and
reboot the system for the change to take effect. Please refer to Intel’s
web site for detailed information.
DCU Streamer Prefetcher (Available when supported by the CPU)
If this item is set to Enable, the DCU (Data Cache Unit) streamer prefetcher will
prefetch data streams from the cache memory to the DCU (Data Cache Unit) to
speed up data accessing and processing for CPU performance enhancement. The
options are Disable and Enable.
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X10SRW-F User’s Manual
DCU IP Prefetcher
If this item is set to Enable, the IP prefetcher in the DCU (Data Cache Unit) will
prefetch IP addresses to improve network connectivity and system performance.
The options are Enable and Disable.
DCU (Data Cache Unit) Mode
Use this item to set the DCU data-prefecting mode. The options are 32KB 8Way
Without ECC and 16KB 4Way With ECC.
Direct Cache Access (DCA)
Select Enable to use Intel DCA (Direct Cache Access) Technology to maximize ef-
ciency in memory data transferring and accessing. The options are Auto, Enable
and Disable.
DCA Prefetch Delay
A DCA prefetcher is used with a TOE (TCP/IP Ofoad Engine) adapter to prefetch
data to shorten execution cycles and to maximize data processing efciency.
Prefetching data too frequently can saturate the cache directory and delay necessary cache access. This feature reduces or increases the frequency of system data
prefetching activities. The options are Disable, [8], [16], [32], [40], [48], [56], [64],
[72], [80], [88], [96], [104], and [112].
Select Enable to allow the BIOS to report the CPU C3 State (ACPI C2) to the
operating system. During the CPU C3 State, the CPU clock generator is turned
off. The options are Enable and Disable.
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X10SRW-F User’s Manual
CPU C6 Report (Available when Power Technology is set to Custom)
Select Enable to allow the BIOS to report the CPU C6 state (ACPI C3) to the
operating system. During the CPU C6 state, power to all caches is turned off.
The options are Enable and Disable.
Enhanced Halt State (C1E)
Select Enabled to enable "Enhanced Halt State" support, which will signicantly
reduce the CPU's power consumption by minimizing CPU's clock cycles and
voltage use during a "Halt State." The options are Disable and Enable.
CPU T State Control
ACPI (Advanced Conguration Power Interface) T-States
If this item is set to Enable, CPU throttling will be supported by the operating
system to reduce power consumption. The options are Enable and Disable.
Socket RAPL (Running Average Power Limit) Conguration
FAST_RAPL_NSTRIKE_PL2_DUTY_CYCLE
This feature displays the value of the item above within the range between 25
(10%) and 64 (25%).
Turbo Power Limit Lock
Select Enable to set the power use limit for the machine when it is running in
the turbo mode. The options are Enable and Disable.
Long Power Limit Override
Select Enable to support long-term power limit override. If this feature is disabled,
BIOS will set the default value. The options are Enable and Disable.
Long Duration Power Limit
This item displays the power limit set by the user during which long duration
power is maintained. The default setting is 0.
Package Clamping Limit1
Use this item to set the limit on power performance states for the run-time proces-
sor, with P0 being the state with the highest frequency (clock speed) and power
(consumption), and P1, a step lower in performance than P0, with its frequency
and voltage scaled back a notch. The options are Between P1/P0 and Below P1.
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Chapter 4: AMI BIOS
Short Duration Power Limit Enable
Select Enable to support Short Duration Power Limit (Power Limit 2). The options
are Enable and Disable.
Short Duration Power Limit
This item displays the time period during which short duration power is main-
tained. The default setting is 0.
Package Clamping Limit2
Use this item to set the limit on power performance states for the processor
operating in turbo mode, with P0 being the state with the highest frequency
(clock speed) and power (consumption), and P1, a step lower in performance
than P0, with its frequency and voltage scaled back a notch. The options are
Between P1/P0 and Below P1.
Chipset Conguration
North Bridge
This feature allows the user to congure the settings for the Intel North Bridge.
IIO Conguration
EV DFX (Device Function On-Hide) Feature
When this feature is set to Enable, the EV_DFX Lock Bits that are located on a
processor will always remain clear during electric tuning. The options are Dis-
able and Enable.
IIO1 Conguration/IIO2 Conguration
IOU2 (II0 PCIe Port 1)
This item congures the PCI-E port Bifuraction setting for a PCI-E port specied
by the user. The options are x4x4, X8, and Auto.
PORT 1A Link Speed
This item congures the link speed of a PCI-E port specied by the user. The
options are Gen 1 (Generation 1) (2.5 GT/s), Gen 2 (Generation 2) (5 GT/s) and
Gen 3 (Generation 3) (8 GT/s).
IOU0 (II0 PCIe Port 2)
This item congures the PCI-E port Bifuraction setting for a PCI-E port specied
by the user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto
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PORT 2A Link Speed
Use this item to congure the link speed of a PCI-E port specied by the user.
The options are Gen 1 (Generation 1) (2.5 GT/s), Gen 2 (Generation 2) (5 GT/s)
and Gen 3 (Generation 3) (8 GT/s).
IOU1 (II0 PCIE Port 3)
Use this item to congure the PCI-E port Bifuraction setting for a PCI-E port speci-
ed by the user. The options are x4x4x4x4, x4x4x8, x8x4x4, x8x8, x16, and Auto.
PORT 3A Link Speed
Use this item to congure the link speed of a PCI-E port specied by the user.
The options are Gen 1 (Generation 1) (2.5 GT/s), Gen 2 (Generation 2) (5 GT/s)
and Gen 3 (Generation 3) (8 GT/s).
PCI-E Completion Timeout
Select Enable for PCI-E Completion Timeout support for electric tuning. The
options are Enable and Disable.
PCI-E Completion Timeout Value
Use this item to set the PCI-E Completion Time-out value for electric tuning.
Enter a value between 260ms to 900ms.
IOAT Conguration
Enable I/OAT
Select Enable to enable Intel I/OAT (I/O Acceleration Technology), which signi-
cantly reduces CPU overhead by leveraging CPU architectural improvements
and freeing the system resource for other tasks. The options are Enable and
Disable.
No Snoop
Select Enable to support no-snoop mode for each CB device. The options are
Disable and Enable.
Relaxed Ordering
Select Enable to enable Relaxed Ordering support which will allow certain trans-
actions to violate the strict-ordering rules of PCI and to be completed prior to
other transactions that have already been enqueued. The options are Disable
and Enable.
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Intel VT for Directed I/O (VT-d)
Intel VT for Direct I/O (VT-d)
®
VT for Directed I/O (VT-d)
Intel
Select Enable to use Intel Virtualization Technology support for Direct I/O VT-d
support by reporting the I/O device assignments to the VMM (Virtual Machine
Monitor) through the DMAR ACPI Tables. This feature offers fully-protected I/O
resource sharing across Intel platforms, providing greater reliability, security and
availability in networking and data-sharing. The options are Enable and Disable.
Interrupt Remapping
Select Enable for Interrupt Remapping support to enhance system performance.
The options are Enable and Disable.
Coherency Support (Non-Isoch)
Select Enable for the Non-Iscoh VT-d engine to pass through DMA (Direct
Memory Access) to enhance system performance. The options are Enable and
Disable.
Coherency Support (Isoch)
Select Enable for the Iscoh VT-d engine to pass through ATS to enhance system
performance. The options are Enable and Disable.
QPI (Quick Path Interconnect) Conguration
QPI Status
The following information will display:
• Number of CPU
• Number of IIO
• Current QPI Link Speed
• Current QPI Link Frequency
• QPI Global MMIO Low Base/Limit
• QPI Global MMIO High Base/Limit
• QPI PCIe Conguration Base/Size
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Link Speed Mode
Use this item to select the data transfer speed for QPI Link connections. The
options are Fast and Slow.
Link Frequency Select
Use this item to select the desired frequency for QPI Link connections. The op-
tions are 6.4GB/s, 8.0GB/s, 9.6GB/s, Auto, and Auto Limited.
Link L0p Enable
Select Enable for Link L0p support. The options are Enable, Auto, and Disable.
Link L1 Enable
Select Enable for Link L1 support. The options are Enable, Auto, and Disable.
Isoc Mode
Select Enabled for Isochronous support to meet QoS (Quality of Service) require-
ments. This feature is especially important for Virtualization Technology. The
options are Enable and Disable.
Memory Conguration
Enforce POR
Select Enable to enforce POR restrictions for DDR4 frequency and voltage
programming. The options are Enabled and Disabled.
Memory Frequency
Use this feature to set the maximum memory frequency for onboard memory
modules. The options are Auto, 1333, 1400, 1600, 1800, 1867, 2000, 2133,
2200, 2400, 2600, 2667, and Reserved (Do not select Reserved).
ECC Support
Select Enable to enable Error Checking & Correction (ECC) support for onboard
memory modules. The options are Auto, Enable and Disable.
Data Scrambling
Select Enabled to enable data scrambling to enhance system performance and
data integrity. The options are Auto, Disabled and Enabled.
Enable ADR
Select Enabled for ADR (Automatic Diagnostic Repository) support to enhance
memory performance. The options are Enabled and Disabled.
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DRAM RAPL (Running Average Power Limit) Baseline
Use this feature to set the run-time power-limit baseline for DRAM modules. The
options are Disable, DRAM RAPL Mode 0, and DRAM RAPL Mode 1.
Set Throttling Mode
Throttling improves reliability and reduces power consumption in the proces-
sor via automatic voltage control during processor idle states. The options are
Disabled and CLTT (Closed Loop Thermal Throttling).
Socket Interleave Below 4GB
Select Enabled for the memory above the 4G Address space to be split between
two sockets. The options are Enable and Disable.
Channel Interleaving
Use this item to set DIMM channel interleaving mood. The options are Auto,
1 Way Interleave, 2 Way Interleave, 3, Way Interleave, and 4 Way Interleave.
Rank Interleaving
Use this item to select a rank memory interleaving method. The options are Auto,
1 Way, 2 Way, 4, Way, and 8 Way.
A7 Mode
Select Enabled to support A7 (Addressing) Mode to improve memory perfor-
mance. The options are Enable and Disable.
DIMM Information
This item displays the status of a DIMM module specied.