Features
VND5E050J-E
VND5E050K-E
Double channel high side driver for automotive applications
Max supply voltage V
Operating voltage range V
Max On-State resistance (per ch.)
Current limitation (typ) I
Off-state supply current I
1. Typical value with all loads connected.
■ General
– Inrush current active management by
power limitation
– Very low standby current
– 3.0V CMOS compatible inputs
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC
european directive
■ Diagnostic functions
– Open Drain status output
– On-state open-load detection
– Off-state open-load detection
– Output short to Vcc detection
– Overload and short to ground (power
limitation) indication
– Thermal shutdown indication
■ Protections
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss
of V
CC
– Over temperature shutdown with auto
restart (thermal shutdown)
– Reverse battery protected (see Figure 32)
– Electrostatic discharge protection
CC
CC
R
ON
LIMH
S
41V
4.5 to 28V
50 mΩ
27 A
(1)
2 µA
PowerSSO-24PowerSSO-12
Applications
■ All types of resistive, inductive and capacitive
loads
Description
The VND5E050J-E and VND5E050K-E are
double channel high-side drivers manufactured in
the ST proprietary VIPower M0-5 technology
and housed in the tiny PowerSSO-12 and
PowerSSO-24 packages.
The
VND5E050J-E and VND5E050K-E
designed to drive automotive
grounded loads
delivering protection, diagnostics and easy 3V
and 5V CMOS-compatible interface with any
microcontroller.
The devices integrate advanced protective
functions such as load current limitation, inrush
and overload active management by power
limitation, over temperature shut-off with
auto-restart and over-voltage active clamp.
A dedicated active low digital status pin is
associated with every output channel in order to
provide Enhanced diagnostic functions including
fast detection of overload and short-circuit to
ground, over temperature indication, short-circuit
to V
diagnosis and on & off-state open-load
CC
detection.
The diagnostic feedback of the whole device can
be disabled by pulling the STAT_DIS pin up, thus
allowing wired-ORing with other similar devices.
are
July 2009 Doc ID 14472 Rev 3 1/40
www.st.com
1
Contents VND5E050K-E
Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 22
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 22
3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . 23
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.3 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.4 Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.5 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 25
4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.2 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5 Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2 PowerSSO-12 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3 PowerSSO-24 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.4 PowerSSO-12 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.5 PowerSSO-24 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2/40 Doc ID 14472 Rev 3
VND5E050K-E List of tables
List of tables
Table 1. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Switching (VCC = 13V; Tj = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Status pin (V
Table 8. Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Openload detection (8V<V
Table 10. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 12. Electrical transient requirements (part 1/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 13. Electrical transient requirements (part 2/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 14. Electrical transient requirements (part 3/3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 15. PowerSSO-12 thermal parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 16. PowerSSO-24 thermal parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 17. PowerSSO-12 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 18. PowerSSO-24™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 20. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
=0V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SD
<18V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CC
Doc ID 14472 Rev 3 3/40
List of figures VND5E050K-E
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Status timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Overload or Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10. Intermittent Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Open-load with external pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. Open-load without external pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13. Short to V
Figure 14. T
evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
J
Figure 15. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 19. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 20. Low level STAT_DIS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 21. On-state resistance vs T
Figure 22. High level STAT_DIS current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 23. On-state resistance vs V
Figure 24. Low level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. I
LIM
vs T
Figure 26. Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 27. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 28. Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 29. STAT_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 30. High level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 31. Low level STAT_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 32. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 33. Open-load detection in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 34. Maximum turn-off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 25
Figure 35. PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 36. Rthj-amb Vs. PCB copper area in open box free air condition (one channel on) . . . . . . . . 26
Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse (one channel on) . . . . . 27
Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . 27
Figure 39. PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 40. Rthj-amb Vs. PCB copper area in open box free air condition (one channel on) . . . . . . . . 29
Figure 41. PowerSSO-24 thermal impedance junction ambient single pulse (one channel on) . . . . . 30
Figure 42. Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . 30
Figure 43. PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 44. PowerSSO-24 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 45. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 46. PowerSSO-12 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 47. PowerSS0-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 48. PowerSSO-24 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
case
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
case
4/40 Doc ID 14472 Rev 3
VND5E050K-E Block diagram and pin description
1 Block diagram and pin description
Figure 1. Block diagram
V
CC
Signal Clamp
Undervoltage
IN1
IN2
ST_
DIS
ST1
ST2
LOGIC
Table 1. Pin function
Control & Diagnostic 1
DRIVER
Over
temp.
OVERLOAD PROT ECTION
(ACTIVE POWER LIMITATION)
Current
Limitation
Power
Clamp
V
ON
Limitation
OFF State
Open load
ON State
Open load
Name Function
V
CC
Battery connection.
OUTPUTn Power output.
GND
Ground connection. Must be reverse battery protected by an external diode/resistor
network.
CH 1
GND
CH 2
Channels 2
OUT2
CONTROL & DIAGNOSTIC
OUT1
INPUTn
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
switch state.
STATUSn Open drain digital diagnostic pin.
STAT_DIS
Active high CMOS compatible pin, to disable the STATUS pin.
Doc ID 14472 Rev 3 5/40
Block diagram and pin description VND5E050K-E
Figure 2. Configuration diagram (top view)
TAB = V
GND
STAT_DIS
INPUT 1
STATUS 1
STATUS 2
INPUT 2
cc
1
2
3
4
5
6
12
11
10
9
8
7
V
cc
OUTPUT 1
OUTPUT 1
OUTPUT 2
OUTPUT 2
V
cc
V
GND.
N.C.
STAT_DIS
INPUT1
STATUS1
N.C.
STATUS2
N.C.
INPUT2
N.C.
V
CC
CC
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
TAB = V
CC
PowerSSO-12
Table 2. Suggested connections for unused and not connected pins
PowerSSO-24
Connection / pin Status N.C. Output Input STAT_DIS
Floating X X X X X
To ground Not allowed X Not allowed
Through 10KΩ
resistor
Through 10KΩ
resistor
6/40 Doc ID 14472 Rev 3
VND5E050K-E Electrical specifications
2 Electrical specifications
Figure 3. Current and voltage conventions
I
S
V
CC
V
CC
Fn
V
I
SD
V
SD
I
INn
INPUTn
V
INn
Note: V
Fn
= V
- VCC during reverse battery condition.
OUTn
2.1 Absolute maximum ratings
Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
GND
OUTPUTnSTAT_DIS
STATUSn
I
GND
I
OUTn
I
STATn
V
STATn
V
OUTn
V
- V
- I
I
OUT
- I
I
STAT
I
STAT_DIS
E
DC supply voltage 41 V
CC
Reverse DC supply voltage 0.3 V
CC
DC reverse ground pin current 200 mA
GND
DC output current Internally limited A
Reverse DC output current 15 A
OUT
DC input current +10 / -1 mA
I
IN
DC status current +10 / -1 mA
DC status disable current +10 / -1 mA
Maximum switching energy
MAX
(L=3 mH; RL=0Ω; V
=13.5V; T
bat
jstart
=150ºC; I
OUT
= I
limL
(Typ.))
104 mJ
Doc ID 14472 Rev 3 7/40
Electrical specifications VND5E050K-E
Table 3. Absolute maximum ratings (continued)
Symbol Parameter Value Unit
Electrostatic discharge
(Human Body Model: R=1.5KΩ; C=100pF)
4000
4000
4000
5000
5000
V
V
V
V
V
V
V
T
– Input
– Status
ESD
–STAT_DIS
– Output
–V
CC
Charge device model (CDM-AEC-Q100-011) 750 V
ESD
Junction operating temperature -40 to 150 °C
T
j
Storage temperature - 55 to 150 °C
stg
2.2 Thermal data
Table 4. Thermal data
Value
Symbol Parameter
PowerSSO-12 PowerSSO-24
Unit
R
thj-case
R
thj-amb
Thermal resistance junction-case (max.)
(with one channel ON)
Thermal resistance junction-ambient
(max.)
2.8 2.8 °C/W
See Figure 36 See Figure 40 °C/W
8/40 Doc ID 14472 Rev 3
VND5E050K-E Electrical specifications
2.3 Electrical characteristics
Values specified in this section are for 8 V<VCC<28V; -40°C<Tj<150 °C, unless otherwise
stated.
.
Table 5. Power section
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
CC
V
USD
V
USDhyst
R
ON
V
clamp
I
I
L(off1)
V
1. PowerMOS leakage included.
2. For each channel.
Operating supply voltage 4.5 13 28 V
Undervoltage shutdown 3.5 4.5 V
Undervoltage shutdown
hysteresis
On-state resistance
Clamp voltage IS=20mA 41 46 52 V
Supply current
S
Off-state output
(2)
current
Output - VCC diode
voltage
(2)
F
I
=2A; Tj=25°C
(2)
OUT
=2A; Tj=150°C
I
OUT
I
=2A; VCC=5V; Tj=25°C
OUT
Off-state; VCC=13V; Tj=25°C;
V
IN=VOUT
On-state; V
I
OUT
VIN=V
= 0V
CC
=0A
=0V; VCC=13V;
OUT
Tj=25°C
V
IN=VOUT
=0V; VCC=13V;
Tj=125°C
-I
=2 A; Tj=150°C 0.7 V
OUT
=13V; VIN=5V;
0.5 V
100
(1)
5
2
3
000.01 3
50
mΩ
mΩ
65
mΩ
(1)
6µAmA
5
µA
Table 6. Switching (VCC=13V; Tj= 25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
t
d(on)
t
d(off)
dV
/dt
OUT
/dt
dV
OUT
W
ON
W
OFF
Turn- On delay time RL= 6.5Ω (see Figure 6)20 µs
Turn- Off delay time RL= 6.5Ω (see Figure 6)40 µs
Turn- On voltage slope RL= 6.5Ω
(on)
Turn- Off voltage slope RL= 6.5Ω
(off)
Switching energy
losses during t
won
Switching energy
losses during t
woff
RL= 6.5Ω (see Figure 6)0.21mJ
RL= 6.5Ω (see Figure 6)0.28mJ
See
Figure 26
See
Figure 28
V/µs
V/µs
Doc ID 14472 Rev 3 9/40
Electrical specifications VND5E050K-E
Table 7. Status pin (VSD=0V)
Symbol Parameter Test conditions Min. Typ. Max Unit
V
STAT
I
LSTAT
C
STAT
V
Table 8. Protections
Status low output
voltage
Status leakage current
Status pin input
capacitance
Status clamp voltage
SCL
(1)
=1.6 mA, VSD=0V 0.5 V
I
STAT
Normal Operation or V
= 5V
V
STAT
SD
=5V,
Normal Operation or VSD=5V,
V
= 5V
STAT
I
STAT
I
STAT
= 1mA
= -1mA
5.5
-0.7
10 µA
100 pF
7V
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
limH
I
limL
T
TSD
T
T
T
HYST
t
SDL
V
DEMAG
V
ON
RS
DC short circuit current VCC=13V;5V<VCC<28V
=13V
Short circuit current
during thermal cycling
V
CC
TR<Tj<T
TSD
Shutdown temperature 150 175 200 °C
Reset temperature
R
Thermal reset of
STATUS
Thermal hysteresis
(T
Status delay in overload
conditions
Turn-off output voltage
clamp
Output voltage drop
limitation
TSD-TR
)
T
I
OUT
I
OUT
T
(see Figure 4)20µs
j>TTSD
=2A; VIN=0; L=6mH
=0.1A;
= -40°C...+150°C
j
(see Figure 5)
19 27 38
38
7A
TRS + 1 TRS + 5
135 °C
7°C
VCC-41 VCC-46 VCC-52
25 mV
V
A
A
°C
V
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.
Table 9. Openload detection (8V<VCC<18V)
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
OL
t
DOL(on)
Openload on-state
detection threshold
Openload on-state
detection delay
10/40 Doc ID 14472 Rev 3
V
= 5V; 10 70 mA
IN
I
= 0A, VCC=13V
OUT
(see Figure 4)
200 µs
VND5E050K-E Electrical specifications
Table 9. Openload detection (8V<VCC<18V) (continued)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Delay between input
t
POL
V
OL
t
DSTKON
falling edge and status
rising edge in open-load
condition
Openload off-state
voltage detection
threshold
Output short circuit to
VCC detection delay at
turn-off
= 0A (see Figure 4) 200 500 1200 µs
I
OUT
VIN = 0V; 2 4 V
See Figure 4 180 t
POL
µs
I
L(off2)
Off-state output
(1)
current
VIN= 0V; V
(see Section 3.4: Open-load
detection in off-state)
OUT
= 4V
-75 0 µA
Delay response from
td_vol
output rising edge to
status falling edge in
V
IN
= 0V; V
= 4V 20 µs
OUT
open-load
1. For each channel.
Table 10. Logic input
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
I
V
I
V
I(hyst)
V
V
I
SDL
V
SDH
I
SDH
V
SD(hyst)
V
SDCL
IH
ICL
SDL
Input low level 0.9 V
IL
Low level input current VIN =0.9 V 1 µA
IL
Input high level 2.1 V
IH
High level input current VIN = 2.1 V 10 µA
Input hysteresis voltage 0.25 V
Input clamp voltage
IIN = 1mA
= -1mA
I
IN
5.5
-0.7
STAT_DIS low level voltage 0.9 V
Low level STAT_DIS current V
= 0.9 V 1 µA
SD
STAT_DIS high level voltage 2.1 V
High level STAT_DIS current V
= 2.1 V 10 µA
SD
STAT_DIS hysteresis voltage 0.25 V
STAT_DIS clamp voltage
ISD=1mA
=-1mA
I
SD
5.5
-0.7
7V
7V
V
V
Doc ID 14472 Rev 3 11/40
Electrical specifications VND5E050K-E
Figure 4. Status timings
OPEN LOAD STATUS TIMING (without external pull-up)
I
< I
OUT
I
OUT
> I
OL
OL
V
t
CC
V
t
DSTKON
OUT
POL
OUT
< V
> V
OL
OL
V
IN
V
STAT
t
DOL(on)
OUTPUT STUCK TO V
V
IN
V
STAT
t
DOL(on)
Figure 5. Output voltage drop limitation
OPEN LOAD STATUS TIMING (with external pull-up)
I
< I
OUT
V
V
IN
STAT
t
DOL(on)
OL
V
OUT
> V
OL
OVER TEMP STATUS TIMING
Tj > T
V
V
IN
STAT
t
SDL
TSD
t
SDL
Vcc-V
out
Tj=150oC
V
on
Von/R
on(T)
Tj=25oC
=-40oC
T
j
I
out
12/40 Doc ID 14472 Rev 3
VND5E050K-E Electrical specifications
Figure 6. Switching characteristics
V
OUT
t
d(off)
90%
t
f
dV
OUT
dV
/dt
OUT
(on)
INPUT
Table 11. Truth table
t
d(on)
80%
t
r
10%
Conditions Input Output Sense (V
Normal operation
Over temperature
Undervoltage
Overload and
short circuit to GND
Output voltage > V
Output current < I
OL
OL
L
H
L
H
L
H
H
H
(no power limitation)
(power limitation)
L
H
L
H
L
H
L
L
L
L
X
Cycling
H
H
L
H
/dt
(off)
H
t
L
t
CSD
H
H
H
L
X
X
H
L
(2)
H
(3)
L
=0V)
(1)
1. If the V
and external circuit.
2. The STATUS pin is low with a delay equal to t
3. The STATUS pin becomes high with a delay equal to t
is high, the SENSE output is at a high impedance, its potential depends on leakage currents
CSD
after INPUT falling edge.
DSTKON
after INPUT falling edge.
POL
Doc ID 14472 Rev 3 13/40
Electrical specifications VND5E050K-E
Table 12. Electrical transient requirements (part 1/3)
ISO 7637-2:
2004(E)
test pulse
Test levels
III IV
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
Impedance
1 -75V -100V 5000 pulses 0.5 s 5 s 2 ms, 10 Ω
2a +37V +50V 5000 pulses 0.2 s 5 s 50 µs, 2 Ω
3a -100V -150V 1h 90 ms 100 ms 0.1 µs, 50 Ω
3b +75V +100V 1h 90 ms 100 ms 0.1 µs, 50 Ω
4 -6V -7V 1 pulse 100 ms, 0.01
(1)
5b
1. Valid in case of external load dump clamp: 40V maximum referred to ground.
+65V +87V 1 pulse 400 ms, 2 Ω
Ω
Table 13. Electrical transient requirements (part 2/3)
ISO 7637-2:
2004(E)
test pulse
Test level results
III IV
(1)
1C C
2a C C
3a C C
3b C C
4C C
(2)
5b
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
CC
Table 14. Electrical transient requirements (part 3/3)
Class Contents
C All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
14/40 Doc ID 14472 Rev 3
VND5E050K-E Electrical specifications
2.4 Waveforms
Figure 7. Normal operation
Normal operation
INPUT
Nominal load Nominal load
I
OUT
V
STATUS
V
ST_DIS
Figure 8. Undervoltage shutdown
Undervoltage shut-down
V
V
V
CC
USD
INPUT
I
OUT
V
STATUS
V
ST_DIS
USDhyst
UNDEFINED
Doc ID 14472 Rev 3 15/40
Electrical specifications VND5E050K-E
Figure 9. Overload or Short to GND
Overload or Short to GND
INPUT
I
>
LimH
I
OUT
V
STATUS
V
ST_DIS
Power Limitation
Figure 10. Intermittent Overload
INPUT
I
>
LimH
I
OUT
Thermal cycling
I
>
LimL
Intermittent Overload
Overload
I
>
LimL
Nominal load
V
STATUS
V
ST_DIS
16/40 Doc ID 14472 Rev 3
VND5E050K-E Electrical specifications
Figure 11. Open-load with external pull-up
Open Load
with external pull-up
INPUT
VPU> V
OL
V
t
DOL(on)
OL
V
OUT
I
OUT
V
STATUS
V
ST_DIS
Figure 12. Open-load without external pull-up
Open Load
without external pull-up
INPUT
V
OUT
I
< I
OUT
OL
I
t
DOL(on)
OL
t
POL
I
OUT
V
STATUS
V
ST_DIS
Doc ID 14472 Rev 3 17/40
Electrical specifications VND5E050K-E
Figure 13. Short to V
INPUT
V
OUT
I
OUT
V
STATUS
V
ST_DIS
CC
Resistive
Short to V
V
> V
OUT
V
OL
I
> I
OUT
I
OL
t
DSTK(on)
Short to V
CC
Hard
CC
OL
OL
Short to V
V
> V
OUT
I
< I
OUT
t
DOL(on)
CC
OL
OL
Figure 14. TJ evolution in overload or short to GND
TJ evolution in
Overload or Short to GND
INPUT
T
J
I
OUT
Self-limitation of fast thermal transients
T
J_START
Power Limitation
I
>
LimH
T
T
TSD
R
< I
T
HYST
LimL
18/40 Doc ID 14472 Rev 3
VND5E050K-E Electrical specifications
2.5 Electrical characteristics curves
Figure 15. Off-state output current Figure 16. High level input current
Iloff (nA)
700
600
500
400
300
200
100
0
-50 -25 0 25 50 75 100 125 150 175
Off State
Vcc=13V
Vin=Vout=0V
Tc (°C)
Figure 17. Input clamp voltage Figure 18. Input high level
Vicl (V)
7
6,8
6,6
6,4
6,2
5,8
5,6
5,4
5,2
lin=1mA
6
5
-50 - 25 0 25 50 75 100 125 150 175
Tc (°C)
Iih (µA)
5
4,5
3,5
2,5
1,5
0,5
Vin=2.1V
4
3
2
1
0
-50 - 25 0 25 50 75 100 125 150 175
Tc (°C)
Vih (V)
4
3,5
3
2,5
2
1,5
1
0,5
0
-50 - 25 0 25 50 75 100 125 150 175
Tc (°C)
Figure 19. Input low level Figure 20. Low level STAT_DIS current
Vil (V)
2
1,8
1,6
1,4
1,2
1
0,8
0,6
0,4
0,2
0
-50 - 25 0 25 50 75 100 125 150 175
Tc (°C)
Doc ID 14472 Rev 3 19/40
Isdl (µA)
5
4,5
3,5
2,5
1,5
0,5
Vsd= 0.9V
4
3
2
1
0
-50 - 25 0 25 50 75 100 125 150 175
Tc (°C)
Electrical specifications VND5E050K-E
Figure 21. On-state resistance vs T
case
Ron (mOhm)
300
250
200
150
100
50
Iout= 2A
Vcc=13V
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Figure 23. On-state resistance vs V
CC
Ron (mOhm)
100
80
60
40
20
0
0 5 10 15 20 25 30 35 40
Tc=150°C
Tc=125°C
Tc=25°C
Tc=-40°C
Tc (°C)
Figure 22. High level STAT_DIS current
Isdh (µA)
5
4,5
3,5
2,5
1,5
0,5
Vsd= 2.1V
4
3
2
1
0
-50 - 25 0 25 50 75 100 125 150 175
Tc (°C)
Figure 24. Low level input current
Iil (µA)
5
4,5
3,5
2,5
1,5
0,5
Vin=0.9V
4
3
2
1
0
-50 - 25 0 25 50 75 100 125 150 175
Tc (°C)
Figure 25. I
LIM
vs T
case
Ilimh (A)
40
35
30
25
20
15
10
Vcc=13V
-50 -25 0 25 50 75 100 125 150
Tc (°C)
20/40 Doc ID 14472 Rev 3
Figure 26. Turn-On voltage slope
(dVout/dt )On (V/ms)
1000
900
800
700
600
500
400
300
200
100
0
-50 -25 0 25 50 75 100 125 150 175
Vcc=13V
RI=6.5 Ohm
Tc (°C)
VND5E050K-E Electrical specifications
Figure 27. Undervoltage shutdown Figure 28. Turn-Off voltage slope
Vusd (V)
8
7
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
(dVout/dt )Off (V/ms)
600
550
500
450
Vcc=13V
RI= 6.5 Ohm
400
350
300
250
200
150
100
50
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Figure 29. STAT_DIS clamp voltage Figure 30. High level STAT_DIS voltage
Vsdcl(V)
10
9
8
Isd = 1 mA
7
6
5
4
3
2
1
0
-50 -25 0 25 50 75 100 125 150 175
Tc (°C)
Figure 31. Low level STAT_DIS voltage
VsdL(V)
3
VsdH(V)
4
3,5
3
2,5
2
1,5
1
0,5
0
-50 - 25 0 25 50 75 100 125 150 175
Tc (°C)
2,5
2
1,5
1
0,5
0
-50 - 25 0 25 50 75 100 125 150 175
Tc (°C)
Doc ID 14472 Rev 3 21/40
Application information VND5E050K-E
3 Application information
Figure 32. Application schematic
+5V
μ
R
R
C
R
prot
prot
prot
+5V
STAT_DIS
STATUS
INPUT
V
CC
OUTPUT
GND
R
GND
GND
D
GND
V
Note: Channel 2 has the same internal circuit as channel 1.
3.1 GND protection network against reverse battery
D
ld
3.1.1 Solution 1: resistor in the ground line (R
This can be used with any type of load.
The following is an indication on how to dimension the R
1. R
2. R
where -I
maximum rating section of the device datasheet.
Power Dissipation in R
P
= (-VCC)2/R
D
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where I
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
R
GND
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same R
22/40 Doc ID 14472 Rev 3
≤ 600mV / (I
GND
≥ (−VCC) / (-I
GND
is the DC reverse ground pin current and can be found in the absolute
GND
S(on)max
GND
GND
).
)
(when VCC<0: during reverse battery situations) is:
GND
will produce a shift (I
S(on)max
* R
GND
GND
only)
GND
resistor.
GND
S(on)max
becomes the sum of the
) in the input thresholds and the status output
.
VND5E050K-E Application information
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2 Solution 2: diode (D
A resistor (R
=1kΩ) should be inserted in parallel to D
GND
) in the ground line
GND
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2 Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
V
max DC rating. The same applies if the device is subject to transients on the VCC line
CC
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3 MCU I/Os protection
If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (R
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC µand the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
if the device drives an
GND
prot
) in line to
-V
CCpeak/Ilatchup
≤ R
prot
≤ (V
OHμC-VIH-VGND
) / I
IHmax
Calculation example:
For V
5kΩ ≤ R
Recommended values: R
CCpeak
prot
= - 100V and I
≤ 180kΩ.
latchup
=10kΩ.
prot
≥ 20mA; V
OHµC
≥ 4.5V
Doc ID 14472 Rev 3 23/40
Application information VND5E050K-E
3.4 Open-load detection in off-state
Off-state open-load detection requires an external pull-up resistor (RPU) connected between
output pin and a positive supply voltage (V
microprocessor.
The external resistor has to be selected according to the following requirements:
1. no false open-load indication when load is connected: in this case we have to avoid
V
to be higher than V
OUT
V
=(VPU/(RL+RPU))RL<V
OUT
; this results in the following condition
Olmin
Olmin
.
2. no misdetection when load is disconnected: in this case the V
V
Because I
up resistor R
; this results in the following condition RPU<(VPU–V
OLmax
may significantly increase if V
s(OFF)
should be connected to a supply that is switched OFF when the module is in
PU
standby.
) like the +5V line used to supply the
PU
has to be higher than
OUT
)/I
OLmax
is pulled high (up to several mA), the pull-
out
L(off2)
.
The values of V
OLmin
, V
OLmax
and I
are available in the Electrical Characteristics
L(off2)
section.
Figure 33. Open-load detection in off-state
V batt. VPU
V
CC
INPUT
STATUS
DRIVER
+
LOGIC
+
-
VOL
GROUND
R
OUT
I
L(off2)
R
PU
RL
24/40 Doc ID 14472 Rev 3
VND5E050K-E Application information
3.5 Maximum demagnetization energy (VCC = 13.5V)
Figure 34. Maximum turn-off current versus inductance (for each channel)
100
A
B
10
I (A)
1
0,1 1 10 100
C
L (mH)
A: T
B: T
C: T
VIN, I
L
Note: Values are generated with R
= 150°C single pulse
jstart
= 100°C repetitive pulse
jstart
= 125°C repetitive pulse
jstart
In case of repetitive pulses, T
must not exceed the temperature specified above for curves A and B.
Demagnetization Demagnetization Demagnetization
=0 Ω.
L
(at beginning of each demagnetization) of every pulse
jstart
t
Doc ID 14472 Rev 3 25/40
Package and PCB thermal data VND5E050K-E
4 Package and PCB thermal data
4.1 PowerSSO-12 thermal data
Figure 35. PowerSSO-12 PC board
Note: Layout condition of R
area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70μm (front and back side),
Copper areas: from minimum pad lay-out to 8cm
Figure 36. R
thj-amb
on)
RTHj_amb(°C/ W)
70
65
60
55
50
45
40
35
30
0246810
and Zth measurements (PCB: Double layer, Thermal Vias, FR4
th
2
).
Vs. PCB copper area in open box free air condition (one channel
PCB Cu heatsink area (cm^ 2)
26/40 Doc ID 14472 Rev 3
VND5E050K-E Package and PCB thermal data
Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse (one
channel on)
ZTH (°C/ W)
100
Footprint
2 cm
8 cm
2
2
10
1
0,1
0,0001 0,001 0,01 0,1 1 10 100 1000
Time ( s)
Equation 1: pulse calculation formula
Z
THδ
where δ = t
Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-12
R
TH
/T
P
δ Z
THtp
1 δ–()+⋅=
(a)
a. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
Doc ID 14472 Rev 3 27/40
Package and PCB thermal data VND5E050K-E
Table 15. PowerSSO-12 thermal parameters
Area/island (cm2)Footprint28
R1= R7 (°C/W) 0.7
R2= R8 (°C/W) 2.8
R3 (°C/W) 4
R4 (°C/W) 8 8 7
R5 (°C/W) 22 15 10
R6 (°C/W) 26 20 15
C1= C7 (W.s/°C) 0.001
C2= C8 (W.s/°C) 0.0025
C3 (W.s/°C) 0.05
C4 (W.s/°C) 0.2 0.1 0.1
C5 (W.s/°C) 0.27 0.8 1
C6 (W.s/°C) 3 6 9
28/40 Doc ID 14472 Rev 3
VND5E050K-E Package and PCB thermal data
4.2 PowerSSO-24 thermal data
Figure 39. PowerSSO-24 PC board
Note: Layout condition of R
area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm
Figure 40. R
thj-amb
on)
RTHj_amb(°C/W)
55
50
45
40
35
30
0246810
and Zth measurements (PCB: Double layer, Thermal Vias, FR4
th
2
).
Vs. PCB copper area in open box free air condition (one channel
PCB Cu heatsink area (cm^2)
Doc ID 14472 Rev 3 29/40
Package and PCB thermal data VND5E050K-E
Figure 41. PowerSSO-24 thermal impedance junction ambient single pulse (one
channel on)
Equation 2: pulse calculation formula
Z
THδ
where δ = t
Figure 42. Thermal fitting model of a double channel HSD in PowerSSO-24
b. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
R
TH
/T
P
δ Z
THtp
1 δ–()+⋅=
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
(b)
30/40 Doc ID 14472 Rev 3
VND5E050K-E Package and PCB thermal data
Table 16. PowerSSO-24 thermal parameters
Area/island (cm2)Footprint28
R1=R7 (°C/W) 0.4
R2=R8 (°C/W) 2
R3 (°C/W) 6
R4 (°C/W) 7.7
R5 (°C/W) 9 9 8
R6 (°C/W) 28 17 10
C1=C7 (W.s/°C) 0.001
C2=C8 (W.s/°C) 0.0022
C3 (W.s/°C) 0.025
C4 (W.s/°C) 0.75
C5 (W.s/°C) 1 4 9
C6 (W.s/°C) 2.2 5 17
Doc ID 14472 Rev 3 31/40
Package and packing information VND5E050K-E
5 Package and packing information
5.1 ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com
ECOPACK
®
is an ST trademark.
5.2 PowerSSO-12 package information
Figure 43. PowerSSO-12 package dimensions
.
32/40 Doc ID 14472 Rev 3
VND5E050K-E Package and packing information
Table 17. PowerSSO-12 mechanical data
Symbol
Min. Typ. Max.
A 1.25 1.62
A1 0 0.1
A2 1.10 1.65
B 0.23 0.41
C 0.19 0.25
D4.8 5.0
E3.8 4.0
e0.8
H5.8 6.2
h 0.25 0.5
L 0.4 1.27
Millimeters
k0° 8°
X1.9 2.5
Y3.6 4.2
ddd 0.1
Doc ID 14472 Rev 3 33/40
Package and packing information VND5E050K-E
5.3 PowerSSO-24 package information
Figure 44. PowerSSO-24 package dimensions
34/40 Doc ID 14472 Rev 3
VND5E050K-E Package and packing information
Table 18. PowerSSO-24™ mechanical data
Millimeters
Symbol
Min Typ Max
A 2.45
A2 2.15 2.35
a1 0 0.1
b0.33 0.51
c0.23 0.32
D 10.10 10.50
E7.4 7.6
e0.8
e3 8.8
F2.3
G 0.1
H 10.1 10.5
h 0.4
k0° 8°
L0.55 0.85
O1.2
Q0.8
S2.9
T3.65
U1.0
N 10°
X4.1 4.7
Y6.5 7.1
Doc ID 14472 Rev 3 35/40
Package and packing information VND5E050K-E
5.4 PowerSSO-12 packing information
Figure 45. PowerSSO-12 tube shipment (no suffix)
B
C
Base Q.ty 100
Bulk Q.ty 2000
Tube length (± 0.5) 532
A
A1.85
B6.75
C (± 0.1) 0.6
All dimensions are in mm.
Figure 46. PowerSSO-12 tape and reel shipment (suffix “TR”)
REEL DIMENSIONS
Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.05) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2
All dimensions are in mm.
End
Start
Top
cover
tape
500mm min
Empty components pockets
saled with cover tape.
User direction of feed
No componentsNo components Components
500mm min
36/40 Doc ID 14472 Rev 3
VND5E050K-E Package and packing information
5.5 PowerSSO-24 packing information
Figure 47. PowerSS0-24 tube shipment (no suffix)
Base Qty 49
C
B
A
Figure 48. PowerSSO-24 tape and reel shipment (suffix “TR”)
Bulk Qty 1225
Tube length (±0.5) 532
A 3.5
B 13.8
C (±0.1) 0.6
All dimensions are in mm.
REEL DIMENSIONS
Base Qty 1000
Bulk Qty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+2 / -0) 24.4
N (min) 100
T (max) 30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 24
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 12
Hole Diameter D (± 0.05) 1.55
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 11.5
Compartment Depth K (max) 2.85
Hole Spacing P1 (± 0.1) 2
End
All dimensions are in mm.
Start
Top
cover
tape
500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
No componentsNo components Components
500mm min
Doc ID 14472 Rev 3 37/40
Order codes VND5E050K-E
6 Order codes
Table 19. Device summary
Order codes
Package
Tube Tape and reel
PowerSSO-12 VND5E050J-E VND5E050JTR-E
PowerSSO-24 VND5E050K-E VND5E050KTR-E
38/40 Doc ID 14472 Rev 3
VND5E050K-E Revision history
7 Revision history
Table 20. Document revision history
Date Revision Changes
04-Feb-2008 1 Initial release.
Table 18: PowerSSO-24™ mechanical data:
– Deleted A (min) value
– Changed A (max) value from 2.47 to 2.45
19-Jun-2009 2
22-Jul-2009 3
– Changed A2 (max) value from 2.40 to 2.35
– Changed a1 (max) value from 0.075 to 0.1
– Added F row
– Updated k row
Updated Figure 44: PowerSSO-24 package dimensions.
Updated Table 18: PowerSSO-24™ mechanical data:
– Deleted G1 row
– Added O, Q, S, T and U rows
Doc ID 14472 Rev 3 39/40
VND5E050K-E
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