ST TDA7590 User Manual
Digital signal processing IC for speech and
Features
■ 24-bit, fixed point, 120 MIPS DSP core
■ Large on-board memory (128KW-24 bit)
■ Host access to internal RAM through
expansion port
■ Access to external RAM (16Mw) through
expansion port
■ Integrated stereo, 18-bit Sigma-DELTA A/D
and 20-bit D/A converters
■
Programmable CODEC sample rate up to 48 kHz
■ On-board PLL for core clock and converters
■
External Flash/SRAM memory bank
management
2
■ I
C and SCI serial interface for external control
■
2 enhanced synchronous serial interface (ESSI)
■ JTAG interface
■ Host interface
■ 144-pin TQFP, 0.50 mm pitch
■ Automotive temperature range
(from -40 °C to +85 °C)
TDA7590
audio applications
TQFP144
Description
The TDA7590 is a high performances, fully
programmable 24-bit, 120 MIPS. Digital signal
processor (DSP), designed to support several
speech and audio applications, as automatic
speech recognition, speech synthesis, MP3
decoding, echo and noise cancellation.
Nevertheless, the embedded CODECs bandwidth
and the generic processing engine allow to
proceed also full-band audio signals. The large
amount of on-chip memory (128 Kwords),
together with the 16 Mwords external memory
addressable and the 32 general purpose I/O pins
permit to build a DSP-system avoiding the usage
of an additional microcontroller.
Applications
■ Real time digital speech and audio processing:
– speech recognition
– speech synthesis
– speech compression
– echo canceling
– noise canceling
– MP3 decoding
Table 1. Device summary
Order code Package Packing
E-TDA7590
E-TDA7590TR Tape and reel
1. In ECOPACK® package (see Section 9: Package information on page 40).
January 2009 Rev 2 1/42
TQFP144 (20x20x1.0 exposed pad down)
The presence of serial and parallel interfaces
allows easy connection with external devices
including CODECs, DSPs, microprocessors and
personal computers.
In particular, the debug/JTAG interface permits the
on-chip emulation of the firmware developed.
Further, the presence of the timers and watchdog
block makes TDA7590 suitable for PWM
processing and allows the integration of a system
watchdog.
(1)
Tr ay
www.st.com
1
Contents TDA7590
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.1 CODEC (ADC/DAC) test description . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 Electrical characteristics for I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 24 bit DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 DSP peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.2 Serial communication interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.3 I
7.4 Host interface (HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.5 ESSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.6 EOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.7 Timers and watchdog block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.8 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.9 CODEC cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2
C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
8 Appendix 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8.1 Benchmarking program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/42
TDA7590 Contents
9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
3/42
List of tables TDA7590
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 4. Key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4/42
TDA7590 List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. TQFP144 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5/42
Block diagram TDA7590
1 Block diagram
Figure 1. Block diagram
2 Channel
Codec
SAI/CCT
rclk
PLL Clock
Oscillator
PROM
sclk
ESSI
ESSI/12C SCI
YRAM
68/64/56/48K x 24
XRAM
4/8/16/14K x 24
PRAM
16K x 24
HOST i/f
Triple
Timer
FLEX RAM
40K x 24
DDB
EBUG
Interface
DAB
YDB
MOZART core
120MIPs, 32 GPIOs
XAB
YAB
XDB
PA B
6/42
Expansion
Por t
EDB
EAB
TDA7590 Pin description
2 Pin description
2.1 Pin connection
Figure 2. Pin connection (top view)
SC11
SC12
TDO
TMS
TCK
TRSTN
IRQD
IRQC
IRQB
IRQA
DB23
DB22
TDI
143
141 139 137
144 142 140 138
DB21
IOVSS
COREVSS
COREVDD
DB19
IOVDD
DB20
136 134 132 130 128 126 124 122 120 118 116 114 112 110
125 121 117 115 109135 133 131 129 127 123 119 113 111
DB15
IOVSS
DB18
DB17
DB16
DB14
DB13
DB12
DB11
DB10
DB9
IOVSS
IOVDD
DB8
IOVDD
DB7
SRD1
STD1
SC02
SC01
DE_N
NMI
SRD0
IOVDD
IOVSS
STD0
SC10
SC00
TXD
SCLK
SCK1
SCK0
RESET
SCANEN
TESTEN
COREVDD
COREVSS
TIO0
VSSSUB
DAC 1
DACOM
DAC OP
REF0
CODEC_VDD
CODEC_VSS
ADC1
ADCOM
ADCOP
IOVDD
IOVSS
EXTDACLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
373839 41 43
40 42 44
454647 49
48
53
56
58
65 67
68
66 70
69
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
DB6
DB5
DB4
DB3
COREVSS
COREVDD
DB2
DB1
DB0
AB19
AB18
AB17
AB16RXD
AB15
AB14
AB13
AB12
IOVSS
IOVDD
AB11
AB10
COREVSS
COREVDD
AB9
AB8
AB7
AB6
IOVSS
IOVDD
AB5
AB4
AB3
AB2
IOVSS
IOVDD
AB1
XTI71PLL_VDD
XTO
HREQ51IOVSS
HDS
HACK50IOVDD52HCS54HAD7
PLL_VSS
HRW
HAS55HA857HAD659HAD461COREVSS63HAD2
HA9
HAD560COREVDD62HAD364HAD1
AA3
AA2
HAD0
BRBBIOVDD
WEN
AA1
IOVSS
BG
OEN
AA0
AB0
7/42
Pin description TDA7590
2.2 Pin function
Table 2. Pin function
N° Name Type Description
1 SRD1/TI02 I/O Serial receive data. Serial input data for receiver. Timer 2 input/output.
2 STD1 I/O Serial transmit data. Serial output data from transmitter.
3SC02I/O
4SC01I/O
Serial control 2.Transmitter frame sync only in asynchronous mode,
transmitter and receiver frame sync in synchronous mode.
Serial control 1. Receive frame sync in asynchronous mode, output
from transmitter 2 or serial flag 1 in synchronous mode.
5 DE_N I/O Test data output (input/output). Debug request input and acknowledge output.
6NMI_NI
Non-maskable interrupt/ PINIT. Used to enable the PLL during RESET
and as a non-maskable interrupt at all other times.
7 SRD0 I/O Serial receive data. Serial input data for receiver.
8 IOVDD I IO power supply.
9 IOVSS I IO ground.
10 STD0 I/O Serial Transmit Data. Serial output data from transmitter.
ESSI1 serial control 0. Receive clock in asynchronous mode, output from
11 SC10/SCL I/O
transmitter or serial flag in synchronous mode.
I2C SCL serial clock line.
12 SC00 I/O
Serial control 0. Receive clock in asynchronous mode, output from transmitter
1 or serial flag 0 in synchronous mode.
13 RXD I/O SCI receive data. Receives byte-oriented serial data.
14 TXD I/O SCI read enable. Transmits serial data from SCI transmit shift register.
SCI serial clock. Input or output clock from which data is transferred in
15 SCLK I/O
synchronous mode and from which the transmit and/or receive baud rate is
derived in asynchronous mode.
Serial clock. Serial bit clock for transmitter only in asynchronous mode, serial
16 SCK1/TI01 I/O
bit clock for both receiver and transmitter in synchronous mode.
Timer 1 input/output.
17 SCK0 I/O
Serial clock. Serial bit clock for transmitter only in asynchronous mode, serial
bit clock for both receiver and transmitter in synchronous mode.
18 RESETN I System reset. A low level applied to RESET_N input initializes the IC.
19 SCANEN I
SCAN enable. When active with TESTEN also active, controls the shifting of
the internal scan chains.
Test enable. When active, puts the chip into test mode and muxes the XTI
20 TESTEN I
clock to all flip-flops. When SCANEN is also active, the scan chain shifting is
enabled.
21 COREVSS I Core ground.
22 COREVDD I Core power supply.
23 TIO0 I/O Timer 0 input/output.
24 VSSSUB I Analog substrate isolation.
8/42
TDA7590 Pin description
Table 2. Pin function (continued)
N° Name Type Description
25 DAC1 O DAC1 left single analog output.
26 DAC0M O DAC0 negative right differential analog output.
27 DAC0P O DAC0 positive right differential analog output.
28 CODEC_VSS I Voltage ground.
29 REF0 I Codec power supply.
30 CODEC_VDD I Codec reference.
31 ADC1 I ADC1 left single analog input.
32 ADC0M I DAC0 negative right differential analog inputs.
33 ADC0P I DAC0 positive right differential analog inputs.
36 EXTDACLK I
37 XTI I Crystal oscillator input. External clock input or crystal connection.
38 XTO O Crystal oscillator output. Crystal oscillator output drive.
39 PLL_VDD I PLL power supply.
40 PLL_VSS I PLL ground input.
External DAC clock. Optional external clock source from which LRCLK and
SCLK can be generated.
Host data strobe. Polarity programmable Host data strobe input for single
41 HDS I/O
42 HRW I/O
43 HACK I/O
44 HREQ I/O
45 IOVDD I IO power supply.
46 IOVSS I IO ground.
47 HCS I/O
48 HA9 I/O
49 HA8 I/O
50 HAS I/O
strobe mode. Polarity programmable Host write strobe input for double strobe
mode.
Host read/write. Host read/write for single strobe bus mode.
Polarity programmable Host read data strobe for double strobe mode.
Host acknowledge. Polarity programmable host interrupt acknowledge for
single host request mode. Polarity programmable host receive request
interrupt for double host request mode.
Host request. Polarity programmable host request interrupt for single host
request mode. Polarity programmable host transfer request interrupt for
double host request mode.
Host chip select. Polarity programmable host chip select for non-multiplexed
mode.
Host address Line 10 for multiplexed mode.
Host address 9. Address line 9 in multiplexed mode otherwise address line 2
in non-multiplexed mode.
Host address 8. Address line 8 in multiplexed mode otherwise address line 1
in non-multiplexed mode.
Host address strobe. Address strobe for multiplexed bus or Address 0 for non
multiplexed.
51 HAD[7] I/O
Host 8-bit data line 7. Host data bus and/or address lines when in multiplexed
mode.
9/42
Pin description TDA7590
Table 2. Pin function (continued)
N° Name Type Description
52 HAD[6] I/O
53 HAD[5] I/O
54 HAD[4] I/O
55 COREVDD I Core power supply.
56 COREVSS I Core ground.
57 HAD[3] I/O
58 HAD[2] I/O
59 HAD[1] I/O
60 HAD[0] I/O
61 AA[3] O
62 AA[2] O
63 BR_N O
64 BB_N I/O
Host 8-bit data line 6. Host data bus and/or address lines when in multiplexed
mode.
Host 8-bit data line 5. Host data bus and/or address lines when in multiplexed
mode.
Host 8-bit data line 4. Host data bus and/or address lines when in multiplexed
mode.
Host 8-bit data line 3. Host data bus and/or address lines when in multiplexed
mode.
Host 8-bit data line 2. Host data bus and/or address lines when in multiplexed
mode.
Host 8-bit data line 1. Host data bus and/or address lines when in multiplexed
mode.
Host 8-bit data line 0. Host data bus and/or address lines when in multiplexed
mode.
Address attributes line 3.Port A address attributes/chip select pins with
programmable polarity.
Address attributes line 2.Port A address attributes/chip select pins with
programmable polarity.
Bus request. Asserted when port A requires bus mastership to perform offchip accesses.
Bus busy. Asserted by port A when bus_busy_in_n is negated and BG_N is
asserted.
65 IOVDD I IO power supply.
66 IOVSS I IO ground.
67 WEN_N O Write enable.
68 OEN_N O Output enable.
69 AA[1] O
70 AA[0] O
71 BG_N I
72 AB[0] O Address bus line 0. Port A external address bus.
73 AB[1] O Address bus line 1. Port A external address bus.
74 IOVDD I IO power supply.
75 IOVSS I IO ground.
76 AB[2] O Address bus line 2. Port A external address bus.
10/42
Address attributes line 1.Port A address attributes/chip select pins with
programmable polarity.
Address attributes line 0.Port A address attributes/chip select pins with
programmable polarity.
Bus grant. When asserted, Port A becomes the bus master elect. Bus
mastership
is attained when bus busy is negated by the current bus master.
TDA7590 Pin description
Table 2. Pin function (continued)
N° Name Type Description
77 AB[3] O Address bus line 3. Port A external address bus.
78 AB[4] O Address bus line 4. Port A external address bus.
79 AB[5] O Address bus line 5. Port A external address bus.
80 IOVDD I IO power supply.
81 IOVSS I IO ground.
82 AB[6] O Address bus line 6. Port A external address bus.
83 AB[7] O Address bus line 7. Port A external address bus.
84 AB[8] O Address bus line 8. Port A external address bus.
85 AB[9] O Address bus line 9. Port A external address bus.
86 COREVDD I Core power supply.
87 COREVSS I Core ground.
88 AB[10] O Address bus line 10. Port A external address bus.
89 AB[11] O Address bus line 11. Port A external address bus.
90 IOVDD I IO power supply.
91 IOVSS I IO ground.
92 AB[12] O Address bus line 12. Port A external address bus.
93 AB[13] O Address bus line 13. Port A external address bus.
94 AB[14] O Address bus line 14. Port A external address bus.
95 AB[15] O Address bus line 15. Port A external address bus.
96 AB[16] O Address bus line 16. Port A external address bus.
97 AB[17] O Address bus line 17. Port A external address bus.
98 AB[18] O Address bus line 18. Port A external address bus.
99 AB[19] O Address bus line 19. Port A external address bus.
100 DB[0] I/O Address bus 0. Port A external data bus.
101 DB[1] I/O Address bus 1. Port A external data bus.
102 DB[2] I/O Address bus 2. Port A external data bus.
103 COREVDD I Core power supply.
104 COREVSS I Core ground.
105 DB[3] I/O Data bus line 3. Port A external data bus.
106 DB[4] I/O Data bus line 4. Port A external data bus.
107 DB[5] I/O Data bus line 5. Port A external data bus.
108 DB[6] I/O Data bus line 6. Port A external data bus.
109 DB[7] I/O Data bus line 7. Port A external data bus.
110 DB[8] I/O Data bus line 8. Port A external data bus.
111 IOVDD I IO Power Supply.
11/42
Pin description TDA7590
Table 2. Pin function (continued)
N° Name Type Description
112 IOVSS I IO Ground.
113 DB[9] I/O Data Bus line 9. Port A external data bus.
114 DB[10] I/O Data bus line 10. Port A external data bus.
115 DB[11] I/O Data bus line 11. Port A external data bus.
116 DB[12] I/O Data bus line 12. Port A external data bus.
117 DB[13] I/O Data bus line 13. Port A external data bus.
118 DB[14] I/O Data bus line 14. Port A external data bus.
119 IOVDD I IO power supply.
120 IOVSS I IO Ground.
121 DB[15] I/O Data bus line 15. port a external data bus.
122 DB[16] I/O Data bus line 16. Port A external data bus.
123 DB[17] I/O Data bus line 17. Port A external data bus.
124 DB[18] I/O Data bus line 18. Port A external data bus.
125 DB[19] I/O Data bus line 19. Port A external data bus.
126 COREVDD I Core power supply.
127 COREVSS I Core ground.
128 DB[20] I/O Data bus line 20. Port A external data bus.
129 IOVDD I IO power supply.
130 IOVSS I IO ground.
131 DB[21] I/O Data bus line 21. Port A external data bus.
132 DB[22] I/O Data bus line 22. Port A external data bus.
133 DB[23] I/O Data bus line 23. Port A external data bus.
134 IRQA I
135 IRQB I
136 IRQC I
137 IRQD I
138 TRSTN I Test reset. JTAG output pin for serial data out from debug interface.
139 TDI I Test data input. JTAG input pin for serial data input for debug interface.
140 TCK I Test clock. JTAG input pin for clocking debug interface.
141 TMS I
142 TDO O Test data output. JTAG output pin for serial data out from debug interface.
Interrupt request line/ Mode control. Used as mode control during RESET
and as interrupt request line at all other times.
Interrupt request line/ Mode control. Used as mode control during RESET
and as interrupt request line at all other times.
Interrupt request line/ Mode control. Used as mode control during RESET
and as interrupt request line at all other times.
Interrupt request line/ Mode control. Used as mode control during RESET
and as interrupt request line at all other times.
Test mode select. JTAG input pin for control of TAP Controller of debug
interface.
12/42
TDA7590 Pin description
Table 2. Pin function (continued)
N° Name Type Description
143 SC12 I/O
Serial control 2.Transmitter frame sync only in asynchronous mode,
transmitter and receiver frame sync in synchronous mode.
Serial control 1. Receive frame sync in asynchronous mode,
144 SC11/SDA I/O
output from transmitter 2 or serial flag 1 in synchronous mode.
I2C SDA. Serial data line.
2.3 Thermal data
Table 3. Thermal data
Symbol Parameter Value Unit
R
th-j-pins
Thermal resistance junction to pins 32 °C/W
13/42
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