ST TDA7590 User Manual

TDA7590

Digital signal processing IC for speech and audio applications

Features

■24-bit, fixed point, 120 MIPS DSP core

■Large on-board memory (128KW-24 bit)

■Host access to internal RAM through expansion port

■Access to external RAM (16Mw) through expansion port

■Integrated stereo, 18-bit Sigma-DELTA A/D and 20-bit D/A converters

■Programmable CODEC sample rate up to 48 kHz

■On-board PLL for core clock and converters

■External Flash/SRAM memory bank management

■I2C and SCI serial interface for external control

■2 enhanced synchronous serial interface (ESSI)

■JTAG interface

■Host interface

■144-pin TQFP, 0.50 mm pitch

■Automotive temperature range (from -40 °C to +85 °C)

Applications

■Real time digital speech and audio processing:

–speech recognition

–speech synthesis

–speech compression

–echo canceling

–noise canceling

–MP3 decoding

Table 1. Device summary

TQFP144

Description

The TDA7590 is a high performances, fully programmable 24-bit, 120 MIPS. Digital signal processor (DSP), designed to support several speech and audio applications, as automatic speech recognition, speech synthesis, MP3 decoding, echo and noise cancellation.

Nevertheless, the embedded CODECs bandwidth and the generic processing engine allow to proceed also full-band audio signals. The large amount of on-chip memory (128 Kwords), together with the 16 Mwords external memory addressable and the 32 general purpose I/O pins permit to build a DSP-system avoiding the usage of an additional microcontroller.

The presence of serial and parallel interfaces allows easy connection with external devices including CODECs, DSPs, microprocessors and personal computers.

In particular, the debug/JTAG interface permits the on-chip emulation of the firmware developed. Further, the presence of the timers and watchdog block makes TDA7590 suitable for PWM processing and allows the integration of a system watchdog.

	Order code	Package	Packing
	E-TDA7590	TQFP144 (20x20x1.0 exposed pad down)(1)	Tray
	E-TDA7590TR		Tape and reel
	1. In ECOPACK® package (see Section 9: Package information on page 40).
	January 2009	Rev 2	1/42
			www.st.com

Contents	TDA7590

Contents

1	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. 6
2	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			7
	2.1	Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		7
	2.2	Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
	2.3	Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		13
3	Key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			14
	3.1	Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		14
		3.1.1	CODEC (ADC/DAC) test description . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
4	Electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			16
	4.1	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
	4.2	Electrical characteristics for I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .		16
5	24 bit DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			17
6	Memories . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
7	DSP peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			19
	7.1	Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
	7.2	Serial communication interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
	7.3	I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
	7.4	Host interface (HI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		19
	7.5	ESSI . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	7.6	EOC . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	20
	7.7	Timers and watchdog block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
	7.8	PLL . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
	7.9	CODEC cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		21
8	Appendix 1 . .		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
	8.1	Benchmarking program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		22

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TDA7590		Contents
9	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 40
10	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . 41

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List of tables	TDA7590

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4. Key parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 6. Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 7. General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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TDA7590	List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. TQFP144 mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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Block diagram	TDA7590

1 Block diagram

Figure 1. Block diagram

	2 Channel			ESSI/12C	SCI	HOST i/f	Triple
	Codec		ESSI
							Timer
	SAI/CCT
	rclk	sclk
	PLL Clock				YRAM
	Oscillator
					68/64/56/48K x 24
					XRAM		FLEX RAM
					4/8/16/14K x 24		40K x 24
					PRAM
	PROM				16K x 24
						Expansion	EDB
						Port	EAB
		DDB	DAB YDB YAB XDB XAB	PAB
	EBUG		MOZART core
	Interface		120MIPs, 32 GPIOs
	6/42

TDA7590	Pin description

2 Pin description

2.1Pin connection

Figure 2.	Pin connection (top view)
		SC11 SC12	TDO TMS			TCK TDI		TRSTN	IRQD	IRQC	IRQB	IRQA	DB23	DB22	DB21	IOVSS	IOVDD	DB20 COREVSS		COREVDD DB19		DB18	DB17	DB16	DB15	IOVSS IOVDD		DB14	DB13	DB12	DB11	DB10	DB9	IOVSS	IOVDD	DB8	DB7
		143		141		139		137		135		133		131		129		127		125		123		121		119		117		115		113		111		109
		144	142		140		138		136		134		132		130		128		126		124		122		120		118		116		114		112		110
SRD1		1																																			108	DB6
STD1		2																																			107	DB5
SC02		3																																			106	DB4
SC01		4																																			105	DB3
DE_N		5																																			104	COREVSS
NMI		6																																			103	COREVDD
SRD0		7																																			102	DB2
IOVDD		8																																			101	DB1
IOVSS		9																																			100	DB0
STD0		10																																			99	AB19
SC10		11																																			98	AB18
SC00		12																																			97	AB17
RXD		13																																			96	AB16
TXD		14																																			95	AB15
SCLK		15																																			94	AB14
SCK1		16																																			93	AB13
SCK0		17																																			92	AB12
RESET		18																																			91	IOVSS
SCANEN		19																																			90	IOVDD
TESTEN		20																																			89	AB11
COREVDD		21																																			88	AB10
COREVSS		22																																			87	COREVSS
TIO0		23																																			86	COREVDD
VSSSUB		24																																			85	AB9
DAC1		25																																			84	AB8
DACOM		26																																			83	AB7
DACOP		27																																			82	AB6
REF0		28																																			81	IOVSS
CODEC_VDD		29																																			80	IOVDD
CODEC_VSS		30																																			79	AB5
ADC1		31																																			78	AB4
ADCOM		32																																			77	AB3
ADCOP		33																																			76	AB2
IOVDD		34																																			75	IOVSS
IOVSS		35																																			74	IOVDD
EXTDACLK		36																																			73	AB1
		37		39		41		43		45		47		49		51		53		55		57		59		61		63		65		67		69		71
		38		40		42		44		46		48		50		52		54		56		58		60		62		64		66		68		70			72
		XTO XTI		VDD PLL	VSS PLL	HDS	HRW	HACK	HREQ	IOVDD	IOVSS	HCS	HA9	HA8	HAS	HAD7	HAD6	HAD5	HAD4	COREVDD	COREVSS	HAD3	HAD2	HAD1	HAD0	AA3	AA2	BR	BB	IOVDD	IOVSS	WEN	OEN	AA1	AA0	BG	AB0
																																						7/42

Pin description	TDA7590

2.2Pin function

Table 2.		Pin function
N°		Name	Type	Description
1		SRD1/TI02	I/O	Serial receive data. Serial input data for receiver. Timer 2 input/output.
2		STD1	I/O	Serial transmit data. Serial output data from transmitter.
3		SC02	I/O	Serial control 2.Transmitter frame sync only in asynchronous mode,
				transmitter and receiver frame sync in synchronous mode.
4		SC01	I/O	Serial control 1. Receive frame sync in asynchronous mode, output
				from transmitter 2 or serial flag 1 in synchronous mode.
5		DE_N	I/O	Test data output (input/output). Debug request input and acknowledge output.
6		NMI_N	I	Non-maskable interrupt/ PINIT. Used to enable the PLL during RESET
				and as a non-maskable interrupt at all other times.
7		SRD0	I/O	Serial receive data. Serial input data for receiver.
8		IOVDD	I	IO power supply.
9		IOVSS	I	IO ground.
10		STD0	I/O	Serial Transmit Data. Serial output data from transmitter.
				ESSI1 serial control 0. Receive clock in asynchronous mode, output from
11		SC10/SCL	I/O	transmitter or serial flag in synchronous mode.
				I2C SCL serial clock line.
12		SC00	I/O	Serial control 0. Receive clock in asynchronous mode, output from transmitter
				1 or serial flag 0 in synchronous mode.
13		RXD	I/O	SCI receive data. Receives byte-oriented serial data.
14		TXD	I/O	SCI read enable. Transmits serial data from SCI transmit shift register.
				SCI serial clock. Input or output clock from which data is transferred in
15		SCLK	I/O	synchronous mode and from which the transmit and/or receive baud rate is
				derived in asynchronous mode.
				Serial clock. Serial bit clock for transmitter only in asynchronous mode, serial
16		SCK1/TI01	I/O	bit clock for both receiver and transmitter in synchronous mode.
				Timer 1 input/output.
17		SCK0	I/O	Serial clock. Serial bit clock for transmitter only in asynchronous mode, serial
				bit clock for both receiver and transmitter in synchronous mode.
18		RESETN	I	System reset. A low level applied to RESET_N input initializes the IC.
19		SCANEN	I	SCAN enable. When active with TESTEN also active, controls the shifting of
				the internal scan chains.
				Test enable. When active, puts the chip into test mode and muxes the XTI
20		TESTEN	I	clock to all flip-flops. When SCANEN is also active, the scan chain shifting is
				enabled.
21		COREVSS	I	Core ground.
22		COREVDD	I	Core power supply.
23		TIO0	I/O	Timer 0 input/output.
24		VSSSUB	I	Analog substrate isolation.

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TDA7590					Pin description
Table 2.		Pin function	(continued)
N°		Name		Type	Description
25		DAC1		O	DAC1 left single analog output.
26		DAC0M		O	DAC0 negative right differential analog output.
27		DAC0P		O	DAC0 positive right differential analog output.
28		CODEC_VSS		I	Voltage ground.
29		REF0		I	Codec power supply.
30		CODEC_VDD		I	Codec reference.
31		ADC1		I	ADC1 left single analog input.
32		ADC0M		I	DAC0 negative right differential analog inputs.
33		ADC0P		I	DAC0 positive right differential analog inputs.
36		EXTDACLK		I	External DAC clock. Optional external clock source from which LRCLK and
					SCLK can be generated.
37		XTI		I	Crystal oscillator input. External clock input or crystal connection.
38		XTO		O	Crystal oscillator output. Crystal oscillator output drive.
39		PLL_VDD		I	PLL power supply.
40		PLL_VSS		I	PLL ground input.
					Host data strobe. Polarity programmable Host data strobe input for single
41		HDS		I/O	strobe mode. Polarity programmable Host write strobe input for double strobe
					mode.
42		HRW		I/O	Host read/write. Host read/write for single strobe bus mode.
					Polarity programmable Host read data strobe for double strobe mode.
					Host acknowledge. Polarity programmable host interrupt acknowledge for
43		HACK		I/O	single host request mode. Polarity programmable host receive request
					interrupt for double host request mode.
					Host request. Polarity programmable host request interrupt for single host
44		HREQ		I/O	request mode. Polarity programmable host transfer request interrupt for
					double host request mode.
45		IOVDD		I	IO power supply.
46		IOVSS		I	IO ground.
					Host chip select. Polarity programmable host chip select for non-multiplexed
47		HCS		I/O	mode.
					Host address Line 10 for multiplexed mode.
48		HA9		I/O	Host address 9. Address line 9 in multiplexed mode otherwise address line 2
					in non-multiplexed mode.
49		HA8		I/O	Host address 8. Address line 8 in multiplexed mode otherwise address line 1
					in non-multiplexed mode.
50		HAS		I/O	Host address strobe. Address strobe for multiplexed bus or Address 0 for non
					multiplexed.
51		HAD[7]		I/O	Host 8-bit data line 7. Host data bus and/or address lines when in multiplexed
					mode.

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Pin description					TDA7590
Table 2.		Pin function	(continued)
N°		Name		Type	Description
52		HAD[6]		I/O	Host 8-bit data line 6. Host data bus and/or address lines when in multiplexed
					mode.
53		HAD[5]		I/O	Host 8-bit data line 5. Host data bus and/or address lines when in multiplexed
					mode.
54		HAD[4]		I/O	Host 8-bit data line 4. Host data bus and/or address lines when in multiplexed
					mode.
55		COREVDD		I	Core power supply.
56		COREVSS		I	Core ground.
57		HAD[3]		I/O	Host 8-bit data line 3. Host data bus and/or address lines when in multiplexed
					mode.
58		HAD[2]		I/O	Host 8-bit data line 2. Host data bus and/or address lines when in multiplexed
					mode.
59		HAD[1]		I/O	Host 8-bit data line 1. Host data bus and/or address lines when in multiplexed
					mode.
60		HAD[0]		I/O	Host 8-bit data line 0. Host data bus and/or address lines when in multiplexed
					mode.
61		AA[3]		O	Address attributes line 3.Port A address attributes/chip select pins with
					programmable polarity.
62		AA[2]		O	Address attributes line 2.Port A address attributes/chip select pins with
					programmable polarity.
63		BR_N		O	Bus request. Asserted when port A requires bus mastership to perform off-
					chip accesses.
64		BB_N		I/O	Bus busy. Asserted by port A when bus_busy_in_n is negated and BG_N is
					asserted.
65		IOVDD		I	IO power supply.
66		IOVSS		I	IO ground.
67		WEN_N		O	Write enable.
68		OEN_N		O	Output enable.
69		AA[1]		O	Address attributes line 1.Port A address attributes/chip select pins with
					programmable polarity.
70		AA[0]		O	Address attributes line 0.Port A address attributes/chip select pins with
					programmable polarity.
					Bus grant. When asserted, Port A becomes the bus master elect. Bus
71		BG_N		I	mastership
					is attained when bus busy is negated by the current bus master.
72		AB[0]		O	Address bus line 0. Port A external address bus.
73		AB[1]		O	Address bus line 1. Port A external address bus.
74		IOVDD		I	IO power supply.
75		IOVSS		I	IO ground.
76		AB[2]		O	Address bus line 2. Port A external address bus.

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TDA7590					Pin description
Table 2.		Pin function	(continued)
N°		Name		Type	Description
77		AB[3]		O	Address bus line 3. Port A external address bus.
78		AB[4]		O	Address bus line 4. Port A external address bus.
79		AB[5]		O	Address bus line 5. Port A external address bus.
80		IOVDD		I	IO power supply.
81		IOVSS		I	IO ground.
82		AB[6]		O	Address bus line 6. Port A external address bus.
83		AB[7]		O	Address bus line 7. Port A external address bus.
84		AB[8]		O	Address bus line 8. Port A external address bus.
85		AB[9]		O	Address bus line 9. Port A external address bus.
86		COREVDD		I	Core power supply.
87		COREVSS		I	Core ground.
88		AB[10]		O	Address bus line 10. Port A external address bus.
89		AB[11]		O	Address bus line 11. Port A external address bus.
90		IOVDD		I	IO power supply.
91		IOVSS		I	IO ground.
92		AB[12]		O	Address bus line 12. Port A external address bus.
93		AB[13]		O	Address bus line 13. Port A external address bus.
94		AB[14]		O	Address bus line 14. Port A external address bus.
95		AB[15]		O	Address bus line 15. Port A external address bus.
96		AB[16]		O	Address bus line 16. Port A external address bus.
97		AB[17]		O	Address bus line 17. Port A external address bus.
98		AB[18]		O	Address bus line 18. Port A external address bus.
99		AB[19]		O	Address bus line 19. Port A external address bus.
100		DB[0]		I/O	Address bus 0. Port A external data bus.
101		DB[1]		I/O	Address bus 1. Port A external data bus.
102		DB[2]		I/O	Address bus 2. Port A external data bus.
103		COREVDD		I	Core power supply.
104		COREVSS		I	Core ground.
105		DB[3]		I/O	Data bus line 3. Port A external data bus.
106		DB[4]		I/O	Data bus line 4. Port A external data bus.
107		DB[5]		I/O	Data bus line 5. Port A external data bus.
108		DB[6]		I/O	Data bus line 6. Port A external data bus.
109		DB[7]		I/O	Data bus line 7. Port A external data bus.
110		DB[8]		I/O	Data bus line 8. Port A external data bus.
111		IOVDD		I	IO Power Supply.

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Pin description					TDA7590
Table 2.		Pin function	(continued)
N°		Name		Type	Description
112		IOVSS		I	IO Ground.
113		DB[9]		I/O	Data Bus line 9. Port A external data bus.
114		DB[10]		I/O	Data bus line 10. Port A external data bus.
115		DB[11]		I/O	Data bus line 11. Port A external data bus.
116		DB[12]		I/O	Data bus line 12. Port A external data bus.
117		DB[13]		I/O	Data bus line 13. Port A external data bus.
118		DB[14]		I/O	Data bus line 14. Port A external data bus.
119		IOVDD		I	IO power supply.
120		IOVSS		I	IO Ground.
121		DB[15]		I/O	Data bus line 15. port a external data bus.
122		DB[16]		I/O	Data bus line 16. Port A external data bus.
123		DB[17]		I/O	Data bus line 17. Port A external data bus.
124		DB[18]		I/O	Data bus line 18. Port A external data bus.
125		DB[19]		I/O	Data bus line 19. Port A external data bus.
126		COREVDD		I	Core power supply.
127		COREVSS		I	Core ground.
128		DB[20]		I/O	Data bus line 20. Port A external data bus.
129		IOVDD		I	IO power supply.
130		IOVSS		I	IO ground.
131		DB[21]		I/O	Data bus line 21. Port A external data bus.
132		DB[22]		I/O	Data bus line 22. Port A external data bus.
133		DB[23]		I/O	Data bus line 23. Port A external data bus.
134		IRQA		I	Interrupt request line/ Mode control. Used as mode control during RESET
					and as interrupt request line at all other times.
135		IRQB		I	Interrupt request line/ Mode control. Used as mode control during RESET
					and as interrupt request line at all other times.
136		IRQC		I	Interrupt request line/ Mode control. Used as mode control during RESET
					and as interrupt request line at all other times.
137		IRQD		I	Interrupt request line/ Mode control. Used as mode control during RESET
					and as interrupt request line at all other times.
138		TRSTN		I	Test reset. JTAG output pin for serial data out from debug interface.
139		TDI		I	Test data input. JTAG input pin for serial data input for debug interface.
140		TCK		I	Test clock. JTAG input pin for clocking debug interface.
141		TMS		I	Test mode select. JTAG input pin for control of TAP Controller of debug
					interface.
142		TDO		O	Test data output. JTAG output pin for serial data out from debug interface.

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TDA7590					Pin description
Table 2.		Pin function	(continued)
N°		Name		Type	Description
143		SC12		I/O	Serial control 2.Transmitter frame sync only in asynchronous mode,
					transmitter and receiver frame sync in synchronous mode.
					Serial control 1. Receive frame sync in asynchronous mode,
144		SC11/SDA		I/O	output from transmitter 2 or serial flag 1 in synchronous mode.
					I2C SDA. Serial data line.

2.3Thermal data

Table 3.	Thermal data
Symbol	Parameter	Value	Unit
Rth-j-pins	Thermal resistance junction to pins	32	°C/W

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