influences
– Adjacent channel mute
– Fully electronic alignment
– Independent weather band input
– All functions I
Description
The TDA7541B is a high performance tuner
circuit with stereo decoder for AM/FM car radio. It
contains a mixer, IF amplifier, demodulator for AM
and FM, stereo decoder, quality detection, ISS
filter and PLL synthesizer with IF counter on a
single chip. Use of BICMOS technology allows the
implementation of several tuning functions and a
minimum of external components.
measured with: 90 % mono signal; 9 % pilot signal; fm=1 kHz; 1% spurious signal (f
5. All thresholds are measured in test mode at the quality output. The thresholds are calculated by V
be adjusted by applying a 150 kHz sinewave at MPXIN.
ƒs110 k Hz2 38 kHz×()–()=;=
ƒs186 k H z5 38 k Hz×()–()=;=
= 110 kHz or 186 kHz, unmodulated)
S
NBTH
- V
PEAK
. V
PEAK
can
Doc ID 16048 Rev 123/77
Electrical specifications and characteristicsTDA7541B
3.3.5 PLL section
T
V
amb
MPX
= 25 °C, V
= 500 mV
= V
CC1
mono, f = 1 kHz, de-emphasis τ = 50 µs, in application circuit, unless
Internal unfiltered field
strength threshold for
SSTOP=HIGH
SSTH, FMON=0
SL = “011”
1.2-4.8V
Output Voltage lowSWM”1”,SW”0”, I24 = -5 µA-0.350.5V
Output Voltage highSWM”1”,SW”1”-VCC-1-V
Output leakage currentV22=5 V-0.5-0.5μA
Output Current, sink---7mA
Output Voltage lowSWM”0”,SW”0”, I22=0 µA-0.10.3V
Output Voltage highSWM”0”,SW”1”, I22=1 mA-VCC-1-V
Output Current, sinkV22=5 V-7--mA
Doc ID 16048 Rev 125/77
Functional descriptionTDA7541B
4 Functional description
4.1 FM part
4.1.1 Mixer 1 AGC and IF amplifier
FM quadrate I/Q-mixer converts FM RF to IF1 of 10.7 MHz. The mixer provides inherent
image rejection and wide dynamic range with low noise and large input signal performance.
For accurate image rejection the phase-error of I/Q can be compensated by software (PH).
It is capable of tuning the US FM, US weather (dedicated WB input), Europe FM, Japan FM
and East Europe FM bands:
–US FM = 87.9 to 107.9 MHz
–US weather = 162.4 to 162.55 MHz
–Europe FM = 87.5 to 108 MHz
–Japan FM = 76 to 91 MHz
–East Europe FM = 65.8 to 74 MHz
The AGC operates on different sensitivities and bandwidths in order to improve the input
sensitivity and dynamic range. AGC thresholds are programmable by software (RFAGC,
IFAGC, and KAGC). The output signal is a controlled current for pin diode attenuator.
A 10.7 MHz programmable amplifier (IFG) correct the IF ceramic insertion loss and the
costumer level plan application.
4.1.2 Mixer2, limiter, FM demodulator and spike cancellation
In the 2nd mixer stage the first 10.7 MHz IF is converted into the second 450 kHz IF.
The fully integrated sample and hold FM demodulator including spike cancellation (DSB)
converts the IF signal from the 450 kHz limiter (limiter gain 80 dB typ.) to the FM multiplex
output signal with very low distortion.
The sensitivity of spike blanking can be set via I
2
C bus.
4.1.3 Quality detection and ISS
Field strength
Parallel to mixer2 input a 10.7 MHz limiter generates a signal for digital IF counter and field
strength voltage V
adjacent channel and multi path detection and is available at PIN27 (FSU) in a range of 0 V
to 5 V. The offset and slope of FSU signal can be adjusted via I
application adaptation.
The voltage VFSWO including offset adjust is externally filtered at PIN37 (FSWO) and used
for weak signal mute function and generation of ISS filter control signals in weak signal
condition. It is possible to combine the IF counter result with this voltage VFSWO by
programmable comparator threshold (SSTH).
. This internal voltage V
FSUint
is used for AM IF noise blanker,
FSUint
2
C bus (FSWO and SL) for
26/77Doc ID 16048 Rev 1
TDA7541BFunctional description
Adjacent channel detector
The input of the adjacent channel detector is AC coupled from VFSW. A programmable
high-pass or band-pass (ACF) as well as rectifier generate a signal which is compared with
adjustable threshold (ACTH). The output signals of this comparator is controlling the charge
and discharge of the external capacitor at PIN30 or PIN31 (dependent on SEEK) with
programmable discharge current (TISS). The level at PIN30/31 is used to generate the two
digital signal ac and ac+ for ISS control. The adjacent channel information behind the
rectifier is available as analog output signal at the multiplexer output (PIN23).
Multipath detector
The input of the multi path detector is AC coupled from internal VFSW too. After filtering with
19 kHz band-pass and rectifying, this voltage is compared with an adjustable threshold
(MPTH). The output signal of this comparator can be used to switch off the adjacent channel
detection. This influence is selectable by I
The multi path information behind the rectifier is available as analog output signal at
multiplexer output (PIN23).
2
C bus (MPENA).
450 kHz IF narrow band pass filter (ISS filter)
The device has an additional 450 kHz IF narrow band-pass filter for suppression of noise
and adjacent channel signal influences. This narrow filter has three switchable bandwidths,
narrow range of 80 kHz, mid range of 120 kHz and 22 kHz for weather band information.
Without ISS (Intelligent Selectivity System) filter the IF bandwidth (wide range) is defined
only by ceramic filter chain and mixer2 bandwidth. The filter is located between mixer2
output buffer and 450 kHz limiter stage. The centre frequency is matched to the
demodulator centre frequency.
Deviation detector
In order to avoid distortion in audio output signal the narrow ISS filter is switched OFF if over
deviation is present. Hence the demodulator output signal is detected. After AC coupling,
low-pass filtering and peak rectifying this signal is charging/discharging the external DEVTC
capacitor by an IIC programmable charge/discharge current (TDEV). The voltage at DEVTC
is compared with adjustable thresholds (DWTH, DTH) and generates two digital control
signals (dev, dev+). For weak signal condition the deviation threshold depends on FSWO.
ISS switch logic
All digital control signals coming from adjacent channel detector, deviation detector and
weak signal mute are acting via switching matrix on ISS filter switch. IF2 narrow band-pass
switch mode is controlled also by software (ISSENA, ISSON, WBON, ISSBW, and BWDEF).
The switching of the IF band-pass is also possible to influence by external manipulation of
DC voltage at PIN30.
The influence of the ISS software control on the functionality of the ISS filter is described in
Ta bl e 1 0 . The value “X” for the control bit means the bit does not influence the filter control in
this condition.
Doc ID 16048 Rev 127/77
Functional descriptionTDA7541B
Table 10.ISS filter control by I
I2C control bits
ISSENA adr4/d2
ISSON adr11/d0
ISSBW adr7/d0
WBON adr11/d1
ISSM adr9/d7
BWDEF adr7/d1
0XXXXXISS filter is switched off (bypass)
110XXX ISS filter is in manual control mode, Band width is 120 kHz
111XXX ISS filter is in manual control mode, Band width is 80 kHz
11X1XX
10XX00
10XX10
100X01
100X11
101X01
101X11
ISS filter is in manual control mode, Band width is 22 kHz
This setting must be used for weather band application
ISS filter is in automatic control mode
Filter activation and band width defined by control table mode1
ISS filter is in automatic control mode
Filter activation and band width defined by control table mode2
ISS filter is in automatic control mode
Filter activation defined by control table mode1
band width fixed to 120 kHz
ISS filter is in automatic control mode
Filter activation defined by control table mode2
band width fixed to 120 kHz
ISS filter is in automatic control mode
Filter activation defined by control table mode1
band width fixed to 80 kHz
ISS filter is in automatic control mode
Filter activation defined by control table mode2
band width fixed to 80 kHz
2
C bus
Notes
Description of I2C bits:
ISSENA
ISS filter enable
“1”: ISS filter control enabled
“0”: ISS filter is switched off (bypass of the filter, wide)
ISSON
ISS filter control mode
“1”: ISS filter is in manual control mode (switched "ON"); the bits ISSBW and WBON are
defining the bandwidth
“0”: ISS filter is in automatic control mode according to mode1/2 table
ISSBW
ISS filter band width
“1”: 80 kHz
28/77Doc ID 16048 Rev 1
TDA7541BFunctional description
“0”: 120 kHz
The bit has only influence if bit BWENA is “1”, or if bit ISSON is “1”
WBON
Weather band enable
“1”: Weather band enable (FMmixer1 is disabled, Wbmixer1enabled, stereo decoder gain
26dB, ISS filter bandwidth 22 kHz, IF2Q=”00”)
“0”: Weather band disable
For weather band enable it is need to set ISSON = “1”
ISSM
ISS filter application mode
“0”: ISS filter application mode1
“1”: ISS filter application mode2
If BWENA is “1” the band width is always switched to ISSBW in case of ISS filter activated
BWDEF
Enable bit ISSBW for ISS filter band with control
“1”: ISS filter is internally controlled, but band width is defined by bit ISSBW
“0”: ISS filter is internally controlled, band width is defined by mode1/2 table
For the internal control two application modes are available (ISSM). The conditions and
settings are described in Ta bl e 1 1 and Tab le 1 2.
4.1.4 Block diagram quality detection principle
(without overdeviation correction)
Table 11.Internal ISS control signals
SignalLowHigh
AcNo adjacent channelAdjacent channel present
ac+No strong adjacent channelAdjacent channel higher as ac
Sm
DevDeviation lower as threshold DWTHDeviation higher as threshold DWTH
dev+Deviation lower as threshold DTH*DWTHDeviation higher as threshold DTH*DWTH
IntonISS filter off by logic (wide)ISS filter on by logic
Under strong adjacent channel it is possible to have disturbance of the audio signal created
by interference between ISS filter control (deviation detection) and adjacent channel mute.
The control bits SACCE and SACCT can be used to avoid this disturbance. If the function is
activated (SACCE = “1”) the IF counter together with the internal field strength is used to
suppress a malfunction of deviation detection. The bit SACCT is changing the sensitivity of
the SACC block (SACCT = “1” means higher sensitivity).
Figure 10 shows the ISS block diagram including the SACC function.
Note:The IF counter must be switched ON if this function is used (Addr25D4 = “1”)
4.1.6 Weak signal mute
The filtered field strength signal (FSWO) is the reference for soft slope mute control in weak
signal condition to eliminate audible effects. The start point and mute depth are
programmable (WMTH, WMD) in a wide range. These settings together with FSWO bits are
influencing the weak signal mute behavior. The time constant is defined by external
capacitance at PIN 42. Additional adjacent channel mute function is supported. A high pass
filter with -3 dB threshold frequency of 100 kHz, amplifier and peak rectifier generates an
adjacent noise signal from Demodulator output. This value is compared with adjustable
threshold (ACMTH). For present strong adjacent channel the MPX signal is additional
attenuated (ACMD) and has the same time constant as weak signal mute.
30/77Doc ID 16048 Rev 1
TDA7541BFunctional description
4.1.7 Weather band input
If the weather band input is used the chip must be set in FM mode (FMON). In addition to
that the ISS filter must be switched ON (ISSENA=”1”), mixer2 quality factor must be set to
IF2Q=”00” and the ISS filter must be set in manual control mode (ISSON=”1”).
The bit WBON is:
●activating the WB input
●switching the ISS filter in WB mode (22 kHz band width)
●switching the stereo decoder InGain to 26 dB.
In order to increase the selectivity in weather band mode the AM 450kHz ceramic filter can
be used in series to the ISS filter by activating ADSEL (please refer to Figure 10, ISS block
diagram and Section 4.2.1, usage of bit ADSEL).
4.2 AM section
signals, narrow band information (DAGC) referred to PIN 56, up conversion signal (IFAGC)
at PIN 61 and wide band information (RFAGC) at PIN 3.This gain control gives two output
signals. The first one is a current for pin diode attenuator and the second one is a voltage for
preamplifier. Time constant of RF and IF-AGC is defined by internal 100 kΩ resistor and
external capacitor at PIN 54. The intervention points for AGC (DAGC, IFAGC and RFAGC)
are programmable by software. The oscillator frequency for upconversion-mixer1 is
generated by dividing the VCO frequency after VCO divider (VCOD) and AM pre-divider
(AMD).
Two 10.7 MHz ceramic filters before mixer2 input increase 900 kHz attenuation.
The AMIF2 block contains mixer2, IF2 amplifier, demodulator and AGC2 The AM/FM mixer2
converts 10.7 MHz IF1 into 450 kHz IF2. Mixer2 output passes a 450 kHz narrow band filter
(LC plus ceramic filter). LC centre frequency is adjustable by I
2
C bus (IF2A). The following
IF2 amplifier provides signal for fully integrated demodulator. If the bit ADSEL is activated,
the ISS filter is inserted between IF2 amplifier and demodulator in order to increase the
selectivity (please refer to Figure 11, AM path block diagram and Section 4.2.1, usage of bit
ADSEL).
Mixer2 and IF2 amplifier have a 2-stage AGC with careful take-over behavior to keep
distortion low. The IF2 AGC range is about 55 dB.
The input signal of IF2 amplifier is used in limiter circuit for in-band level detection. The
electrical characteristics are described in FM section.
The demodulator is a peak detector to generate the audio output signal.
At the MUX output the AMIF stereo is available.
AM IF noise blanker
In order to remove in AM short spikes a noise cancellation conception is used in 450 kHz IF
AM level. The advantage is to avoid long narrow AGC- and demodulator- time constants,
which enlarge spike influences on audio signal and makes difficult to remove it in audio path.
The 10.7 MHz AM IF signal behind IF1 amplifier generates via limitation an unweighted field
strength signal including slope of noise spike. The comparison of this detected slope
between fast and slow rectifier ignores audio modulation whereby the threshold of slow
Doc ID 16048 Rev 131/77
Functional descriptionTDA7541B
rectifier is programmable (AINBT). A comparator activates a pulse generator. The duration
of this pulse is software programmable (AINT) and is smooth blanking out the spikes in mixer2.
4.2.1 Usage of control bit ADSEL (Addr23D7)
The control bit ADSEL can be used to increase the selectivity of the application in AM mode
and WB mode. In FM it has no function. Table 12 shows the functionality of the control bit.
Table 13.Usage of ADSEL
FMONWBONADSEL
Note
Addr4D7 Addr11D1 Addr23D7
10XStandard FM mode
Weather band mode using 450 kHz ceramic filter;
ISS filter must be manually switched on in order to limit the band
11 0
11 1
000Standard AM mode
00 1
width at 450 kHz IF (ISSENA/ISSON = "1");
450 kHz ceramic filter is switched in series to ISS filter to
increase selectivity
Standard weather band mode;
ISS filter must be manually switched on in order to limit the band
width at 450 kHz IF (ISSENA/ISSON = "1")
AM mode using ISS filter;
ISS filter (22 kHz band width) is switched in series to the 450 kHz
ceramic filter
01 XNot allowed
4.3 Stereo decoder
4.3.1 Decoder
The stereo decoder-part of the TDA7541B contains all functions necessary to demodulate
the MPX-signal, like pilot tone-dependent MONO/STEREO switching as well as the stereo
blend and high cut.
Adaptations like programmable input gain, roll-off compensation, selectable de-emphasis
time constant and a programmable field strength input allow easy adoption to different
applications.
th
The 4
and noise and acts as an anti-aliasing filter for the following switch capacitor filters.
Demodulator
In the demodulator block the left and the right channel are separated from the MPX-signal.
In this stage also the 19 kHz pilot tone is canceled. For reaching a high channel separation
the TDA7541B offers an I
compensate the low pass behavior of the tuner section. Within the compensation range an
adjustment to obtain about 40 dB channel separation is possible. The bits for this
adjustment are located together with the level gain adjustment in one byte. This gives the
order input filter has a corner frequency of 80 kHz and is used to attenuate spikes
2
C bus programmable roll-off adjustment, which is able to
32/77Doc ID 16048 Rev 1
TDA7541BFunctional description
possibility to perform an optimization step during the production of the car radio where the
channel separation and the field strength control are trimmed.
In addition to that the FM signal can be inverted.
De-emphasis and high cut
The de-emphasis low pass allows to choose between a time constant of 50 µs/75 µs
(DEEMP). The high cut control range will be in both cases T
cut control range (between VHCHT and VHCLT) the LEVEL signal is converted into a 5-bit
word, which controls the low pass time constant between T
resolution will remain 5 bits referred to the voltage range between the VHCHT- and minimum
VHCLT-values.
The high cut function can be switched off by I
2
C-bus.
Figure 3.Programming of HC filter
High Cut Filter
Time Constant
00
3*T
Deemp
11
HCMax
01
= 2 x T
HC
Deemp
Deemp
...3 x T
. Inside the high
. Thereby the
Deemp
T
Deemp
V
LG
FSTC*
V
HCLT
V
HCHT
In AM mode (FMON = 0) the DEEMP bit together with the AM corner frequency bits (AMCF)
can be used as programmable AM frequency response. The maximum corner frequency is
defined by T
, the minimum is defined by 3 x T
Deemp
For the over all frequency
Deemp
response it is need to take into account the frequency response of the AF output at
MPXOUT and the Stereo decoder demodulator too.
19 kHz PLL and pilot tone detector
The PLL has the task to lock on the 19 kHz pilot tone during a stereo-transmission to allow a
correct demodulation. The included pilot tone-detector enables the demodulation if the pilot
tone reaches the selected pilot tone threshold VPTHST. Two different thresholds are
available. The status of the detector output can be checked by reading the status byte of the
TDA7541B via I
2
C bus or by reading the STEREO status at MUX pin23.
Field strength control
The field strength input is used to control the high cut- and the stereo blend-function. In
addition the signal can be also used to control the noise blanker thresholds and as input for
the multipath detector.
Level input and gain
As level input for the stereo decoder is used the FSU voltage (pin 27). Applying a capacitor
at FSTC (pin28) a desired time constant can by reached together with the internal resistor of
Doc ID 16048 Rev 133/77
Functional descriptionTDA7541B
10k between FSU pin and FSTC pin. The second stage is a programmable gain stage to
adapt the VFSTC signal internally. The gain (LG) is widely programmable in 16 steps from
0 dB to 8.25 dB (step=0.55dB).
T
hese 4 bits are located together with the Roll-Off
compensation bits in byte 14 to simplify a possible adaptation during the production of the car radio.
Stereo blend control
The stereo blend control block converts the internal LEVEL-voltage into a demodulator
compatible analog signal, which is used to control the channel separation between 0dB and
the maximum separation. Internally this control range has a fixed upper limit, which is the
internal reference voltage VREF1. The lower limit can be programmed between 29 and
58 % of VREF1 in 4 % steps. In order to adjust the external voltage VFSTC to the internal
control range two values must be defined: the Level gain LG and VSBL. Full channel
separation is reached when the internal level voltage (VST) becomes bigger than VREF1.
Therefore the following equation can be used to estimate the gain:
LG
The MONO-voltage VMO (0dB channel separation) can be chosen selecting SBC.
The high cut control set-up is similar to the stereo blend control set-up: the starting point
VHCH can be set with 2 bits to be 42, 50, 58 or 66 % of VREF1 whereas the range can be
set to be 11, 18.3, 25.7 or 33 % of VHCH.
4.3.2 Noise blanker
In the automotive environment spikes produced for example by the ignition or the wipermotor disturb the MPX-signal. The aim of the noise blanker part is to cancel the audible
influence of the spikes. Therefore the output of the stereo decoder is held at the actual
voltage for a time between 22 ms and 38 ms (programmable).
In a first stage the spikes must be detected but to avoid a wrong triggering on high
frequency (white) noise a complex trigger control is implemented. Behind the trigger stage a
pulse former generates the "blanking"-pulse. An own biasing circuit supplies the noise
blanker in order to avoid any cross talk to the signal path.
34/77Doc ID 16048 Rev 1
TDA7541BFunctional description
Trigger p ath
The incoming FM demodulator output signal is taken in front of the weak signal mute, high
pass filtered, amplified and rectified. This second order high pass filter has a cornerfrequency of 140 kHz. The rectified signal, VRECT, is low pass filtered to generate a signal
called V
resulting voltage can be adjusted by use of the noise rectifier discharge current. The V
voltage is fed to a threshold generator, which adds to the V
VTH. Both signals, V
. Noise with a frequency above 140 kHz increases the V
PEAK
RECT
and V
+VTH are fed to a comparator, which triggers a re-
PEAK
voltage. The
PEAK
voltage a DC threshold
PEAK
PEAK
triggerable monoflop. The output of the monoflop activates the sample-and-hold circuit in
the signal path for the selected duration.
Automatic noise controlled threshold adjustment
There are mainly two independent possibilities for programming the trigger threshold:
1. Low threshold in 8 steps (NBLT)
2. Noise adjusted threshold in 4 steps (NBCT).
The low threshold is active in combination with a good MPX signal without any noise; the
V
voltage is less than 1V. The sensitivity in this operation is high.
PEAK
If the MPX signal is noisy (low field strength) the V
noise, which is also rectified. With increasing of the V
increases, too. This particular gain is programmable in 4 steps (NBCT).
voltage increases due to the higher
PEAK
voltage the trigger threshold
PEAK
Figure 5.Adaptive threshold control of noise blanker
Besides the noise controlled threshold adjustment there is an additional possibility for
influencing the noise blanker trigger threshold using the bits NBFC. This influence depends
on the stereo blend control. The point where the MPX signal starts to become noisy is fixed
by the RF part. This point is also the starting point of the normal noise-controlled trigger
adjustment. But in some cases the noise blanker can create a wrong triggering, which
create distortion, already in the region of mono/stereo transition. Therefore an opportunity to
control the V
voltage by the stereo blend function it is implemented.
If the system is tuned to stations with a high deviation the noise blanker can trigger on the
higher frequencies of the modulation. To avoid this wrong behavior, which causes noise in
the output signal, the noise blanker offers a deviation-dependent threshold adjustment. By
rectifying the MPX signal a further signal representing the actual deviation is obtained. It is
used to increase the PEAK voltage. The gain of this circuit is programmable in 3 steps
(NBDC) of the stereo decoder-byte (the first step turns off the detector).
Figure 7.Deviation controlled threshold adjust
V
PEAK
[V ]
OP
00
2.0
1.5
1.0
0.8
2032.54575
01
10
11
Detector off
DEVIATION [KHz]
Multipath influence on noise blanker
To react on high repetitive spikes caused by a Multipath-situation, the discharge-time of the
V
voltage can be decreased depending on the voltage-level at Pin MPTC. There are
PEAK
two ways to do this.
a) Switch on the linear influence of the Multipath-Level on the PEAK-signal. In this
case the discharge slew rate is 1 V/ms. The slew rate is measured with R
= infinite and VMPTC = 2.5 V
b) Activate a function, which switches to the 18k discharge resistor if the Multipath-
Level is below 2.5 V. If multipath influence on noise blanker is switched ON than
MPF bit has to be set to 0.
36/77Doc ID 16048 Rev 1
Discharge
TDA7541BFunctional description
Noise blanker in AM mode
In AM mode the noise blanker is activated if a spike on the audio signal is bigger than a fixed
threshold. In order to blank the whole spike in AM mode the hold time of the S&H circuit is
much longer than in FM mode (64 0µs -1,2 ms). It is not recommended to use the AM noise
blanker without to use the AMIF noise blanker inside the tuner.
4.3.3 Functional description of the multipath detector
Using the internal multi path detector the audible effects of a multi path condition can be
minimized. A multi path condition is detected by rectifying the 19 kHz spectrum in the field
strength signal. An external capacitor is used to define the attack- and decay-times. The
MPTC pin is used as detector output connected to a capacitor. Using this configuration an
external adaptation to the user's requirement is possible without affecting the "normal" field
strength input (FSTC) for the stereo decoder.
To keep the old value of the multi path detector during an alternative frequency jump, the
MPFAST bit can disconnect the external capacitor.
Selecting MPINT the channel separation is automatically reduced during a multipath
condition according to the voltage appearing at the MPTC pin.
To obtain a good multipath performance an adaptation is necessary. Therefore the gain of
the 19 kHz band pass is programmable in four steps (MPG) and the rectifier gain is
programmable in four steps (MPRG). The attack- and decay-times can be set by the
external capacitor value and the multipath detector charge current MPCC.
4.3.4 Quality detector
The TDA7541B offers a quality detector output, which gives a voltage representing the FMreception conditions. To calculate this voltage the MPX-noise and the multipath-detector
output are summed according to the following formula:
The V
V
Qual
signal is described in noise blanker session. The factor 'a' can be programmed
PEAK
0.8 bV
PEAK
0.8–()aV
from 0.6 to 1.05 (QDC) and the factor b can be programmed from 6 dB to 15 dB (QNG). The
quality output voltage can be read at the MUX pin. The MUX pin is a low impedance output
and is able to drive external circuitry as well as simply fed to an AD-converter for RDS
applications.
4.3.5 AFS control and stereo decoder mute
In case of AFS (alternative frequency search) jump it is recommended to set the stereo
decoder in mute condition (SDM) and in addition to set the SEEK mode. Since these two
bits are placed in the first written byte, this can be done in the same write cycle as the PLL
jump. The stereo decoder mute is high impedance mute, which means the charge on the
coupling capacitor will be kept. Simultaneously the pilot detector circuit of the stereo
decoder is switched into hold mode. The SEEK mode is switching the multi path detector
into fast mode. The external capacitor at MPTC is disconnected from multipath detector
which keeps the stereo blend condition, but makes the quality information in fast mode
available at the MUX pin.
–()⋅+⋅⋅=
REF1VMPTC
Doc ID 16048 Rev 137/77
Functional descriptionTDA7541B
4.4 PLL and IF counter section
4.4.1 PLL frequency synthesizer block
This part contains a frequency synthesizer and a loop filter for radio tuning system. Only one
VCO is required to build a complete PLL system for FM world tuning and AM up conversion.
VCO and dividers
The varactor tuned LC oscillator together with the dividers provides the local oscillator signal
for both AM and FM front-end mixers. The VCO has an operating frequency of
approximately 160 MHz to 260 MHz. In FM mode the VCO frequency is divided (VCOD) by
1, 2 or 3. These dividers generate in-phase and quadrature-phase output signals using in
FM mixer for image rejection.
In AM mode the divided VCO frequency is additional pre-divided (AMD) by 4, 6, 8 or 10
dependent on selected AM band.
PLL frequency generation for phase comparison
The VCO divided signals applies a two modulus counter (32/33), which is controlled by a 5bit A-divider. The 5-bit register (PC0 to PC4) controls this divider. In parallel the output of the
swallow counter is connected to an 11-bit B-divider. The 11-bit PC register (PC5 to PC15)
controls this divider. Dividing range behind VCO divider:
ƒ
VCOdiv
Warning:For correct operation: A ≤ 32; B ≥ A
32 B⋅A32++[]ƒ
⋅=
REF
Crystal oscillator
The crystal oscillator provides 10.25 MHz signal for conversion from IF1 to IF2 as well as
switching signals for ISS- and quality detection filter. Furthermore reference dividers
generate from adjustable crystal frequency (XTAL) reference frequencies for the tuning PLL,
IF counter and FM demodulator.
The various reference frequencies f
of PLL (RC) can be chosen by IIC-bus.
REF
Three state phase comparator
The phase comparator generates a phase error signal according to phase difference
between f
SYN
and f
. This phase error signal drives the charge pump current generator.
REF
Charge pump current generator
This system generator signed pulses of current. The phase error signal decides the duration
and polarity of those pulses. The current absolute values are programmable by register ICP.
In lock detector
After reaching a phase difference about lower than 40 ns the inlock detector is automatically
switching the charge-pump in low current mode (LDENA).
38/77Doc ID 16048 Rev 1
TDA7541BFunctional description
Low noise CMOS op-amp
An internal voltage divider at pin 19 connects the positive input of the low noise op-amp. The
charge pump output connects the negative input. This internal amplifier in cooperation with
external components can provide an active filter. The negative input is switchable to two
input pins, to increase the flexibility in application. While the high current mode is activated
LPHC output is switched on.
Antenna DAC
For tuning of FM antenna tank circuit two different modes are available (TVM). One is the
auto-alignment measurement of VCO tuning voltage with offset of 8-bit DAC (TVO). The
other one is an adjustment of 8-bit DAC independent on PLL tracking. For big differences
between VCO tuning voltage and antenna tank control voltage an additional constant offset
voltage can be switched to antenna circuit (TVO+).
4.4.2 IF counter block
The aim of IF counter is it to measure the intermediate frequency of the tuner. The input
signals are the output level of 10.7 MHz IF-limiter in FM and output level of 450 kHz IFlimiter in AM.
The grade of integration is adjustable by different measuring cycle times (IFS). The
tolerance of the accepted count value is adjustable too (EW), to reach an optimum
compromise for search speed and precision of the evaluation.
Sampling timer
A sampling timer generates the gate signal for the main counter. The basically sampling
time are in FM 6.25 kHz (t
asynchronous divider to generate several sampling times.
Intermediate frequency main counter
This counter is an 11 - 21-bit synchronous auto reload down counter. The counter length is
automatic adjusted to the chosen sampling time and the counter mode (FM or AM).
At the start the counter will be loaded with a defined value which is an equivalent to the
divider value (t
If a correct frequency is applied to the IF counter frequency input at the end of the sampling
time the main counter is changing its state. This is detected by control logic and an external
search stop output is changing from LOW to HIGH.
The IF counter is started only by the in lock information from the PLL part.
Sample
x fIF).
4.5 I2C bus interface
The TDA7541B supports the I2C bus protocol. This protocol defines any device that sends
data onto the bus as a transmitter, and the receiving device as the receiver. The device that
controls the transfer is a master and device being controlled is the slave. The master will
always initiate data transfer and provide the clock to transmit or receive operations.
= 160 s) and in AM 1 kHz (t
TIM
= 1 ms). This is followed by an
TIM
Doc ID 16048 Rev 139/77
Functional descriptionTDA7541B
Data transition
Data transition on the SDA line must only occur when the clock SCL is LOW. SDA transitions
while SCL is HIGH will be interpreted as START or STOP condition.
Start condition
A start condition is defined by a HIGH to LOW transition of the SDA line while SCL is at a
stable HIGH level. This "START" condition must precede any command and initiate a data
transfer onto the bus. The device continuously monitors the SDA and SCL lines for a valid
START and will not response to any command if this condition has not been met.
Stop condition
A STOP condition is defined by a LOW to HIGH transition of the SDA while the SCL line is at
a stable HIGH level. This condition terminates the communication between the devices and
forces the bus-interface of the device into the initial condition.
Acknowledge
Indicates a successful data transfer. The transmitter will release the bus after sending 8 bits
of data. During the 9
it receives the eight bits of data.
th
clock cycle the receiver will pull the SDA line to LOW level to indicate
Data transfer
During data transfer the device samples the SDA line on the leading edge of the SCL clock.
Therefore, for proper device operation the SDA line must be stable during the SCL LOW to
HIGH transition.
Device addressing
To start the communication between two devices, the bus master must initiate a start
instruction sequence, followed by an eight bit word corresponding to the address of the
device it is addressing.
The most significant 6 bits of the slave address are the device type identifier.
The TDA7541B device type is fixed as "110001".
The next significant bit is used to address a particular device of the previous defined type
connected to the bus.
The state of the hardwired PIN 57 defines the state of this address bit. Using this feature up
to two devices could be connected on the same bus. When PIN 57 is connected to VCC via
an external resistor of about 82 kΩ the address bit "1" is selected. Please note: in this case
the AM part doesn't work. Otherwise the address bit "0" is selected (FM and AM is working).
Therefore a double FM tuner concept is possible.
The last bit of the start instruction defines the type of operation to be performed:
–When set to "1", a read operation is selected
–When set to "0", a write operation is selected
The TDA7541B connected to the bus will compare their own hardwired address with the
slave address being transmitted, after detecting a START condition. After this comparison,
the TDA7541B will generate an "acknowledge" on the SDA line and will do either a read or a
write operation according to the state of R/W bit.
40/77Doc ID 16048 Rev 1
TDA7541BFunctional description
Write operation
Following a START condition the master sends a slave address word with the R/W bit set to
"0". The device will generate an "acknowledge" after this first transmission and will wait for a
second word (the word address field). This 8-bit address field provides an access to any of
the 32 internal addresses. Upon receipt of the word address the TDA7541B slave device will
respond with an "acknowledge". At this time, all the following words transmitted to the
TDA7541B will be considered as Data. The internal address will be automatically
incremented. After each word receipt the TDA7541B will answer with an "acknowledge".
Read operation
If the master sends a slave address word with the R/W bit set to "1", the TDA7541B will
transmit one 8-bit data word. This data word includes the following informations.
SD High cut19DEEMPHCLT6HCLT5HCHT4HCHT3 HCMAX2 HCMAX1HCENA
SD MP20MSMPFASTMPINTMPCCMPRG3MPRG2MPG1MPG0
SD quality21NBFC7NBFC6NBDC5NBDC4QNG3QNG2QDC1QDC0
SD Audio NB I22NBCT7NBCT6NBLT5NBLT4NBLT3NBT2NBT1NBENA
SD Audio NB II23ADSELPCMVCONNBSMPNBMPNBRR2NBRR1NBPC
SD Testing24------ - -
T PLL/IFC Testing25EWEXPIFSEXP111111
T Testing26------ - -
T Testing27------ - -
T Testing28------ - -
T Testing29------ - -
Not used30----- - - -
Not used31----- - - -
T Tuner
SDStereo decoder
Data bytes which are unused or dedicated for testing only don't need to be written, because
they are set internally to FEH (power on reset condition). But if somebody it writing these
bytes they must be written to FEH, otherwise some malfunction of the chip can happen.
Doc ID 16048 Rev 143/77
Software specificationTDA7541B
5.3 Control register function
Table 15.I2C control bit description
Register
Name
Function
ACFAdjacent channel detector filter select
ACMDAdjacent channel mute depth
ACMTHAdjacent channel mute threshold
ACTHAdjacent channel detector threshold
ADSELAdditional selectivity
AINENA AM IF noise blanker enable
AINTAM IF noise blanking time
AINTHAM IF noise blanker threshold
AMCFStereo decoder attenuation @ 3.5 kHz
AMDAM VCO pre-divider
ASFCAlternative station frequency check in FM (AGC and weak signal mute on hold)
ASIAudio signal inversion
BWDEFEnables bit ISSBW for ISS bandwidth control
DAGCAM narrow band AGC threshold
DEEMPStereo decoder de-emphasis
DSBFM demodulator spike blanker
DTHDeviation detector threshold for ISS filter “OFF”
DWTHDeviation detector threshold for ISS filter 120 kHz
EWIF counter frequency error window
EWEXPExpanded IF counter error window
FMONInternal switch FM-AM mode
FSWOWeighted fieldstrength with offset adjust
HCENAHigh cut enable
HCHTStart level high cut
HCLTStop level high cut
HCMAXMaximum high cut depth
ICPCharge pump current tuner PLL
IF1GIF1 Amplifier Gain
IF2AIF2 LC band pass fine adjust
IF2QIF2 LC band pass quality adjust
IFAGCFM/AM IF AGC threshold
IFAGCSAM IFAGC threshold shift
44/77Doc ID 16048 Rev 1
TDA7541BSoftware specification
Table 15.I2C control bit description (continued)
Register
Name
IFSIF counter sampling time
IFSEXPExpanded IF counter sampling time
ISSBWISS filter band width select
ISSENA ISS filter enable
ISSONISS filter control mode
ISSMISS filter application mode
KAGCFM keying AGC
LDENALock detector enable tuner PLL
LGStereo decoder level gain adjust
LMFM local mode enable
LNAAM LNA Pin/FET mode
MPACInfluence tuner multi path detection on adjacent channel behavior
MPCCStereo decoder multi path detector charge current
MPENATuner multi path detector influence on adjacent channel enable
MPFAST Fast mode of multi path information at quality pin
MPGMulti path detector gain
MPINTStereo decoder multi path internal influence enable
Function
MPRGStereo decoder multi path detector rectifier gain
----0---Multipath influence on peak discharge “OFF”
1Multipath influence on peak discharge “ON” (-3 V/ms)
NBSMP
---0----Strong multipath influence on peak discharge “OFF”
1Strong multipath influence on peak discharge “ON”
VCON
--0-----Stereo decoder VCO “OFF”
1Stereo decoder VCO “ON”
PCM
-0------Pilot cancellation mode: always
1Pilot cancellation mode: if pilot > pilot threshold
ADSEL
0-------Additional selectivity OFF
1Additional selectivity ON
66/77Doc ID 16048 Rev 1
TDA7541BSoftware specification
Table 41.Addr 24, 26, 27, 28, 29 testing (FEh)
MSBLSB
Function
d7d6d5d4d3d2d1d0
1 111111 0Only for testing
Table 42.Addr 25 Testing (FEh)
MSBLSB
Function
d7d6d5d4d3d2d1d0
- - 11111 0Only for testing
IFSEXP
-0------Enable expand mode of IF sampling time (see addr 4)
1Disable expand mode of IF sampling time
EWEXP
0-------Enable expand mode of error window (see addr 4)
1Disable expand mode of error window
Doc ID 16048 Rev 167/77
AppendixTDA7541B
6 Appendix
Figure 8.Block diagram FM part
68/77Doc ID 16048 Rev 1
TDA7541BAppendix
Figure 9.Block diagram VCO
Doc ID 16048 Rev 169/77
AppendixTDA7541B
Figure 10. Block diagram ISS function
70/77Doc ID 16048 Rev 1
TDA7541BAppendix
Figure 11. Block diagram AM path
Doc ID 16048 Rev 171/77
AppendixTDA7541B
Figure 12. Block diagram stereo decoder
MPXOUTMPXIN
L
R
MUX
MPTC
FSTC
Figure 13. Block diagram audio noise blanker
MPXIN
FMON
RECT
Deviation
detector
NBDC
FMDEMOut
140kHz HPF
(2nd. order)
Rectifier
Integrator
discharge control
NBPC
NBMP
NBRR
NBSMP
PEAK
VTH
FMON
Threshold
generator
NBCTNBLT
Fieldstrenght
adjust
NBFC
Stereo
decoder
S&H NBENA
Monoflop
FM:22-40µs
AM:0.3-1.2ms
L/R
NBT
FSTC
MPTC
72/77Doc ID 16048 Rev 1
TDA7541BAppendix
Figure 14. Block diagram multi path detection for stereo decoder
FSTC
MUX
FS
internal
Attack/Decay
Rectifier
Bandpass
19kHz
MPCCMPFAST/
Rectifier
MPGMPRG
Stereo
blend
MPINT
SEEK
MPTC
Doc ID 16048 Rev 173/77
Application circuitTDA7541B
7 Application circuit
Figure 15. Application circuit
8.5V
22
100n
R
100n
37
35
36
R
VCC1
FSWO
GNDSTD
L
34
33
1
L
XTALD
GNDVCC
32
3.3n
ISSTC2
31
X1
330n
ISSTC1
XTALG
FSTC
FSU
SCL
SDA
SSTOP
MUX
SW
LPHC
LPF
VREF2
LPOUT
GNDVCO
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
100n
FSU
SCL
SDA
SSTOP
MUX
1µ
Q_Loaded 28
10.7MHz0 .7MHz450kHz
470n
AM_AF/MPX
470n
22µ
4.7
8.5V
CF3
L=560nH
CF2
CF1
100n
100n
180p
1µ
100n
2.2µ
100n
100n
4.7
8.5V
680n H
330p
1µ
48
47
VREF1
GNDVCC2
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
MIX2AMPOUT
VCC2
MIX2REF
MIX2OUT
AMRFAGCTC
MIX2INREF
MIX2IN
AMAGC2TC
IF1REF
IF1AMPOUT
VCCIF1
IF1AMPIN
GNDIF
MIX1REF
MIX1OUT
2.2µ
46
43
44
45
AMI F2IN
MPXOUT
GNDDEM
AMIF2REF
FMREFDEMC
100n
470n
41
40
39
42
MPXIN
MUTETC
AMREFDEMC
TDA7541B
470n
38
MPTC
220n
1
8.5V
8.5V
WB5AMMI X1REF6AMPI NDR
AMRFAGCOUT4AMMI X1IN3DEVTC2VCCMIX 1
330n10100n
FMMIX1IN18GNDRF
7
9
FMPINDR
FMMIX1IN210TV11FMAGCTC13VCOB14VCOE15VCCVCO
12
1µ
100n
16
100p
10
8.5V
22n
FM_AM
74/77Doc ID 16048 Rev 1
AC00706
TDA7541BPackage information
8 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
Figure 16. LQFP64 mechanical data and package dimensions
DIM.
A1.600.063
A10.050.15 0.0020.006
A21.351.401.45 0.053 0.055 0.0 57
B0.170.220.27
C0 .090.0035
D11.80 12. 00 12.20 0.464 0.472 0.480
D19.80 10.00 10.20 0.386 0.394 0.401
D37.500.295
e0.500.0197
E11.80 12.00 12.20 0.464 0.472 0.480
E19.80 10.00 10.20 0.386 0.394 0.401
E37.500 .295
L0.450.600.75 0.0177 0.0236 0.0295
L11.000.0393
K0˚ (min.), 3.5˚ (min.), 7˚(max.)
ccc0.0800.0 031
mminch
MIN. TYP. MAX . MIN. TYP. MAX.
0.0066 0.0086 0.0106
0.20
0.0079
OUTLINE AND
MECHANICAL DATA
LQFP64 (10 x 10 x 1.4mm)
D
D1
48
49
B
64
1
e
TQFP64
33
32
E3D3E1
17
16
E
L1
L
K
0.08mm
Seating Plane
A
A2
A1
ccc
B
C
0051434 F
Doc ID 16048 Rev 175/77
Revision historyTDA7541B
9 Revision history
Table 43.Document revision history
DateRevisionChanges
22-Jul-20091Initial release.
76/77Doc ID 16048 Rev 1
TDA7541B
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