cancellation of adjacent channel and noise
influences
■ Adjacent channel mute
■ Fully electronic alignment
■ All functions I
Description
The TDA7540N is a high performance tuner
circuit for AM/FM car radio. It contains mixer, IF
amplifier, demodulator for AM and FM,
stereodecoder, quality detection, ISS filter and
PLL synthesizer with IF counter on a single chip.
Use of BICMOS technology allows the
implementation of several tuning functions and a
minimum of external components.
2
C-Bus controlled
Order codeTemp range, °CPackagePacking
TDA7540N-40 to 85°CLQFP80 (14x14x1.4mm)Tube
TDA7540NTR-40 to 85°CLQFP80 (14x14x1.4mm)Tape and reel
FM quadrature I/Q-mixer converts FM RF to IF1 of 10.7MHz. The mixer provides inherent
image rejection and wide dynamic range with low noise and large input signal performance.
The mixer1 tank can be adjusted by software (IF1T). For accurate image rejection the
phase-error of I/Q can be compensated by software (PH)
It is capable of tuning the US FM, US weather, Europe FM, Japan FM and East Europe FM
bands
–US FM = 87.9 to 107.9 MHz
–US weather = 162.4 to 162.55 MHz
–Europe FM = 87.5 to 108 MHz
–Japan FM = 76 to 91 MHz
–East Europe FM = 65.8 to 74 MHz
The AGC operates on different sensitivities and bandwidths in order to improve the input
sensitivity and dynamic range. AGC thresholds are programmable by software
(RFAGC,IFAGC,KAGC). The output signal is a controlled current for pin diode attenuator.
A 10.7MHz programmable amplifier (IFG1) correct the IF ceramic insertion loss and the
costumer level plan application.
4.1.2 Mixer2, limiter and demodulator
In this 2nd mixer stage the first 10.7MHz IF is converted into the second 450kHz IF. A multistage limiter generates signals for the complete integrated demodulator including spike
cancellation (DNB). MPX output DC offset versus noise DC level is correctable by software
(DEM), if tuner softmute is activated.
4.1.3 Quality detection and ISS
Fieldstrength
Parallel to mixer2 input a 10.7MHz limiter generates a signal for digital IF counter and a
fieldstrength output signal. This internal unweighted fieldstrength is used for keying AGC,
adjacent channel and multipath detection and is available at PIN22 (FSU) after +6dB buffer
stage. It is possible to combinate the IF counter result with this FSU via programmable
comparator (SSTH). The behaviour of FSU signal can be corrected for DC offset (SL) and
slope (SMSL). The generated unweighted fieldstrength is externally filtered and used for
softmute function and generation of ISS filter switching signal for weak input level (sm).
Adjacent channel detector
The input of the adjacent channel detector is AC coupled from internal unweighted
fieldstrength. A programmable highpass or bandpass (ACF) and amplifier (ACG) as well as
rectifier determines the influences. This voltage is compared with adjustable comparator1
thresholds (ACWTH, ACNTH). The output signal of this comparator generates a DC level at
PIN27 by programmable time constant. Time control (TISS) for a present adjacent channel
27/76
Functional descriptionTDA7540N
is made by charge and discharge current after comparator1 in an external capacitance. The
charge current is fixed and the discharge current is controlled by I
produces digital signals (ac, ac+) in an additional comparator4. The adjacent channel
information is available as analog output signal after rectifier and +8dB output buffer.
2
C Bus. This level
Multipath detector
The input of the multipath detector is AC coupled from internal unweighted fieldstrength. A
programmable bandpass (MPF) and amplifier (MPG) as well as rectifier determines the
influences. This voltage is compared with an adjustable comparator2 thresholds (MPTH).
The output signal of this comparator2 is used for the "Milano" effect. In this case the
adjacent channel detection is switched off. The "Milano" effect is selectable by I
(MPOFF). The multipath information is available as analog output signal after rectifier and
+8dB output buffer.
2
C Bus
450kHz IF narrow bandpass filter (ISS filter)
The device gets an additional 450KHz IF narrow bandpass filter for suppression of noise
and adjacent channel signal influences. This narrow filter has three switchable bandwidthes,
narrow range of 80kHz, mid range of 120kHz and 30KHz for weather band information.
Without ISS filter the IF bandwidth (wide range) is defined only by ceramic filter chain. The
filter is located between mixer2 and 450kHz limiter stage. The centre frequency is matched
to the demodulator center frequency.
Deviation detector
In order to avoid distortion in audio output signal the narrow ISS filter is switched OFF for
present overdeviation. Hence the demodulator output signal is detected. A lowpass filtering
and peak rectifier generates a signal that is defined by software controlled current (TDEV) in
an external capacitance.
This value is compared with a programmable comparator3 thresholds (DWTH, DTH) and
generates two digital signals (dev, dev+). For weak signal condition deviation threshold is
dependent on FSWO.
ISS switch logic
All digital signals coming from adjacent channel detector, deviation detector and softmute
are acting via switching matrix on ISS filter switch. The IF bandpass switch mode is
controlled by software (ISSON, ISS30, ISS80, CTLOFF). The switch ON of the IF bandpass
is also available by external manipulation of voltage at PIN27. Two application modes are
available (APPM).
The conditions are described in Ta bl e 5 2 .
4.1.4 Soft mute control
The filtered fieldstrength (FSWO) signal is the reference for mute control. The startpoint and
mute depth are programmable (SMTH, SMD) in a wide range. The time constant is defined
by external capacitance. Additional adjacent channel mute function is supported. A
highpass filter with -3dB threshold frequency of 100kHz, amplifier and peak rectifier
generates an adjacent noise signal from MPX output with the same time constant for
softmute. This value is compared with comparator5 thresholds (ACM). For present strong
adjacent channel the MPX signal is additional attenuated (ACMD).
28/76
TDA7540NFunctional description
4.2 AM section
The up/down conversion is combined with gain control circuit sensing three input signals,
narrow band information at PIN 54, upconversion signal (IF2AGC) at PIN 71and wide band
information (RFAGC) at PIN 4.This gain control gives two output signals. The first one is a
current for pin diode attenuator and the second one is a voltage for preamplifier. Time
constant of RF- and IF-AGC is defined by internal 100k resistor and external capacitor at
PIN 67. The intervention points for AGC (DAGC,WAGC) are programmable by software.
In order to avoid a misbehaviour of AGC intervention point it is important to know that the
DAGC threshold has to be lower than WAGC threshold !
The oscillator frequency for upconversion-mixer1 is generated by dividing the VCO
frequency after VCO divider (VCOD) and AM predivider(AMD).
Two 10,7MHz ceramic filters before mixer2 input increases 900KHz attenuation.In mixer2
the IF1 is down converted into the IF2 450kHz. After filtering by ceramic filter a 450kHz
amplifier is included with an additional gain control of IF2 below DAGC threshold. Time
constant is defined by capacitance at PIN 78.
Mixer1 and mixer2 tanks are software controlled adjustable (IF1T, IF2T).
The demodulator is a peak detector to generate the audio output signal.
A separate output is available for AMIF stereo (AMST).
AM IF noise blanker
In order to remove in AM short spikes a noise cancellation conception is used in 450KHz IF
AM level. The advantage is to avoid long narrow AGC- and demodulator- time constants,
wich enlarge spike influences on audio signal and makes difficult to remove it in audio path.
The 10.7MHz AM IF signal generates before 10.7 MHz ceramic filter via limitation an
unweighted fieldstrenght signal including slope of noise spike. The comparison of these
detected slope between fast and slow rectifier ignores audio modulation whereby the
threshold of slow rectifier is programmable (AINBT). A comparator activates a pulse
generator.
The duration of this pulse is software programmable (AINT) and is smooth blanking out the
spikes in 450KHz AM mixer2. Additionally this funtionality is controlled by narrow AM
fieldstrenght (AINBD).
4.3 Stereodecoder
4.3.1 Decoder
The stereo decoder-part of the TDA7540N (see Figure 14) contains all functions necessary
to demodulate the MPX-signal like pilot tone-dependent MONO/STEREO-switching as well
as "stereoblend" and "highcut". Adaptations like programmable input gain, roll-off
compensation, selectable deemphasis time constant and a programmable field strength
input allow easy adaption to different applications.
th
The 4
and noise and acts as an anti-aliasing filter for the following switch capacitor filters.
order input filter has a corner frequency of 80kHz and is used to attenuate spikes
29/76
Functional descriptionTDA7540N
Demodulator
In the demodulator block the left and the right channel are separated from the MPX-signal.
In this stage also the 19-kHz pilot tone is canceled. For reaching a high channel separation
the TDA7540 offers an I2C-bus programmable roll-off adjustment, which is able to
compensate the low pass behavior of the tuner section. Within the compensation range an
adjustment to obtain at least 40dB channel separation is possible. The bits for this
adjustment are located together with the level gain adjustment in one byte. This gives the
possibility to perform an optimization step during the production of the car radio where the
channel separation and the header are trimmed.
In addition to that the FM signal can be inverted.
Deemphasis and highcut
The deemphasis low pass allows to choose between a time constant of 50µs/ 75μs
(DEEMP) and 25μs/37.5μs (DESFT). The highcut control range will be in both cases τ
2xτ
. Inside the highcut control range (between VHCH and VHCL) the LEVEL signal is
Deemp
converted into a 5-bit word, which controls the low pass time constant between
τ
Deemp
...3xτ
. Thereby the resolution will remain always 5 bits independently of the
Deemp
absolute voltage range between the VHCH- and VHCL-values.
The highcut function can be switched off by I
2
C-bus .
HC
=
In AM mode (AMON = 1) the bits DEEMP and DESFT together with the AM corner
frequency bits (AMCF1...5) can be used as programmable AM frequency response. The
maximum corner frequency is defined by τ
, the minimum is defined by 3xτ
Deemp
Deemp
19kHz PLL and pilot tone detector
The PLL has the task to lock on the 19kHz pilot tone during a stereo-transmission to allow a
correct demodulation. The included pilot tone-detector enables the demodulation if the pilot
tone reaches the selected pilot tone threshold V
. Two different thresholds are
PTHST
available. The status of the detector output can be checked by reading the status byte of the
TDA7540N via I
2
C-bus or by reading the STEREO pin (pin 25).
Field strength control
The field strength input is used to control the highcut- and the stereoblend-function. In
addition the signal can be also used to control the noise blanker thresholds and as input for
the multipath detector.
Level-input and -gain
As level input for the stereo decoder is used the FSU voltage (pin22). Appling a capacitor at
FSTC (pin33) a desired time constant can by reached together with the internal resistor of
10k between FSU pin and FSTC pin.
In addition to that the LEVEL signal is low pass filtered internally in order to suppress
undesired high frequency modulation on the highcut- and stereoblend-function . The filter is
a combination of a 1
order switched capacitor low pass at 2.2kHz. The second stage is a programmable gain
stage to adapt the LEVEL signal internally . The gain is widely programmable in 8 steps
from 0dB to 4,7dB (step=0.67dB). These 3bits are located together with the Roll-Off bits in
the "Stereo decoder 8"-byte to simplify a possible adaptation during the production of the
car radio.
st
-order RC-low pass at 53kHz (working as anti-aliasing filter) and a 1st-
30/76
TDA7540NFunctional description
L
t
r
τ
Stereoblend control
The stereoblend control block converts the internal LEVEL-voltage into a demodulator
compatible analog signal, which is used to control the channel separation between 0dB and
the maximum separation. Internally this control range has a fixed upper limit, which is the
internal reference voltage
V
in 4% steps (see Figure 6).
REF1
To adjust the external LEVEL-voltage to the internal range two values must be defined: the
LEVEL gain L
and VSBL. To adjust the voltage where the full channel separation is
G
reached (VST) the LEVEL gain L
estimate the gain:
The MONO-voltage VMO (0dB channel separation) can be chosen selecting VSBL.
Figure 6.Relation between internal and external level-voltagees and setup of
stereoblend
V
. The lower limit can be programmed between 29 and 58% of
REF1
has to be defined. The following equation can be used to
G
L
G
= V
/FSU@full stereo
REF1
The stereo blend function can be switched ON/OFF using bit Addr25<d2>. Please note that
in AM it must be switched in forced mono!
Highcut control
The highcut control set-up is similar to the stereoblend control set-up: the starting point
VHCH can be set with 2 bits to be 42, 50, 58 or 66% of V
to be 11, 18.3, 25.7 or 33% of VHCH (see Figure 7).
Figure 7.Highcut characteristics
owpass
ime con stant
3
•
Deem p
Deem p
VHCLVHC
whereas the range can be set
REF1
HFieldst
ength
31/76
Functional descriptionTDA7540N
4.3.2 Functional description of the noise blanker
In the automotive environment spikes produced by the ignition or for example the wipermotor disturb the MPX-signal. The aim of the noise blanker part is to cancel the audible
influence of the spikes. Therefore the output of the stereo decoder is held at the actual
voltage for a time between 22
blanker is given inFigure 15.
In a first stage the spikes must be detected but to avoid a wrong triggering on high
frequency (white) noise a complex trigger control is implemented. Behind the trigger stage a
pulse former generates the "blanking"-pulse. An own biasing circuit supplies the noise
blanker in order to avoid any cross talk to the signal path.
Trigg er pa th
The incoming MPX signal is high pass filtered, amplified and rectified. This second order
high pass filter has a corner-frequency of 140kHz. The rectified signal, RECT, is low pass
filtered to generate a signal called PEAK. Also noise with a frequency 140kHz increases the
PEAK voltage. The resulting voltage can be adjusted by use of the noise rectifier discharge
current. The PEAK voltage is fed to a threshold generator, which adds to the PEAK-voltage
a DC-dependent threshold VTH. Both signals, RECT and PEAK+VTH are fed to a
comparator, which triggers a re-triggerable monoflop. The monoflop's output activates the
sample-and-hold circuits in the signal path for the selected duration.
μs and 38μs (programmable). The block diagram of the noise
There are mainly two independent possibilities for programming the trigger threshold:
1.the low threshold in 8 steps (NBLTH)
2. and the noise adjusted threshold in 4 steps (NBCTH).
The low threshold is active in combination with a good MPX signal without any noise; the
PEAK voltage is less than 1V. The sensitivity in this operation is high.
If the MPX signal is noisy (low fieldstrength) the PEAK voltage increases due to the higher
noise, which is also rectified. With increasing of the PEAK voltage the trigger threshold
increases, too. This particular gain is programmable in 4 steps (NBCTH).
Automatic threshold control by the stereoblend voltage (Figure 5)
Besides the noise controlled threshold adjustment there is an additional possibility for
influencing the noise blanker trigger threshold using the bits NBFS. This influence depends
on the stereoblend control.
The point where the MPX signal starts to become noisy is fixed by the RF part. This point is
also the starting point of the normal noise-controlled trigger adjustment. But in some cases
the noise blanker can create a wrong triggering, which create distortion, already in the
region of mono/stereo transition. Therefore a opportunity to control the PEAK voltage by the
stereo blend function it is implemented.
Over deviation detector (Figure 4)
If the system is tuned to stations with a high deviation the noise blanker can trigger on the
higher frequencies of the modulation. To avoid this wrong behavior, which causes noise in
the output signal, the noise blanker offers a deviation-dependent threshold adjustment. By
rectifying the MPX signal a further signal representing the actual deviation is obtained. It is
32/76
TDA7540NFunctional description
used to increase the PEAK voltage. Offset and gain of this circuit are programmable in 3
steps (NBDTH) of the stereo decoder-byte (the first step turns off the detector).
Multipath-level
To react on high repetitive spikes caused by a Multipath-situation, the discharge-time of the
PEAK voltage can be decreased depending on the voltage-level at Pin MPout. There are
two ways to do this. One way is to switch on the linear influence of the Multipath-Level on the
PEAK-signal . In this case the discharge slew rate is 1V/ms
1)
. The second possibility is to
activate a function, which switches to the 18k discharge if the Multipath-Level is below 2.5V.
If multipath influence on noise blanker is switched ON than MPF bit has to be set to 0.
1)
The slew rate is measured with R
Discharge
=infinite and V
MPout
=2.5V
AM Mode of Noise Blanker
The TDA7540N offers an AM audio noise blanker too.
If the AM noise blanker is used the AM audio delay filter and the AM audio filter must be
switched on. It is not recommented to use the AM noise blanker without to use the AMIF
noiseblanker inside the tuner.
The noise blanker is activated if the spike is bigger than a fixed threshold
In order to blank the whole spike in AM mode the hold time of the S&H circuit is much longer
than in FM mode (640µs -1.2ms).
4.3.3 Functional description of the multipath-detector
Using the internal Multipath-Detector the audible effects of a multipath condition can be
minimized. A multipath-condition is detected by rectifying the 19kHz spectrum in the
fieldstrength signal. An external capacitor is used to define the attack- and decay-times (see
block diagram, Figure 16). The MP_OUT-pin is used as detector-output connected to a
capacitor of about 47nF. Using this configuration an external adaptation to the user's
requirement is possible without affecting the "normal" fieldstrength input (LEVEL) for the
stereo decoder.
To keep the old value of the Multipath Detector during an AF-jump, the MP-Hold switch can
disconnect the external capacitor. This switch is controlled directly by the AFS-Pin.
Selecting MPION the channel separation is automatically reduced during a multipath
condition according to the voltage appearing at the MP_OUT-pin.
Programming
To obtain a good multipath performance an adaptation is necessary. Therefore the gain of
the first 19kHz-bandpass is programmable in two steps (MPG), the gain of the second
19kHz-bandpass is programmable in four steps (MPBPG) and the rectifier gain is
programmable in four steps(MPRG). Please note that the frequency of the first multipath
bandpass (MPF) must be set to 19kHz! The attack- and decay-times can be set by the
external capacitor value and the multipath detector charge current MPCC.
4.3.4 Quality detector
The TDA7540N offers a quality detector output, which gives a voltage representing the FMreception conditions. To calculate this voltage the MPX-noise and the multipath-detector
output are summed according to the following formula:
33/76
Functional descriptionTDA7540N
VQual = 0.8b (VNoise-0.8 V)+ a (V
The noise-signal is the PEAK-signal without additional influences (see noise blanker
description). The factor 'a' can be programmed from 0.6 to 1.05(QDC) and the factor b can
be programmed from 6dB to 15dB ( QNG). The output is a low impedance output able to
drive external circuitry as well as simply fed to an AD-converter for RDS applications.
4.3.5 AFS control and stereo decoder mute
The TDA7540N is supplied with several functionality to support AF-checks using the stereo
decoder. The additional pin (AFS) is implemented in order to speed up the stereo decoder
AF-functions compared to IIC controlling.
The block diagramm of AFS function is shown in Figure 17.
In order to separate the differentfunctions of the AFS pin, two different logic thresholds are
implemented. Below the higher threshold voltage (2.4V) only the multipath-detector is
switched into small time constant (internal logical signal MPfast).
Below the lower threshold voltage (0.8V) the full AFS function is activated. The MPXIN pin is
switched into high impedance mode (internal signal AFSMute), which avoids any clicks
during the jump condition. If the stereo decoder is not muted, it is possible at the same time
to evaluate the noise- and multipath-content of the alternate frequency using the Quality
detector output.
Furthermore the AFS pin does also freeze the condition of pilot locking and magnitude
(internal signal PDhold). The Pdhold signal is defined by V
PDH signal.
REF1
th1
-VMpout).
or V
, dependent on the
th2
4.4 PLL and IF counter section
4.4.1 PLL frequency synthesizer block
This part contains a frequency synthesizer and a loop filter for the radio tuning system. Only
one VCO is required to build a complete PLL system for FM world tuning and AM
upconversion (Figure 9). For auto search stop operation an IF counter system is available.
The PLL counter works in a two stages configuration. The first stage is a swallow counter
with a two modulus (32/33) precounter. The second stage is an 11-bit programmable
counter.
The circuit receives the scaling factors for the programmable counters and the values of the
reference frequencies via an I
adjustable internal (XTAL) oscillator followed by the reference divider. The main reference
and step-frequencies are free selectable (RC, PC).
Output signals of the phase detector are switching the programmable current sources. The
loop filter integrates their currents to a DC voltage.
The values of the current sources are programmable by 6 bits also received via the I
(A, B, CURRH, LPF).
To minimize the noise induced by the digital part of the system, a special guard
configuration is implemented.
The loop gain can be set for different conditions by setting the current values of the
chargepump generator.
2
C-Bus interface.The reference frequency is generated by an
2
C Bus
34/76
TDA7540NFunctional description
Frequency generation for phase comparison
The RF signals applies a two modulus counter (32/33) pre-scaler, which is controlled by a 5bit A-divider. The 5-bit register (PC0 to PC4) controls this divider. In parallel the output of the
prescaler connects to an 11-bit B-divider. The 11-bit PC register (PC5 to PC15) controls this
divider
Dividing range behind VCO divider:
f
= [33 x A + (B + 1 - A) x 32] x f
VCOdiv
f
= (32 x B + A + 32) x f
VCOdiv
REF
REF
Important: For correct operation: A ≤ 32; B ≥ A
Three state phase comparator
The phase comparator generates a phase error signal according to phase difference
between f
SYN
and f
. This phase error signal drives the charge pump current generator.
REF
Charge pump current generator
This system generators signed pulses of current. The phase error signal decides the
duration and polarity of those pulses. The current absolute values are programmable by A
register for high current and B register for low current.
Inlock detector
Switching the chargepump in low current mode can be done either via software or
automatically by the inlock detector, by setting bit LDENA to "1".
After reaching a phase difference about lower than 40nsec the chargepump is forced in low
current mode. A new PLL divider alternation by I
high current mode.
Low noise CMOS op-amp
An internal voltage divider at pin VREF2 connects the positive input of the low noise opamp. The charge pump output connects the negative input. This internal amplifier in
cooperation with external components can provide an active filter. The negative input is
switchable to three input pins, to increase the flexibility in application. This feature allows two
separate active filters for different applications.
While the high current mode is activated LPHC output is switched on.
4.4.2 IF counter block
The aim of IF counter is to measure the intermediate frequency of the tuner for AM and FM
mode. The input signal for FM and AM upconversion is the same 10.7MHz IF level after
limiter. AM 450KHz signal is coming from narrow filtered IF2 before demodulation. A switch
controlled by IF counter mode (IFCM) is choosing the input signal for IF counter.
The grade of integration is adjustable by eight different measuring cycle times. The
tolerance of the accepted count value is adjustable, to reach an optimum compromise for
search speed and precision of the evaluation.
2
C-Bus will switch the chargepump in the
The IF-counter mode
The IF counter works in 3 modes controlled by IFCM register.
35/76
Functional descriptionTDA7540N
Sampling timer
A sampling timer generates the gate signal for the main counter. The basically sampling
time are in FM mode 6.25kHz (t
=160μs) and in AM mode 1kHz (t
TIM
=1ms). This is
TIM
followed by an asynchronous divider to generate several sampling times.
Intermediate frequency main counter
This counter is a 11 - 21-bit synchronous autoreload down counter. Five bits (CF) are
programmable to have the possibility for an adjust to the centre frequency of the IF-filter.
The counter length is automatic adjusted to the chosen sampling time and the counter mode
(FM, AM-UPC, AM).
At the start the counter will be loaded with a defined value which is an equivalent to the
divider value (t
SamplexfIF
If a correct frequency is applied to the IF counter frequency input at the end of the sampling
time the main counter is changing its state from 0h to 1FFFFFh.
This is detected by a control logic and an external search stop output is changing from LOW
to HIGH. The frequency range inside which a successful count result is adjustable by the
EW bits.
t
= (CF + 1696+1) / f
CNT
t
= (CF + 10688+1) / fIF AM up conversion mode
CNT
t
= (CF + 488+1) / f
CNT
).
IF
IF
FM mode
AM mode
Counter result succeeded:
t
≥ t
≤ t
CNT
CNT
- t
+ t
ERR
ERR
TIM
t
TIM
Counter result failed:
t
> t
TIM
t
< t
TIM
t
= IF timer cycle time (sampling time)
TIM
t
CNT
t
ERR
+ t
CNT
CNT
- t
ERR
ERR
= IF counter cycle time
= discrimination window (controlled by the EW registers)
The IF counter is only started by inlock information from the PLL part. It is enabled by
software (IFENA).
Adjustment of the measurement sequence time
The precision of the measurements is adjustable by controlling the discrimination window.
This is adjustable by programming the control registers EW.
The measurement time per cycle is adjustable by setting the registers IFS.
Adjust of the frequency value
The center frequency of the discrimination window is adjustable by the control registers CF.
36/76
TDA7540NFunctional description
4.5 I2C-Bus interface
The TDA7540N supports the I2C-Bus protocol. This protocol defines any device that sends
data onto the bus as a transmitter, and the receiving device as the receiver. The device that
controls the transfer is a master and device being controlled is the slave. The master will
always initiate data transfer and provide the clock to transmit or receive operations.
Data transition
Data transition on the SDA line must only occur when the clock SCL is LOW. SDA transitions
while SCL is HIGH will be interpreted as START or STOP condition.
Start condition
A start condition is defined by a HIGH to LOW transition of the SDA line while SCL is at a
stable HIGH level. This "START" condition must precede any command and initiate a data
transfer onto the bus. The device continuously monitors the SDA and SCL lines for a valid
START and will not response to any command if this condition has not been met.
Stop condition
A STOP condition is defined by a LOW to HIGH transition of the SDA while the SCL line is at
a stable HIGH level. This condition terminates the communication between the devices and
forces the bus-interface of the device into the initial condition.
Acknowledge
Indicates a successful data transfer. The transmitter will release the bus after sending 8 bits
of data. During the 9th clock cycle the receiver will pull the SDA line to LOW level to indicate
it receive the eight bits of data.
Data transfer
During data transfer the device samples the SDA line on the leading edge of the SCL clock.
Therefore, for proper device operation the SDA line must be stable during the SCL LOW to
HIGH transition.
Device addressing
To start the communication between two devices, the bus master must initiate a start
instruction sequence, followed by an eight bit word corresponding to the address of the
device it is addressing.
The most significant 6 bits of the slave address are the device type identifier.
The TDA7540N device type is fixed as "110001".
The next significant bit is used to address a particular device of the previous defined type
connected to the bus.
The state of the hardwired PIN 59 defines the state of this address bit. So up to two devices
could be connected on the same bus. When PIN 59 is connected to VCC2 and a resistor at
PIN 55 versus ground of about 5.6k Ohm the address bit “1” is selected. In this case the AM
part doesn’t work. Otherwise the address bit “0” is selected (FM and AM is working).
Therefor a double FM tuner concept is possible.
37/76
Functional descriptionTDA7540N
The last bit of the start instruction defines the type of operation to be performed:
–When set to "1", a read operation is selected
–When set to "0", a write operation is selected
The TDA7540N connected to the bus will compare their own hardwired address with the
slave address being transmitted, after detecting a START condition. After this comparison,
the TDA7540N will generate an "acknowledge" on the SDA line and will do either a read or a
write operation according to the state of R/W bit.
Write operation
Following a START condition the master sends a slave address word with the R/W bit set to
"0". The device will generate an "acknowledge" after this first transmission and will wait for a
second word (the word address field). This 8-bit address field provides an access to any of
the 64 internal addresses.
Upon receipt of the word address the TDA7540N slave device will respond with an
"acknowledge". At this time, all the following words transmitted to the TDA7540N will be
considered as Data. The internal address will be automatically incremented up to hex40 in
page mode. Than again subaddresse hex60 has to be transmitted for following registers
above 32.
After each word receipt the TDA7540N will answer with an "acknowledge".
Read operation
If the master sends a slave address word with the R/W bit set to "1", the TDA7540N will
transit one 8-bit data word. This data word includes the following informations:
bit0 (ISS filter, 1 = ON, 0 = OFF)
bit1 (ISS filter bandwidth, 1 = 80kHz, 0 = 120kHz)
bit2 (STEREO,1 = STEREO, 0 = MONO)
bit3 (1 = PLL is locked in , 0 = PLL is locked out).
bit4 (fieldstrength indicator, 1 = lower as softmute threshold, 0 = higher as softmute
The pagermode is only working up to byte 31. After byte 31 it is need to send again the chip
address followed by the subaddress 32 and the databytes starting from 32 up to 39!
Table 54.Part list (application- and measurment circuit)
ItemDescription
F1TOKO 5KM 396INS-A543EK
F2TOKO MC152 E558HNA-100092
F3TOKO 7PSG P826RC-5134N
F4TOKO PGL 5PGLC-5103N
L1TOKO FSLM 2520-150 15uH
L2,L4TOKO FSLM 2520-680 68uH
L3SIEMENS SIMID03 B82432 1mH
L5TOKO LLQ 2012-220
L6TOKO LLQ 2012-680
CF1,CF2muRata SFE10.7MS3A10-A 180KHz
CF3muRata SFE10.7MJA10-A 150KHz
CF4muRata SFPS 450H
D1TOSHIBA 1SV172
D2,D3TOKO KP2311E
D4TOKO KV1410
D5PHILIPS BB156
Q1TOSHIBA HN3G01J
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Application circuitTDA7540N
8 Application circuit
Figure 18. Application circuit
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TDA7540NApplication notes
9 Application notes
Following items are important to get highest performance of TDA7540N in application:
1.In order to avoid leakage current from PLL loop filter input to ground a guardring is
recommended around loop filter PIN’s with PLL reference (VREF2) voltage potential.
2. Distance between Xtal and VCO input PIN 18 should be far as possible and Xtal
package should get a shield versus ground.
3. Blocking of VCO supply should be near at PIN 20 and PIN 21.
4. Blocking of VCC2 supply should be near at PIN 64 and PIN 61.
5. Wire lenght to FM mixer1-input and -output should be symetrically and short.
6. FM demodulator capacitance at PIN 56 should be sense connected as short as
possible versus demodulator ground at PIN 57.
7. Wire lenght from AM mixer tank output to 9KHz ceramic filter input has to be short as
possible.
8. To minimize “AM TWEET” the AM demodulator capacitor should be connected versus
GNDVCC1 at PIN 41 and FSU output at PIN 22 should be filtered with capacitor of
about 2,2nF versus GNDVCC2.
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Package informationTDA7540N
10 Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 19. LQFP80 (14x14x1.40mm) mechanical data and package dimensions
DIM.
A1.6000.0630
A10.0500.150 0.00200.0059
A21.350 1.400 1.450 0.0531 0.0551 0.0571
b0.220 0.320 0.380 0.0087 0.0126 0.0150
c0.0900.200 0.00350.0079
D15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D312.3500.4862
E15.800 16.000 16.200 0.6220 0.6299 0.6378
E1 13.800 14.000 14.20 0 0.5433 0.5512 0.5591
E312.3500.4862
e0.6500.0256
L0.450 0.600 0.750 0.0177 0.0236 0.0295
L11.0000.0394
k0˚ (m in.); 3.5˚ (typ,); 7˚ (max.)
ccc0.1000.0039
mminch
MIN. TYP. MAX. MIN. TYP. MAX.
OUTLINE AND
MECHANICAL DATA
LQFP80 (14x14x1.40mm)
Low profile Quad Flat Package
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0062342 D
TDA7540NRevision history
11 Revision history
Table 55.Document revision history
DateRevisionChanges
12-Nov-20071Initial release.
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TDA7540N
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