ST TDA7505 User Manual

TDA7505

Car radio DSP for advanced signal processing

Features

■Full software flexibility with two 24x24 bit DSP cores

■FM processing

■AM processing

■Dolby B noise reduction

■MP3 and C3 decoding

■Echo AND noise cancellation

■Audio processor

■Special sound effect processor

■Dual media processing

■RDS Filter, Demodulator & Decoder

■4 + 1 channel ADC, 6 channel DAC CODEC

■IIC/SPI control busses

■SAI 6 channel serial audio interface

■SPDIF interface with sample rate converter

■Dual core external memory interface

■Debug interface

■On-chip PLL

LQFP100

(14x14x1.4mm)

■5V-tolerant 3V I/O interface

■Multifunction general purpose I/O ports

Description

The TDA7505 is an MPX-sampling DSP for car radio applications.

Table 1.	Device summary
	Order code	Package	Packing
	TDA7505	LQFP100	Tray

October 2007

Rev 1

1/38

www.st.com

Contents	TDA7505

Contents

1	Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. 6
2	Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		7
3	Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		8
4	Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		15
	4.1	Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	4.2	Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	15
	4.3	Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	16

4.3.1 Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.2 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.3 Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3.4 General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 17 4.3.5 High voltage CMOS interface DC electrical characteristics . . . . . . . . . . 17 4.3.6 DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

	4.4	SAI interface timing - receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	4.5	SAI interface timing - transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	18
	4.6	SAI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	4.7	SPDIF receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	19
	4.8	SPI interfaces (Buffered SPI, Display SPI, RDS SPI) . . . . . . . . . . . . . . .	20
	4.9	I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	21
	4.10	DRAM/SRAM interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
	4.11	Debug port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	22
5	Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		27
	5.1	24-bit DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	27
	5.2	DSP peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	28

5.2.1 Data and program memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.2.2 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.4 Sony/Philips digital interface (S/PDIF) . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.2.5 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2/38

TDA7505	Contents

5.2.6 DRAM/SRAM interface (DEMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.2.7 Debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.8 General purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.9 Asynchronous sample rate converter . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.10 SINCOS co-processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.11 PLL clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.2.12 CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.13 Radio data system (RDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2.14 Clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

6	Software features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		34
	6.1	AM/FM base band signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
	6.2	Generic audio signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
	6.3	TAPE signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
	6.4	CD signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
	6.5	Audiophile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
	6.6	Audio decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	34
	6.7	Other . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
	6.8	Functional modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	35
7	Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		36
8	Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		37

3/38

List of tables	TDA7505

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 6. Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 7. Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 8. General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 9. High voltage CMOS interface DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 10. DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 11. SAI interface timing - receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 12. SAI interface timing - transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 13. SPDIF receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 14. SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 15. I2C Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 16. DRAM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 17. DRAM refresh period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 18. SRAM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 19. Debug port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 20. ASRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 21. Fractional-N PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 22. ADC electrical characteristics - measurement bandwidth 10Hz to 20kHz . . . . . . . . . . . . . 25 Table 23. ADC electrical characteristics - measurement bandwidth 10Hz to 53kHz . . . . . . . . . . . . . 25 Table 24. ADC electrical characteristics - measurement bandwidth 10Hz to 192kHz . . . . . . . . . . . . 25 Table 25. Level ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 26. DAC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 27. FM stereo decoder (SW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 28. Examples of convenient clock schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 29. Example of possible modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 30. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4/38

TDA7505	List of figures

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 2. LQFP100 pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 3. SAI interface timing - receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 4. SAI interface timing - transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 5. SAI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 6. SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 7. SPI clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 8. I2C Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 9. Debug port serial clock timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 10. Debug port acknowledge timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 11. Debug port data I/O to status timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 12. Debug port read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 13. Debug port DBCK next command after read register timing. . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 14. LQFP100 (14x14x1.4mm) mechanical data and package dimensions. . . . . . . . . . . . . . . . 36

5/38

Overview	TDA7505

1 Overview

The TDA7505 integrates two 75 MIPS DSP cores. One core is used for stereo decoding, noise blanking, weak signal processing, Dolby B, music search and MP3 decoding. The second core is used for audio and sound processing and Echo & Noise cancellation. All functions are realized in SW and thus are flexible on customer request.

The device may be controlled by a main micro through either SPI or I2C interface. Through the same pins, but with separate device address (I2C) respectively separate chip select line (SPI) the main micro may communicate with the DSP or with the RDS block.

An additional SPI is available allowing a separate communication (e.g. to a display micro).

The DSP cores are integrated with their associated data and program memories.

DSP0 is declared as master. Its associated peripherals and interfaces are: I2C, SPI1 (Master SPI), SPI2 (Display SPI), Serial Audio Interface (SAI), PLL Oscillator, External Memory Interface (EMI), General Purpose I/O ports (DSP0 GPIO[0..11]), RDS filter and D/A converters.

DSP1 is declared as Co-DSP. Its associated peripherals and interfaces are: A/D converters, SPDIF, Sample Rate Converter (SRC) and General Purpose I/O ports (DSP1 GPIO[0..11]).

Both DSP´s are identical (ST Orpheus core, 75 MHz clock). Only the peripherals and memory configurations are different. The internal communication takes place through a bidirectional 24/10-word exchange interface (XCHG) with complex flag and interrupts capability.

The Radio Data System (RDS, respectively RBDS) function is realized via dedicated hardware. It may run fully autonomous without SW intervention. Thus an efficient background mode as well as a low current standby mode is possible. The RDS input is connected to the A/D converter to receive the FM multiplex signal (MPX) automatically. Its output may be configured to I2C or SPI format. The pins are shared with the I2C and SPI1 of DSP0.

The device is equipped with a debug and test interface. It allows the SW development with a 100% compatible emulation system.

All functions, except RDS, are implemented in SW. Thus, the device may be adapted to customers´ requirements. This implies the variable implementation of SW modules developed by the customer, ST and third parties. This flexibility also allows the usage for applications others than car radios, e.g.: Boosters.

6/38

TDA7505	Block diagram

2 Block diagram

Figure 1. Block diagram

analog audio in

CD

Navi.

AM/FM Mpx

analog audio out

CC

Tel.

Mpx RDS

AM/FMLevel

2

4

2

2

3

Qdiff.

Diff.

Diff.

Qdiff.

Input Source Selector

SC

SC

SC

SC

SC

SC

PLL Clock

Filter

Filter

Filter

Filter

Filter

Filter

DAC-ref

ADC-ref

Noise

Noise

Noise

Generator

ΣΔ

ΣΔ

ΣΔ

ΣΔ

AM/FM

Shaper

Shaper

Shaper

DACVDD

Oversampl.

Oversampl.

Oversampl.

ADCVDD

level

DACGND

Decimation

Decimation

ADC

Filter

Filter

Filter

ADCGND

Audio

FM/Audio

RDS Int.

AVDD

RDS

Grp & blk

sync., error

SPI/

RDSCS

Filter

Demod.

AGND

correction

IIC

SINCOS

CLK in

Crystal

4

μP control

8.55MHz

Oscillator

10 word SPI 1

IIC / SPI 1

6 Ch. Audio Bus

receive stack

SPI 2

4

Display μP

2

3

receive bit&wordclk

SAI 6ch.

SAI Transmitter

6 Channel

digital audio in

Receiver

2ch sample

2

Audio Bus

SPDIF 2ch.

8+3

SPDIF audio in

rate converter

SRAM 4Mx8

Interface

External Memory Interface

17

DRAM 64Mx4

INT

DSP1 Orpheus Core

X Ram 4096

DSP0 Orpheus Core

NRESET

Including 12 GPIO´s

Including 12 GPIO´s

AM processing,

X Rom 4096

Xchg

X Ram 4096

4

VDD

FM processing,

Y Ram 40969

Interface

Y Ram 4096

Audio processing,

4

GND

CD compression,

Sound processing,

Dolby B,

P Ram 4096

P Ram 4096

TAM,

Debug/Test

MP3

Echo & noisecancell.

P Rom 16384

P Rom 16384

5

Debug Interface

Debug Interface

7/38

Pin description	TDA7505

3 Pin description

Table 2.		Pin description
N°		Name	Type						Function
1		DAC4	A	Signal output D/A converter (single ended)
2		DAC5	A	Signal output D/A converter (single ended)
N°		Name	Type		Voltage						Function
3	VDD1V8_1		S		1.8V				Digital Supply dedicated to internal logic
4	GND1V8_1		S			0V			Digital Ground dedicated to internal logic
N°		Name	Type	Reset	After boot with				I/O		Function
				state
					SPI		I2C *	EMI
											System Reset. A low level
5	NRESET		I	E0	E1		E1	E1	Input 5VT		applied to NRESET input
											initializes the IC.
	SRCCD								Input 5VT		SPDIF input source 1 (e.g.: CD)
6	MISOD output		I/O	Z	Z		Z	Z	Output 2mA PP/OD		Display SPI SO (slave mode)
	MISOD input								Input 5VT		Display SPI MI (master mode)
	SRCMD								Input 5VT		SPDIF input source 2 (e.g.: MD)
	MOSID input								Input 5VT		Display SPI SI (slave mode)
7	MOSID output		I/O						Output 2mA PP		Display SPI MO (master mode)
	DSP0 GPIO0			Z	Z		Z	Z	Input 5VT		GPIO input
	DSP0 GPIO0								Output 2mA PP		GPIO output
	SSD input								Input 5VT		Display SPI SS slave select
8	INT		I/O						Input 5VT		DSP0 external interrupt (IRQA)
	DSP0 GPIO1			Z	Z		Z	Z	Input 5VT		GPIO input
	DSP0 GPIO1								Output 2mA PP		GPIO output
	CLKIN								Input 5VT		External clock input for PLL
9	SCKD input		I/O	Z	Z		Z	Z	Input 5VT		Display SPI clock (slave mode)
	SCKD output								Output 2mA PP		Display SPI clock (master mode)
N°		Name	Type		Voltage						Function
10	AVDD		S		3.3V				Supply dedicated to the PLL
11	XTI		A			AC			Crystal oscillator input
12	XTO		A			AC			Crystal oscillator output
13	AGND		S			0V			Ground dedicated to the PLL

8/38

TDA7505											Pin description
Table 2.		Pin description			(continued)
N°		Name	Type	Reset		After boot with				I/O	Function
				State
						SPI		I2C *	EMI
	RDSCS									Input 5VT	RDS SPI CS chip select in
14	-		I/O							Output 2mA OD	RDS bit data
	DSP0 GPIO2				Z	Z		Z	Z	Input 5VT	GPIO input
	DSP0 GPIO2									Output 2mA PP	GPIO output
	INT									Input 5VT	DSP0 external interrupt (IRQA)
	-									Output 2mA OD	RDS bit clock
15	RDSINT		I/O							Output 2mA PP	RDS Interrupt Output
	DSP0 GPIO3				Z	Z		Z	Z	Input 5VT	GPIO input
	DSP0 GPIO3									Output 2mA PP	GPIO output
N°		Name	Type			Voltage					Function
16	VDD3V3_1		S			3.3V				Digital supply dedicated to I/O structures
17	GND3V3_1		S				0V			Digital ground dedicated to I/O structures
	SCKM input									Input 5VT	Master/RDS SPI clock (slave m.)
	SCKM output									Output 2mA PP	Master SPI clock (master mode)
18	SCL bi-direct		I/O			0/1		Z		In 5VT/Out 2mA OD	I2C clock
	DSP0 GPIO4				Z				Z	Input 5VT	GPIO input
	DSP0 GPIO4									Output 2mA PP	GPIO output
N°		Name	Type	Reset		After boot with				I/O	Function
				state
						SPI		I2C *	EMI
	MISOM output									Output 2mA PP/OD	Master/RDS SPI SO (slave m.)
	MISOM input									Input 5VT	Master SPI MI (master mode)
19	ADDR select		I/O			0/1		Z		Input 5VT	I2C Address select line
	DSP0 GPIO5				Z				Z	Input 5VT	GPIO input
	DSP0 GPIO5									Output 2mA PP	GPIO output
	MOSIM input									Input 5VT	Master/RDS SPI SI (slave m.)
	MOSIM output									Output 2mA PP	Master SPI MO (master mode)
20	SDA bi-direct		I/O			0/1		Z		In 5VT/Out 2mA OD	I2C data
	DSP0 GPIO6				Z				Z	Input 5VT	GPIO input
	DSP0 GPIO6									Output 2mA PP	GPIO output
	SSM input					Z				Input 5VT	Master SPI SS slave select
21	DSP0 GPIO7		I/O		Z			Z	Z	Input 5VT	GPIO input
	DSP0 GPIO7									Output 2mA PP	GPIO output
22	DSRA<0>		I/O		0	1		1	Z	In/Out 2mA PP	EMI SRAM Data 0
	DSRA<0>									In/Out 2mA PP	EMI DRAM Data 0
23	DSRA<1>		I/O		0	1		1	Z	In/Out 2mA PP	EMI SRAM Data 1
	DSRA<1>									In/Out 2mA PP	EMI DRAM Data 1
24	DSRA<2>		I/O		0	1		1	Z	In/Out 2mA PP	EMI SRAM Data 2
	DSRA<2>									In/Out 2mA PP	EMI DRAM Data 2

9/38

Pin description											TDA7505
Table 2.		Pin description			(continued)
N°	Name		Type	Reset		After boot with				I/O	Function
				state
						SPI		I2C *	EMI
25	DSRA<3>		I/O		0	1		1	Z	In/Out 2mA PP	EMI SRAM Data 3
	DSRA<3>									In/Out 2mA PP	EMI DRAM Data 3
26	DSRA<4>		I/O		0	1		1	Z	In/Out 2mA PP	EMI SRAM Data 4
27	DSRA<5>		I/O		0	1		1	Z	In/Out 2mA PP	EMI SRAM Data 5
28	DSRA<6>		I/O		0	1		1	Z	In/Out 2mA PP	EMI SRAM Data 6
29	DSRA<7>		I/O		0	1		1	Z	In/Out 2mA PP	EMI SRAM Data 7
30	SRA<0>		O		0	1		1	0/1	Output 2mA PP	EMI SRAM Address 0
	SRA<0>									Output 2mA PP	EMI DRAM Address 0
31	SRA<1>		O		0	1		1	0/1	Output 2mA PP	EMI SRAM Address 1
	SRA<1>									Output 2mA PP	EMI DRAM Address 1
N°	Name		Type			Voltage					Function
32	VDD3V3_2		S			3.3V				Digital Supply dedicated to I/O structures
33	GND3V3_2		S				0V			Digital Ground dedicated to I/O structures
N°	Name		Type	Reset		After boot with				I/O	Function
				state
						SPI		I2C *	EMI
34	SRA<2>		O		0	1		1	0/1	Output 2mA PP	EMI SRAM Address 2
	SRA<2>									Output 2mA PP	EMI DRAM Address 2
35	SRA<3>		O		0	1		1	0/1	Output 2mA PP	EMI SRAM Address 3
	SRA<3>									Output 2mA PP	EMI DRAM Address 3
36	SRA<4>		O		0	1		1	0/1	Output 2mA PP	EMI SRAM Address 4
	SRA<4>									Output 2mA PP	EMI DRAM Address 4
37	SRA<5>		O		0	1		1	0/1	Output 2mA PP	EMI SRAM Address 5
	SRA<5>									Output 2mA PP	EMI DRAM Address 5
38	SRA<6>		O		0	1		1	0/1	Output 2mA PP	EMI SRAM Address 6
	SRA<6>									Output 2mA PP	EMI DRAM Address 6
39	SRA<7>		O		0	1		1	0/1	Output 2mA PP	EMI SRAM Address 7
	SRA<7>									Output 2mA PP	EMI DRAM Address 7
40	SRA<8>		O		0	1		1	0/1	Output 2mA PP	EMI SRAM Address 8
	SRA<8>									Output 2mA PP	EMI DRAM Address 8
N°	Name		Type	Reset		After boot with				I/O	Function
				state
						SPI		I2C *	EMI
41	SRA<9>		O		0	1		1	0/1	Output 2mA PP	EMI SRAM Address 9
	SRA<9>									Output 2mA PP	EMI DRAM Address 9
42	SRA<10>		O		0	1		1	0/1	Output 2mA PP	EMI SRAM Address 10
	SRA<10>									Output 2mA PP	EMI DRAM Address 10

10/38

TDA7505											Pin description
Table 2.		Pin description			(continued)
N°	Name		Type	Reset		After boot with				I/O	Function
				state
						SPI		I2C *	EMI
43	SRA<11>		O		0	1		1	0/1	Output 2mA PP	EMI SRAM Address 11
	SRA<11>									Output 2mA PP	EMI DRAM Address 11
44	SRA<12>		O		0	1		1	0/1	Output 2mA PP	EMI SRAM Address 12
	SRA<12>									Output 2mA PP	EMI DRAM Address 12
N°	Name		Type			Voltage					Function
45	VDD1V8_2		S			1.8V				Digital Supply dedicated to internal logic
46	GND1V8_2 &		S				0V			Digital Ground dedicated to internal logic and I/O
	GND3V3_3									structures
47	VDD3V3_3		S			3.3V				Digital Supply dedicated to I/O structures
N°	Name		Type	Reset		After boot with				I/O	Function
				state
						SPI		I2C *	EMI
48	DRD		O		1	1		1	1	Output 2mA PP	EMI data read strobe
49	DWR		O		1	1		1	1	Output 2mA PP	EMI data write strobe
50	CAS		O							Output 2mA PP	EMI DRAM CAS
	SRA<13>				0	1		1	0/1	Output 2mA PP	EMI SRAM Address 13
51	SRA<14>		O		0	1		1	0/1	Output 2mA PP	EMI SRAM Address 14
	SRA<15>									Output 2mA PP	EMI SRAM Address 15
52	DSP0 GPIO8		I/O		Z	Z		Z	0/1	Input 5VT	GPIO input
	DSP0 GPIO8									Output 2mA PP	GPIO output
	INOUTA									In 5VT/Out 2mA PP	Multi function I/O
53	SRA<16>		I/O							Output 2mA PP	EMI SRAM Address 16
	DSP1 GPIO0				Z	Z		Z	0/1	Input 5VT	GPIO input
	DSP1 GPIO0									Output 2mA PP	GPIO output
	INOUTB									In 5VT/Out 2mA PP	Multi function I/O
54	SRA<17>		I/O							Output 2mA PP	EMI SRAM Address 17
	DSP1 GPIO1				Z	Z		Z	0/1	Input 5VT	GPIO input
	DSP1 GPIO1									Output 2mA PP	GPIO output
	INOUTC									In 5VT/Out 2mA PP	Multi function I/O
55	SRA<18>		I/O							Output 2mA PP	EMI SRAM Address 18
	DSP1 GPIO2				Z	Z		Z	0/1	Input 5VT	GPIO input
	DSP1 GPIO2									Output 2mA PP	GPIO output
N°	Name		Type	Reset		After boot with				I/O	Function
				state
						SPI		I2C *	EMI
	INOUTD									In 5VT/Out 2mA PP	Multi function I/O
56	SRA<19>		I/O						0/1	Output 2mA PP	EMI SRAM Address 19
	DSP1 GPIO3				Z	Z		Z		Input 5VT	GPIO input
	DSP1 GPIO3									Output 2mA PP	GPIO output

11/38

Pin description											TDA7505
Table 2.		Pin description			(continued)
N°	Name		Type	Reset		After boot with				I/O	Function
				state
						SPI		I2C *	EMI
	INOUTE									In 5VT/Out 2mA PP	Multi function I/O
57	SRA<20>		I/O						0/1	Output 2mA PP	EMI SRAM Address 20
	DSP1 GPIO4				Z	Z				Input 5VT	GPIO input
	DSP1 GPIO4							Z		Output 2mA PP	GPIO output
	INOUTF									In 5VT/Out 2mA PP	Multi function I/O
	SRA<21>								0/1	Output 2mA PP	EMI SRAM Address 21
58	RAS		I/O							Output 2mA PP	EMI DRAM RAS
	DSP1 GPIO5				Z	Z		Z		Input 5VT	GPIO input
	DSP1 GPIO5									Output 2mA PP	GPIO output
	INOUTG									In 5VT/Out 2mA PP	Multi function I/O
59	DSP1 GPIO6		I/O		Z	Z		Z	Z	Input 5VT	GPIO input
	DSP1 GPIO6									Output 2mA PP	GPIO output
	INOUTH									In 5VT/Out 2mA PP	Multi function I/O
60	DSP1 GPIO7		I/O		Z	Z		Z	Z	Input 5VT	GPIO input
	DSP1 GPIO7									Output 2mA PP	GPIO output
N°	Name		Type			Voltage					Function
61	VDD3V3_4		S			3.3V				Digital Supply dedicated to I/O structures
62	GND3V3_4		S				0V			Digital Ground dedicated to I/O structures
N°	Name		Type	Reset		After boot with				I/O	Function
				state
						SPI		I2C *	EMI
	INOUTI									In 5VT/Out 2mA PP	Multi function I/O
63	DSP1 GPIO8		I/O		Z	Z		Z	Z	Input 5VT	GPIO input
	DSP1 GPIO8									Output 2mA PP	GPIO output
64	INOUTJ		I/O		Z	Z		Z	Z	In 5VT/Out 2mA PP	Multi function I/O
	DBCK									Input 5VT	Debug clock
65	OS1		I/O							Out 2mA PP	Chip status 1
	DSP0/1 GPIO9					0		0	0	Input 5VT	GPIO input
					Z
	DSP0/1 GPIO9									Output 2mA PP	GPIO output
	DBOUT									Output 2mA PP	Debug output
66	DSP0/1 GPIO10		I/O		Z	1		1	1	Input 5VT	GPIO input
	DSP0/1 GPIO10									Output 2mA PP	GPIO output
N°	Name		Type	Reset		After boot with				I/O	Function
				state
						SPI		I2C *	EMI
	DBIN									Input 5VT	Debug input
67	OS0		I/O							Out 2mA PP	Chip status 0
	DSP0/1 GPIO11					0		0	0	Input 5VT	GPIO input
					Z
	DSP0/1 GPIO11									Output 2mA PP	GPIO output

12/38