ST TDA7505 User Manual
Car radio DSP for advanced signal processing
Features
■ Full software flexibility with two 24x24 bit DSP
cores
■ FM processing
■ AM processing
■ Dolby B noise reduction
■ MP3 and C3 decoding
■ Echo AND noise cancellation
■ Audio processor
■ Special sound effect processor
■ Dual media processing
■ RDS Filter, Demodulator & Decoder
■ 4 + 1 channel ADC, 6 channel DAC CODEC
■ IIC/SPI control busses
■ SAI 6 channel serial audio interface
■ SPDIF interface with sample rate converter
■ Dual core external memory interface
■ Debug interface
■ On-chip PLL
Table 1. Device summary
TDA7505
LQFP100
(14x14x1.4mm)
■ 5V-tolerant 3V I/O interface
■ Multifunction general purpose I/O ports
Description
The TDA7505 is an MPX-sampling DSP for car
radio applications.
Order code Package Packing
TDA7505 LQFP100 Tray
October 2007 Rev 1 1/38
www.st.com
1
Contents TDA7505
Contents
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.1 Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.2 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.3 Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3.4 General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 17
4.3.5 High voltage CMOS interface DC electrical characteristics . . . . . . . . . . 17
4.3.6 DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.4 SAI interface timing - receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5 SAI interface timing - transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.6 SAI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.7 SPDIF receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.8 SPI interfaces (Buffered SPI, Display SPI, RDS SPI) . . . . . . . . . . . . . . . 20
4.9 I
2
C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.10 DRAM/SRAM interface (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.11 Debug port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 24-bit DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 DSP peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2.1 Data and program memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.2.2 Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.4 Sony/Philips digital interface (S/PDIF) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2.5 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/38
TDA7505 Contents
5.2.6 DRAM/SRAM interface (DEMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2.7 Debug interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.8 General purpose input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.9 Asynchronous sample rate converter . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.10 SINCOS co-processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.11 PLL clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.2.12 CODEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2.13 Radio data system (RDS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.2.14 Clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6 Software features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.1 AM/FM base band signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.2 Generic audio signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.3 TAPE signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.4 CD signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.5 Audiophile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.6 Audio decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.7 Other . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.8 Functional modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3/38
List of tables TDA7505
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Recommended DC operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. General interface electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. High voltage CMOS interface DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. DSP core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 11. SAI interface timing - receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 12. SAI interface timing - transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 13. SPDIF receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 14. SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 15. I
Table 16. DRAM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 17. DRAM refresh period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 18. SRAM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 19. Debug port interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 20. ASRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 21. Fractional-N PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 22. ADC electrical characteristics - measurement bandwidth 10Hz to 20kHz . . . . . . . . . . . . . 25
Table 23. ADC electrical characteristics - measurement bandwidth 10Hz to 53kHz . . . . . . . . . . . . . 25
Table 24. ADC electrical characteristics - measurement bandwidth 10Hz to 192kHz . . . . . . . . . . . . 25
Table 25. Level ADC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 26. DAC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 27. FM stereo decoder (SW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 28. Examples of convenient clock schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 29. Example of possible modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 30. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2
C Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4/38
TDA7505 List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. LQFP100 pins connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3. SAI interface timing - receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 4. SAI interface timing - transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 5. SAI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 6. SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 7. SPI clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 8. I
Figure 9. Debug port serial clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10. Debug port acknowledge timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. Debug port data I/O to status timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Debug port read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. Debug port DBCK next command after read register timing. . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. LQFP100 (14x14x1.4mm) mechanical data and package dimensions. . . . . . . . . . . . . . . . 36
2
C Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5/38
Overview TDA7505
1 Overview
The TDA7505 integrates two 75 MIPS DSP cores. One core is used for stereo decoding,
noise blanking, weak signal processing, Dolby B, music search and MP3 decoding. The
second core is used for audio and sound processing and Echo & Noise cancellation. All
functions are realized in SW and thus are flexible on customer request.
The device may be controlled by a main micro through either SPI or I
the same pins, but with separate device address (I
2
C) respectively separate chip select line
(SPI) the main micro may communicate with the DSP or with the RDS block.
An additional SPI is available allowing a separate communication (e.g. to a display micro).
The DSP cores are integrated with their associated data and program memories.
DSP0 is declared as master. Its associated peripherals and interfaces are: I
(Master SPI), SPI2 (Display SPI), Serial Audio Interface (SAI), PLL Oscillator, External
Memory Interface (EMI), General Purpose I/O ports (DSP0 GPIO[0..11]), RDS filter and D/A
converters.
DSP1 is declared as Co-DSP. Its associated peripherals and interfaces are: A/D converters,
SPDIF, Sample Rate Converter (SRC) and General Purpose I/O ports (DSP1 GPIO[0..11]).
Both DSP´s are identical (ST Orpheus core, 75 MHz clock). Only the peripherals and
memory configurations are different. The internal communication takes place through a bidirectional 24/10-word exchange interface (XCHG) with complex flag and interrupts
capability.
2
C interface. Through
2
C, SPI1
The Radio Data System (RDS, respectively RBDS) function is realized via dedicated
hardware. It may run fully autonomous without SW intervention. Thus an efficient
background mode as well as a low current standby mode is possible. The RDS input is
connected to the A/D converter to receive the FM multiplex signal (MPX) automatically. Its
output may be configured to I
2
C or SPI format. The pins are shared with the I2C and SPI1 of
DSP0.
The device is equipped with a debug and test interface. It allows the SW development with a
100% compatible emulation system.
All functions, except RDS, are implemented in SW. Thus, the device may be adapted to
customers´ requirements. This implies the variable implementation of SW modules
developed by the customer, ST and third parties. This flexibility also allows the usage for
applications others than car radios, e.g.: Boosters.
6/38
TDA7505 Block diagram
μ
μ
Σ
/
2 Block diagram
Figure 1. Block diagram
analog audio in
ADC - ref
ADCVDD
ADCGND
AVDD
AGND
CLK in
8.55 MHz
6 Ch. Audio B us
receive bit&word clk
digital audio in
SPDIF audio in
CC
2
Qdiff
ΣΔ
Decimation
Audio
Crystal
Oscillator
2
DSP1 Orpheus Cor e
Including 12 GPIO´s
AM processing,
FM processing,
CD compression,
Dolby B
MP3
Debug Interface
CD
Navi
Tel.
2
4
.
Input Source Selector
Diff .
Diff .
Δ ΣΔ ΣΔ
Decimation
FM/Audio
SAI 6ch.
Receiver
SPDIF 2ch.
Interface
,
.
2
Mpx
AM/FM
RDS
Qdiff
SINCOS
2ch sample
rate converter
X Ram 4096
X Rom 4096
Y Ram 40969
P Ram
P Rom 16384
M
AM
3
.
4096
px
FMLevel
AM/FM
level
ADC
PLL Clock
Generator
Xchg
Interface
analog audio out
SC
FilterSCFilter
Noise
Shaper
Oversampl.
Filter
RDS
Filter
External Memory Interface
X Ram
Y Ram
P Ram
P Rom 16384
SC
FilterSCFilter
Oversampl.
Filter
Demod
10 word SPI 1
receive stack
4096
4096
4096
Noise
Shaper
.
SC
SC
Filter
Filter
Noise
Shaper
Oversampl .
Filter
Grp&blk
sync., error
correction
IIC / SPI 1
SPI 2
SAI Transmit ter
SRAM 4Mx
DRAM 64Mx4
DSP0 Orpheus Core
Including 12 GPIO´s
Audio processing,
Sound processing,
TAM,
Echo & noise
SPI
IIC
8
cancell
Debug Interface
-
DAC
ref
DACVDD
DACGND
4
4
3
2
8+3
17
4
4
Debug
5
RDS Int.
RDSCS
P
control
Display
6 Channel
Audio Bus
INT
NRESET
VDD
GND
/
Test
P
/
.
7/38
Pin description TDA7505
3 Pin description
Table 2. Pin description
N° Name Type Function
1 DAC4 A Signal output D/A converter (single ended)
2 DAC5 A Signal output D/A converter (single ended)
N° Name Type Voltage Function
3 VDD1V8_1 S 1.8V Digital Supply dedicated to internal logic
4 GND1V8_1 S 0V Digital Ground dedicated to internal logic
N° Name Type
5 NRESET I E0 E1 E1 E1 Input 5VT
SRCCD
6
MISOD output
MISOD input
SRCMD
MOSID input
7
MOSID output
DSP0 GPIO0
DSP0 GPIO0
Reset
state
I/OZ ZZZ
I/O
Z ZZZ
After boot with
2
SPI I
C * EMI
I/O Function
Input 5VT
Output 2mA PP/OD
Input 5VT
Input 5VT
Input 5VT
Output 2mA PP
Input 5VT
Output 2mA PP
System Reset. A low level
applied to NRESET input
initializes the IC.
SPDIF input source 1 (e.g.: CD)
Display SPI SO (slave mode)
Display SPI MI (master mode)
SPDIF input source 2 (e.g.: MD)
Display SPI SI (slave mode)
Display SPI MO (master mode)
GPIO input
GPIO output
SSD input
INT
8
DSP0 GPIO1
DSP0 GPIO1
CLKIN
9
SCKD input
SCKD output
N° Name Type Voltage Function
10 AVDD S 3.3V Supply dedicated to the PLL
11 XTI A AC Crystal oscillator input
12 XTO A AC Crystal oscillator output
13 AGND S 0V Ground dedicated to the PLL
I/O
I/OZ ZZZ
Z ZZZ
Input 5VT
Input 5VT
Input 5VT
Output 2mA PP
Input 5VT
Input 5VT
Output 2mA PP
Display SPI SS slave select
DSP0 external interrupt (IRQA)
GPIO input
GPIO output
External clock input for PLL
Display SPI clock (slave mode)
Display SPI clock (master mode)
8/38
TDA7505 Pin description
Table 2. Pin description (continued)
After boot with
2
SPI I
C * EMI
I/O Function
Input 5VT
Output 2mA OD
Input 5VT
Output 2mA PP
Input 5VT
Output 2mA OD
Output 2mA PP
Input 5VT
Output 2mA PP
RDS SPI CS chip select in
RDS bit data
GPIO input
GPIO output
DSP0 external interrupt (IRQA)
RDS bit clock
RDS Interrupt Output
GPIO input
GPIO output
N° Name Type
RDSCS
-
14
DSP0 GPIO2
I/O
DSP0 GPIO2
INT
-
15
RDSINT
I/O
DSP0 GPIO3
DSP0 GPIO3
Reset
State
Z ZZZ
Z ZZZ
N° Name Type Voltage Function
16 VDD3V3_1 S 3.3V Digital supply dedicated to I/O structures
17 GND3V3_1 S 0V Digital ground dedicated to I/O structures
SCKM input
SCKM output
18
SCL bi-direct
DSP0 GPIO4
DSP0 GPIO4
I/O
Z
0/1 Z
Input 5VT
Output 2mA PP
In 5VT/Out 2mA OD
Z
Input 5VT
Output 2mA PP
Master/RDS SPI clock (slave m.)
Master SPI clock (master mode)
I2C clock
GPIO input
GPIO output
N° Name Type
MISOM output
MISOM input
19
ADDR select
I/O
DSP0 GPIO5
DSP0 GPIO5
MOSIM input
MOSIM output
20
SDA bi-direct
I/O
DSP0 GPIO6
DSP0 GPIO6
SSM input
21
DSP0 GPIO7
I/O Z
DSP0 GPIO7
DSRA<0>
22
23
24
DSRA<0>
DSRA<1>
DSRA<1>
DSRA<2>
DSRA<2>
I/O 0 1 1 Z
I/O 0 1 1 Z
I/O 0 1 1 Z
Reset
state
Z
Z
After boot with
2
SPI I
C * EMI
0/1 Z
0/1 Z
Z
ZZ
Output 2mA PP/OD
Input 5VT
Input 5VT
Z
Input 5VT
Output 2mA PP
Input 5VT
Output 2mA PP
In 5VT/Out 2mA OD
Z
Input 5VT
Output 2mA PP
Input 5VT
Input 5VT
Output 2mA PP
In/Out 2mA PP
In/Out 2mA PP
In/Out 2mA PP
In/Out 2mA PP
In/Out 2mA PP
In/Out 2mA PP
I/O Function
Master/RDS SPI SO (slave m.)
Master SPI MI (master mode)
2
C Address select line
I
GPIO input
GPIO output
Master/RDS SPI SI (slave m.)
Master SPI MO (master mode)
2
C data
I
GPIO input
GPIO output
Master SPI SS slave select
GPIO input
GPIO output
EMI SRAM Data 0
EMI DRAM Data 0
EMI SRAM Data 1
EMI DRAM Data 1
EMI SRAM Data 2
EMI DRAM Data 2
9/38
Pin description TDA7505
Table 2. Pin description (continued)
After boot with
2
SPI I
C * EMI
I/O Function
In/Out 2mA PP
In/Out 2mA PP
EMI SRAM Data 3
EMI DRAM Data 3
N° Name Type
DSRA<3>
25
DSRA<3>
I/O 0 1 1 Z
Reset
state
26 DSRA<4> I/O 0 1 1 Z In/Out 2mA PP EMI SRAM Data 4
27 DSRA<5> I/O 0 1 1 Z In/Out 2mA PP EMI SRAM Data 5
28 DSRA<6> I/O 0 1 1 Z In/Out 2mA PP EMI SRAM Data 6
29 DSRA<7> I/O 0 1 1 Z In/Out 2mA PP EMI SRAM Data 7
30
31
SRA<0>
SRA<0>
SRA<1>
SRA<1>
O0 110/1
O0 110/1
Output 2mA PP
Output 2mA PP
Output 2mA PP
Output 2mA PP
EMI SRAM Address 0
EMI DRAM Address 0
EMI SRAM Address 1
EMI DRAM Address 1
N° Name Type Voltage Function
32 VDD3V3_2 S 3.3V Digital Supply dedicated to I/O structures
33 GND3V3_2 S 0V Digital Ground dedicated to I/O structures
After boot with
2
SPI I
C * EMI
I/O Function
N° Name Type
Reset
state
SRA<2>
34
35
36
37
38
39
40
SRA<2>
SRA<3>
SRA<3>
SRA<4>
SRA<4>
SRA<5>
SRA<5>
SRA<6>
SRA<6>
SRA<7>
SRA<7>
SRA<8>
SRA<8>
O0 110/1
O0 110/1
O0 110/1
O0 110/1
O0 110/1
O0 110/1
O0 110/1
N° Name Type
SRA<9>
41
42
SRA<9>
SRA<10>
SRA<10>
O0 110/1
O0 110/1
Reset
state
After boot with
2
SPI I
C * EMI
Output 2mA PP
Output 2mA PP
Output 2mA PP
Output 2mA PP
Output 2mA PP
Output 2mA PP
Output 2mA PP
Output 2mA PP
Output 2mA PP
Output 2mA PP
Output 2mA PP
Output 2mA PP
Output 2mA PP
Output 2mA PP
I/O Function
Output 2mA PP
Output 2mA PP
Output 2mA PP
Output 2mA PP
EMI SRAM Address 2
EMI DRAM Address 2
EMI SRAM Address 3
EMI DRAM Address 3
EMI SRAM Address 4
EMI DRAM Address 4
EMI SRAM Address 5
EMI DRAM Address 5
EMI SRAM Address 6
EMI DRAM Address 6
EMI SRAM Address 7
EMI DRAM Address 7
EMI SRAM Address 8
EMI DRAM Address 8
EMI SRAM Address 9
EMI DRAM Address 9
EMI SRAM Address 10
EMI DRAM Address 10
10/38
TDA7505 Pin description
Table 2. Pin description (continued)
After boot with
2
SPI I
C * EMI
I/O Function
Output 2mA PP
Output 2mA PP
Output 2mA PP
Output 2mA PP
EMI SRAM Address 11
EMI DRAM Address 11
EMI SRAM Address 12
EMI DRAM Address 12
N° Name Type
SRA<11>
43
44
SRA<11>
SRA<12>
SRA<12>
O0 110/1
O0 110/1
Reset
state
N° Name Type Voltage Function
45 VDD1V8_2 S 1.8V Digital Supply dedicated to internal logic
GND1V8_2 &
46
GND3V3_3
S0V
Digital Ground dedicated to internal logic and I/O
structures
47 VDD3V3_3 S 3.3V Digital Supply dedicated to I/O structures
After boot with
2
SPI I
C * EMI
I/O Function
N° Name Type
Reset
state
48 DRD O 1 1 1 1 Output 2mA PP EMI data read strobe
49 DWR O 1 1 1 1 Output 2mA PP EMI data write strobe
50
CAS
SRA<13>
O
0110/1
Output 2mA PP
Output 2mA PP
EMI DRAM CAS
EMI SRAM Address 13
51 SRA<14> O 0 1 1 0/1 Output 2mA PP EMI SRAM Address 14
SRA<15>
52
DSP0 GPIO8
DSP0 GPIO8
INOUTA
SRA<16>
53
DSP1 GPIO0
DSP1 GPIO0
INOUTB
SRA<17>
54
DSP1 GPIO1
DSP1 GPIO1
I/O Z Z Z 0/1
I/O
I/O
ZZZ0/1
ZZZ0/1
Output 2mA PP
Input 5VT
Output 2mA PP
In 5VT/Out 2mA PP
Output 2mA PP
Input 5VT
Output 2mA PP
In 5VT/Out 2mA PP
Output 2mA PP
Input 5VT
Output 2mA PP
EMI SRAM Address 15
GPIO input
GPIO output
Multi function I/O
EMI SRAM Address 16
GPIO input
GPIO output
Multi function I/O
EMI SRAM Address 17
GPIO input
GPIO output
INOUTC
SRA<18>
55
DSP1 GPIO2
I/O
DSP1 GPIO2
N° Name Type
INOUTD
SRA<19>
56
DSP1 GPIO3
I/O
DSP1 GPIO3
ZZZ0/1
Reset
state
After boot with
2
SPI I
C * EMI
0/1
ZZZ
In 5VT/Out 2mA PP
Output 2mA PP
Input 5VT
Output 2mA PP
Multi function I/O
EMI SRAM Address 18
GPIO input
GPIO output
I/O Function
In 5VT/Out 2mA PP
Output 2mA PP
Input 5VT
Output 2mA PP
Multi function I/O
EMI SRAM Address 19
GPIO input
GPIO output
11/38
Pin description TDA7505
Table 2. Pin description (continued)
After boot with
2
SPI I
C * EMI
Z
In 5VT/Out 2mA PP
0/1
Output 2mA PP
Input 5VT
Output 2mA PP
In 5VT/Out 2mA PP
0/1
Output 2mA PP
Output 2mA PP
Input 5VT
Output 2mA PP
In 5VT/Out 2mA PP
Input 5VT
Output 2mA PP
In 5VT/Out 2mA PP
Input 5VT
Output 2mA PP
I/O Function
Multi function I/O
EMI SRAM Address 20
GPIO input
GPIO output
Multi function I/O
EMI SRAM Address 21
EMI DRAM RAS
GPIO input
GPIO output
Multi function I/O
GPIO input
GPIO output
Multi function I/O
GPIO input
GPIO output
N° Name Type
INOUTE
SRA<20>
57
DSP1 GPIO4
I/O
DSP1 GPIO4
INOUTF
SRA<21>
58
RAS
I/O
DSP1 GPIO5
DSP1 GPIO5
INOUTG
59
DSP1 GPIO6
I/OZ ZZZ
DSP1 GPIO6
INOUTH
60
DSP1 GPIO7
I/OZ ZZZ
DSP1 GPIO7
Reset
state
ZZ
ZZZ
N° Name Type Voltage Function
61 VDD3V3_4 S 3.3V Digital Supply dedicated to I/O structures
62 GND3V3_4 S 0V Digital Ground dedicated to I/O structures
After boot with
2
SPI I
C * EMI
I/O Function
In 5VT/Out 2mA PP
Input 5VT
Output 2mA PP
Multi function I/O
GPIO input
GPIO output
N° Name Type
INOUTI
63
DSP1 GPIO8
I/OZ ZZZ
DSP1 GPIO8
Reset
state
64 INOUTJ I/O Z Z Z Z In 5VT/Out 2mA PP Multi function I/O
DBCK
OS1
65
DSP0/1 GPIO9
I/O
DSP0/1 GPIO9
DBOUT
66
DSP0/1 GPIO10
I/O
DSP0/1 GPIO10
N° Name Type
DBIN
OS0
67
DSP0/1 GPIO11
I/O
DSP0/1 GPIO11
Z
Z
Reset
state
Z
000
111
After boot with
2
SPI I
C * EMI
000
Input 5VT
Out 2mA PP
Input 5VT
Output 2mA PP
Output 2mA PP
Input 5VT
Output 2mA PP
I/O Function
Input 5VT
Out 2mA PP
Input 5VT
Output 2mA PP
Debug clock
Chip status 1
GPIO input
GPIO output
Debug output
GPIO input
GPIO output
Debug input
Chip status 0
GPIO input
GPIO output
12/38
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