160-watt + 160-watt dual BTL class-D audio amplifier
Features
■ 160-W + 160-W output power at
THD = 10% with R
■ 1 x 220 W output power mono parallel BTL at
THD = 10% with R
■ Wide-range single-supply operation (14 - 36 V)
■ High efficiency (η = 85%)
■ Parallel BTL function using the MODE pin
■ Four selectable, fixed gain settings of
nominally 23.8 dB, 29.8 dB, 33.3 dB and
35.8 dB
■ Differential inputs minimize common-mode
noise
■ Standby and mute features
■ Smart protection
■ Thermal overload protection
■ Small offset less than 20 mV
= 4 Ω and V
L
= 3 Ω and V
L
CC
CC
= 36 V
= 36 V
TDA7498E
Preliminary data
PowerSSO36
with exposed pad up
Description
The TDA7498E is a dual BTL class-D audio
amplifier with a single power supply designed for
home systems and active speaker applications.
It comes in a 36-pin PowerSSO package with
exposed pad up (EPU) to facilitate mounting a
separate heatsink.
Table 1. Device summary
Order code Operating temp. range Package Packaging
TDA7498E 0 to 70 °C PowerSSO36 (EPU) Tube
TDA7498ETR 0 to 70 °C PowerSSO36 (EPU) Tape and reel
December 2011 Doc ID 022595 Rev 1 1/20
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
www.st.com
20
Contents TDA7498E
Contents
1 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Pin list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.3 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.5 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 Characterization curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1 For RL = 4 Ω, stereo configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 For R
= 3 Ω, mono BTL configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
L
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Stereo and mono BTL operation selection using the MODE pin . . . . . . . 16
5.2 Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3 Smart protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20 Doc ID 022595 Rev 1
TDA7498E List of figures
List of figures
Figure 1. Internal block diagram (showing one channel only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Pin connections (top view, PCB view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Test circuit stereo application and mono BTL mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. Output power vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. THD vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. FFT performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Crosstalk vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Output power vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. THD vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. THD vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12. PowerSSO36 EPU outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Doc ID 022595 Rev 1 3/20
Device block diagram TDA7498E
1 Device block diagram
Figure 1 shows the block diagram of one of the two identical channels of the TDA7498E.
Figure 1. Internal block diagram (showing one channel only)
4/20 Doc ID 022595 Rev 1
TDA7498E Pin description
2 Pin description
2.1 Pinout
Figure 2. Pin connections (top view, PCB view)
36
35
34
33
32
31
30
29
28
27
26
25
24
VSS
SVCC
VREF
INNB
INPB
MODE
GAIN
SVR
DIAG
SGND
VDDS
SYNCLK
ROSC
SUB_GND
OUTPB
OUTPB
PGNDB
PGNDB
PVCCB
PVCCB
OUTNB
OUTNB
OUTNA
OUTNA
PVCCA
PVCCA
1
2
3
4
5
6
7
8
9
10
11
12
13
23
22
21
20
19
INNA
INPA
MUTE
STBY
VDDPW
PGNDA
EP, exposed pad
Connect to ground
Doc ID 022595 Rev 1 5/20
PGNDA
OUTPA
OUTPA
PGND
14
15
16
17
18
Pin description TDA7498E
2.2 Pin list
Table 2. Pin description list
Number Name Type Description
1 SUB_GND PWR Connect to the frame
2,3 OUTPB O Positive PWM for right channel
4,5 PGNDB PWR Power stage ground for right channel
6,7 PVCCB PWR Power supply for right channel
8,9 OUTNB O Negative PWM output for right channel
10,11 OUTNA O Negative PWM output for left channel
12,13 PVCCA PWR Power supply for left channel
14,15 PGNDA PWR Power stage ground for left channel
16,17 OUTPA O Positive PWM output for left channel
18 PGND PWR Power stage ground
19 VDDPW O
3.3-V (nominal) regulator output referred to ground for power
stage
20 STBY I Standby mode control
21 MUTE I Mute mode control
22 INPA I Positive differential input of left channel
23 INNA I Negative differential input of left channel
24 ROSC O Master oscillator frequency-setting pin
25 SYNCLK I/O Clock in/out for external oscillator
26 VDDS O
3.3-V (nominal) regulator output referred to ground for signal
blocks
27 SGND PWR Signal ground
28 DIAG O Open-drain diagnostic output
29 SVR O Supply voltage rejection
30 GAIN I Gain setting input
31 MODE I Enables stereo or mono BTL mode of operation
32 INPB I Positive differential input of right channel
33 INNB I Negative differential input of right channel
34 VREF O Half VDDS (nominal) referred to ground
35 SVCC PWR Signal power supply
36 VSS O 3.3-V (nominal) regulator output referred to power supply
- EP - Exposed pad for heatsink, to be connected to ground
6/20 Doc ID 022595 Rev 1
TDA7498E Electrical specifications
3 Electrical specifications
3.1 Absolute maximum ratings
Table 3. Absolute maximum ratings
Symbol Parameter Value Unit
V
VI
T
CC
j
DC supply voltage for pins PVCCA, PVCCB, SVCC 40 V
Voltage limits for input pins STBY, MUTE, INNA, INPA, INNB, INPB,
GAIN, MODE
-0.3 to 4.0 V
Operating junction temperature 0 to 150 °C
Top Operating ambient temperature 0 to 70 °C
T
stg
Storage temperature -40 to 150 °C
3.2 Thermal data
Table 4. Thermal data
Symbol Parameter Min Typ Max Unit
R
th j-case
Thermal resistance, junction to case - 3.0 °C/W
3.3 Recommended operating conditions
Table 5. Recommended operating conditions
Symbol Parameter Min Typ Max Unit
V
CC
Supply voltage for pins PVCCA, PVCCB, SVCC 14 - 36 V
Tamb Ambient operating temperature 0 - 70 °C
Doc ID 022595 Rev 1 7/20
Electrical specifications TDA7498E
3.4 Electrical specifications
Unless otherwise stated, the values in the table below are specified for the conditions:
V
=36V, RL = 4 Ω, R
CC
Ta mb = 2 5 ° C.
Table 6. Electrical specifications
Symbol Parameter Condition Min Typ Max Unit
= R3 = 39 kΩ, C8 = 100 nF, f = 1 kHz, GV = 23.6 dB
OSC
I
q
I
qSTBY
V
OS
I
OCP
T
j
R
i
V
UVP
Total quiescent current No LC filter, no load - 60 mA
Quiescent current in standby - - 1 µA
Output offset voltage
Vi = 0 Av = 23.6 dB,
no load
-20 - 20 mV
Overcurrent protection threshold RL = 0 Ω 10 11 14 A
Junction temperature at thermal
shutdown
- 140 150 160 °C
Input resistance Differential input 69 - kΩ
Undervoltage protection threshold - - - 8 V
High side - 0.15 -
R
dsON
Power transistor on resistance
Low side - 0.15 -
THD = 10% - 160 -
P
o
P
o
Output power
Parallel BTL (mono) output power,
= 3 ohm, Vcc = 36 V
R
L
THD = 1% - 125 -
THD = 10% - 220 -
THD = 1% - 170 -
η Efficiency - 85 - %
THD Total harmonic distortion P
= 1 W - 0.05 - %
o
GAIN0 < 0.25*VDD 23.8
0.25*VDD < GAIN < 0.5*VDD 29.8
G
V
Closed-loop gain
0.5*VDD < GAIN < 0.75*VDD 33.3
Ω
W
W
dB
GAIN > 0.75*VDD 35.8
ΔG
C
V
T
Gain matching - -1 - 1 dB
Crosstalk f = 1 kHz, Po = 1 W 50 60 - dB
Inputs shorted and to Ground A
curve
Vn Total output noise
Inputs shorted and to Ground
f = 20 Hz to 20 kHz
SVRR Supply voltage rejection ratio
T
r
f
SW
f
SWR
, T
f
Rise and fall times - - 35 - ns
Switching frequency Internal oscillator 240 310 400 kHz
Output switching frequency range
fr = 100 Hz, Vr = 0.5 Vpp,
= 10 µF
C
SVR
With internal oscillator by changing
(1)
Rosc
8/20 Doc ID 022595 Rev 1
231 µV
400 µV
-55-dB
240 - kHz
TDA7498E Electrical specifications
Table 6. Electrical specifications (continued)
Symbol Parameter Condition Min Typ Max Unit
V
inH
V
inL
Function
mode
A
MUTE
1. fSW = 106 / ((16 * R
Digital input high (H)
Digital input low (L) - - 0.8
Standby & mute & play
Mute attenuation V
+ 182) * 4) kHz, f
OSC
-
STBY < 0.5 V, MUTE = X StandBy
STBY > 2.5 V ; MUTE < L Mute
STBY > 2.5 V, MUTE > H Play
< L, V
MUTE
= 2 * fSW with R3 = 39 kΩ (see Figure 3)
SYNCLK
= H - 75 - dB
STBY
2.0 - V
Doc ID 022595 Rev 1 9/20
Electrical specifications TDA7498E
3.5 Test circuit
Figure 3. Test circuit stereo application and mono BTL mode
D2
VCC
R-OUTPUT
8R
C18
220nF
2
1
R+
Load=4 ohm
C42
220nF
C20
R-
1uF
J14
C43
220nF
C22
R18
220nF
J9
J10
J11
J12
8R
GAIN SETTING
GAIN JUMPER
23.6dB
29.6dB
33.1dB
35.6dB
J5
J6,J3,J8
R15
8R
C28
LOUTPUT
Load=4 ohm
C40
220nF
220nF
1
L+
C26
2
1uF
J13
L-
VCC
C41
220nF
R16
8R
GND
2
1
R17
J2
+
C24
220nF
C23
50V
2200uF
+
C32
50V
L3
L4
L4S
WL+
WR+
MONO
OUT
L3S
2200uF
L1
L1S
WL-
WR-
MONO
OUT
L2
L2S
MODE SETTING
MODE JUMPER
Optional components or circuitry
MONO
STEREO
VCC
R6
22R
D3
14
16
17
15
OUTPA
OUTPA
PGNDA
PGNDA
C30
C25
1uF
100nF
C27
12
PVCCA
330pF
13
PVCCA
VCC
D4
10
OUTNA
R5
D6
22R
D5
D7
7
11
OUTNA
3
OUTPB
6
2
PVCCB
PVCCB
OUTPB
C19
C31
1uF
100nF
C21
330pF
5
4
PGNDB
PGNDB
VCC
D9
D8
9
OUTNB
C17
8
34
VREF
OUTNB
10uF
10V
29
SVR
C16
10uF
10V
IC1
TDA7498E
(PSSO36)
TDA7498E
INPA
SUB_GND
1
22
C1
C3
1uF
INNA
23
1nF
C2
C4
1uF
SGND
27
1nF
VDDS
26
VDDS
C5
J1
DIAG
28
R1
100nF
L-
INPUT
DIAG
47k
R7
22R
Input
For
Single-Ended
J7
L+
3
VDDPW18PGND
19
C6
100nF
FREQUENCY SHIFT
R+
R-
241
R9
MONO
SYNCLK
25
SYNC
3
180K
Q1
KTC3875(S)
INPUT
ROSC
24
R3
39K
C8
100nF
2
1
R14
R13
47k
L+, L- Only
GAIN
30
J12
VDDS
100k
PS
MODE35SVCC
31
J9
J6
J11
R11
R10
VDDS
J5
J10
100k
100k
10/20 Doc ID 022595 Rev 1
VSS
36
C10
100nF
VDDS
R12
100k
Input and
J8
For Single-Ended
J3
MONO
INPB
32
C11
MONO Config
Config
1uF
C13
PS
3V3
1nF
C12
INNB
33
J4
C14
1uF
MUTE
S2
MUTE
21
1nF
R4
2
1
3
C15
+
2.2uF
120k
R19
STBY
S1
STBY
20
16V
R2
33k
1
CLASS-D AMPLIFIER
C7
2.2uF
16V
+
VCC
33k
R8
6.8k
D1
18V
2
3
IN
IC2
OUT
C9
3
100nF
GND
2
L4931CZ33
1
3V3 POWER SUPPLY
2.2uF
C29
Characterization curves TDA7498E
4 Characterization curves
Unless otherwise stated, measurements were made under the following conditions:
Vcc = 36 V, f = 1 kHz , G
= 23.6 dB, Rosc = 39 kΩ, Cosc = 100 nF, Tamb = 25 °C.
V
4.1 For RL = 4 Ω, stereo configuration
Figure 4. Output power vs. supply voltage
11/20 Doc ID 022595 Rev 1
Characterization curves TDA7498E
Figure 5. THD vs. output power
Figure 6. THD vs. frequency
12/20 Doc ID 022595 Rev 1
TDA7498E Characterization curves
Figure 7. FFT performance
Figure 8. Crosstalk vs. frequency
Doc ID 022595 Rev 1 13/20
Characterization curves TDA7498E
4.2 For RL = 3 Ω, mono BTL configuration
Figure 9. Output power vs. supply voltage
14/20 Doc ID 022595 Rev 1
TDA7498E Characterization curves
Figure 10. THD vs. output power
Figure 11. THD vs. frequency
Doc ID 022595 Rev 1 15/20
Application information TDA7498E
5 Application information
5.1 Stereo and mono BTL operation selection using the MODE pin
The TDA7498E can be used in stereo applications or mono BTL applications. Connecting
the MODE pin to the VDDS pin configures the device in mono BTL. The output of the two
channels can be paralleled. When the MODE pin is connected to ground or floating (pulled
down internally) the device works as a stereo amplifier.
5.2 Gain setting
The gain of the TDA7498E is set by GAIN (pin 30).
Table 7. Gain settings
GAIN0 Total Gain Application suggestion
VGAIN < 0.25*VDDS 23.6 dB GAIN pin connected to SGND
0.25*VDDS < VGAIN < 0.5*VDDS 29.6 dB Rc10 = Rc11= Rc12 = 100 K max
0.5*VDDS < VGAIN < 0.75*VDDS 33.1 dB Rc10 = Rc11 = Rc12 = 100K max
VGAIN > 0.75*VDDS 35.6 dB GAIN pin connected to VDDS
5.3 Smart protection
To avoid dynamic impedance drop, two overcurrent thresholds are set. The first threshold is
for the overcurrent limit. The device limits the output current to the first threshold but does
not shut down the PWM outputs.
If the device is shorted and at least one of the two output currents reaches the second
threshold, the device is shut down immediately. The device will recover automatically when
the fault is removed from the BTL outputs.
16/20 Doc ID 022595 Rev 1
TDA7498E Package mechanical data
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK®
®
is an ST trademark.
The TDA7498E comes in a 36-pin PowerSSO package with exposed pad up.
Figure 12 shows the package outline and Tab le 8 gives the dimensions.
Table 8. PowerSSO36 EPU dimensions
Dimensions in mm Dimensions in inches
Symbol
Min Typ Max Min Typ Max
A 2.15 - 2.45 0.085 - 0.096
A2 2.15 - 2.35 0.085 - 0.093
a1 0 - 0.10 0 - 0.004
b 0.18 - 0.36 0.007 - 0.014
c 0.23 - 0.32 0.009 - 0.013
D 10.10 - 10.50 0.398 - 0.413
E 7.40 - 7.60 0.291 - 0.299
e - 0.5 - - 0.020 -
e3 - 8.5 - - 0.335 -
F - 2.3 - - 0.091 -
G- - 0.10 - - 0.004
H 10.10 - 10.50 0.398 - 0.413
h- - 0.40 - - 0.016
k 0 - 8 degrees - - 8 degrees
L 0.60 - 1.00 0.024 - 0.039
M - 4.30 - - 0.169 -
N - - 10 degrees - - 10 degrees
O - 1.20 - - 0.047 -
Q - 0.80 - - 0.031 -
S - 2.90 - - 0.114 -
T - 3.65 - - 0.144 -
U - 1.00 - - 0.039 -
X 4.10 - 4.70 0.161 - 0.185
Y 4.90 - 7.10 0.193 - 0.280
Doc ID 022595 Rev 1 17/20
Doc ID 022595 Rev 1 18/20
Figure 12. PowerSSO36 EPU outline drawing
TDA7498E Package mechanical data
h x 45°
TDA7498E Revision history
7 Revision history
Table 9. Document revision history
Date Revision Changes
12-Dec-2011 1 Initial release.
Doc ID 022595 Rev 1 19/20
TDA7498E
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20/20 Doc ID 022595 Rev 1
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